CN1165405A - Narrow forbidden band source leckage range metal oxide semiconductor field effect transistor and integrated circuit - Google Patents

Abstract

A series of MOSFETs features that the narrow-energy-gap heterogeneous material different from substrate is used as source area or source and drain areas of device to make the emitter junction of parasitic BJT in device become heterojucntion and beta be less than 1, so thoroughly eliminating the influence of parasic BJT on BVDS. The CMOS IC made up by means of present invention can also eliminate block-up effect thoroughly. The rule to select narrow-energy-gap material is also disclosed. Its advantages are easy manufacture, less chip area and high performance.

Description

Narrow forbidden band source leckage range metal oxide semiconductor field effect transistor and integrated circuit

The invention belongs to semiconductor device and technical field of integrated circuits, particularly mos field effect transistor and integrated circuit thereof.

As everyone knows, since mos field effect transistor (MOSFET) came out from 60 generations, because its structure and manufacturing process are simple, it was very extensive and be particularly suitable for integrated basic device to have become purposes.This traditional MOSFET, no matter it is to make by Si, SiC material or by the III-V compound material, it all is to make substrate and source region (S), drain region (D) by commaterial (Si, SiC or III-V compound material) to each device or IC, just conduction type is different with doping content, in the present invention, we claim that it is homogeneity source, drain region.Because this MOSFET structure itself exists pnp or npn parasitic bipolar transistor (BJT) inevitably, this makes the source drain breakdown voltage BV of MOSFET _DSBV by parasitic BJT _CEODecision (BV _CEOCollector Emitter puncture voltage during for the open base of parasitic BJT), well-known, the BV of parasitic BJT _CBO(collector electrode-base break down voltage during the emitter open circuit) and BV _CEOBetween the pass be: ${\mathrm{BV}}_{\mathrm{CEO}}={\mathrm{BV}}_{\mathrm{CBO}}/\sqrt{\mathrm{\β}}$ β is the common emitter current gain of parasitic BJT in the formula.That is to say, when parasitic BJT exists, conventional MOS FET's ${\mathrm{BV}}_{\mathrm{DS}}={\mathrm{BV}}_{\mathrm{CEO}}={\mathrm{BV}}_{\mathrm{CBO}}/\sqrt{\mathrm{\β}}$ , promptly it makes the puncture voltage BV of conventional MOS FET _DSReduced

Doubly, this has brought a series of problems for the application of device; In addition, the CMOS IC that forms by a pair of complementary P ditch MOSFET and N ditch MOSFET at least, the four layer crystal brake tube structures that its structure itself exists parasitic npn and pnp transistor to form inevitably, when the product of the common emitter current gain of parasitic npn and pnp:

β _Npn* β _Pnp〉=1 when being met, and CMOS IC produces locking, and this will influence the reliability of IC, and limit the raising of circuit performance.For this reason, people have adopted a series of measures to reduce the β of parasitic BJT, in the hope of reducing parasitic BJT to MOS device electric breakdown strength BV _DSInfluence and make CMOS IC produce the problem of locking, such as, the short-circuit structure of employing source (S) utmost point and substrate (being the emitter of parasitic BJT and the short-circuit structure of base stage), and adopt two buried regions substrates, shading ring, puppet to collect at CMOS IC and tie or the like, but because the existence of semiconductor bulk resistor, desirable short-circuit structure is difficult to realize, add short-circuit structure itself and also have problems such as having increased chip area and on-resistance per unit Rons, make parasitic BJT can not get overcoming at all the influence of MOS device and IC.

The problems referred to above at conventional MOS FET and integrated circuit existence thereof, the objective of the invention is to propose a kind of MOSFET of new construction, make it to eliminate more up hill and dale the influence of parasitic BJT to the MOS device withstand voltage, there is not latch-up problem with the CMOS integrated circuit of forming by new construction MOSFET, and realize that technology is easy, and do not increase chip area.

According to the invention task, a kind of narrow forbidden band source leckage range metal oxide semiconductor field effect transistor provided by the invention (being called for short MOHET) and integrated circuit (IC), the low energy gap dissimilar materials has been adopted in the source region that it is characterized in that it, its structural representation as shown in Figure 1, it is included in to be separated by on the face of substrate 1 and is provided with and heterogeneous source region 2 of the high-dopant concentration of substrate 1 transoid and high-dopant concentration homogeneity drain region 3, described 2, be channel region 4 between 3 liang of districts, on described part source region and surface, drain region and channel region 4 surfaces, be formed with gate insulation deielectric-coating 6, from 2 surfaces, described source region, channel region gate insulation deielectric-coating surface, 4 top and 3 surfaces, drain region are formed with good electrode of electric conductivity and the corresponding S of drawing, G, the D utmost point.

Second kind of MOHET provided by the invention and IC, the low energy gap dissimilar materials has all been adopted in the source region and the drain region that it is characterized in that it, its structural representation such as Fig. 2, it comprises: being separated by on a face of substrate 1 is provided with and heterogeneous source region 2 of the high-dopant concentration low energy gap of its transoid and the heterogeneous drain region 5 of high-dopant concentration low energy gap, described 2, be channel region 4 between 5 liang of districts, on described part source region and surface, drain region and channel region 4 surfaces, be formed with gate insulation deielectric-coating 6, from 2 surfaces, described source region, channel region gate insulation deielectric-coating surface, 4 top and 5 surfaces, drain region are formed with good electrode of electric conductivity and the corresponding S of drawing, G, the D utmost point constitutes S, D is the MOHET of symmetry fully.The S of this structure, D can exchange use.

The third and the 4th kind of MOHET provided by the invention are in the MOHET of above-mentioned two structures, adjacent in the heterogeneous source region 2 of high-dopant concentration is manufactured with the high-dopant concentration homogeneity source electrode shorting region 7 with heterogeneous source region 2 transoids, its structural representation as shown in Figure 3 and Figure 4, these two kinds of structures can be used on when needing substrate ground connection in some use, it has reduced the shared area of source electrode shorting region greatly, and then reaches the purpose of saving chip area.

The said low energy gap dissimilar materials of the present invention is meant that this kind material is different from device substrate and energy gap is narrower than corresponding backing material again, MOS device to different backing materials, said low energy gap dissimilar materials is different, such as, to with silicon (Si) be substrate the MOS device it can be the SiGe material, the content of Ge component is transformable in this SiGe material, its Ge content difference, the energy gap difference that means the SiGe material, when the content of Ge component was 100%, the SiGe material then became the Ge material; To with GaAs being the MOS device of substrate, it can be Si or SiGe material; To with GaAlAs being the MOS device of substrate, it can be the GaAs material; To with SiC be substrate the MOS device it can be Si material or the like.

From as can be seen above-mentioned: the emitter of parasitic BJT is a homojunction among conventional MOS FET, and among the present invention, the emitter of parasitic BJT then is a heterojunction, and the pass of the β of its heterojunction and homojunction β is:

β _{R is different}=β _{R together}Exp (△ Eg/KT)

In the formula: β _{R is different}And β _{R together}Be respectively the emission maximum electrode current gain of heterogeneous and homogeneity emitter injection efficiency r decision; What △ Eg was heterogeneous small gap material with corresponding backing material energy gap is poor

β when △ Eg=0.05ev _{R is different}=0.15 _{R together}

β during △ Eg=0.25ev _{R is different}=6.7 * 10 ^-5β _{R together}

β during △ Eg=0.42ev _{R is different}=10 * 10 ^-7β _{R together}

From finding out, the forbidden band of low energy gap dissimilar materials is narrower, and is just bigger with the energy gap difference △ Eg of corresponding backing material, its β _DifferentWill be littler.And draw thus: the heterogeneous emitter junction of low energy gap has the advantage of low β.

The selection principle that can be drawn the low energy gap dissimilar materials by above-mentioned analysis is satisfied:

β _{R is different}=β _{R together}Exp (△ Eg/KT)≤1

In the present invention, owing to adopted the low energy gap dissimilar materials as source region (S district) or source, drain region (S, D district), make β≤1 of parasitic BJT wherein, thereby can think that parasitic BJT is inoperative, so the present invention has thoroughly eliminated parasitic BJT to MOS device BV from device architecture _DSInfluence, can realize the BV of MOS device _DS=BV _CEO=BV _CBOAnd the CMOSIC that forms by the present invention, also the β because of parasitic BJT can be not being met the condition that produces locking much smaller than 1, and has eliminated latch up effect.

Low energy gap dissimilar materials described in the present invention can be a pseudo-crystal, also can be polycrystalline material.

The preparation of high-dopant concentration low energy gap dissimilar materials among the present invention, for example to the SiMOS device, it can adopt conventional etching technics, with the Si on the S district of conventional MOS device or S, the D zone position carve go after, with chemical vapor deposition (CVD) method deposit SiGe material (can determine wherein Ge component content) thereon according to the concentration of device channel length, channel doping concentration, epitaxial substrate and thickness, simultaneously carry out autodoping phosphorus, arsenic or boron on demand, promptly can be made into required n ⁺Or P ⁺SiGe S district or S, D district; Also can be in the S district of traditional Si MOS device or S, place, D district carry out the Ge ion and inject and carry out high annealing and make the S district of SiGe of high-dopant concentration or S, D district.Its manufacturing process belongs to conventional semiconductor fabrication process, simple, easily realization, and don't increase maybe can reduce chip area.

Several structure provided by the invention is suitable for the MOS device that the various types of substrates material is made such as Si, GaAs and SiC etc.; Also be suitable for various structures backing material such as monocrystal material, epitaxial material, have material of compound buffer layer or the like; It both had been suitable for P ditch MOSFET, also was suitable for N ditch MOSFET, and certainly, it also is suitable for the different integrated circuits be made up of P ditch MOSFET, N ditch MOSFET particularly on the CMOS IC; Simultaneously it also is suitable for all kinds of MOS power devices such as VDMOS, LDMOS, offset gate MOS, RMOS or the like.Only enumerate a few class devices and the CMOS IC that utilize the present invention to make below, as the vertical double diffusion MOHET of P ditch of Fig. 4; As the horizontal double diffusion MOHET of the P ditch of Fig. 5; P ditch offset gate MOHET as Fig. 6; As the P ditch rectangular channel grid MOHET of Fig. 7 with as the basic cell structure of the SiGe source region P trap CMOS IC of Fig. 8.

Utilize following advantage arranged behind the MOHET of the present invention:

At first, make the withstand voltage of MOS device from BV _CEOBring up to BV _CBO, improve approximately 30～50%, this is particularly important to power device, and it means that the device operating voltage improves and the power handling capability enhancing;

The second, second breakdown no longer takes place in the MOS device, and CMOS IC no longer produces latch up effect, and the reliability of device and circuit is strengthened;

The 3rd, (15～200V) power MOS (Metal Oxide Semiconductor) devices owing to worrying that no longer channel length L shortens the too high problem of bringing of parasitic BJT β, can reduce L as far as possible in the scope that technology allows, thereby make the drain current I of device for low pressure especially _D, conducting resistance Ron and mutual conductance g _mObtain the above improvement of an order of magnitude, make the high linear MOS device of manufacturing become possibility simultaneously;

The 4th, saved the source electrode shorting region, saved 10～20% chip area;

The 4th, make the MOS device of S, D symmetry become possibility, this has not only simplified device fabrication, and S, D are interchangeable, for use brings great convenience or the like.

Accompanying drawing and description of drawings

Fig. 1: first kind of MOHET structural representation of the present invention

Among the figure: 1 substrate; The heterogeneous source region of 2 low energy gaps; 3 homogeneity drain regions; 4 channel regions; 6 gate insulation deielectric-coating.

Fig. 2: second kind of structural representation of the present invention (S, D be the MOHET of symmetry fully)

Among the figure: 1 substrate; The heterogeneous source region of 2 low energy gaps; 4 channel regions; The heterogeneous drain region of 5 low energy gaps; 6 gate insulation deielectric-coating.

Fig. 3: the third structural representation of the present invention (a kind of source electrode shorting region area of having saved)

Among the figure: 1 substrate; The heterogeneous source region of 2 low energy gaps; 3 homogeneity drain regions; 4 channel regions; 6 gate insulation deielectric-coating; 7 source electrode shorting regions.

Fig. 4: the 4th kind of structural representation of the present invention (another kind has been saved source electrode shorting region area)

Among the figure: 1 substrate; The heterogeneous source region of 2 low energy gaps; The heterogeneous drain region of 5 low energy gaps; 4 channel regions; 6 gate insulation deielectric-coating; 7 source electrode shorting regions.

Fig. 5: first embodiment of the present invention: silicon P ditch VDMOHET structural representation

Among the figure: 8 P ⁺The Si drain region; 9 extension P ^-The Si drift region; 10 nSi channel regions; 11 P ⁺The SiGe source region; 12 SiO ₂Film; 15 n ⁺Polycrystalline Si.

Fig. 6: second embodiment of the present invention: silicon P ditch LDMOHET structural representation

Among the figure: 8 P ⁺The Si drain region; 10 nSi channel regions; 11 P ⁺The SiGe source region; 12 SiO ₂Film; 13 n ^-The Si substrate; 14 P ^-The Si drift region.

Fig. 7: the 3rd embodiment of the present invention: silicon P ditch offset gate MOHET structural representation

Among the figure: 8 P ⁺The Si drain region; 10 nSi channel regions; 11 P ⁺The SiGe source region; 12 SiO ₂Film; 13 n ^-The Si substrate; 14 P ^-The Si drift region.

Fig. 8: the 4th embodiment of the present invention: silicon P ditch RMOHET structural representation

Among the figure: 8 P ⁺The Si drain region; 9 extension P ^-The Si substrate; 10 nSi channel regions; 11 P ⁺The SiGe source region; 12 SiO ₂Film; 15 n ⁺Polysilicon.

Fig. 9: the 5th embodiment of the present invention: SiGe source region CMOS IC basic cell structure schematic diagram

Among the figure: 12 SiO ₂Film; 13 n ^-The Si substrate; 16 P traps; 17 NMOS n ⁺The Si source region; 18 NMOS n ⁺The Si drain region; 19 NMOS P ⁺Si source electrode shorting region; 20 NMOS channel regions; 21 PMOS P ⁺The SiGe source region; 22 PMOS P ⁺The Si drain region; 23 PMOS n ⁺Si source electrode shorting region; 24 PMOS channel regions.

The embodiment that provides below in conjunction with Fig. 5～9 further specifies the present invention:

Fig. 5 is first embodiment P ditch VDMOHET structural representation of the present invention, and it is at P ^-/ P ⁺The P of epitaxy Si substrate ^-The near surface of Si drift region 9 is provided with heterogeneous P ⁺ SiGe source region 11, and nSi channel region 10 is arranged, the P of epitaxy Si substrate at its adjacent ⁺Si is formed with SiO as homogeneity drain region 8 on the Si surface beyond surface, described part source region and the source region ₂Film 12, the SiO above 11 surfaces, described source region, channel region 10 ₂Film surface and 8 surfaces, drain region are formed with the good electrode of electric conductivity, and also the corresponding S of drawing, G, the D utmost point constitute.It has saved the n of traditional VDMOS ⁺The shorting region of Si source electrode, thus chip area saved; Owing to adopted the heterogeneous SiGe of low energy gap source region, from device architecture, thoroughly eliminated parasitic BJT simultaneously to BV _DSInfluence, improved the operating voltage of device and power handling capability etc.

Fig. 6 is second embodiment of the present invention: P ditch LDMOHET structural representation, it is at n ^-One deck P is arranged on the Si substrate 13 ^- Si drift region 14, being separated by on surface, described 14 district is provided with P ⁺SiGe source region 11 and P ⁺Si drain region 8 is at described P ⁺The adjacent in SiGe source region 11 has nSi channel region 10, is formed with SiO on the Si surface outside described part source region and surface, drain region and source region and the drain region ₂Film 12, the SiO above 11 surfaces, described source region, channel region 10 ₂Surface and 8 surfaces, drain region are formed with the good electrode of electric conductivity, and also the corresponding S of drawing, G, the D utmost point constitute.It has equally also saved the source electrode shorting region among traditional LDMOS, thereby has saved chip area; Simultaneously owing to adopted the heterogeneous P of low energy gap ⁺The SiGe source region makes on structure and has thoroughly eliminated parasitic BJT to BV _DSInfluence, thereby brought foregoing series of advantages.

Fig. 7 is the 3rd embodiment of the present invention: P ditch offset gate MOHET structural representation.It is at n ^-Be separated by on the surface of Si substrate 13 and be provided with P ⁺ SiGe source region 11 and P ⁺Si drain region 8, described 11,8 liang of intervals are grown and the PSi drift region 14 of book every one, and described 11,14 liang of intervals are channel region 10, are formed with SiO on the Si surface beyond described part source region and surface, drain region and source region and the drain region ₂Film 12, the SiO above 11 surfaces, source region, channel region 10 ₂Film surface and 8 surfaces, drain region are formed with the good electrode of electric conductivity, and also the corresponding S of drawing, G, the D utmost point constitute.Because it has adopted the heterogeneous SiGe of low energy gap source region, makes on structure and has thoroughly eliminated parasitic BJT to BV _DSInfluence, thereby brought foregoing series of advantages.

Fig. 8 is the 4th embodiment of the present invention: P ditch RMOHET structural representation.It is at P ^-/ P ⁺One deck nSi channel region 10 is arranged on the low concentration drift region 9 of epitaxy Si substrate, and also have one deck P thereon ⁺SiGe source region 11 has a rectangular channel in described 9,10,11 3 districts, SiO is arranged on the cell wall ₂12, be filled with n in the groove ⁺Polysilicon 15, the P of epitaxy Si substrate ⁺Si is as drain region 8, and Si outside surface, described part source region and source region and polycrystalline Si surface are formed with SiO ₂ Film 12, and in the source region 11 surfaces, rectangular channel top surface and 8 surfaces, drain region are formed with the good electrode of the electric conductivity also corresponding S of drawing, G, the D utmost point.It has saved the source electrode shorting region of traditional RMOS equally, has saved chip area; Equally also, make on structure and thoroughly eliminated parasitic BJT BV owing to adopted the heterogeneous SiGe of low energy gap source region _DSInfluence.

Fig. 9 is the 5th embodiment of the present invention: SiGe source region P trap CMOS IC basic cell structure schematic diagram.It is made up of the P ditch MOSFET and the N ditch MOSFET of a pair of complementation, and its concrete structure is: its N ditch MOSFET is that a face of nSi substrate 13 is provided with P trap 16, and being separated by on the surface in the P trap is provided with NMOSn ⁺Si source region 17 and n ⁺ Si drain region 18, described 17,18 liang of intervals are channel region 20, at described n ⁺The adjacent in Si source region 17 has P ⁺Si source electrode shorting region 19, described 17,19 liang of districts form source area, and the Si surface beyond described part source area and surface, drain region and source area and drain region is formed with SiO ₂ Film 12, the SiO above described source area surface, channel region ₂Surface and 18 surfaces, drain region are formed with the good electrode of the electric conductivity also corresponding NMOS of drawing S, G, the D utmost point; Its P ditch MOSFET is on the nSi substrate 13 and P trap 16 same surfaces, and being separated by in a distance, trap external distance trap edge is provided with P ⁺Si drain region 22 and P ⁺ SiGe source region 21, described 22,21 liang of intervals are channel region 24, at described P ⁺The adjacent in SiGe source region 21 has n ⁺Si source electrode shorting region 23, described 21 and 23 liang of districts form source area, are formed with SiO on the Si surface beyond described part source area and surface, drain region and source area and the drain region ₂Film 12 is from described source area surface, the SiO of channel region 24 tops ₂Film surface and 22 surfaces, drain region are formed with the good electrode of the electric conductivity also corresponding PMOS of drawing S, G, the D utmost point.Because the heterogeneous SiGe of low energy gap has been adopted in the source region of its P ditch MOSFET, CMOS IC makes the condition β that produces locking _Npn* β _Pnp〉=1 is not being met, and has thoroughly eliminated latch up effect from circuit structure, has strengthened the reliability of circuit, and device size particularly channel length L can further dwindle, therefore, the performance of circuit and integrated level are expected further raising.Also be suitable for n trap or two trap CMOS IC with spline structure.

Claims (11)

1, a kind of MOHET and IC is characterized in that its source region adopted the low energy gap dissimilar materials, it comprises: being separated by on a face of substrate (1) is provided with and heterogeneous source region of the high-dopant concentration of its transoid (2) and high-dopant concentration homogeneity drain region (3), described (2), between (3) two districts channel region (4), on described part source region and surface, drain region and channel region (4) surface, be formed with gate insulation deielectric-coating (6), from surface, described source region (2), channel region (4) gate insulation deielectric-coating surface, top and surface, drain region (3) are formed with good electrode of electric conductivity and the corresponding S of drawing, G, the D utmost point.

2, a kind of MOHET and IC is characterized in that its source region and drain region all adopted the low energy gap dissimilar materials, it comprises: being separated by on a face of substrate (1) is provided with heterogeneous source region of high-dopant concentration low energy gap (2) and the heterogeneous drain region of high-dopant concentration low energy gap (5) with its transoid, described (2), between (5) two districts channel region (4), on described part source region and surface, drain region and channel region (4) surface be formed with gate insulation deielectric-coating (6), be formed with good electrode of electric conductivity and the corresponding S of drawing from gate insulation deielectric-coating surface, top, described source region (2) surface channel districts (4) and surface, drain region (5), G, the D utmost point constitutes S, D is the MOHET of symmetry fully.

3, a kind of MOHET and IC is characterized in that its source region adopted the low energy gap dissimilar materials, it comprises: being separated by on a face of substrate (1) is provided with and heterogeneous source region of the high-dopant concentration of its transoid (2) and high-dopant concentration homogeneity drain region (3), described (2), between (3) two districts channel region (4), with the heterogeneous source region of described high-dopant concentration low energy gap (2) adjacent high-dopant concentration homogeneity source electrode shorting region (7) with its transoid is being arranged, on described part source region and surface, drain region and channel region (4) surface be formed with gate insulation deielectric-coating (6), from described source region (2) and source electrode shorting region (7) surface, channel region (4) gate insulation deielectric-coating (6) surface, top and surface, drain region (3) are formed with good electrode of electric conductivity and the corresponding S of drawing, G, the D utmost point has constituted a kind of MOHET that saves source electrode shorting region area occupied.

4, a kind of MOHET and IC is characterized in that it comprises: being separated by on a face of substrate (1) is provided with heterogeneous source region of high-dopant concentration low energy gap (2) and the heterogeneous drain region of high-dopant concentration low energy gap (5) with its transoid, described (2), between (5) two districts channel region (4), with the heterogeneous source region of described high-dopant concentration low energy gap (2) adjacent high-dopant concentration homogeneity source electrode shorting region (7) with its transoid is being arranged, on described part source region and surface, drain region surface channel district (4), be formed with gate insulation deielectric-coating (6), from described source region (2) and source electrode shorting region (7) surface, channel region (4) gate insulation deielectric-coating surface, top and surface, drain region (5) are formed with good electrode of electric conductivity and the corresponding S of drawing, G, the D utmost point has constituted the MOHET of another kind of saving source electrode shorting region area occupied.

5, it is characterized in that according to the described MOHET of claim 1～4 and IC the selection principle of the low energy gap dissimilar materials that described source region (2), drain region (5) are used should satisfy:

β _{R is different}=β _{R together}Exp (△ Eg/KT)≤1

6, it is characterized in that according to described MOHET of claim 1～4 and IC the low energy gap dissimilar materials that described source region (2), drain region (5) are adopted is:

(1) pseudo-crystal material;

(2) polycrystalline material.

7, MOHET according to claim 1 and IC is characterized in that described P ditch VDMOHET comprises: at P ^-/ P ⁺Epitaxy Si substrate P ^-The surface in Si district (9) is provided with P ⁺SiGe source region (11), and nSi channel region (10), the P of epitaxy Si substrate are arranged at its adjacent ⁺Si is drain region (8), on surface, described part source region and the source region beyond the Si surface be formed with SiO ₂Film (12), described source region (11) surface, channel region (10)) top SiO ₂Film surface and surface, drain region (8) are formed with the good electrode of the electric conductivity also corresponding S of drawing, G, the D utmost point.

8, MOHET according to claim 1 and IC is characterized in that described P ditch LDMOHET comprises: at n ^-The Si substrate has one deck P on (13) ^-Si drift region (14), being separated by on surface, described (14) district is provided with P ⁺SiGe source region (11) and P ⁺Si drain region (8) is at described P ⁺The adjacent in SiGe source region (11) has nSi channel region (10), is formed with SiO on the Si surface outside described part source region and surface, drain region and source region and the drain region ₂Film (12), the SiO above described source region (11) surface, channel region (10) ₂Surface and surface, drain region (8) are formed with the good electrode of the electric conductivity also corresponding S of drawing, G, the D utmost point.

9, MOHET according to claim 1 and IC is characterized in that: described P ditch offset gate MOHET comprises: at n ^-Be separated by on the surface of Si substrate (13) and be provided with P ⁺SiGe source region (11) and P ⁺Si drain region (8), grow and thin PSi drift region (14) across one in described (11), (8) two intervals, described (11) and (14) two intervals are channel region (10), are formed with SiO on the Si surface outside described part source region and surface, drain region and source region and the drain region ₂Film (12), the SiO above described source region (11) surface, channel region (10) ₂Surface and drain region (8) surface is formed with the good electrode of the electric conductivity also corresponding S of drawing, G, the D utmost point.

10, MOHET according to claim 1 and IC is characterized in that described P ditch RMOHET comprises: at P ^-/ P ⁺The low concentration region P of epitaxy Si substrate ^-One deck nSi channel region (10) is arranged on the Si (9), and also have one deck P thereon ⁺SiGe source region (11) has a rectangular channel in described (9), (10), (11) three districts, SiO is arranged on the cell wall ₂Film (12) is filled with n in the groove ⁺Polysilicon (15), the P of epitaxy Si substrate ⁺Si is as drain region (8), on surface, described part source region and the Si surface beyond the source region be formed with SiO ₂Film (12), and in the source region (11) surface, surface, rectangular channel top and surface, drain region (8) are formed with the good electrode of electric conductivity and the corresponding S of drawing, G, the D utmost point.

11, MOHET according to claim 1 and IC is characterized in that described SiGe source region P trap CMOS IC elementary cell comprises: the P ditch MOSFET of a pair of complementation and N ditch MOSFET, its N ditch MOSFET comprises: a face of nSi substrate (13) is provided with P trap (16), and being separated by on the surface in the P trap is provided with n ⁺Si source region (17) and n ⁺Si drain region (18), described (17), (18) two intervals are channel region (20), at described n ⁺The adjacent in Si source region (17) has P ⁺Si source electrode shorting region (19), described (17), (19) two districts form source area, and the Si surface beyond described part source area and surface, drain region and source area and drain region is formed with SiO ₂Film (12) is on described source area surface, the SiO of channel region (20) top ₂Surface and surface, drain region (18) are formed with the good electrode of the electric conductivity also corresponding S of drawing, G, the D utmost point; Its P ditch MOSFET comprises: nSi substrate (13) go up and the same surface of P trap (16) on, being separated by in a distance, trap external distance trap edge is provided with P ⁺Si drain region (22) and P ⁺SiGe source region (21), described (22) and (21) two intervals are channel region (24), at described P ⁺The adjacent in SiGe source region (21) has n ⁺Si source electrode shorting region (23), described (21) and (23) two districts form source area, and the Si surface beyond described part source area and surface, drain region and source area and drain region is formed with SiO ₂Film (12) is from described source area surface, the SiO of channel region (24) top ₂Film surface and surface, drain region (22) are formed with the good electrode of the electric conductivity also corresponding S of drawing, G, the D utmost point.

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