CN116529851A

CN116529851A - Epitaxial substrate, preparation method thereof and semiconductor wafer

Info

Publication number: CN116529851A
Application number: CN202080107580.8A
Authority: CN
Inventors: 赫然; 丁瑶; 刘静遐; 焦慧芳
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2023-08-01
Also published as: WO2022120825A1

Abstract

The epitaxial substrate, the preparation method thereof, the semiconductor wafer and the preparation method of the semiconductor device can solve the problem that epitaxial materials have defects due to lattice mismatch and/or thermal mismatch between the epitaxial materials and the epitaxial substrate, and are beneficial to reducing the cost of the semiconductor device. The preparation method of the epitaxial substrate comprises the following steps: a first substrate and a second substrate are provided, wherein the lattice constant of the second substrate matches the lattice constant of the epitaxial material to be grown. A damaged layer is formed inside the second substrate such that the second substrate is separated by the damaged layer into a base and a lattice matching layer. Forming a peeling layer on the first substrate, and bonding a lattice matching layer of the second substrate on one side of the peeling layer, which is away from the first substrate; alternatively, a release layer is formed over the lattice matching layer, and the first substrate is bonded to a side of the release layer facing away from the lattice matching layer. The damaged layer and the substrate are removed and the surface of the lattice matching layer facing away from the release layer is polished. The polished surface of the lattice matching layer is used to grow epitaxial material.

Description

Epitaxial substrate, preparation method thereof and semiconductor wafer

Technical Field

The present disclosure relates to the field of electronic technology, and in particular, to an epitaxial substrate, a method for manufacturing the epitaxial substrate, a semiconductor wafer, and a method for manufacturing a semiconductor device.

Background

Modern semiconductor devices and integrated circuits often employ epitaxial materials as the base material from which they are fabricated. The epitaxial material is high-quality monocrystalline material with specific material characteristics and thickness, which is obtained by regularly and directionally growing atoms or molecules of gallium nitride, silicon carbide or silicon and other materials on an epitaxial substrate under certain process conditions. However, epitaxial growth of low cost and high quality epitaxial materials, particularly gallium nitride layers, has been a difficulty in research in the semiconductor field.

By way of example, a substrate commonly used in epitaxially growing a gallium nitride layer is a heteroepitaxial substrate, such as a silicon carbide substrate or a sapphire substrate. In the process of epitaxially growing a gallium nitride layer, an aluminum nitride (AlN) nucleation layer is prepared on a heteroepitaxial substrate, and then an organic metal chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD for short) is adopted to grow a monocrystalline gallium nitride layer. However, the heteroepitaxial substrate may be made of limited materials, and the lattice constant and/or thermal expansion coefficient of the heteroepitaxial substrate may be easily different from the corresponding parameters of the gallium nitride layer, so that the lattice mismatch and/or thermal mismatch of the epitaxial material may occur. For example, when a silicon carbide substrate is selected for the heteroepitaxial substrate, the silicon carbide substrate may have a better lattice match with the gallium nitride layer, but also have a larger thermal mismatch than the sapphire substrate. Therefore, the gallium nitride layer prepared by the method is easy to have more dislocation defects and larger internal stress due to lattice mismatch and/or thermal mismatch problems, so that the epitaxial growth quality of the gallium nitride layer is poor.

Furthermore, high quality epitaxial substrates are costly. In addition, in the process of manufacturing a semiconductor device or an integrated circuit using a gallium nitride layer, the back side of an epitaxial substrate on which the gallium nitride layer is grown is typically subjected to destructive thinning to obtain a reasonable thickness. Most of the material of the epitaxial substrate is wasted, and the process cost caused by thinning the epitaxial substrate is increased, so that the production cost of the semiconductor device or the integrated circuit is high.

Disclosure of Invention

The embodiment of the disclosure provides an epitaxial substrate, a preparation method thereof, a semiconductor wafer and a preparation method of a semiconductor device, which not only can solve the problem that the epitaxial material is easy to generate defects due to lattice mismatch and/or thermal mismatch between the epitaxial substrate and the epitaxial material, but also can solve the problem that the semiconductor device or integrated circuit has high cost due to destructive thinning of the epitaxial substrate when the semiconductor device or integrated circuit is prepared.

In one aspect, some embodiments of the present disclosure provide a method for preparing an epitaxial substrate. The preparation method of the epitaxial substrate comprises the following steps.

First, a first substrate and a second substrate are provided, wherein the lattice constant of the second substrate is matched to the lattice constant of the epitaxial material to be grown.

Next, a damaged layer is formed inside the second substrate such that the second substrate is partitioned by the damaged layer into a base and a lattice matching layer.

Then, forming a peeling layer on the first substrate, bonding a lattice matching layer of the second substrate on a side of the peeling layer facing away from the first substrate; alternatively, a release layer is formed over the lattice matching layer, and the first substrate is bonded to a side of the release layer facing away from the lattice matching layer.

Finally, the damaged layer and the substrate are removed and the surface of the lattice matching layer facing away from the release layer is polished. Here, the polished surface of the lattice matching layer is used to generate epitaxial material, which is the epitaxially grown side of the epitaxial substrate. Thereby obtaining an epitaxial substrate.

In the embodiment of the disclosure, the lattice matching layer is prepared by using the second substrate with the lattice constant matched with that of the epitaxial material to be grown, and the lattice matching layer is bonded on the first substrate through the stripping layer, so that a composite substrate can be obtained as the epitaxial substrate. The preparation method of the epitaxial substrate is simple and easy to operate.

And, in the epitaxial substrate obtained by the aforementioned preparation method, the lattice constant of the lattice matching layer is matched with the lattice constant of the epitaxial material to be grown. Therefore, the polished surface of the lattice matching layer is used as an epitaxial growth surface of the epitaxial substrate, and the problem of lattice mismatch between the epitaxial substrate and the epitaxial material can be effectively solved. On the basis, the first substrate is used for bearing the stripping layer and the lattice matching layer, and is positioned on the back side of the epitaxial growth face of the lattice matching layer, so that the lattice constant of the first substrate can be free from the limitation of the lattice constant of the epitaxial material. So that the first substrate may have more material choices. Since the thermal expansion coefficient of the epitaxial substrate is determined by the combination of the layer structures. Therefore, on the premise of ensuring that the lattice constant of the lattice matching layer is matched with that of the epitaxial material, the first substrate is reasonably selected according to the thermal expansion coefficient, and the thermal expansion coefficient of the epitaxial substrate can be influenced by the thermal expansion coefficient of the first substrate, so that the thermal expansion coefficient of the epitaxial substrate is matched with that of the epitaxial material to be grown, and the problem of thermal mismatch between the epitaxial substrate and the epitaxial material is effectively solved.

By growing the epitaxial material on the epitaxial growth surface of the epitaxial substrate prepared by the embodiment of the disclosure, the lattice constant and the thermal expansion coefficient which are matched between the epitaxial material and the epitaxial substrate can be ensured, so that defects of the epitaxial material due to lattice mismatch and/or thermal mismatch are avoided, and the growth quality of the epitaxial material is improved.

Further, in embodiments of the present disclosure, the release layer is disposed between the lattice matching layer and the first substrate, for example, formed on a surface of the first substrate that is adjacent to the lattice matching layer, or formed on a surface of the lattice matching layer that is adjacent to the first substrate. In the process of preparing a semiconductor device or an integrated circuit by using the epitaxial substrate, if the epitaxial substrate needs to be thinned, the lattice matching layer and the first substrate are separated by peeling the peeling layer, so that the thinning of the epitaxial substrate can be realized. The first substrate can be selected without the limitation of the lattice constant of the epitaxial material, so that the first substrate can be selected with lower cost. On this basis, the separated first substrate can also be reused to prepare a new epitaxial substrate. Therefore, the first substrate does not need to be destructively thinned, and material waste can be avoided. Therefore, the first substrate and the lattice matching layer can be separated when needed by utilizing the stripping layer, so that the thinning of the epitaxial substrate is realized in a low-cost mode, and the problem of high cost caused by destructive thinning of the epitaxial substrate in the preparation process of a semiconductor device or an integrated circuit is effectively solved.

In some embodiments, the epitaxial substrate further comprises a bonding layer. The epitaxial substrate is prepared according to the positional relationship between the bonding layer, the lattice matching layer and the first substrate as follows.

Optionally, a release layer is formed on one side surface of the first substrate, and a bonding layer is disposed between the release layer and the lattice matching layer. Accordingly, after forming the peeling layer on the first substrate, the manufacturing method further includes: a bonding layer is formed on a surface of the release layer facing away from the first substrate. Bonding the lattice matching layer of the second substrate on the side of the peeling layer facing away from the first substrate comprises: a lattice matching layer of a second substrate is bonded to a surface of the bonding layer facing away from the release layer.

Optionally, a release layer is formed on one side surface of the first substrate, and a bonding layer is disposed between the release layer and the lattice matching layer. The bonding layer comprises a first bonding layer and a second bonding layer, wherein the first bonding layer is formed on the surface of the stripping layer, which is away from the first substrate, and the second bonding layer is formed on the lattice matching layer. Accordingly, after forming the peeling layer on the first substrate, the manufacturing method further includes: a first bonding layer is formed on a surface of the release layer facing away from the first substrate and a second bonding layer is formed on the lattice matching layer of the second substrate. Bonding the lattice matching layer of the second substrate on the side of the peeling layer facing away from the first substrate comprises: the first bonding layer and the second bonding layer are bonded.

Optionally, a release layer is formed on one side surface of the lattice matching layer, and a bonding layer is disposed between the release layer and the first substrate. Accordingly, after forming the peeling layer on the lattice matching layer, the manufacturing method further includes: a bonding layer is formed on a surface of the release layer facing away from the lattice matching layer. Bonding the first substrate on the side of the peeling layer facing away from the lattice matching layer comprises: a first substrate is bonded to a surface of the bonding layer facing away from the release layer.

Optionally, a release layer is formed on one side surface of the lattice matching layer, and a bonding layer is disposed between the release layer and the first substrate. The bonding layer comprises a first bonding layer and a second bonding layer, wherein the first bonding layer is formed on one side surface of the first substrate, and the second bonding layer is formed on the surface of the stripping layer, which is away from the lattice matching layer. Accordingly, after forming the peeling layer on the lattice matching layer, the manufacturing method further includes: a first bonding layer is formed on a surface of the first substrate and a second bonding layer is formed on a surface of the release layer facing away from the lattice matching layer. Bonding the first substrate on the side of the peeling layer facing away from the lattice matching layer comprises: the first bonding layer and the second bonding layer are bonded.

In some embodiments, a process for forming a release layer includes: a hydride vapor phase epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or a pulsed laser deposition process. The chemical vapor deposition process comprises: an organometallic chemical vapor deposition process.

In addition, the formation process of the corresponding release layer may be the same or different depending on the release layer material.

Optionally, the release layer is a gallium nitride layer. The forming process of the stripping layer comprises the following steps: a hydride vapor phase epitaxy process, an organometallic chemical vapor deposition process, or a physical vapor deposition process.

Optionally, the release layer is a gallium oxide layer or a zinc oxide layer. A process for forming a release layer, comprising: a physical vapor deposition process, a pulsed laser deposition process, or an organometallic chemical vapor deposition process.

Optionally, the release layer is a porous silicon layer or a porous silicon dioxide layer. A process for forming a release layer, comprising: a physical vapor deposition process or a chemical vapor deposition process.

In another aspect, some embodiments of the present disclosure provide an epitaxial substrate that may be obtained by the preparation method in some of the foregoing embodiments. The epitaxial substrate includes: a first substrate, a lattice matching layer, and a release layer between the first substrate and the lattice matching layer. The lattice constant of the lattice matching layer matches the lattice constant of the epitaxial material. The surface of the lattice matching layer facing away from the release layer is used for growing epitaxial material, i.e. the surface of the lattice matching layer facing away from the release layer is an epitaxial growth face of the epitaxial material. The release layer is capable of peeling under a triggering condition to cause the first substrate and the lattice matching layer to separate.

In the embodiment of the disclosure, the epitaxial substrate is a composite substrate, and has the same advantages as those of the epitaxial substrate prepared by the preparation method, and will not be described herein.

In some embodiments, the epitaxial substrate further comprises a bonding layer.

Optionally, a release layer is formed on one side surface of the first substrate, and a bonding layer is disposed between the release layer and the lattice matching layer. The lattice matching layer is bonded to the peeling layer through the bonding layer. According to the embodiment of the disclosure, the bonding layer is arranged between the stripping layer and the lattice matching layer, and the lattice matching layer and the stripping layer are bonded by utilizing the bonding layer, so that the bonding effect between the lattice matching layer and the stripping layer can be improved, and the bonding process difficulty between the lattice matching layer and the stripping layer can be reduced.

Optionally, a release layer is formed on one side surface of the lattice matching layer, and a bonding layer is disposed between the release layer and the first substrate. The first substrate is bonded to the release layer through the bonding layer. According to the embodiment of the disclosure, the bonding layer is arranged between the stripping layer and the first substrate, and the first substrate and the stripping layer are bonded by utilizing the bonding layer, so that the bonding effect between the first substrate and the stripping layer can be improved, and the bonding process difficulty between the first substrate and the stripping layer can be reduced.

In some embodiments, the bonding layer includes a first bonding layer and a second bonding layer.

Optionally, a release layer is formed on the first substrate. The first bonding layer is formed on a surface of the release layer facing away from the first substrate. The second bonding layer is formed on the lattice matching layer. The first bonding layer and the second bonding layer are bonded. In the embodiment of the disclosure, a peeling layer and a first bonding layer are formed on the surface of a first substrate in a laminated manner, and a second bonding layer is formed on the surface of a lattice matching layer. Thus, the first bonding layer and the second bonding layer are used for bonding, the bonding effect between the lattice matching layer and the first substrate can be further improved, and the bonding process difficulty between the lattice matching layer and the first substrate can be further reduced.

Optionally, the first bonding layer is formed on the first substrate. The release layer is formed on the lattice matching layer. The second bonding layer is formed on a surface of the release layer facing away from the lattice matching layer. The first bonding layer and the second bonding layer are bonded. In the embodiment of the disclosure, the peeling layer and the second bonding layer are formed on the surface of the lattice matching layer in a laminated manner, and the first bonding layer is formed on the surface of the first substrate. Thus, the first bonding layer and the second bonding layer are used for bonding, the bonding effect between the lattice matching layer and the first substrate can be further improved, and the bonding process difficulty between the lattice matching layer and the first substrate can be further reduced.

In some embodiments, the material of the bonding layer may be selected according to practical requirements, for example, a metal material or a non-metal material.

In some examples, the material of the bonding layer is a metallic material comprising: titanium, tantalum, chromium, nickel, tungsten or gold. Thereby facilitating bonding between the lattice matching layer and the first substrate at lower process temperature conditions.

In other examples, the material of the bonding layer is a non-metallic material comprising: spin-on glass, silicon oxide, silicon nitride or silicon oxynitride. Thereby facilitating the preparation of the bonding layer and enabling the bonding layer to have light transmission characteristics.

In some embodiments, the lattice matching layer has a thickness less than a thickness of the first substrate. Under the condition that the thickness of the first substrate is large, the thermal expansion coefficient of the first substrate is matched with that of the epitaxial material, so that the thermal expansion coefficient of the epitaxial substrate is favorably matched with that of the epitaxial material.

In some embodiments, the material of the release layer is different from the material of the first substrate. Therefore, the first substrate and the lattice matching layer can be effectively separated, and the good separation effect can be achieved.

In addition, the epitaxial substrate adopts the composite structure, so that the first substrate can be selected without being limited by the lattice constant of the epitaxial material. That is, the material of the first substrate may be more selected, e.g., a low cost polycrystalline material, while ensuring that the epitaxial substrate can grow high quality epitaxial material. Illustratively, the material of the first substrate comprises: single crystal silicon carbide, polycrystalline silicon carbide, single crystal sapphire, polycrystalline sapphire, single crystal gallium nitride, polycrystalline gallium nitride, single crystal gallium arsenide, polycrystalline gallium arsenide, single crystal silicon, polycrystalline silicon, single crystal aluminum nitride, polycrystalline aluminum nitride, single crystal gallium oxide, or polycrystalline gallium oxide.

Optionally, on ensuring that the material of the release layer is different from the material of the first substrate, the material of the release layer comprises: zinc oxide, gallium nitride, gallium oxide, porous silicon or porous silicon dioxide.

The material of the lattice matching layer is related to the epitaxial material to be grown. Alternatively, the material of the lattice matching layer comprises monocrystalline silicon carbide, monocrystalline gallium nitride, monocrystalline aluminum nitride, monocrystalline silicon, or monocrystalline gallium oxide.

In yet another aspect, some embodiments of the present disclosure provide a semiconductor wafer. The semiconductor wafer includes: the epitaxial substrate of some embodiments above, and an epitaxial layer grown on an epitaxially grown face of the lattice matching layer.

Optionally, the lattice matching layer is a monocrystalline gallium nitride layer or a monocrystalline aluminum nitride layer, and the epitaxial layer is a monocrystalline gallium nitride layer.

Optionally, the lattice matching layer is a monocrystalline silicon carbide layer and the epitaxial layer is a monocrystalline silicon carbide layer.

Optionally, the lattice matching layer is a monocrystalline silicon layer, and the epitaxial layer is a monocrystalline silicon layer.

Optionally, the lattice matching layer is a monocrystalline silicon carbide layer or a monocrystalline silicon layer, and the epitaxial layer includes an aluminum nitride nucleation layer and a monocrystalline gallium nitride layer stacked in a direction away from the lattice matching layer.

In the embodiment of the disclosure, the epitaxial layer is grown on the epitaxial growth surface of the epitaxial substrate, and the semiconductor wafer with the high-quality epitaxial layer can be obtained to prepare a semiconductor device or an integrated circuit by using the semiconductor wafer.

In yet another aspect, some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, as follows.

First, a semiconductor wafer according to some of the embodiments described above is provided, and a device layer is prepared on an epitaxial layer of the semiconductor wafer, the device layer including at least a portion of a layer of semiconductor devices.

And secondly, providing a supporting substrate, and bonding the supporting substrate on the surface of the device layer, which is away from the epitaxial layer.

Optionally, bonding the support substrate on a surface of the device layer facing away from the epitaxial layer, including: and forming a temporary bonding layer on the support substrate, and bonding the temporary bonding layer on the surface of the device layer, which is away from the epitaxial layer. Accordingly, removing the support substrate includes: and removing the temporary bonding layer and the support substrate by at least one process selected from laser treatment, heat treatment, chemical treatment, etching, grinding or polishing.

Then, the peeling layer and the first substrate are peeled from the lattice matching layer.

Here, the peeling process of the peeling layer is related to the material of the peeling layer.

Optionally, the release layer is a gallium nitride layer. The release layer may be peeled off by a laser lift-off process.

Optionally, the release layer is a gallium oxide layer or a zinc oxide layer. The release layer may be peeled off by a chemical peeling process.

Optionally, the release layer is a porous silicon layer or a porous silicon dioxide layer. The peeling layer may be peeled off by a chemical peeling process or a water knife cutting process.

Thereafter, the back surface of the lattice matching layer is polished. The back side of the lattice matching layer is the surface facing away from the epitaxial layer.

Optionally, the semiconductor wafer further includes a bonding layer disposed between the exfoliation layer and the lattice matching layer. The method of manufacturing the semiconductor device after peeling the peeling layer and the first substrate and before polishing the back surface of the lattice matching layer, further includes: and polishing to remove the bonding layer.

Then, a metal layer is formed on the back surface of the lattice matching layer.

Finally, the support substrate is removed. Thereby obtaining a semiconductor device.

In the embodiment of the disclosure, after the device layer is prepared on the semiconductor wafer, the first substrate and the stripping layer in the semiconductor wafer can be effectively stripped by virtue of the support substrate, and the metal layer is formed on the back surface of the lattice matching layer, so that the preparation of the semiconductor device is completed, the operation is simple and convenient, and the improvement of the production efficiency is facilitated.

In yet another aspect, some embodiments of the present disclosure further provide a method of manufacturing a semiconductor device, as follows.

First, a semiconductor wafer according to any of the embodiments above is provided, and a device layer comprising at least part of the layers of the semiconductor device or integrated circuit is prepared on an epitaxial layer of the semiconductor wafer.

Then, the peeling layer and the first substrate are peeled from the lattice matching layer. And removing the lattice matching layer to expose the epitaxial layer.

Optionally, the semiconductor wafer further includes a bonding layer disposed between the exfoliation layer and the lattice matching layer. After the peeling layer and the first substrate are peeled off, before the lattice matching layer is removed, the method for manufacturing a semiconductor device further includes: and removing the bonding layer.

Providing a third substrate, and bonding the epitaxial layer on the third substrate; or, forming a third substrate on a surface of the epitaxial layer facing away from the device layer.

Here, the third substrate is used to carry the epitaxial layer and the device layer in the semiconductor device, and the third substrate may be selected from substrates having a higher thermal conductivity, a higher resistance value, and a lower cost, so as to ensure that the semiconductor device has excellent heat dissipation capability and electrical properties, and lower cost. Optionally, the third substrate is: a silicon carbide substrate, a diamond substrate, or a silicon substrate.

Optionally, a metal layer is formed on the back side of the third substrate. The back side of the third substrate is its surface facing away from the epitaxial layer.

In the embodiment of the disclosure, after the device layer is prepared on the semiconductor wafer, the epitaxial substrate in the semiconductor wafer can be effectively removed by means of the support substrate, so that the substrate is bonded or prepared on the back surface of the epitaxial layer, the preparation of the semiconductor device is completed, the operation is simple and convenient, and the production efficiency is improved.

Drawings

In order to more clearly illustrate the technical solutions of some embodiments of the present disclosure, the drawings that are required to be used in the descriptions of some embodiments will be briefly introduced below, and it is apparent that the drawings in the following descriptions are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings for those of ordinary skill in the art.

Fig. 1 is a schematic diagram of the structure of an epitaxial substrate in accordance with some embodiments;

fig. 2 is a schematic diagram of the structure of another epitaxial substrate in accordance with some embodiments;

fig. 3 is a schematic diagram of the structure of yet another epitaxial substrate in accordance with some embodiments;

fig. 4 is a schematic structural view of yet another epitaxial substrate in accordance with some embodiments;

Fig. 5 is a schematic diagram of the structure of yet another epitaxial substrate in accordance with some embodiments;

fig. 6 is a schematic diagram of a method of preparing an epitaxial substrate shown in fig. 1;

fig. 7 is a schematic diagram of a method of preparing an epitaxial substrate shown in fig. 2;

fig. 8 is a schematic diagram of a method of preparing an epitaxial substrate shown in fig. 3;

fig. 9 is a schematic diagram of a method of preparing an epitaxial substrate shown in fig. 4;

fig. 10 is a schematic view of a method of preparing an epitaxial substrate shown in fig. 5;

FIG. 11 is a schematic diagram of a semiconductor wafer according to some embodiments;

FIG. 12 is a schematic diagram of another semiconductor wafer in accordance with some embodiments;

FIG. 13 is a schematic structural view of yet another semiconductor wafer in accordance with some embodiments;

FIG. 14 is a schematic diagram of a structure of yet another semiconductor wafer in accordance with some embodiments;

fig. 15 is a schematic diagram of a method of fabricating a semiconductor device according to some embodiments;

fig. 16 is a schematic diagram of a transistor structure according to some embodiments;

fig. 17 is a schematic diagram of a structure of a semiconductor device according to some embodiments;

fig. 18 is a schematic diagram of a structure of another semiconductor device in accordance with some embodiments;

FIG. 19 is a schematic diagram of bonding a support substrate to a device layer according to one embodiment;

fig. 20 is a schematic diagram of another method of fabricating a semiconductor device according to some embodiments;

fig. 21 is a schematic structural diagram of another semiconductor device in accordance with some embodiments.

Reference numerals:

a 100-epitaxial substrate; 110-a first substrate; 120-a second substrate;

121-a substrate; 122-a damaged layer; 123-a lattice matching layer;

130-a release layer; 140-a bonding layer; 141-a first bonding layer;

142-a second bonding layer; 200-semiconductor wafer; 210-an epitaxial layer;

1000-a semiconductor device; 1001-device layer; 1002-supporting a substrate;

1003-metal layer; 1004-a third substrate; 300-a semiconductor layer;

301 a channel layer; 302-a barrier layer; 400-passivation layer;

501-grid; 502-source; 503-drain;

600-metal pattern; 700-temporary bonding layer.

Detailed Description

The following description of the aspects of some embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings in some embodiments of the disclosure, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments that are available to one of ordinary skill in the art based on some embodiments in this disclosure are within the scope of this disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", "some examples", "and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In the following, directional terms such as "upper", "lower", "left", "right" and the like may be defined with reference to the orientation in which the components are schematically disposed in the drawings, and it should be understood that these directional terms may be relative concepts, which are used for the description and clarity with respect thereto, and which may be correspondingly varied according to the variation in orientation in which the components are disposed in the drawings.

The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled (communicatively coupled)" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C," both include the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

In addition, the thickness of each layer in the drawings is exaggerated for clarity in the representation of the various layers and regions in the drawings, to clearly illustrate the relative positions between the layers. When a portion expressed as a layer, film, region, plate, or the like is located "over" or "on" other portions, the expression includes not only the case where it is "directly over" the other portions but also the case where there is another layer in the middle.

As shown in fig. 1, some embodiments of the present disclosure provide an epitaxial substrate 100 for growing epitaxial material. The epitaxial substrate 100 is a composite substrate. The epitaxial substrate 100 includes: a first substrate 110, a lattice matching layer 123, and a peeling layer 130 between the first substrate 110 and the lattice matching layer 123. The peeling layer 130 is formed on the surface of the first substrate 110 or the lattice matching layer 123, and the peeling layer 130 can be peeled off under a trigger condition to separate the first substrate 110 and the lattice matching layer 123.

The surface of the lattice matching layer 123 facing away from the exfoliation layer 130 is an epitaxially grown surface of epitaxial material for growing epitaxial material. The lattice constant of the lattice matching layer 123 matches the lattice constant of the epitaxial material. That is, the lattice constant of the lattice matching layer 123 is equal to or close to the lattice constant of the epitaxial material. Here, the two lattice constants are close to each other, and the difference between the two lattice constants is within a permissible range, and the permissible range can be selected and set according to practical requirements. The lattice matching layer 123 may be formed by using a single crystal material, for example, single crystal silicon carbide, single crystal gallium nitride, single crystal aluminum nitride, single crystal silicon, single crystal gallium oxide, or the like. The lattice matching layer 123 is disposed in the epitaxial substrate 100 in the embodiment of the disclosure, so that the lattice constant of the lattice matching layer 123 is matched with the lattice constant of the epitaxial material to be grown, and the problem of lattice mismatch between the epitaxial substrate 100 and the epitaxial material can be effectively solved.

On the basis that the first substrate 110 is located on the back side of the epitaxially grown surface of the lattice matching layer 123, the lattice constant of the first substrate 110 may not be limited by the lattice constant of the epitaxial material. Thus, the first substrate 110 may have more options, for example, the first substrate 110 is not limited to a single crystal substrate, but may be a polycrystalline substrate.

Illustratively, the materials of the first substrate 110 include: single crystal silicon carbide, polycrystalline silicon carbide, single crystal sapphire, polycrystalline sapphire, single crystal gallium nitride, polycrystalline gallium nitride, single crystal gallium arsenide, polycrystalline gallium arsenide, single crystal silicon, polycrystalline silicon, single crystal aluminum nitride, polycrystalline aluminum nitride, single crystal gallium oxide, or polycrystalline gallium oxide.

Furthermore, the thermal expansion coefficient of the epitaxial substrate 100 is determined by the combination of its respective layer structures. On the premise of ensuring that the lattice constant of the lattice matching layer 123 is matched with that of the epitaxial material, the first substrate 110 is used as a main support of the epitaxial substrate 100, and the thermal expansion coefficient of the first substrate 110 can be used to influence the thermal expansion coefficient of the epitaxial substrate 100 by reasonably selecting the first substrate 110. So that the thermal expansion coefficient of the epitaxial substrate 100 is matched (equal or close) to that of the epitaxial material to be grown, to effectively solve the problem of thermal mismatch between the epitaxial substrate 100 and the epitaxial material.

Illustratively, the lattice matching layer 123 has a thickness less than the thickness of the first substrate 110. The thickness of the lattice matching layer 123 is limited to meet the growth requirements of the epitaxial material. In the case where the thickness of the first substrate 110 is large, the thermal expansion coefficient of the first substrate 110 may largely affect the thermal expansion coefficient of the epitaxial substrate 100. Thus, the first substrate 110 having a thermal expansion coefficient matching that of the epitaxial material is selected to facilitate ensuring that the thermal expansion coefficient of the epitaxial substrate 100 matches that of the epitaxial material.

In summary, the epitaxial material is grown on the epitaxial substrate 100 provided by the embodiments of the present disclosure, so that the lattice constant and the thermal expansion coefficient of the epitaxial material and the epitaxial substrate can be matched, thereby avoiding defects of the epitaxial material due to lattice mismatch and/or thermal mismatch, and being beneficial to improving the growth quality of the epitaxial material.

In the disclosed embodiment, the exfoliation layer 130 is located between the lattice matching layer 123 and the first substrate 110. In the fabrication of a semiconductor device or integrated circuit using the epitaxial substrate 100, if the epitaxial substrate 100 is thinned, it can be achieved by separating the lattice matching layer 123 from the first substrate 110 by peeling the peeling layer 130.

Since the first substrate 110 may be selected without being limited by the lattice constant of the epitaxial material, the first substrate 110 may be selected with a lower cost. On this basis, the separated first substrate 110 can be reused to prepare a new epitaxial substrate 100, so that the first substrate 110 does not need to be subjected to destructive thinning, and material waste can be avoided. In this manner, the first substrate 110 and the lattice matching layer 123 are separated by the peeling layer 130, so that the epitaxial substrate 100 can be thinned in a low-cost manner, and the problem that the cost of the semiconductor device or the integrated circuit is high due to destructive thinning of the epitaxial substrate when the semiconductor device or the integrated circuit is manufactured is effectively solved.

It should be added that the peeling of the peeling layer 130 needs to be performed under the trigger condition. For example, the material properties of the peeling layer 130 can be changed under the condition of laser irradiation or exposure to a chemical solution so that the first substrate 110 and the lattice matching layer 123 are separated.

The material of the peeling layer 130 is, for example, zinc oxide (ZnO), gallium nitride (GaN), gallium oxide (Ga ₂ O ₃ ) Porous silicon or porous silicon dioxide.

Optionally, the material of the release layer 130 is gallium nitride. The process of forming the peeling layer 130 includes: a hydride vapor phase epitaxy (Hydride Vapor Phase Epitaxy, HVPE for short) process, a Metal-organic chemical vapor deposition (Metal-Organic Chemical Vapor Deposition, MOCVD for short) process, or a physical vapor deposition process. The peeling layer 130 can be peeled off by laser peeling. The technology of laser stripping is mature, and the machine required by the implementation of laser stripping is also easy to obtain. The laser light is absorbed by gallium nitride through the first substrate 110 (e.g., a sapphire substrate), and the gallium nitride is thermally decomposed after absorbing the laser energy, so that nitrogen gas and gallium in a molten state can be generated, thereby facilitating separation of the first substrate 110 and the lattice matching layer 123.

Further, the surface of the first substrate 110 separated from the lattice matching layer 123 and the surface of the lattice matching layer 123 separated from the first substrate 110 may be subjected to a cleaning or polishing treatment as needed. Optionally, the material of the release layer 130 is gallium oxide. A process for forming the peeling layer 130, comprising: a physical vapor deposition process, a pulsed laser deposition process, or an organometallic chemical vapor deposition process. The release layer 130 can be peeled off by chemical peeling, for example, the release layer 130 can be peeled off by etching due to chemical reaction with a hydrofluoric acid solution after being placed in the hydrofluoric acid solution.

Optionally, the material of the release layer 130 is zinc oxide. A process for forming the peeling layer 130, comprising: a physical vapor deposition process, a pulsed laser deposition process, or an organometallic chemical vapor deposition process. The peel-off layer 130 can be peeled off by chemical peeling, for example, the peel-off layer 130 can be peeled off by corrosion due to its chemical reaction with hydrochloric acid (HCl) solution after being placed in the hydrochloric acid (HCl) solution.

Alternatively, the material of the peeling layer 130 is porous silicon. A process for forming the peeling layer 130, comprising: a physical vapor deposition process or a chemical vapor deposition process. The peeling layer 130 can be peeled off by chemical peeling or water jet cutting. For example, the peel layer 130 may be etched away by a chemical reaction with a potassium hydroxide (KOH) solution after being placed in the KOH solution.

Alternatively, the material of the release layer 130 is porous silica. A process for forming the peeling layer 130, comprising: a physical vapor deposition process or a chemical vapor deposition process. The peeling layer 130 can be peeled off by chemical peeling or water jet cutting. For example, the release layer 130 may be etched away after being placed in a hydrofluoric acid (HF) solution due to its chemical reaction with the hydrofluoric acid solution.

In some of the above embodiments, chemical lift-off may be used in cases where laser lift-off cannot be used due to the low laser transmissivity of the first substrate 110. The peeling layer 130 adopts chemical peeling, which is convenient for mass production and processing of peeling the peeling layer 130, does not need to design a special machine, and is beneficial to improving the production efficiency of subsequent semiconductor devices or integrated circuits. In addition, the stripping layer 130 is cut and stripped by a water knife, so that the method has good environmental protection benefit.

In order to ensure that the first substrate 110 and the lattice matching layer 123 can be effectively separated and have a good separation effect, the material of the peeling layer 130 is different from that of the first substrate 110. Optionally, the material of the release layer 130 and the material of the lattice matching layer 123 are also different.

In some embodiments, referring to fig. 2 and 3, epitaxial substrate 100 further includes a bonding layer 140.

Alternatively, as shown in fig. 2, the peeling layer 130 is formed on the surface of the first substrate 110 adjacent to the lattice matching layer 123, and the bonding layer 140 is formed on the surface of the peeling layer 130 adjacent to the lattice matching layer 123 and bonded to the lattice matching layer 123. Bonding refers herein to the integration of two different substances by interatomic forces.

In the embodiment of the disclosure, the release layer 130 and the bonding layer 140 are formed on the surface of the first substrate 110 in a stacked manner, and the bonding layer 140 and the lattice matching layer 123 are bonded, so that the bonding effect between the lattice matching layer 123 and the release layer 130, that is, between the lattice matching layer 123 and the first substrate 110, can be improved by using the bonding layer 140, and the difficulty of the bonding process between the lattice matching layer 123 and the first substrate 110 can be reduced.

Alternatively, as shown in fig. 3, the peeling layer 130 is formed on the surface of the lattice matching layer 123 adjacent to the first substrate 110, and the bonding layer 140 is formed on the surface of the peeling layer 130 adjacent to the first substrate 110 and bonded to the first substrate 110. Bonding refers herein to the integration of two different substances by interatomic forces.

In the embodiment of the disclosure, the peeling layer 130 and the bonding layer 140 are formed on the surface of the lattice matching layer 123 in a stacked manner, and the bonding layer 140 is bonded to the first substrate 110, so that the bonding effect between the first substrate 110 and the peeling layer 130, that is, between the first substrate 110 and the lattice matching layer 123, can be improved by using the bonding layer 140, and the difficulty of the bonding process between the lattice matching layer 123 and the first substrate 110 can be reduced.

In addition, referring to fig. 4 and 5, the bonding layer 140 may include a first bonding layer 141 and a second bonding layer 142.

In some examples, as shown in fig. 4, a release layer 130 is formed on the first substrate 110. The first bonding layer 141 is formed on a surface of the peeling layer 130 facing away from the first substrate 110. The second bonding layer 142 is formed on the lattice matching layer 123. The first bonding layer 141 and the second bonding layer 142 are bonded. In the embodiment of the disclosure, the peeling layer 130 and the first bonding layer 141 are formed on the surface of the first substrate 110 in a lamination manner, and the second bonding layer 142 is formed on the surface of the lattice matching layer 123, so that the first bonding layer 141 and the second bonding layer 142 are bonded, the bonding effect between the lattice matching layer 123 and the first substrate 110 can be further improved, and the bonding process difficulty between the lattice matching layer 123 and the first substrate 110 can be further reduced.

In other examples, as shown in fig. 5, a release layer 130 is formed on the lattice matching layer 123. The second bonding layer 142 is formed on the surface of the peeling layer 130 facing away from the lattice matching layer 123. The first bonding layer 141 is formed on the first substrate 110. The first bonding layer 141 and the second bonding layer 142 are bonded. The embodiment of the disclosure stacks the peeling layer 130 and the second bonding layer 142 on the surface of the lattice matching layer 123, and forms the first bonding layer 141 on the surface of the first substrate 110, so that the first bonding layer 141 and the second bonding layer 142 are bonded, which can further improve the bonding effect between the lattice matching layer 123 and the first substrate 110, and further reduce the difficulty of the bonding process between the lattice matching layer 123 and the first substrate 110.

In some embodiments described above, the material of the bonding layer 140 may be selected according to practical requirements, for example, a metal material or a non-metal material. However, no matter which material is used for the bonding layer 140, the melting point of the material used for the bonding layer 140 needs to be higher than the temperature required for the subsequent epitaxial material growth.

Illustratively, the material of the bonding layer 140 is a metallic material comprising: titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), tungsten (W), or gold (Au). In this manner, bonding between the lattice matching layer 123 and the first substrate 110 is facilitated at lower process temperature conditions.

The bonding layer 140 may have a single-layer structure or a stacked-layer structure.

Alternatively, the bonding layer 140 is a laminate structure, such as a titanium-gold-titanium laminate, in which a gold-gold bond is formed between two gold layers. That is, the bonding layer 140 includes a first bonding layer 141 and a second bonding layer 142, wherein the first bonding layer 141 is a titanium-gold laminate, the second bonding layer 142 is a titanium-gold laminate, and the bonding between the first bonding layer 141 and the second bonding layer 142 is a gold-gold bonding. Therefore, the adhesion of the gold layer can be effectively enhanced by utilizing the titanium layer, so that the bonding process difficulty of the bonding layer 140 is reduced on the premise of ensuring the bonding effect of the bonding layer 140.

Illustratively, the material of the bonding layer 140 is a non-metallic material that includes: spin-on glass, silicon oxide (SiO) ₂ ) Silicon nitride (SiN) or silicon oxynitride (SiON). Thus, not only is the preparation of the bonding layer 140 convenient, but also the bonding layer 140 can have light transmission property.

The epitaxial substrate 100 is structured as described above. Accordingly, some embodiments of the present disclosure provide a method of preparing an epitaxial substrate 100, as follows.

In some embodiments, the epitaxial substrate 100 is structured as shown in fig. 1. As understood with reference to fig. 6, the method for preparing the epitaxial substrate 100 includes: s100 to S600.

S100, providing a first substrate 110 and a second substrate 120.

The first substrate 110 and the second substrate 120 may be determined according to epitaxial materials to be grown. Wherein the lattice constant of the second substrate 120 matches the lattice constant of the epitaxial material. Optionally, the coefficient of thermal expansion of the first substrate 110 is matched to the coefficient of thermal expansion of the epitaxial material.

Examples of the present disclosure illustratively give some materials having lattice constants as shown in table 1 and thermal expansion coefficients as shown in table 2.

TABLE 1

In the case where the epitaxial material is gallium nitride (GaN), the lattice constant based on gallium nitride is 3.189, and the second substrate 120 is preferably: single crystal 6H-silicon carbide (SiC), single crystal 4H-silicon carbide (SiC), or single crystal aluminum nitride (AlN) such that the lattice constant of the second substrate 120 matches that of gallium nitride.

TABLE 2

Material of first substrate	Coefficient of thermal expansion (ppm/K)
Sapphire (sapphire)	7.5

Silicon carbide (SiC)	4.2
Gallium arsenide (GaAs)	5.7-6
Gallium nitride (GaN)	5
Molybdenum (Mo)	4.8
Chromium (Cr)	4.9
Silicon (Si)	2.6

The thermal expansion coefficient of the sapphire, silicon carbide, gallium arsenide, gallium nitride or silicon is not affected by the single crystal structure or the polycrystalline structure. That is, the thermal expansion coefficient of the sapphire, silicon carbide, gallium arsenide, gallium nitride or silicon is the same as or similar to that of the sapphire, gallium carbide, gallium arsenide, gallium nitride or silicon in the case of a single crystal structure.

It should be added that the cost of sapphire, silicon carbide, gallium arsenide, gallium nitride or silicon is far higher than that of the single crystal structure. And, as the defect density in the material decreases, the better the quality of the material, the higher the cost of the material.

In the case where the epitaxial material is gallium nitride (GaN), the first substrate 110 is preferably selected from the group consisting of gallium nitride having a thermal expansion coefficient of 5.59 ppm/K: polycrystalline gallium arsenide (GaAs) or polycrystalline gallium nitride (GaN) may have lower production costs.

S200, as shown in (a) and (b) of fig. 6, a damaged layer 122 is formed inside the second substrate 120 such that the second substrate 120 is partitioned into a base 121 and a lattice matching layer 123 by the damaged layer 122.

Here, the second substrate 120 is, for example, a single crystal silicon carbide substrate, a single crystal aluminum nitride substrate, or a single crystal silicon substrate. The damaged layer 122 may be formed by laser irradiation or ion implantation. The damaged layer 122 refers to a portion of the second substrate where the crystal lattice is broken, and the portion has a large number of defects, such as vacancies after more atomic shift, and is more prone to cracking under stress conditions.

S300, as shown in (c) and (d) in fig. 6, a peeling layer 130 is formed on the first substrate 110.

Here, the first substrate 110 is, for example, a single crystal silicon carbide substrate, a polycrystalline silicon carbide substrate, a single crystal sapphire substrate, a polycrystalline sapphire substrate, a single crystal gallium nitride substrate, a polycrystalline gallium nitride substrate, a single crystal gallium arsenide substrate, a polycrystalline gallium arsenide substrate, a single crystal silicon substrate, a polycrystalline silicon substrate, a single crystal aluminum nitride substrate, a polycrystalline aluminum nitride substrate, a single crystal gallium oxide substrate, or a polycrystalline gallium oxide substrate.

The material of the peeling layer 130 is different from that of the first substrate 110, and the material of the peeling layer 130 includes, but is not limited to, zinc oxide (ZnO), gallium nitride (GaN), gallium oxide (Ga ₂ O ₃ ) Porous silicon or porous silicon dioxide. The peel layer 130 is capable of peeling under a trigger condition.

S400, as shown in (e) of fig. 6, the lattice matching layer 123 of the second substrate 120 is bonded on the side of the peeling layer 123 facing away from the first substrate 110.

It should be noted that, the execution of S200 and S300 is not limited in order, and may be performed simultaneously or alternatively. Alternatively, the release layer 130 may be formed on the lattice matching layer 123 of the second substrate 120, and then the first substrate 110 may be bonded to a side of the release layer 130 (not shown in fig. 4) facing away from the lattice matching layer 123.

S500, as shown in (f) of fig. 6, the damaged layer 122 and the substrate 121 are removed, and the surface of the lattice matching layer 123 facing away from the peeling layer 130 is polished to form an epitaxial growth plane.

Here, the removal of the substrate 121 and the damaged layer 122 may be achieved by peeling the damaged layer 122 by heat treatment. Based on this, the base 121 can also be reused as a new second substrate 120.

It is understood that during the process of removing the damaged layer 122, the first portion 122-1 of the damaged layer 122 is removed along with the substrate 121, and the first portion 122-1 is a portion of the damaged layer 122 close to the substrate 121. The second portion 122-2 of the damaged layer 122 is easily left on the surface of the lattice matching layer 123 and removed in a subsequent polishing process; the second portion 122-2 is a portion of the damaged layer 122 that is adjacent to the lattice matching layer 123.

The polished surface of the lattice matching layer 123 has a good planarity, which is advantageous for growing high quality epitaxial materials.

S600, as shown in (g) of fig. 6, the epitaxial substrate 100 shown in fig. 1 is obtained.

In the embodiment of the present disclosure, the preparation method of the epitaxial substrate 100 is simple and easy to operate, and the preparation method of the epitaxial substrate 100 has the same advantages as those of the epitaxial substrate 100 described above, and will not be described in detail herein.

In other embodiments, the epitaxial substrate 100 is structured as shown in fig. 2. As understood with reference to fig. 7, the method for preparing the epitaxial substrate 100 includes: s100 'to S600'.

Hereinafter, the same parts as those in S100 to S600 in S100 'to S600' will not be described in detail.

S100', a first substrate 110 and a second substrate 120 are provided.

S200', as shown in (a) and (b) of fig. 7, a damaged layer 122 is formed inside the second substrate 120 such that the second substrate 120 is partitioned into a base 121 and a lattice matching layer 123 by the damaged layer 122.

S300', as shown in (c) and (d) of fig. 7, a peeling layer 130 and a bonding layer 140 are sequentially formed on the first substrate 110.

The release layer 130 and the bonding layer 140 are stacked, and the material of the bonding layer 140 may be selected according to practical requirements, for example, a metal material or a non-metal material. The metal material includes: titanium (Ti)), tantalum (Ta), chromium (Cr), tungsten (W), nickel (Ni), or gold (Au). The nonmetallic material includes: spin-on glass, silicon oxide (SiO 2), silicon nitride (SiN), or silicon oxynitride (SiON).

S400', as shown in (e) of fig. 7, the lattice matching layer 123 of the second substrate 120 is bonded on the surface of the bonding layer 140 facing away from the peeling layer 130.

S500', as shown in (f) of fig. 7, the damaged layer 122 and the substrate 121 are removed, and the surface of the lattice matching layer 123 facing away from the peeling layer 130 is polished to form an epitaxial growth plane.

S600', as shown in (g) of fig. 7, the epitaxial substrate 100 shown in fig. 2 is obtained.

In other embodiments, the structure of epitaxial substrate 100 is shown in fig. 3. As understood with reference to fig. 8, the method for preparing the epitaxial substrate 100 includes: s100 "to S600".

Hereinafter, the same parts as those in S100 to S600 in S100 "to S600" will not be described in detail.

S100", a first substrate 110 and a second substrate 120 are provided.

S200", as shown in (a) and (b) of fig. 8, a damaged layer 122 is formed inside the second substrate 120 such that the second substrate 120 is partitioned into a base 121 and a lattice matching layer 123 by the damaged layer 122.

S300", as shown in (c) of fig. 8, the peeling layer 130 and the bonding layer 140 are sequentially formed on the lattice matching layer 123 of the second substrate 120.

S400", as shown in (d) and (e) of fig. 8, the first substrate 110 is bonded on the surface of the bonding layer 140 facing away from the peeling layer 130.

S500", as shown in (f) of fig. 8, the damaged layer 122 and the substrate 121 are removed, and the surface of the lattice matching layer 123 facing away from the peeling layer 130 is polished to form an epitaxial growth plane.

S600", as shown in (g) of fig. 8, the epitaxial substrate 100 shown in fig. 3 is obtained.

In still other embodiments, the epitaxial substrate 100 is structured as shown in fig. 4 or 5, and the bonding layer 140 thereof includes a first bonding layer 141 and a second bonding layer 142. Correspondingly, the method for preparing the epitaxial substrate 100 is similar to the aforementioned embodiments, and only the formation steps of the bonding layer 140 are different, and the same parts of the embodiments of the disclosure will not be described in detail.

The epitaxial substrate 100 is illustrated in fig. 4, and the method of fabrication is illustrated in fig. 9. Referring to fig. 9, after forming the peeling layer 130 on the first substrate 110, the preparation method further includes: forming a first bonding layer 141 on a surface of the peeling layer 130 facing away from the first substrate 110, as shown in (f) of fig. 9; a second bonding layer 142 is formed on the lattice matching layer 123 of the second substrate 120, as shown in (c) of fig. 9. Here, the first bonding layer 141 and the second bonding layer 142 are formed without limitation in order, and may be simultaneously performed or may be performed first.

Correspondingly, bonding the lattice matching layer 123 of the second substrate 120 on the side of the release layer 130 facing away from the first substrate 110, comprises: the first bonding layer 141 and the second bonding layer 142 are bonded.

By way of example, the structure of epitaxial substrate 100 is shown in fig. 5 and the method of fabrication is shown in fig. 10. Referring to fig. 10, after forming the peeling layer 130 on the lattice matching layer 123, the manufacturing method further includes: forming a first bonding layer 141 on a surface of the first substrate 110, as shown in (d) of fig. 10; a second bonding layer 142 is formed on the surface of the peeling layer 130 facing away from the lattice matching layer 123, as shown in (c) of fig. 10. Here, the first bonding layer 141 and the second bonding layer 142 are formed without limitation in order, and may be simultaneously performed or may be performed first.

Correspondingly, bonding the first substrate 110 on the side of the release layer 130 facing away from the lattice matching layer 123, comprises: the first bonding layer 141 and the second bonding layer 142 are bonded.

It should be added that in some of the above embodiments, after the second substrate 120 is bonded to the first substrate 110, the bonding strength may be effectively enhanced by performing the first heat treatment. After that, the second heat treatment is performed again, so that the second substrate 120 is peeled off at the damaged layer 122, thereby forming the lattice matching layer 123 bonded on the peeling layer 130 or the bonding layer 140. Wherein the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

Referring to fig. 11-13, some embodiments of the present disclosure provide a semiconductor wafer 200. The semiconductor wafer 200 includes: epitaxial substrate 100 as described in some embodiments above, and epitaxial layer 210 grown on the epitaxially grown side of lattice matching layer 123. Here, the epitaxial layer 210 is a thin film formed of the foregoing epitaxial material. The growth of epitaxial layer 210 is related to lattice-matching layer 123 in epitaxial substrate 100. The epitaxial substrate 100 has the above-described structure, and a high-quality epitaxial layer 210 can be grown.

In some embodiments, the lattice constant of epitaxial layer 210 matches the lattice constant of lattice matching layer 123. Epitaxial layer 210 may be grown as a monolayer film directly on the epitaxially grown side of lattice matching layer 123.

Alternatively, the lattice matching layer 123 is a monocrystalline gallium nitride layer or a monocrystalline aluminum nitride layer. Epitaxial layer 210 is a monocrystalline gallium nitride layer. The epitaxial layer 210 is directly grown on the epitaxial growth surface of the lattice matching layer 123 to form a film, and can have better film forming quality.

Alternatively, lattice matching layer 123 is a single crystal silicon carbide layer. Epitaxial layer 210 is a single crystal silicon carbide layer. The epitaxial layer 210 is directly grown on the epitaxial growth surface of the lattice matching layer 123 to form a film, and can have better film forming quality.

Alternatively, the lattice matching layer 123 is a single crystal silicon layer. Epitaxial layer 210 is a monocrystalline silicon layer. The epitaxial layer 210 is directly grown on the epitaxial growth surface of the lattice matching layer 123 to form a film, and can have better film forming quality.

In other embodiments, where the lattice constant of epitaxial layer 210 differs from the lattice constant of lattice matching layer 123, epitaxial layer 210 may be grown as a multilayer film on the epitaxially grown side of lattice matching layer 123. That is, a nucleation layer may be first formed on the epitaxial growth surface of the lattice matching layer 123, and then a single crystal material layer may be formed on the surface of the nucleation layer, thereby obtaining the semiconductor wafer 200.

Alternatively, as shown in fig. 14, the epitaxial layer 210 includes an aluminum nitride nucleation layer 2101 and a single crystal gallium nitride layer 2102 which are stacked. In the process of forming the epitaxial layer 210, it is necessary to grow an aluminum nitride nucleation layer 2101 on the epitaxial growth surface of the lattice matching layer 123, and then grow a single crystal gallium nitride layer 2102 on the surface of the aluminum nitride nucleation layer 2101, so as to ensure formation of the single crystal gallium nitride layer 2102 with good film formation quality.

In the disclosed embodiment, the semiconductor wafer 200 may be obtained by growing the epitaxial layer 210 on the epitaxial growth surface of the epitaxial substrate 100 to prepare a semiconductor device or an integrated circuit using the semiconductor wafer 200.

Referring to fig. 15, some embodiments of the present disclosure provide a method for manufacturing a semiconductor device 1000, as follows.

First, as shown in fig. 15 (a), a semiconductor wafer 200 according to any of the embodiments described above is provided, and a device layer 1001 is prepared on the epitaxial layer 210 of the semiconductor wafer 200, the device layer 1001 including at least part of the layers in the semiconductor device.

It will be appreciated that the structure of the semiconductor device may be variously embodied, and the embodiments of the present disclosure are not limited thereto. The main constituent element in the semiconductor device is a transistor, and the embodiment of the present disclosure is described taking a partial layer structure in which the device layer 1001 includes a transistor as an example.

As illustrated in fig. 16, the transistor M includes a semiconductor layer 300, a passivation layer 400, a gate electrode 501, a source electrode 502, and a drain electrode 503. The semiconductor layer 300 includes a channel layer 301 and a barrier layer 302 which are stacked. The passivation layer 400 includes a plurality of openings. The gate 501, the source 502, and the drain 503 are respectively formed in the corresponding openings of the passivation layer 400 and are in direct contact with the barrier layer 302. The source 502 and drain 503 form ohmic contacts with the barrier layer 302, respectively. The gate 501 forms a schottky barrier with the barrier layer 302. Further, it is also permissible to provide a gate insulating layer between the gate electrode 501 and the barrier layer 302. The passivation layer 400 and the gate insulating layer are insulating layers and can be prepared from inorganic insulating materials such as silicon nitride, silicon oxide or silicon oxynitride.

As will be appreciated in conjunction with fig. 15-17, in semiconductor device 1000, a device layer 1001 is formed over epitaxial layer 210. The epitaxial layer 210 may be used as the channel layer 301 of the transistor M. On this basis, optionally, as shown in fig. 17, the device layer 1001 includes a barrier layer 302, a passivation layer 400, a gate electrode 501, a source electrode 502, and a drain electrode 503, but is not limited thereto.

Optionally, as shown in fig. 18, the device layer 1001 further includes a plurality of metal patterns 600 correspondingly coupled to the gate electrode 501, the source electrode 502, and the drain electrode 503; wherein a plurality of metal patterns 600 are insulated from each other.

Here, the metal pattern 600 is used for transmitting an electrical signal to the electrode (including the gate 501, the source 502 or the drain 503) coupled to the transistor M, and the pattern can be designed according to practical requirements, so as to facilitate the electrical coupling between the semiconductor device and the external device, or to limit the specific function of the semiconductor device. Optionally, the metal pattern 600 is a combination of one or more of a metal electrode, a metal line, a bond pad, or a bonding pad.

Next, as shown in (b) of fig. 15, a support substrate 1002 is provided, and the support substrate 1002 is bonded on the surface of the device layer 1001 facing away from the epitaxial layer 210.

Here, the support substrate 1002 has a certain mechanical strength, and the support substrate 1002 is, for example, a silicon substrate or a glass substrate. The bond between the support substrate 1002 and the device layer 1001 is a temporary bond. The temporary bonding means that the bonding may also be released after bonding, i.e., the support substrate 1002 may be removed in the event that it is not needed later.

The bond between the support substrate 1002 and the device layer 1001 may be a direct bond or an indirect bond.

Alternatively, the structure of the device layer 1001 is as shown in fig. 17, and the surfaces of the gate 501, the source 502, and the drain 503 facing away from the barrier layer 302 are flush or substantially flush with the surface of the passivation layer 400 facing away from the barrier layer 302. In this way, the surface of the device layer 1001 facing away from the epitaxial layer 210 may be directly bonded to the support substrate 1002, so that the bonding interface between the device layer 1001 and the support substrate 1002 has better flatness, and thus, better bonding effect of the device layer 1001 and the support substrate 1002 is ensured.

Alternatively, as shown in fig. 18, the structure of the device layer 1001 is that the surface of the device layer 1001 facing away from the epitaxial layer 210 is the surface of the metal pattern 600 facing away from the passivation layer 400. The surface of the device layer 1001 facing away from the epitaxial layer 210 may be bonded to the support substrate 1002 indirectly, for example by a temporary bonding layer, to ensure a good bonding effect.

Illustratively, bonding the support substrate 1002 on the surface of the device layer 1001 facing away from the epitaxial layer 210, as shown in fig. 19, includes: a temporary bonding layer 700 is formed on the support substrate 1002, bonding the temporary bonding layer 700 on the surface of the device layer 1001 facing away from the epitaxial layer 210.

Alternatively, the temporary bonding layer 700 is made of at least one material selected from glass, silicon dioxide, or silicon nitride, and is formed on the support substrate 1002 by spin coating or vapor deposition process. The temporary bonding layer 700 may thus be removed without requiring its presence using at least one of a laser treatment, a heat treatment, a chemical treatment, an etching, grinding or polishing process, etc. Also, the temporary bonding layer 700 is formed using the above material, and it is also ensured that the temporary bonding layer 700 is not affected by a high temperature environment in a subsequent process. The temperature of the high-temperature environment is, for example, 200 ℃.

Then, as shown in (c) of fig. 15, the peeling layer 130 and the first substrate 110 are peeled off from the lattice matching layer 123.

In the case where the epitaxial substrate 100 includes the bonding layer 140, and the bonding layer 140 is disposed between the lattice matching layer 123 and the peeling layer 140, the peeling interface of the peeling layer 130 is the interface of the peeling layer 130 and the bonding layer 140.

In addition, the peeling process of the peeling layer 130 is related to the material thereof.

Optionally, the release layer 130 is a gallium nitride layer. The peeling process of the peeling layer 130 includes: and (5) laser stripping. That is, the peeling layer 130 may be peeled off under the triggering condition of laser irradiation.

Optionally, the release layer 130 is a gallium oxide layer or a zinc oxide layer. A peeling process of the peeling layer 130, comprising: chemical stripping. That is, the release layer 130 may be peeled off under a trigger condition placed in a chemical solution. For example, the gallium oxide layer may be stripped in a hydrofluoric acid solution. The zinc oxide layer can be peeled off in a hydrochloric acid solution.

Alternatively, the release layer 130 is a porous silicon layer or a porous silicon dioxide layer. A peeling process of the peeling layer 130, comprising: chemical stripping or water knife cutting stripping.

Thereafter, as shown in (d) of fig. 15, the back surface of the lattice matching layer 123 is polished. The back side of lattice matching layer 123 is its surface facing away from epitaxial layer 210.

In some examples, semiconductor wafer 200 includes bonding layer 140. Accordingly, after peeling the peeling layer 130 and the first substrate 110, before polishing the back surface of the lattice matching layer 123, the manufacturing method of the semiconductor device further includes: the bonding layer 140 is polished away.

Thereafter, as shown in (e) of fig. 15, a metal layer 1003 is formed on the back surface of the lattice matching layer 123.

The metal layer 1003 may be made of a metal material having a good heat radiation capability, for example, at least one of copper, aluminum, platinum, tungsten, nickel, iridium, cobalt, or the like. In this manner, the heat dissipation capability of the semiconductor device 1000 obtained by the production can be improved by using the metal layer 1003.

The metal layer 1003 may also be coupled to an electrode (e.g., gate 501, source 502, or drain 503), metal pattern 600, or other electronic element in the device layer 1001 through a via to provide a ground signal or a floating signal. The layer structure through which the via hole needs to penetrate corresponds to the layer structure between the metal layer 1003 and the layer to be coupled. The layer structure through which the via passes may vary depending on the structure of the semiconductor device or integrated circuit 1000 and will not be described in detail herein. The via hole in the embodiment of the present disclosure includes a via hole and a metal conductor filled in the via hole, and the metal conductor may be prepared with the same metal material as the metal layer 1003 to simplify the preparation process.

Finally, as shown in (f) of fig. 15, the support substrate 1002 is removed. Thereby obtaining the semiconductor device 1000.

In the case where the support substrate 1002 is bonded to the device layer 1001 through the temporary bonding layer 700, correspondingly, removing the support substrate 1002 further includes: the temporary bonding layer 700 and the support substrate 1002 are removed using at least one process of laser treatment, heat treatment, chemical treatment, etching, grinding, or polishing.

In the embodiment of the disclosure, after the device layer 1001 is prepared on the semiconductor wafer 200, the first substrate 110 and the peeling layer 130 in the semiconductor wafer 200 can be effectively peeled off by means of the supporting substrate 1002, and the metal layer 1003 is formed on the back surface of the lattice matching layer 123, so that the preparation of the semiconductor device 1000 is completed, and the operation is simple and convenient, which is beneficial to improving the production efficiency.

Referring to fig. 20, some embodiments of the present disclosure also provide another method for manufacturing a semiconductor device 1000, as follows.

First, as shown in fig. 20 (a), a semiconductor wafer 200 according to any of the embodiments described above is provided, and a device layer 1001 is prepared on the epitaxial layer 210 of the semiconductor wafer 200, the device layer 1001 including at least part of the layers in the semiconductor device 1000.

The structure of the device layer 1001 may be referred to in the foregoing embodiments and will not be described in detail herein.

Next, as shown in (b) of fig. 20, a support substrate 1002 is provided, and the support substrate 1002 is bonded on the surface of the device layer 1001 facing away from the epitaxial layer 210.

The structure of the support substrate 1002, and its bonding to the device layer 1001, may be as described in connection with some of the embodiments described above.

Then, as shown in (c) of fig. 20, the peeling layer 130 and the first substrate 110 are peeled off from the lattice matching layer 123.

Thereafter, as shown in (d) of fig. 20, the lattice matching layer 123 is removed so that the epitaxial layer 210 is exposed.

In some examples, semiconductor wafer 200 includes bonding layer 140. Accordingly, after peeling the peeling layer 130 and the first substrate 110, before removing the lattice matching layer 123, the manufacturing method of the semiconductor device further includes: the bonding layer 140 is removed.

In addition, the removal of the lattice matching layer 123 and the bonding layer 140 may be achieved by etching, grinding or polishing, etc.

Thereafter, as shown in fig. 20 (e), a third substrate 1004 is provided, and the epitaxial layer 210 is bonded on the third substrate 1004. Alternatively, a third substrate 1004 is prepared on the surface of epitaxial layer 210 facing away from device layer 1001.

Here, the third substrate 1004 serves as an operation support of the semiconductor device, and a material of the third substrate 1004 may be selectively set according to actual requirements. For example, the third substrate 1004 may employ a substrate having a higher thermal conductivity, a higher resistance value, and a lower cost to ensure that the semiconductor device or integrated circuit has excellent heat dissipation capability, electrical performance, and lower production cost.

Optionally, the third substrate 1004 includes: a silicon carbide substrate, a diamond substrate, or a silicon substrate.

In some examples, as shown in fig. 21, the semiconductor device 1000 further includes a metal layer 1003, and the method of manufacturing the same further includes: a metal layer 1003 is formed on the back surface of the third substrate 1004. The metal layer 1003 may be made of a metal material having a good heat radiation capability, for example, at least one of copper, aluminum, platinum, tungsten, nickel, iridium, cobalt, or the like. In this manner, the heat dissipation capability of the semiconductor device 1000 obtained by the fabrication can be further improved by using the metal layer 1003.

The metal layer 1003 may also be coupled to an electrode (e.g., gate 501, source 502, or drain 503) or other electronic element in the device layer 1001 through a via to provide a ground signal or a floating signal. As shown for example in fig. 21, the metal layer 1003 is coupled to the source 502 of the transistor M by a via H that extends through at least the third substrate 1004, the epitaxial layer 210 and the barrier layer 302.

Finally, as shown in (f) of fig. 20, the support substrate 1002 is removed. Thereby obtaining the semiconductor device 1000.

In the embodiment of the disclosure, after the device layer 1001 is prepared on the semiconductor wafer 200, the epitaxial substrate 100 in the semiconductor wafer 200 can be effectively removed by means of the support substrate 1002, so that the third substrate 1004 is bonded or prepared on the back surface of the epitaxial layer 210, thereby completing the preparation of the semiconductor device 1000, which is simple and convenient to operate and is beneficial to improving the production efficiency.

In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

A method of preparing an epitaxial substrate, comprising:

providing a first substrate and a second substrate; the lattice constant of the second substrate is matched with the lattice constant of the epitaxial material to be grown;

forming a damaged layer inside the second substrate such that the second substrate is separated into a base and a lattice matching layer by the damaged layer;

forming a peeling layer on the first substrate, and bonding a lattice matching layer of the second substrate on one side of the peeling layer, which is away from the first substrate; or forming a peeling layer on the lattice matching layer, and bonding the first substrate on one side of the peeling layer, which is away from the lattice matching layer;

and removing the damaged layer and the substrate, and polishing a surface of the lattice matching layer facing away from the peeling layer, wherein the polished surface of the lattice matching layer is used for growing the epitaxial material.
The method for producing an epitaxial substrate according to claim 1, wherein,

after forming the peeling layer on the first substrate, the manufacturing method further includes: forming a bonding layer on a surface of the release layer facing away from the first substrate;

wherein bonding the lattice matching layer of the second substrate on a side of the release layer facing away from the first substrate comprises: and bonding the lattice matching layer of the second substrate on the surface of the bonding layer, which is away from the stripping layer.
The method of preparing an epitaxial substrate of claim 1, wherein the bonding layer comprises a first bonding layer and a second bonding layer;

after forming the peeling layer on the first substrate, the manufacturing method further includes: forming a first bonding layer on a surface of the peeling layer facing away from the first substrate, and forming a second bonding layer on the lattice matching layer of the second substrate;

wherein bonding the lattice matching layer of the second substrate on a side of the release layer facing away from the first substrate comprises: and bonding the first bonding layer and the second bonding layer.
The method for producing an epitaxial substrate according to claim 1, wherein,

after forming the release layer on the lattice matching layer, the manufacturing method further includes: forming a bonding layer on a surface of the release layer facing away from the lattice matching layer;

wherein bonding the first substrate on a side of the release layer facing away from the lattice matching layer comprises: the first substrate is bonded on a surface of the bonding layer facing away from the release layer.
The method of preparing an epitaxial substrate of claim 1, wherein the bonding layer comprises a first bonding layer and a second bonding layer;

After forming the release layer on the lattice matching layer, the manufacturing method further includes: forming a second bonding layer on a surface of the release layer facing away from the lattice matching layer; forming a first bonding layer on the first substrate;

wherein bonding the first substrate on a side of the release layer facing away from the lattice matching layer comprises: and bonding the first bonding layer and the second bonding layer.
The method for producing an epitaxial substrate according to any one of claims 1 to 5, wherein the process for forming the peeling layer comprises: hydride vapor phase epitaxy process, physical vapor deposition process, chemical vapor deposition process or pulsed laser deposition process; wherein, the chemical vapor deposition process comprises: an organometallic chemical vapor deposition process.
An epitaxial substrate comprising: a first substrate, a lattice matching layer, and a release layer between the first substrate and the lattice matching layer;

wherein a surface of the lattice matching layer facing away from the exfoliation layer is used to grow an epitaxial material, the lattice constant of the lattice matching layer matching the lattice constant of the epitaxial material.
The epitaxial substrate of claim 7, further comprising: a bonding layer;

The peeling layer is formed on one side surface of the first substrate, and the bonding layer is arranged between the peeling layer and the lattice matching layer; the lattice matching layer is bonded to the release layer through the bonding layer.
The epitaxial substrate of claim 7, further comprising: a bonding layer;

the peeling layer is formed on one side surface of the lattice matching layer, and the bonding layer is arranged between the peeling layer and the first substrate; the first substrate is bonded to the release layer through the bonding layer.
The epitaxial substrate of claim 7, wherein the lattice matching layer has a thickness less than a thickness of the first substrate.
The epitaxial substrate of claim 10, wherein the first substrate has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the epitaxial material.
An epitaxial substrate according to any of claims 7 to 11 in which the material of the release layer is different to the material of the first substrate.
The epitaxial substrate of claim 12, wherein the material of the first substrate comprises: single crystal silicon carbide, polycrystalline silicon carbide, single crystal sapphire, polycrystalline sapphire, single crystal gallium nitride, polycrystalline gallium nitride, single crystal gallium arsenide, polycrystalline gallium arsenide, single crystal silicon, polycrystalline silicon, single crystal aluminum nitride, polycrystalline aluminum nitride, single crystal gallium oxide, or polycrystalline gallium oxide.
A semiconductor wafer, comprising: the epitaxial substrate of any one of claims 7-13, and an epitaxial layer grown on a surface of the lattice matching layer facing away from the exfoliation layer.
A method of fabricating a semiconductor device, comprising:

providing a semiconductor wafer as claimed in claim 14, preparing a device layer on the epitaxial layer of the semiconductor wafer, the device layer comprising at least part of the layers of the semiconductor device;

providing a supporting substrate, and bonding the supporting substrate on the surface of the device layer, which is away from the epitaxial layer;

peeling the peeling layer and the first substrate from the lattice matching layer;

polishing the back surface of the lattice matching layer, wherein the back surface is the surface of the lattice matching layer, which is away from the epitaxial layer;

forming a metal layer on the back surface of the lattice matching layer;

and removing the supporting substrate to obtain the semiconductor device.
The method for manufacturing a semiconductor device according to claim 15, wherein the semiconductor wafer includes a bonding layer provided between the peeling layer and the lattice matching layer;

after peeling the peeling layer and the first substrate, before polishing the back surface of the lattice matching layer, the manufacturing method further includes: and polishing to remove the bonding layer.
The method for manufacturing a semiconductor device according to claim 15, wherein,

bonding the support substrate on a surface of the device layer facing away from the epitaxial layer, comprising: forming a temporary bonding layer on the support substrate, and bonding the temporary bonding layer on the surface of the device layer, which is away from the epitaxial layer;

removing the support substrate, comprising: and removing the temporary bonding layer and the support substrate by at least one process of laser treatment, heat treatment, chemical treatment, etching, grinding or polishing.
The method for manufacturing a semiconductor device according to any one of claims 15 to 17, wherein the peeling layer is peeled by a laser peeling process, a chemical peeling process, or a water jet cutting process.
A method of fabricating a semiconductor device, comprising:

providing a semiconductor wafer according to claim 14, preparing a device layer on the epitaxial layer of the semiconductor wafer, wherein the device layer comprises at least part of the layers in the semiconductor device;

providing a supporting substrate, and bonding the supporting substrate on the surface of the device layer, which is away from the epitaxial layer;

peeling the peeling layer and the first substrate from the lattice matching layer;

Removing the lattice matching layer to expose the epitaxial layer;

providing a third substrate, and bonding the epitaxial layer on the third substrate; or preparing a third substrate on the surface of the epitaxial layer facing away from the device layer;

and removing the supporting substrate to obtain the semiconductor device.
The method of manufacturing a semiconductor device of claim 19, wherein the semiconductor wafer comprises: a bonding layer disposed between the release layer and the lattice matching layer;

after the peeling layer and the first substrate are peeled off, before the lattice matching layer is removed, the manufacturing method further includes: and removing the bonding layer.