CN116528347A - Clock synchronization method, open wireless unit and radio access network structure - Google Patents

Clock synchronization method, open wireless unit and radio access network structure Download PDF

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Publication number
CN116528347A
CN116528347A CN202310396287.3A CN202310396287A CN116528347A CN 116528347 A CN116528347 A CN 116528347A CN 202310396287 A CN202310396287 A CN 202310396287A CN 116528347 A CN116528347 A CN 116528347A
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CN
China
Prior art keywords
clock
synchronization
data information
network data
compensation
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Pending
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CN202310396287.3A
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Chinese (zh)
Inventor
张塑涵
张乐健
李强
任蕾波
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Sichuan Hengwan Technology Co Ltd
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Sichuan Hengwan Technology Co Ltd
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Priority to CN202310396287.3A priority Critical patent/CN116528347A/en
Publication of CN116528347A publication Critical patent/CN116528347A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The embodiment of the invention discloses a clock synchronization method, an open wireless unit and a radio access network structure. According to the embodiment of the invention, the received network data information is analyzed, and the corresponding coarse alignment mode of clock synchronization is determined based on the analyzed data packet type, wherein when the analyzed data packet only comprises a PTP data packet, the clock coarse alignment is performed through the corresponding clock compensation parameter, when the analyzed data packet comprises the PTP data packet and a Sync E data packet, the coarse alignment is performed through the corresponding synchronous frequency difference of the Sync data packet, and then the output clock is subjected to frequency modulation or phase modulation according to the clock compensation parameter corresponding to the received network data information after the clock coarse alignment, so that the clock synchronization is realized. Therefore, the embodiment of the invention can realize time transmission and clock synchronization through PTP or PTP+SyncE, simplify the time synchronization configuration of the O-RU and the O-RAN, and improve the applicability of the O-RU and the O-RAN.

Description

Clock synchronization method, open wireless unit and radio access network structure
Technical Field
The present invention relates to the field of communications, and in particular, to a clock synchronization method, an open wireless unit, and a radio access network structure.
Background
In the current communication networks, radio access networks, such as 2G/3G/4G/5G, established by telecom operators for public services are common public radio access networks. However, most of the conventional wireless access networks are closed wireless access networks, that is, the hardware devices in the access networks are proprietary hardware devices of all device merchants, the corresponding application software is also proprietary software of all device merchants, and devices among different device merchants cannot be directly replaced, so that network operators (such as China Mobile, china telecom and the like) can only select hardware products and application software of one device merchant when planning network base stations, and in order to solve the problem, domestic and foreign network operators such as China Mobile and the like propose open wireless access networks (Open Radio Access Network, abbreviated as O-RAN). The existing RAN functions are stripped from the proprietary hardware and the proprietary embedded operating system platform, migrated to the universal hardware, the universal operating system and the universal cloud platform, and tried to open the software interface and even the software open source.
The O-RU is a key component in the entire O-RAN network architecture, and is directly facing the user, and carries the transceiving of user data traffic. As a communication network, time synchronization needs to be implemented between node units in the network, so that low delay of data interacted with users can be ensured. Time synchronization is also required between an O-RU (Open Radio Unit) and an O-DU (Open Distributed Unit, open distribution Unit), so how time synchronization is achieved is important in an O-RAN.
Disclosure of Invention
In view of this, the embodiments of the present invention provide a clock synchronization method, an open wireless unit, and a radio access network structure, so as to achieve clock synchronization, simplify time synchronization configuration of an O-RU and an O-RAN, and improve applicability of the O-RU and the O-RAN.
In a first aspect, an embodiment of the present application provides a clock synchronization method, where the method includes:
receiving network data information;
determining a first compensation clock according to a high-precision time synchronization protocol in response to the network data information including the high-precision time synchronization protocol data packet;
performing time coarse alignment according to the first compensation clock until the second compensation clock does not exceed a threshold clock;
responding to network data information comprising a high-precision time synchronization protocol data packet and a synchronous Ethernet data packet, and determining a second compensation clock and a first synchronization frequency difference according to the network data information;
performing time coarse alignment according to the first synchronous frequency difference until the second compensation clock does not exceed a threshold clock;
determining a third compensation clock according to the network data information received after the time coarse alignment;
and regulating the output clock according to the third compensation clock so as to realize clock synchronization.
Further, the adjusting according to the third compensation clock, and determining the output clock includes:
responsive to the third compensation clock exceeding a predetermined time, frequency modulating and then phase modulating the output clock according to the third compensation clock;
in response to the third compensation clock not exceeding a predetermined time, phase modulating the output clock according to the third compensation clock.
Further, the method further comprises:
in response to the network data information being lost, the output clock is maintained to achieve clock conservation.
Further, the method further comprises:
calculating the average value of the historical synchronous frequency difference corresponding to the first synchronous frequency difference and the network data information received in the previous period;
and responding to the network data information loss, and adjusting the output clock according to the average value so as to achieve clock timekeeping.
Further, the method further comprises:
responding to the network data information comprising high-precision time synchronization protocol data packets and synchronous Ethernet data packets which are lost;
and adjusting the phase-locked loop module according to the synchronous frequency difference average value to achieve clock conservation.
Further, adjusting the output clock according to the third compensation clock includes:
the output clock is subjected to frequency modulation and/or phase modulation through a phase-locked loop module.
Further, the method further comprises: clock synchronization is resumed in response to network data information recovery.
In a second aspect, an embodiment of the present invention provides an open wireless unit, including:
a phase-locked loop module;
the control module is configured to analyze the received network data information, acquire a corresponding compensation clock and/or synchronization frequency difference, and control the phase-locked loop module to jointly complete the clock synchronization method according to the first aspect;
a photoelectric conversion module configured to convert a signal input to the open wireless unit from an optical signal to an electrical signal, generate and transmit the network data information to the control module;
a clock generation module configured to provide a reference clock to the phase-locked loop module;
a signal transceiver module configured to down-convert demodulation or up-convert debugging of a received or transmitted signal;
and the power conversion module is configured to supply power to each module in the open wireless unit.
Further, the control module includes:
the servo transmission unit is configured to control the phase-locked loop unit in the phase-locked loop module to carry out clock adjustment and receive a second pulse signal fed back by the phase-locked loop unit in the phase-locked loop module to complete clock synchronization;
and the port physical layer unit is configured to receive the network data information and send the network data information to the servo transmission unit.
In a third aspect, an embodiment of the present invention provides an open radio access network structure, where the open radio access network structure includes a clock synchronization open distribution unit and an open radio unit, where the open distribution unit and the open radio unit perform clock synchronization based on any one of the clock synchronization methods described in the first aspect.
The method comprises the steps of analyzing received network data information, determining a corresponding coarse alignment mode of clock synchronization based on the type of the analyzed data packet, wherein when the analyzed data packet only comprises a PTP data packet, performing clock coarse alignment through corresponding clock compensation parameters, when the analyzed data packet comprises the PTP data packet and a SyncE data packet, performing coarse alignment through corresponding synchronization frequency difference of the SyncE data packet, and performing frequency modulation or phase modulation on an output clock according to the clock compensation parameters corresponding to the received network data information after clock coarse alignment to realize clock synchronization. Therefore, the embodiment of the invention can realize time transmission and clock synchronization through PTP or PTP+SyncE, simplify the time synchronization configuration of the O-RU and the O-RAN, and improve the applicability of the O-RU and the O-RAN.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of a clock-synchronized open wireless unit according to an embodiment of the present application;
FIG. 2 is a flow chart of a clock synchronization method of an embodiment of the present application;
FIG. 3 is a schematic diagram of a clock synchronization application principle of an embodiment of the present application;
FIG. 4 is a schematic diagram of an application principle of a time synchronization process according to an embodiment of the present application;
FIG. 5 is a clock synchronous clock message sending schematic diagram of an embodiment of the present application;
FIG. 6 is a flow chart of clock adjustment of a clock synchronization process of an embodiment of the present application;
FIG. 7 is a flow chart of clock adjustment of a time synchronization process of an embodiment of the present application;
FIG. 8 is a flow chart of a clock conservation method of an embodiment of the present application;
fig. 9 is a schematic diagram of a clock-synchronized open radio access network structure according to an embodiment of the present application.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Meanwhile, it should be understood that in the following description, "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like in the description are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
The related art generally realizes clock synchronization by means of PTP (PTP, precision Time Protocol, high precision clock synchronization protocol), or SyncE (Synchronous Ethernet ), or ptp+synce, which has higher precision. Meanwhile, the PTP message and the SyncE clock can be transmitted through the network data packet, and the PTP message and the SyncE clock can share a cable with the network for receiving and transmitting data without erecting an extra cable for time synchronization. However, since the clock synchronization protocols supported by different stations may be different, for example, some stations only support PTP protocol, and some stations may support ptp+synce, which makes the configuration of the clock synchronization scheme in the O-RAN complicated. Therefore, the embodiment provides a clock synchronization method, an open wireless unit and a radio access network structure to realize clock synchronization, simplify time synchronization configuration of an O-RU and an O-RAN, and improve applicability of the O-RU and the O-RAN.
Fig. 1 is a schematic diagram of a clock-synchronized open wireless unit according to an embodiment of the present invention.
As shown in fig. 1, the clock synchronization open wireless unit according to the embodiment of the present invention includes a photoelectric conversion module 100, a control module 110, a phase-locked loop module 120, a signal transceiver module 130, a clock generation module 140, and a power conversion module 150. The photoelectric conversion module 100 is configured to convert a signal input to the open wireless unit from an optical signal to an electrical signal, obtain and send network data information to the control module 110. The control module 110 is configured to parse the received network data information, and when the corresponding base station only has a clock synchronization function (that is, PTP), it can parse to obtain a high-precision time synchronization protocol data packet. And when the corresponding base station has a clock synchronization function (PTP) and an Ethernet synchronization function (SyncE), the high-precision time synchronization protocol data packet and the synchronous Ethernet data packet can be obtained by analysis.
Further, the high-precision time synchronization protocol data packet includes a delay_req message, a Sync message, a follow_up message, and a delay_response message. The Sync message includes the estimated time of the message sending time of the master clock. After the Sync message is sent, the master clock sends a Follow_Up message, wherein the Follow_Up message contains the accurate time of the message sending time of the master clock. The delay Req message is sent by the slave clock, which contains the exact time the message left the slave clock. The delay_response message contains the exact time value of the moment the master clock receives the message.
Further, when the corresponding base station only has a clock synchronization function (that is, PTP), the control module 110 is a high-precision time synchronization protocol packet for the acquired network data information. Further, the control module 110 analyzes the data information in the high-precision time synchronization protocol data packet, and determines the first compensation clock according to the accurate time values of the send-receive packet included in the delay_req packet, the Sync packet, the follow_up packet, and the delay_response packet, and performs coarse alignment on the clock according to the first compensation clock, for example, for time deviation above seconds, the first compensation clock is directly processed in the timestamp processing process until the first compensation clock does not exceed the threshold clock. In this embodiment, after the coarse alignment of the clocks is completed, fine adjustment of the clocks is performed to achieve clock synchronization.
Further, the clock fine adjustment may specifically be: and determining a third compensation clock according to the network data information received after the time coarse alignment, and sending the third compensation clock to the phase-locked loop module 120 as a control signal. At the same time, the control module 110 sends a PTP packet to the phase-locked loop module 120, where the PTP packet includes the reference value T1 required for fine tuning. The reference value T1 is used for comparing with the third compensation clock and judging the accurate result of clock synchronization after the clock synchronization is roughly aligned. The phase-locked loop module 120 adjusts the output clock according to the third compensation clock output by the control module 110 according to the comparison result, so as to realize clock synchronization.
When the corresponding base station has a clock synchronization function (PTP) and an ethernet synchronization function (SyncE), the control module 110 analyzes the acquired network data information, and may obtain a high-precision time synchronization protocol data packet and a synchronous ethernet data packet. The control module 110 sends the reference clock contained in the synchronous ethernet packet to the phase-locked loop module 120. The pll module 120 may determine synchronization frequency difference information according to the reference clock provided by the clock generating module 140 and the reference clock obtained by the control module 110 analyzing the synchronous ethernet packet.
Further, the control module 110 analyzes the data information in the high-precision time synchronization protocol data packet, and can determine the second compensation clock through accurate time values of the transceiving messages included in the delay_req message, the Sync message, the follow_up message, and the delay_response message. The pll module 120 performs time coarse alignment according to the first synchronization frequency difference until the second compensation clock does not exceed a threshold clock. In this embodiment, after the coarse alignment of the clocks is completed, fine adjustment of the clocks is performed to achieve clock synchronization.
Further, the clock fine adjustment may specifically be: a third compensation clock is determined according to the network data information received after the coarse alignment of time, and the third compensation clock is sent to the phase-locked loop module 120. The phase-locked loop module 120 adjusts the output clock according to the third compensation clock output by the control module 110, so as to achieve the purpose of clock synchronization.
Further, the signal transceiver module 130 in the clock-synchronized open wireless unit is configured to perform down-conversion demodulation or up-conversion debugging on the received or transmitted signal. And the power conversion module is configured to supply power to each module in the open wireless unit.
According to the embodiment of the invention, the received network data information is analyzed, and the corresponding coarse alignment mode of clock synchronization is determined based on the analyzed data packet type, wherein when the analyzed data packet only comprises a PTP data packet, the clock coarse alignment is performed through the corresponding clock compensation parameter, when the analyzed data packet comprises the PTP data packet and a Sync E data packet, the coarse alignment is performed through the corresponding synchronous frequency difference of the Sync data packet, and then the output clock is subjected to frequency modulation or phase modulation according to the clock compensation parameter corresponding to the received network data information after the clock coarse alignment, so that the clock synchronization is realized. Therefore, the embodiment of the invention can realize time transmission and clock synchronization through PTP or PTP+SyncE, simplify the time synchronization configuration of the O-RU and the O-RAN, and improve the applicability of the O-RU and the O-RAN.
Fig. 2 is a flowchart of a clock synchronization method of an embodiment of the present application. In this embodiment, the clock synchronization method includes the steps of:
step S210, receiving network data information.
Specifically, in this embodiment, the received network data information is analyzed, and when the corresponding base station only has the clock synchronization function (that is, PTP), a high-precision time synchronization protocol data packet can be obtained by analysis. When the corresponding base station has a clock synchronization function (PTP) and an Ethernet synchronization function (SyncE), a high-precision time synchronization protocol data packet and a synchronous Ethernet data packet can be obtained by analysis.
The high-precision time synchronization protocol data packet comprises a Dely_Req message, a Sync message, a Follow_up message and a Dely_response message. The Sync message includes the estimated time of the message sending time of the master clock. After the Sync message is sent, the master clock sends a Follow_up message, wherein the Follow_up message contains the accurate time of the message sending time of the master clock. The delay Req message is sent by the slave clock, which contains the exact time the message left the slave clock. The delay_response message contains the exact time value of the moment the master clock receives the message. The synchronous ethernet packet includes a synchronous ethernet clock (i.e., a reference clock). The synchronous ethernet packets include corresponding reference clocks.
Step S220, in response to the network data information including the high-precision time synchronization protocol data packet, determining a first compensation clock according to the high-precision time synchronization protocol.
Fig. 3 is a schematic diagram of a clock synchronization application principle according to an embodiment of the present application. The clock synchronization application principle is applied when the corresponding base station only has a clock synchronization function (namely, PTP).
As shown in fig. 3, in the embodiment of the present invention, the control module 310 includes a port physical layer (PHY) unit 311, a medium access control sublayer (MAC) unit 312, a Servo (Servo) unit 313, a 1588Stack unit 314, a Time Stamp Engine unit 315, and a 1588Timer unit 316. Among them, a port physical layer (PHY) unit 311, a medium access control sublayer (MAC) unit 312 are used to realize data transmission. The 1588Stack unit 314 and the 1588Timer unit 316 are used for implementing 1588 protocol processing, and the Time Stamp Engine unit 315 is used for performing timestamp processing (such as time stamping, etc.). A Servo drive (Servo) unit 313 is used to effect control of the phase-locked loop module.
Further, the port physical layer unit 311 is configured to receive the network data information and send the network data information to the servo drive unit. The servo transmission unit 313 is configured to control the pll unit in the pll module 320 to perform clock adjustment, and receive the second pulse signal fed back by the pll unit in the pll module 320 to perform clock synchronization.
In an alternative implementation, the present embodiment may initiate the Holdover mode of configuring the phase-locked loop module 320. The Holdover mode of the phase-locked loop module 320 may be such that clock stability is maintained when the clocks are switched. It should be appreciated that the present embodiment is not limited to the Holdover mode of the phase-locked loop module 320, and may be configured according to the specific application.
The pll module 320 in the embodiment of the present invention includes a first pll unit 321 and at least one pll unit 322. The network data information comprises a high-precision time synchronization protocol data packet, wherein the high-precision time synchronization protocol data packet comprises a delay_req message, a Sync message, a follow_Up message and a delay_response message. The Sync message includes the estimated time of the message sending time of the master clock. After the Sync message is sent, the master clock sends a Follow_Up message, wherein the Follow_Up message contains the accurate time of the message sending time of the master clock. The delay Req message is sent by the slave clock, which contains the exact time the message left the slave clock. The delay_response message contains the exact time value of the moment the master clock receives the message. The 1588Stack unit 314, time Stamp Engine unit 315 and 1588Timer unit 316 are configured to participate in clock synchronization together, wherein the 1588Stack unit 314 and 1588Timer unit 316 are configured to implement 1588 protocol processing, and the Time Stamp Engine unit 315 is configured to perform time stamping processing (e.g., time stamping, etc.). The first phase locked loop unit 321 is configured in a voltage controlled oscillator mode. The first pll unit 321 is further configured to receive the control signal and information in the high-precision time synchronization protocol data packet sent by the Servo unit 313, and send the output second pulse signal to the corresponding control module 310 and each pll unit 322.
Further, fig. 5 is a schematic diagram of clock synchronous clock packet transmission according to an embodiment of the present application. As shown in fig. 5, the Sync message includes the estimated time of the master clock sending the message. After the Sync message is sent, the master clock sends a Follow_up message, the precise time when the messages contained in the Sync message and the Follow_up message leave the master clock is T1, and the slave clock records the precise time T2 when the Sync message reaches the slave clock. The delay_req message is sent by the slave clock, which contains the exact time T3 when the message leaves the slave clock, while the master clock records that the delay_req message reaches the exact time T4 of the slave clock. The master clock sends a delay_response message containing T4 to the slave clock.
Further, determining a first compensation clock (T) according to the accurate time contained in each message in the high-accuracy time synchronization protocol adj )。
Step S230, performing time coarse alignment according to the first compensation clock until the first compensation clock does not exceed a threshold clock.
Specifically, according to the first compensation clock T adj The clocks are roughly aligned, and the purpose of preliminarily eliminating the output clock deviation is achieved. Compensation clock T adj And determining the accurate time contained in each message in the high-precision time synchronization protocol after the clocks are roughly aligned. The compensation clock T adj The determining method is consistent with the first compensating clock determining method, and the precise time contained in each message in the high-precision time synchronization protocol is different. Alternatively, step S230 may be performed a plurality of times until the compensation clock T adj The threshold clock is not exceeded, and the threshold clock is a preset value. Optionally, the smaller the threshold clock, the more accurate the clock synchronization but the same increase in the cycle number, and the larger the threshold clock, the less the clock synchronization cycle number decreasesBut the accuracy can be reduced, and threshold clock setting can be performed according to different requirements, so that the requirements of each accuracy and clock synchronization cycle times are met.
That is, in the present embodiment, coarse alignment is performed by the compensation clock corresponding to the received network data information in response to the corresponding station having only the PTP clock synchronization function.
Step S240 determines a second compensation clock and a first synchronization frequency difference according to the network data information in response to the network data information including the high precision time synchronization protocol data packet and the synchronization ethernet data packet.
Fig. 4 is a schematic diagram of an application principle of a clock synchronization process according to an embodiment of the present application. The application principle of the clock synchronization process is applied when the corresponding base station has a clock synchronization function (PTP) and an ethernet synchronization function (SyncE).
As shown in fig. 4, in the embodiment of the present invention, the control module 410 includes a port physical layer (PHY) unit 411, a medium access control sublayer (MAC) unit 412, a Servo (Servo) unit 413, a 1588Stack unit 414, a Time Stamp Engine unit 415, and a 1588Timer unit 416. The pll module 420 in the embodiment of the present invention includes a first pll unit 421 and at least one pll unit 422. The reference clock provided by the clock generation module 430. Among them, a port physical layer (PHY) unit 411, a medium access control sublayer (MAC) unit 412 are used to realize data transmission. The 1588Stack unit 414 and the 1588Timer unit 416 are used for implementing 1588 protocol processing, and the Time Stamp Engine unit 415 is used for performing time stamping processing (such as time stamping, etc.). A Servo drive (Servo) unit 413 is used to implement control of the phase locked loop module.
Further, the port physical layer unit 411 is configured to receive network data information and send the network data information to the servo drive unit. The servo transmission unit 414 is configured to control the pll unit in the pll module 420 to perform clock adjustment, and receive the second pulse signal fed back by the pll unit in the pll module 420 to complete clock synchronization.
The PHY unit 411 in the control module 410 is configured to receive network data information and transmit the network data information to the MAC unit 412. The network data information includes high precision time synchronization protocol data packets and synchronous ethernet data packets. The control module 410 parses the synchronous ethernet packet to obtain a reference clock and sends the reference clock to at least one synchronous pll unit 422 in the pll module 420. The pll unit 422 may determine synchronization frequency difference information according to the reference clock provided by the clock generation module 430 and the reference clock obtained by the control module 410 analyzing the synchronous ethernet packet, and send the synchronization frequency difference information to the first pll unit 421.
Step S250 performs time coarse alignment according to the first synchronization frequency difference until the second compensation clock does not exceed a threshold clock.
Specifically, the clocks are roughly aligned according to the synchronous frequency difference, so that the purpose of preliminarily eliminating the output clock deviation is achieved. The second compensation clock T adj The clock is roughly aligned and then is determined by accurate time values of receiving and transmitting messages contained in a Dely_Req message, a Sync message, a Follow_Up message and a Dely_Response message in a high-precision time synchronization protocol. Alternatively, step S240 may be performed multiple times until the compensation clock T adj The threshold clock is not exceeded, and the threshold clock is a preset value. Optionally, the smaller the threshold clock is, the more accurate the clock synchronization is, but the cycle number is also increased, the larger the threshold clock is, the clock synchronization cycle number is reduced, but the accuracy is reduced, and the threshold clock can be set according to different requirements, so that the requirements of each accuracy and the clock synchronization cycle number are met.
Step S260 determines a third compensation clock according to the network data information received after the time coarse alignment.
Specifically, when the corresponding base station has only the clock synchronization function (PTP) or the corresponding base station has the clock synchronization function (PTP) and the ethernet synchronization function (SyncE), the third compensation clock is determined by performing the same calculation as the first compensation clock or the second compensation clock according to the packet in the high-precision time synchronization protocol packet included in the clock with which the clock coarse alignment is completed.
Step S270 adjusts the output clock according to the third compensation clock to achieve clock synchronization.
Specifically, in response to the third compensation clock exceeding a predetermined time, the output clock is frequency modulated and then phase modulated according to the third compensation clock. In response to the third compensation clock not exceeding a predetermined time, phase modulating the output clock according to the third compensation clock.
That is, the determined third compensation clock is sent to the Servo unit in the control module, and the Servo unit modulates the frequency and/or phase of the first pll unit in the pll module. And judging whether the third compensation clock exceeds T1, wherein T1 is the accurate time when a Sync message contained in the Follow_Up message leaves the master clock. If the third compensation clock exceeds T1, the clock synchronization is not accurate enough, and the output clock needs to be frequency modulated and then phase modulated to complete the clock synchronization. Conversely, if the third compensated clock does not exceed T1, it is only necessary to phase modulate the output clock to achieve clock synchronization.
Fig. 6 is a flow chart of clock adjustment of the clock synchronization process of an embodiment of the present application.
The clock adjustment of the clock synchronization procedure when the corresponding base station has only a clock synchronization function (i.e. PTP) is shown in fig. 6.
Specifically, the clock adjustment of the clock synchronization process is divided into coarse adjustment and fine adjustment, and the clock synchronization process is a closed loop cycle process. The decision to coarsely adjust or finely adjust the clock is made by determining whether the compensated clock exceeds a threshold clock. A coarse adjustment in response to the compensated clock exceeding a threshold clock, the coarse adjustment comprising the steps of:
at step 610, network data information is received.
And step 620, analyzing the network data information to obtain a high-precision time synchronization protocol data packet.
The analyzed high-precision time synchronization protocol data packet comprises a Dely_Req message, a Sync message, a Follow_Up message and a Delay_response message.
Step 630, a compensation clock is determined.
The method for determining the compensation clock is calculated by using accurate time values of the receiving and transmitting messages contained in the delay_req message, the Sync message, the Follow_Up message and the delay_response message. The specific calculation process is similar to the above embodiment, and will not be described here again.
Step 640, determine if the compensated clock exceeds a threshold clock.
Determining that the compensated clock exceeds the threshold clock proceeds to step 650 where a coarse alignment of clocks is performed based on the compensated clock.
Determining that the compensated clock does not exceed the threshold clock proceeds to step 660 where clock adjustment is performed based on the compensated clock.
In step S650, in the current network data information receiving period, if the corresponding compensation clock exceeds the threshold clock, coarse clock alignment is performed according to the compensation clock. For example, for time deviations above seconds, a coarse alignment operation is employed that is processed directly in the time stamp processing process.
After the coarse alignment operation is performed, step S610 is continuously performed to receive the network data information, so as to determine whether the compensation clock corresponding to the network data information after the coarse alignment of the clock in the previous period exceeds the threshold clock in the current network data information receiving period, if yes, coarse alignment is continuously performed until the compensation clock corresponding to the received network data information does not exceed the threshold clock, and step S660 is performed.
Step S660, performing clock adjustment according to the compensation clock. It should be understood that the clock adjustment of the present embodiment is similar to the phase-locked loop module adjustment principle shown in fig. 3, and will not be described herein.
Therefore, in this embodiment, when the corresponding base station only has the clock synchronization function (that is, PTP), the corresponding compensating clock corresponding to the PTP data packet in the received network data information is aligned by Zhong Cu, and fine tuning is performed based on the phase-locked loop module, so as to achieve clock synchronization, which improves clock synchronization efficiency.
Fig. 7 is a flow chart of clock adjustment of a clock synchronization process of an embodiment of the present application.
The clock adjustment of the clock synchronization process when the corresponding base station has only a clock synchronization function (PTP) and an ethernet synchronization function (SyncE) is shown in fig. 7.
Specifically, the clock adjustment of the clock synchronization process is divided into coarse adjustment and fine adjustment, and the clock synchronization process is a closed loop cycle process. The decision to coarsely adjust or finely adjust the clock is made by determining whether the compensated clock exceeds a threshold clock. A coarse adjustment in response to the compensated clock exceeding a threshold clock, the coarse adjustment comprising the steps of:
step 710, network data information is received.
And step 720, analyzing the network data information to obtain a high-precision time synchronization protocol data packet and a synchronous Ethernet data packet.
The high-precision time synchronization protocol data packet comprises a Dely_Req message, a Sync message, a Follow_Up message and a Delay_response message, and the synchronous Ethernet data packet comprises a reference clock.
In step 730, the offset clock and synchronization frequency difference is determined.
The method for determining the compensation clock is calculated by using accurate time values of the receiving and transmitting messages contained in the delay_req message, the Sync message, the Follow_Up message and the delay_response message. The synchronous frequency difference determining method is obtained by comparing a reference clock with a reference clock. The specific calculation process is similar to the above embodiment, and will not be described here again.
Step 740, determine if the compensated clock exceeds a threshold clock.
Determining that the compensated clock exceeds the threshold clock proceeds to step 750, where coarse alignment of the clocks is performed according to the synchronization frequency difference.
Determining 760 that the compensated clock does not exceed the threshold clock, performing clock adjustment based on the compensated clock.
Step S750, in the current network data information receiving period, if the corresponding compensation clock exceeds the threshold clock, performing coarse clock alignment according to the synchronous frequency difference.
After the coarse alignment operation is performed, step S710 is continuously performed to receive the network data information, so as to determine whether the compensation clock corresponding to the network data information after the coarse alignment of the clock in the previous period exceeds the threshold clock in the current network data information receiving period, and if the compensation clock exceeds the threshold clock, coarse alignment is performed again according to the synchronization frequency difference of the current period until the compensation clock corresponding to the received network data information does not exceed the threshold clock, and step S760 is performed.
Step S760, performing clock adjustment according to the compensation clock. It should be understood that the clock adjustment of this embodiment is similar to the phase-locked loop module adjustment principle shown in fig. 4, and will not be described here again.
Therefore, in this embodiment, when the corresponding base station has a clock synchronization function (PTP) and an ethernet synchronization function (SyncE), the synchronization frequency difference is determined by the reference clock in the synchronized ethernet packet in the received network data information and the reference clock provided by the clock generation module, and the clock coarse alignment is performed by using the synchronization frequency difference. And then fine tuning is performed based on the phase-locked loop module to realize clock synchronization, which improves clock synchronization efficiency.
According to the clock synchronization method, the received network data information can be analyzed, the corresponding coarse alignment mode of clock synchronization is determined based on the type of the analyzed data packet, wherein when the analyzed data packet only comprises the PTP data packet, the clock coarse alignment is performed through the corresponding clock compensation parameter, when the analyzed data packet comprises the PTP data packet and the Sync data packet, the coarse alignment is performed through the corresponding synchronization frequency difference of the Sync data packet, and then the output clock is subjected to frequency modulation or phase modulation according to the clock compensation parameter corresponding to the received network data information after the clock coarse alignment, so that the clock synchronization is realized. Therefore, the embodiment of the invention can realize time transmission and clock synchronization through PTP or PTP+SyncE, simplify the time synchronization configuration of the O-RU and the O-RAN, and improve the applicability of the O-RU and the O-RAN.
Further, there may be a case where network data information is lost in the clock synchronization process.
When the corresponding base station only has a clock synchronization function (PTP), responding to the network data information loss, maintaining the output clock to achieve clock timekeeping, wherein the maintaining of the output clock means maintaining the frequency of the output clock unchanged so as to realize time transmission between the O-RU and the O-DU and clock synchronization.
Fig. 8 is a flow chart of a clock conservation method of an embodiment of the present application.
When the corresponding base station has a clock synchronization function (PTP) and an ethernet synchronization function (SyncE), as shown in fig. 8, the clock timing step includes:
step 810, calculating a mean value of the historical synchronization frequency difference corresponding to the first synchronization frequency difference and the network data information received in the previous period.
Specifically, when the corresponding base station has a clock synchronization function (PTP) and an ethernet synchronization function (SyncE), a first synchronization frequency difference generated between the reference clock and the reference clock can be obtained in each clock coarse alignment period and each clock fine adjustment period in the clock synchronization process. And calculating the average value of the first synchronization frequency difference and the historical synchronization frequency difference corresponding to the network data information received in the previous period.
And step 820, in response to the network data information loss, adjusting the output clock according to the average value to achieve clock conservation.
Specifically, the average value of the obtained synchronous frequency difference is sent to at least one synchronous phase-locked loop unit, and clock time keeping is performed through the average value of the synchronous frequency difference. The clock time keeping is carried out through the synchronous frequency difference average value, so that the clock frequency synchronization can be better kept when the network data information is lost, and unstable special events such as clock frequency hopping and the like are prevented from being generated. By the method, when the corresponding base station has a clock synchronization function (PTP) and an Ethernet synchronization function (SyncE) and network data information is lost, the output clock is kept, and meanwhile, the synchronization frequency difference average value is utilized to carry out more accurate clock time keeping so as to realize time transmission between the O-RU and the O-DU and clock synchronization.
Fig. 9 is a schematic diagram of a clock-synchronized open radio access network structure according to an embodiment of the present application.
In particular, as a communication network, time synchronization needs to be implemented between node units in the network, so that low delay of data interacted with users can be ensured. Time synchronization is also required between the O-RU and the O-DU. As shown in fig. 9, the open distribution unit 910 and the open wireless unit 920 may perform time or clock transfer and synchronization through PTP or ptp+synce. The above method for clock synchronization and time keeping based on a single O-RU can also be applied to O-DUs.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method of clock synchronization, the method comprising:
receiving network data information;
determining a first compensation clock according to a high-precision time synchronization protocol in response to the network data information including the high-precision time synchronization protocol data packet;
performing time coarse alignment according to the first compensation clock until the first compensation clock does not exceed a threshold clock;
responding to network data information comprising a high-precision time synchronization protocol data packet and a synchronous Ethernet data packet, and determining a second compensation clock and a first synchronization frequency difference according to the network data information;
performing time coarse alignment according to the first synchronous frequency difference until the second compensation clock does not exceed a threshold clock;
determining a third compensation clock according to the network data information received after the time coarse alignment;
and regulating the output clock according to the third compensation clock so as to realize clock synchronization.
2. The method of claim 1, wherein the adjusting according to the third compensation clock, determining an output clock comprises:
responsive to the third compensation clock exceeding a predetermined time, frequency modulating and then phase modulating the output clock according to the third compensation clock;
in response to the third compensation clock not exceeding a predetermined time, phase modulating the output clock according to the third compensation clock.
3. The method according to claim 1, wherein the method further comprises:
in response to the network data information being lost, the output clock is maintained to achieve clock conservation.
4. The method according to claim 1, wherein the method further comprises:
calculating the average value of the historical synchronous frequency difference corresponding to the first synchronous frequency difference and the network data information received in the previous period;
and responding to the network data information loss, and adjusting the output clock according to the average value so as to achieve clock timekeeping.
5. The method according to claim 1, wherein the method further comprises:
responding to the network data information comprising high-precision time synchronization protocol data packets and synchronous Ethernet data packets which are lost;
and adjusting the phase-locked loop module according to the synchronous frequency difference average value to achieve clock conservation.
6. The method of claim 1, wherein adjusting the output clock according to the third compensation clock comprises:
the output clock is subjected to frequency modulation and/or phase modulation through a phase-locked loop module.
7. The method according to claim 3 or 4, characterized in that the method further comprises:
clock synchronization is resumed in response to network data information recovery.
8. An open wireless unit, comprising:
a phase-locked loop module;
the control module is configured to analyze the received network data information, acquire a corresponding compensation clock and/or synchronization frequency difference, and control the phase-locked loop module to jointly execute the clock synchronization method according to any one of claims 1-7;
the photoelectric conversion module is configured to convert a signal input into the open wireless unit from an optical signal into an electric signal, acquire and send the network data information to the control module;
a clock generation module configured to provide a reference clock to the phase-locked loop module;
a signal transceiver module configured to down-convert demodulation or up-convert debugging of a received or transmitted signal;
and the power conversion module is configured to supply power to each module in the open wireless unit.
9. The open wireless unit of claim 8, wherein the control module comprises:
the servo transmission unit is configured to control the phase-locked loop unit in the phase-locked loop module to perform clock adjustment and receive a second pulse signal fed back by the phase-locked loop unit in the phase-locked loop module to complete clock synchronization;
and the port physical layer unit is configured to receive the network data information and send the network data information to the servo transmission unit.
10. An open radio access network architecture comprising a clock-synchronized open distribution unit and an open wireless unit, wherein the open distribution unit and the open wireless unit are clock synchronized based on a clock synchronization method as claimed in any one of claims 1-7.
CN202310396287.3A 2023-04-13 2023-04-13 Clock synchronization method, open wireless unit and radio access network structure Pending CN116528347A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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