CN116526819A

CN116526819A - Computing node and computing device

Info

Publication number: CN116526819A
Application number: CN202310316172.9A
Authority: CN
Inventors: 李振华; 童建利; 任海; 王彦斌
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2023-08-01

Abstract

The embodiment of the application discloses a computing node and computing equipment, wherein the computing node comprises a power supply, a slow start circuit and a load; the slow start circuit comprises a first switch tube, a charge pump, a first driving circuit and a hot plug controller; the first driving circuit includes a transistor; the hot plug controller is used for outputting a first control signal to the first driving circuit; the charge pump is used for amplifying the power supply input voltage to obtain a driving voltage and outputting the driving voltage to the first driving circuit; the first driving circuit is used for outputting a second control signal to the first switching tube according to the first control signal; the second control signal is used for controlling the working state of the first switching tube. The transistor of the first driving circuit is used for amplifying the first control signal to obtain a second control signal with larger current so as to drive the first switching tube, so that the starting time of the slow starting circuit can be shortened, the selectable range of the MOS tube in the slow starting circuit is enlarged, and the flexibility of the slow starting circuit design is improved.

Description

Computing node and computing device

Technical Field

The application relates to the technical field of power supplies, in particular to a computing node and computing equipment.

Background

In order to ensure the safe and reliable power supply of the load in the server, a slow start circuit is usually arranged between the power supply and the load. The surge current impact caused by hot plug of load equipment is relieved through the slow start circuit, so that the problem that the surge current greatly reduces the bus voltage or damages devices on a power supply circuit is avoided.

In the prior art, in order to make the start time of the slow start circuit meet the corresponding start requirement, MOS transistors with smaller parasitic capacitance are generally required to be adopted in the slow start circuit, or the number of MOS transistors connected in parallel is reduced, so as to shorten the start time. However, such a solution would limit the possibilities of circuit design.

Disclosure of Invention

The embodiment of the application provides a computing node and computing equipment, which can enlarge the selectable range of a MOS tube and improve the flexibility of circuit design while shortening the starting time by enhancing the driving capability of the MOS tube in a slow starting circuit.

A first aspect of the present application provides a computing node comprising a power supply, a slow start circuit, and a load;

the slow start circuit comprises a first switch tube, a charge pump, a first driving circuit and a hot plug controller; wherein the first driving circuit includes a transistor; the first end of the first switch tube and the input end of the charge pump are coupled with the output end of the power supply; the second end of the first switch end is coupled with a load; the output end of the charge pump is coupled with the first end of the transistor; the second end of the transistor is coupled with the third end of the first switch tube; the third end of the transistor is coupled with the control signal output end of the hot plug controller;

The hot plug controller is used for outputting a first control signal to the first driving circuit; the charge pump is used for amplifying the power supply input voltage to obtain a driving voltage and outputting the driving voltage to the first driving circuit; the first driving circuit is used for outputting the second control signal to the first switch tube according to the first control signal; the second control signal is used for controlling the working state of the first switching tube.

In the application, under the condition that the charge pump provides driving voltage for the first driving circuit, the first driving circuit can amplify the first control signal output by the hot plug controller and output the second control signal with larger current to the first switching tube, so that the starting time of the slow starting circuit is shortened. Meanwhile, the short starting time brought by the second control signal with larger current can meet the requirement of higher safe starting time, and the design scheme of the slow starting circuit can select MOS (metal oxide semiconductor) tubes with larger parasitic capacitance and/or more MOS tubes, so that the selectable range of the MOS tubes in the design scheme of the slow starting circuit is enlarged, and the flexibility of the design of the slow starting circuit is improved.

In one possible implementation, the charge pump includes a timing circuit and a boost circuit; the first input end of the boost circuit is coupled with the power supply, the second input end of the boost circuit is coupled with the output end of the timing circuit, and the output end of the boost circuit is coupled with the first end of the transistor; the timing circuit is used for sending pulse signals to the boost circuit; the boost circuit is used for amplifying the power input voltage according to the pulse signal.

In this application, through setting up the charge pump that timing circuit and boost circuit constitute simple structure, can reduce the cost, reduce simultaneously to the occupation of circuit design space.

In one possible implementation, the timing circuit includes a first power supply, a timer, a first resistor, a second resistor, a first diode, a second diode, and a first capacitor; wherein, the first end of the first resistor is coupled with the first power supply; the second end of the first resistor, the first end of the second resistor and the anode of the first diode are coupled with the discharge end of the timer; the second end of the second resistor is coupled with the cathode of the second diode; the cathode of the first diode, the anode of the second diode and the first end of the first capacitor are coupled with the input end of the timer; the second end of the first capacitor is coupled with the ground end of the timer; the output of the timer is coupled to the second input of the boost circuit.

In this application, through setting up timer, two resistance, two diodes, a capacitor constitution timing circuit, can reduce the cost, reduce simultaneously the occupation to circuit design space.

In one possible implementation, the charge pump includes a processor, a second drive circuit, and a boost circuit; the output end of the processor is coupled with the input end of the second driving circuit; the first input end of the boost circuit is coupled with the power supply, the second input end of the boost circuit is coupled with the output end of the second driving circuit, and the output end of the boost circuit is coupled with the first end of the transistor; the processor is used for sending pulse signals to the second driving circuit; the second driving circuit is used for amplifying the pulse signal and outputting the amplified pulse signal to the boosting circuit; the booster circuit is used for amplifying the power supply input voltage according to the amplified pulse signal.

In the application, the processor on the circuit board where the slow start circuit is located can be externally connected with the driving chip and the booster circuit to form the charge pump, and the existing processor on the circuit board is used as a pulse signal source of the charge pump to control the charge pump to work, so that the cost and the circuit design space can be saved.

In one possible implementation, the second driving circuit includes a second power supply and a driving chip; the power supply end of the driving chip is coupled with the second power supply; the output end of the processor is coupled with the input end of the driving chip; the output end of the driving chip is coupled with the second input end of the boost circuit; the grounding end and the heat dissipation end of the driving chip are coupled to the ground.

In the application, the pulse signal of the processor is amplified through the driving chip, so that the situation that the processor directly drives the booster circuit to cause overheat damage can be avoided.

In one possible implementation, the boost circuit includes a third diode, a fourth diode, a second capacitor, and a third capacitor; wherein, the anode of the third diode is coupled with the output end of the power supply; the cathode of the third diode is coupled with the first end of the second capacitor and the anode of the fourth diode; the second end of the second capacitor is coupled with a pulse signal source; the cathode of the fourth diode is coupled with the first end of the third capacitor and the first end of the transistor; the second end of the third capacitor is coupled to ground.

In this application, through setting up two diodes and two electric capacity constitution boost circuit, can reduce the cost, reduce simultaneously the occupation to circuit design space.

In one possible implementation, the transistor is any one of the following crystals: a transistor, a MOS transistor, a gallium nitride transistor, or a silicon carbide transistor.

In the application, different types of transistors can be set according to the characteristics of the first control signals sent by different hot plug controllers so as to obtain the second control signals with larger current.

In one possible implementation, the first driving circuit further includes a transient voltage suppression diode; the first end of the transient voltage suppression diode is coupled with the second end of the transistor, and the second end of the transient voltage suppression diode is coupled with the third end of the transistor.

In the application, the transient voltage suppression diode is arranged, so that surge power can be absorbed, and the voltage clamp between the second end and the third end of the transistor is positioned at a preset value, thereby effectively protecting devices in the first driving circuit from being damaged by various transient surge pulses.

In one possible implementation, the computing node further includes a fourth capacitance and a zener diode; the first end of the fourth capacitor and the cathode of the zener diode are coupled with the second end of the first switch tube; the second end of the fourth capacitor and the anode of the zener diode are coupled to ground.

In the method, the fourth capacitor is arranged, so that power supply ripples can be filtered, and the energy storage of the fourth capacitor can provide current when a large load occurs, so that the overlarge drop amplitude of power supply voltage is avoided; through setting up zener diode, can play the steady voltage effect to the power supply loop.

A second aspect of the present application provides a computing device comprising a cabinet and a computing node as described in any one of the possible implementations of the first aspect; the computing node is arranged in the cabinet.

It should be appreciated that the implementation and benefits of the various aspects described above may be referenced to one another.

Drawings

FIG. 1 is a schematic diagram of a computing node according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a slow start circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a start-up timing of a slow start circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of parasitic capacitance of a MOS transistor in a slow start circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a computing node according to an embodiment of the present application;

FIG. 6 is a schematic circuit diagram of a slow start circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of another slow start circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic circuit diagram of a charge pump according to an embodiment of the present application;

fig. 9 is a schematic circuit diagram of a charge pump according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some, but not all embodiments of the present application. As a person of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical solutions provided in the embodiments of the present application are applicable to similar technical problems.

The terms "first," "second," and the like in embodiments of the present application are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a computing node according to an embodiment of the present application. The computing node 10 includes a power supply 100, a slow start circuit 200, and a load 300. The output end of the power supply 100 is coupled to the input end of the slow start circuit 200, and the output end of the slow start circuit 200 is coupled to the load 300.

Illustratively, the output of the power supply 100 is coupled to a power bus, the input of the slow start circuit 200 is also coupled to the power bus, and the power supply 100 and the slow start circuit 200 are coupled via the bus.

The power supply 100 is configured to convert an input voltage into a supply voltage; the slow start circuit 200 is used for delaying power supply during hot plug of the load 300, so that the power supply can provide stable power supply for the load.

By way of example, the load 300 may be a Central Processing Unit (CPU), a hard disk, a PCIe (peripheralcomponentinterconnectexpress) card, a fan, and other electrical components. The specific type of load is not limited in the embodiments of the present application.

Illustratively, the computing node 10 includes, but is not limited to, an electronic device having computing functionality, such as a server, a switch, a router, or a minicomputer. The embodiments of the present application are not limited to a particular type of computing device.

The following describes a scenario of an embodiment of the present application taking the computing node 10 as a server node as an example.

In an exemplary whole cabinet server, the whole cabinet server includes a cabinet, a switching power supply and a server node, wherein the switching power supply and the server node are arranged in the cabinet, and an output end of the switching power supply is coupled with a power supply input end of the server node. Specifically, the switching power supply converts an input voltage (including an ac input voltage or a dc input voltage) into a supply voltage and outputs the supply voltage to the bus. The power supply input of the server node is coupled to the bus. The switching power supply is used to provide the server node with the supply voltage required for operation.

The number of server nodes that can be set inside the whole cabinet server can be one or more. The number of server nodes in the embodiment of the present application is not limited.

The server node comprises a case, a power supply, a slow start circuit and a load. The power supply, the slow start circuit and the load are arranged in the case. The input end of the power supply is coupled with a power supply bus of the whole cabinet server, the output end of the power supply is coupled with the input end of the slow starting circuit, and the output end of the slow starting circuit is coupled with the load.

The power supply in the server node may be a dc-dc voltage conversion module, for example, converting the output voltage of the switching power supply to a power supply voltage of the server node, for example, converting a bus voltage of 48V to a power supply voltage of 12V. The servers may also be other types of servers, such as rack servers, high density servers, ai servers, tower servers, and blade servers, for example. Taking a rack server as an example, the rack server comprises a case, and a power supply, a slow start circuit and a load which are arranged in the case. The power supply converts an input voltage (including an ac input voltage or a dc input voltage) into a supply voltage and outputs the supply voltage to the bus. The power supply is illustratively a switching power supply with an output voltage of 12V.

The server node and the server suitable for the rack mount may be collectively referred to as a computing node.

Referring to fig. 2, fig. 2 is a schematic diagram of a slow start circuit, and as shown in fig. 2, the slow start circuit 200 includes a switch circuit 210 and a hot plug controller 220. Wherein the voltage input terminal of the switch circuit 210, the power supply input terminal of the hot plug controller 220, and the output terminal of the power supply 100 are coupled; the control signal output end of the hot plug controller 220 is coupled to the control end of the switch circuit 210; an output of the switching circuit 210 is coupled to an input of the load 300.

In one implementation, the switching circuit 210 may be composed of metal oxide semiconductor (metaloxide semiconductor, MOS) transistors.

The power supply 100 may be configured to supply power to the hot plug controller 220, so that the hot plug controller 220 controls the MOS transistor in the switch circuit 210 to be turned on, so that the electrical energy of the power supply 100 can be delivered to the load 300 through the MOS transistor. The power supply 100 may be a 48V or 12V dc power supply, or may be a battery with an output voltage of 48V or 12V.

Specifically, after the hot plug controller 220 is powered on, a control signal can be sent to the gate of the MOS transistor, so as to control the output current, the output voltage and the on state of the MOS transistor, and realize slow power supply to the load and stable power supply for ensuring safe hot plug of the load.

Referring to fig. 3 and fig. 4, fig. 3 is a schematic diagram illustrating a start-up timing of a slow start circuit according to an embodiment of the present application. The start time of the slow start circuit can be divided into three stages, namely t1, t2 and t3, and two curves in fig. 3 respectively represent the output voltage Vo of the MOS transistor and the gate-source voltage Vgs of the MOS transistor in the slow start circuit.

Fig. 4 is a schematic diagram of a parasitic capacitance structure of a MOS transistor in a slow start circuit according to an embodiment of the present application. As shown in fig. 4, the parasitic capacitance between the gate g and the drain d of the MOS transistor is the gate-drain capacitance Cgd, the parasitic capacitance between the gate g and the source s is the gate-source capacitance Cgs, and the parasitic capacitance between the drain d and the source s is the drain-source capacitance Cds.

The starting time sequence of the slow start circuit will be described below by taking the MOS transistor in FIG. 4 as the MOS transistor in the slow start circuit; in the example of fig. 4, the MOS transistor is an N-type MOS transistor, a drain d thereof is coupled to a power source, a source s is coupled to a load, and a gate g is coupled to a hot plug controller.

Specifically, in the stage t1, the hot plug controller sends a control signal to the gate g, and the source voltage Vs is 0 at this time, so that the control signal is equivalent to charging the gate-source parasitic capacitance Cgs of the MOS transistor, so that the voltage Vgs between the gate and the source of the MOS transistor gradually increases; in the stage t1, vgs gradually rises from 0 to the on voltage Vgs (th) of the MOS transistor, the drain d and the source s of the MOS transistor are in an off state, the drain-source voltage Vds is a power input voltage, and the output voltage Vo is 0.

In the t2 stage, the rising of the gate-source voltage Vgs enables the drain electrode of the MOS tube not to be clamped by the power supply voltage any more, the conducting channel between the drain electrode d and the source electrode s is widened, and the on-resistance is reduced; since the output current is unchanged, the on-resistance decreases, and the drain-source voltage Vds decreases. When the drain-source voltage Vds decreases, the control signal flows to the gate-drain capacitance Cgd, which is also referred to as a miller capacitance; the Vgs voltage is thus kept constant and enters the miller plateau.

Meanwhile, the MOS tube enters a constant current region after being conducted, and the output current Ids depends on Vgs; the slow start circuit can enter a constant current mode or a constant power mode and output constant current or power to ensure that the output voltage Vo rises with a controllable slope.

In the stage t3, the MOS tube enters a variable resistance area, and a control signal simultaneously charges a Miller capacitor Cgd and a gate-source capacitor Cgs, so that Vgs continuously rises; because Vgs is improved, the on-resistance of the MOS tube is further reduced until the Vgs reaches a preset value, the MOS tube is completely conducted, and the slow start circuit is started.

In the slow start process, the start time is positively related to the magnitude of the miller capacitance Cgd and the gate-source capacitance Cgs of the MOS transistor, so when designing the slow start circuit, the time from t1 to t3 in the start time sequence is shortened by adopting the MOS transistor with smaller miller capacitance Cgd and gate-source capacitance Cgs or reducing the number of parallel MOS transistors in the slow start circuit to reduce the capacitance in the slow start circuit; or selecting a MOS tube with a larger Safe Operating Area (SOA), wherein the MOS tube can bear larger starting current to shorten the time of the t2 stage, and can improve the starting time upper limit of the MOS tube under the safety requirement; or designing a slow start circuit according to the maximum bearing capacity indicated by the SOA edge specification of the MOS tube.

However, these methods limit the selectable range of the MOS transistor to different degrees, limiting the possibility of circuit design; in addition, the circuit reliability can be reduced according to the SOA edge specification design scheme of the MOS tube. Therefore, the embodiment of the application provides the computing node, and the slow start circuit in the computing node can shorten the start time, enlarge the selectable range of the MOS tube and improve the response speed of the circuit and the flexibility of design.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a computing node according to an embodiment of the present application. As shown in fig. 5, the computing node 10 includes a power supply 100, a soft start power supply 200, and a load 300.

The slow start circuit 200 includes a first switching tube 210, a hot plug controller 220, a first driving circuit 230, and a charge pump 240. The first driving circuit 230 includes a transistor 231.

The first end of the first switch tube 210 and the input end of the charge pump 240 are coupled to the output end of the power supply 100; a second end of the first switching tube 210 is coupled to the load 300; an output terminal of the charge pump 240 is coupled to a first terminal of the transistor 231; a second terminal of the transistor 231 is coupled to the third terminal of the first switching transistor 210; a third terminal of the transistor 231 is coupled to the control signal output terminal of the hot plug controller 220; the power supply terminal of the hot plug controller 220 is coupled to the output terminal of the power supply 100.

The hot plug controller 220 is configured to output a first control signal to the first driving circuit 230.

The charge pump 240 is configured to amplify a power input voltage of the power supply 100 input to the charge pump 240, obtain a driving voltage, and output the driving voltage to the first driving circuit 230.

The first driving circuit 230 is configured to output the second control signal to the first switching tube 210 according to the first control signal; the second control signal is used to control the working state of the first switch tube 210.

The first driving circuit 230 is for amplifying the current of the first control signal to generate a second control signal, and the second control signal is for directly controlling the operation state of the first switching tube 210.

Specifically, the operating state includes on and off; further, the second control signal is also used to control the voltage and current outputted by the first switch tube 210.

The first switching tube 210 is used for a switching circuit, and the first switching tube 210 realizes slow start based on a control signal of the hot plug controller 220 to delay power supply to the load 300.

It should be noted that, the first switch tube 210 may be an N-type MOS tube or a P-type MOS tube. In addition, the first switch transistor 210 may be a gallium nitride transistor 231 or a silicon carbide transistor 231, which is not limited in the embodiment of the present application.

It can be understood that, when the first switching tube 210 is an N-type MOS tube, the first end of the first switching tube 210 is a drain d, the second end is a source s, and the control end is a gate g; when the first switching tube 210 is an N-type MOS tube, the first end of the first switching tube 210 is a source s, the second end is a drain d, and the control end is a gate g.

The transistor 231 may be a triode, a MOS transistor, or a gallium nitride transistor 231 or a silicon carbide transistor 231, which is not limited in the embodiment of the present application. The transistor 231 is configured to generate a second control signal according to the driving voltage sent by the charge pump 240 and the first control signal sent by the hot plug controller 220; the second control signal is then output to the first switching tube 210 to drive the first switching tube 210 to operate.

The charge pump 240 is a boost charge pump, which may be a switching regulator boost pump, a non-regulated capacitive charge pump, or an adjustable capacitive charge pump. The charge pump 240 is configured to amplify a power input voltage of the power supply 100 to obtain a driving voltage, and then output the driving voltage to the first driving circuit 230.

In this embodiment, by setting the charge pump 240 in the slow start circuit 200, the charge pump 240 provides the amplified driving voltage to the first driving circuit 230 to satisfy the external power supply condition that the transistor 231 operates in the amplifying operation state, so that the transistor 231 can still maintain to operate in the amplifying state under the condition that the input voltage of the first control signal is larger, thereby increasing the upper limit of the driving current of the first switching tube 210.

For example, when the transistor 231 in the first driving circuit 230 is a triode, the condition that the triode keeps working in the amplifying state is that the collector voltage is higher than the base voltage, so that the collector junction of the triode is in the reverse bias state, therefore, the larger the collector voltage input by the charge pump 240 is, the higher the upper limit of the base voltage of the triode is in the amplifying state, the higher the corresponding upper limit of the base current is, and the higher the upper limit of the current (emitter current) of the second control signal output by the triode is; when the transistor 231 is a MOS transistor, the condition that the MOS transistor keeps working in an amplified state is that the drain-source voltage Vds is greater than the difference between the gate-source voltage Vgs and the turn-on voltage Vgs (th) of the MOS transistor, and the greater the drain-source voltage Vds input by the charge pump 240, the higher the upper limit of the gate-source voltage Vgs in the amplified state of the MOS transistor; the output current of the MOS transistor in the amplifying state is positively correlated with the gate-source voltage Vgs, so that the higher the upper current limit of the second control signal is.

The slow start circuit 200 operates as follows:

when the hot plug controller 220 detects a predetermined event, such as that the load 300 is turned on, the load 300 is turned off, or at least one of the load 300 and the power supply 100 fails to cause the output current of the power supply 100 to be greater than a preset threshold, the hot plug controller 220 may output a first control signal to the first driving circuit 230, and the first driving circuit 230 outputs a second control signal to the first switching tube 210 according to the first control signal and the driving voltage input by the charge pump 240; the first switching tube 210 supplies power to the load 300 according to the second control signal.

It will be appreciated that for a fixed power input voltage and the soft start circuit 200, the first driver circuit 230 may output the same second control signal according to the same first control signal. Therefore, there is a correspondence between the first control signal and the second control signal.

For example, when the load 300 is connected, the hot plug controller 220 may send out a first control signal of 50 microamps, and the first driving circuit 230 amplifies the first control signal to a second control signal of 4 milliamps, so that the first switching tube 210 is smoothly started with a strong driving capability within a safe starting time; after the first switching tube 210 is started, if the output current of the power supply 100 is detected to be greater than the preset threshold, the hot plug controller 220 may send a first control signal of 0.1 microamps, and the first driving circuit 230 sends a second control signal of 8 microamps to the first switching tube 210, so that the input resistance of the first switching tube 210 is increased, and the excessive current is limited to be output to the load.

In this embodiment, the first driving circuit 230 and the charge pump 240 are added to the slow start circuit 200. The first control signal output by the hot plug controller 220 can be amplified by the first driving circuit 230, which increases the current of the second control signal input to the first switching tube 210, shortens the time spent in t1, t2 and t3 phases for charging the parasitic capacitor in the slow start process, and shortens the start time of the slow start circuit 200. Meanwhile, the short starting time caused by the second control signal with larger current can meet the requirement of corresponding safe starting time, so that the design scheme of the slow starting circuit 200 can select MOS (metal oxide semiconductor) tubes with larger parasitic capacitance and/or MOS tubes with larger number, thereby enlarging the selectable range of the MOS tubes in the design scheme of the slow starting circuit and improving the flexibility of the design of the slow starting circuit.

Referring to fig. 6, fig. 6 is a schematic circuit diagram of a slow start circuit according to an embodiment of the present application.

In the example of fig. 6, the slow start circuit includes a first switching tube 210, a hot plug controller 220, a first driving circuit 230, and a charge pump 240.

The transistor 231 in the first driving circuit 230 is a triode. In this embodiment, the first switch tube 210 is taken as an example of a MOS tube.

The hot plug controller 220 includes an enable terminal EN, a power supply terminal VCC, a GATE driving terminal GATE (control signal output terminal), and a ground terminal GND. The enable terminal EN and the power supply terminal VCC are coupled to the power supply 100, and the power supply outputs a power signal with a voltage Vin, and the power signal can activate the hot plug controller 220 through the enable terminal EN, so that the hot plug controller 220 works normally; meanwhile, the power signal supplies power to the hot plug controller 220 through the power supply terminal VCC. The GATE driving end GATE is used as a control signal output end of the hot plug controller 220 and is used for outputting a first control signal to the base electrode B of the triode; the ground end GND is grounded.

In one possible implementation, a GATE resistor R-GATE may be provided between the GATE drive GATE and the base B of the transistor to limit current and protect the base and the GATE drive GATE of the hot plug controller 220.

The output terminal of the charge pump 240 is coupled to the collector C of the triode, and is used for outputting the driving voltage to the collector C of the triode, and providing the power supply voltage for the collector C. By raising the supply voltage of the collector C, the external supply condition of the triode in the current amplification state is satisfied.

It can be appreciated that the voltage of the first control signal output by the hot plug controller 220 may be greater than the on voltage of the triode, so as to ensure the on state of the triode. The triode works in an amplifying state, the base current Ib is amplified tens of times, and the specific amplification factor is determined by the structure and the type of the triode.

Illustratively, the maximum withstand voltage between collector C and emitter E of the transistor is greater than the voltage Vin of the power input signal, and the amplification of the transistor is greater than 10 times.

The emitter E of the triode is coupled to the gate of the first switching tube 210, and outputs the second control signal to the gate of the first switching tube 210 through the emitter E to drive the first switching tube 210, so that the first switching tube 210 outputs a voltage of Vo to the load Ro.

In one possible implementation, the first driving circuit 230 further includes a fifth diode D5, where an anode of the fifth diode D5 is coupled to the emitter E of the transistor, and a cathode of the fifth diode D5 is coupled to the base B of the transistor, and is used to form a discharge path from the second end of the first switching tube 210 to the GATE driving end GATE.

In a possible implementation, a fourth capacitor C4 and a zener diode ZD are further disposed between the second end of the first switching tube 210 and the ground for protecting the power supply loop.

The first end of the fourth capacitor C4 is coupled to the second end of the first switching tube 210, the second end is coupled to the ground end, the fourth capacitor C4 may be specifically used for filtering and storing energy, the power ripple may be filtered through the filtering action of the fourth capacitor C4, and the energy stored by the fourth capacitor C4 may provide a current when a larger load occurs, so as to avoid the excessive drop amplitude of the power voltage of the power source 100.

The cathode of the zener diode ZD is coupled to the second end of the first switching tube 210, and the anode is coupled to the ground end, so as to stabilize the voltage of the power supply loop by utilizing the characteristic that the voltage of the power supply loop is basically unchanged due to the fact that the current passing through the power supply loop can be changed in a large range after the power supply loop is broken down reversely.

In this embodiment, by using the triode as the signal amplifying device in the first driving circuit 230, a larger output current can be generated with a small current variation of the first control signal, so that the driving capability of the hot plug controller 220 to the first switching tube 210 is enhanced under the condition that the current of the first control signal is smaller; on the other hand, when the current of the first control signal outputted from the hot plug controller 220 is large, the second control signal having the current as large as possible can be outputted by the current amplification characteristic of the transistor.

In another possible implementation manner, the transistor 231 in the first driving circuit 230 may be a MOS transistor, and in particular, referring to fig. 7, fig. 7 is a schematic circuit diagram of another slow start circuit provided in the embodiment of the present application.

In the specific example of fig. 7, the slow start circuit includes a first switching tube 210, a hot plug controller 220, a driving circuit 230, and a charge pump 240. In this embodiment, the first switch tube 210 is taken as an example of a MOS tube. For convenience of distinction, the first switching transistor 210 is referred to as a first MOS transistor, and the transistor 231 in the first driving circuit 230 is referred to as a second MOS transistor.

The embodiment shown in fig. 7 is different from the embodiment shown in fig. 6 in that the transistor in the first driving circuit 230 is replaced by a second MOS transistor. The base electrode B, the collector electrode C and the emitter electrode E of the triode are respectively equivalent to the gate electrode G, the drain electrode D and the source electrode S of the second MOS transistor in the embodiment; the overall operation principle of the slow start circuit is similar, and similar parts will not be described again here, and can be understood by referring to the corresponding description in the embodiment shown in fig. 6.

The output end of the charge pump 240 is coupled to the drain D of the second MOS transistor, and is configured to send the boosted driving voltage to the drain D, so as to provide the input voltage for the drain D. By amplifying the input voltage of the drain electrode D, the external power supply condition that the second MOS tube works in the constant current region can be met. Specifically, the external power supply condition is that the drain-source voltage Vds is greater than the difference between the gate-source voltage Vgs and the second MOS transistor turn-on voltage Vgs (th).

When the second MOS transistor works in a constant current area state, the second MOS transistor obtains a second control signal according to the gate-source voltage Vgs and the driving voltage. Specifically, the current magnitude of the second control signal depends on the transconductance capability of the second MOS transistor, where the transconductance capability is a ratio between a variation value of the second control signal current and a variation value of the gate voltage Vgs.

The sixth diode D6 is a body diode formed inside the second MOS transistor, the sixth diode D6 may be regarded as a diode having an anode coupled to the source S of the second MOS transistor and a cathode coupled to the drain D of the second MOS transistor; when the voltage of the drain electrode and the source electrode is too high, the body diode is broken down to generate short circuit, high current is connected to the ground terminal, and the second MOS tube is protected from being burnt.

In one possible implementation, the first driving circuit 230 further includes a transient suppression diode TVS, a first terminal of which is coupled to the second terminal of the transistor 231, and a third terminal of which falls into the single coupling transistor 231. In the specific example of fig. 7, the transient suppression diode TVS is coupled between the gate G and the source S of the second MOS transistor.

The TVS can absorb up to several kilowatts of surge power, so that the voltage clamp between the two ends of the transistor is at a predetermined value, and the devices in the first driving circuit 230 are effectively protected from various transient surge pulses.

In a possible implementation, a fourth capacitor C4 and a zener diode ZD are further disposed between the second end of the first MOS transistor 210 and the ground end for protecting the power supply loop.

The operation principle of the fourth capacitor C4 and the zener diode ZD is similar to that of the fourth capacitor C4 and the zener diode ZD in fig. 6, and will not be described herein.

In this embodiment, by using the second MOS transistor as the signal amplifying device in the first driving circuit 230, the current variation of the second control signal can be controlled by the voltage variation of the first control signal, so that the hot plug controller 220 can also drive the first switching transistor 210 by the second control signal with larger current through the first driving circuit 230 under the condition that the voltage of the first control signal is lower, thereby enhancing the driving capability of the first switching transistor 210; on the other hand, when the voltage of the first control signal output by the hot plug controller 220 is large, the second control signal having the largest current possible can be output by the transconductance characteristic of the second MOS transistor.

In one possible implementation, the charge pump may include a timing circuit 241 and a boost circuit 242, and referring specifically to fig. 8, fig. 8 is a schematic circuit diagram of a charge pump according to an embodiment of the present application.

The first input terminal of the voltage boosting circuit 242 is coupled to the power source, the second input terminal of the voltage boosting circuit 242 is coupled to the output terminal of the timing circuit 241, and the output terminal of the voltage boosting circuit 242 is coupled to the first terminal of the transistor 231 in the first driving circuit 230.

The timing circuit 241 is configured to send a pulse signal to the booster circuit 242; the booster circuit 242 is configured to amplify the power input voltage Vin according to the pulse signal to obtain a driving voltage.

In one possible implementation, the timing circuit 241 includes a first power supply VCC, a timer 2411, a first resistor R1, a second resistor R1, a first diode D1, a second diode D2, and a first capacitor C1; wherein, the first end of the first resistor R1 is coupled to the first power supply VCC; the second end of the first resistor R1, the first end of the second resistor R2, and the anode of the first diode D1 are coupled to the discharge end of the timer 2411; the second end of the second resistor R2 is coupled with the cathode of the second diode D2; the cathode of the first diode D1, the anode of the second diode D2, and the first end of the first capacitor C1 are coupled to the input end of the timer 2411; the second end of the first capacitor C1 is coupled to the ground GND of the timer 2411; an output of the timer 2411 is coupled to a second input of the boost circuit 242.

The timer 2411 may include a power supply terminal VCC, an output terminal OUT, a ground terminal GND, a first input terminal TRG, a second input terminal THR, and a discharge terminal DIS. It will be appreciated that in this embodiment, the output terminal of the timer 241 is the output terminal OUT, and the input terminal of the timer 2411 includes a first input terminal TRG and a second input terminal THR.

Specifically, the timer 2411 receives, through the power supply terminal VCC, electric energy output by the first power supply VCC to perform operation, where the first power supply VCC may be a power supply coupled to the slow start circuit, or may be an external power supply independently used for supplying power to the timer 2411; the output terminal OUT is used for outputting a high or low level; the first input terminal TRG is used for judging whether the received input voltage is greater than 1/3VCC; the second input terminal THR is used for judging whether the received input voltage is greater than 2/3VCC; the grounding end GND is used for grounding; the discharge terminal DIS is used to discharge the first capacitor C1.

The first power supply VCC further charges the first capacitor C1 through the first resistor R1, and the first capacitor C1 discharges to the discharge terminal DIS through the second resistor R2. In the process of charging and discharging the first capacitor C1, the timer 2411, the first resistor R1, the second resistor R2, and the first capacitor C1 connected externally form an oscillator, and the timer 2411 may output a square wave through the output terminal OUT.

After the first power VCC supplies power to the timer 2411 and the first capacitor C1, a specific workflow of the timer 2411 is as follows:

since the first capacitor C1 is connected to the first input terminal TRG, when the voltage of the first capacitor C1 is less than 1/3VCC, the output terminal OUT outputs a high level, and the discharge terminal DIS is in a high resistance state until the voltage of the first capacitor C1 reaches 2/3VCC; when the voltage of the first capacitor C1 reaches 2/3VCC, exceeding the corresponding threshold value of the second input terminal THR, the output terminal OUT becomes output low level, and the discharge terminal DIS becomes low level, at this time, the first capacitor C1 discharges to the discharge terminal DIS through the second resistor R2; when the voltage of the first capacitor C1 drops due to discharge, it is detected by the first input terminal TRG when it is lower than 1/3VCC, the output terminal OUT outputs a high level again, and the discharge terminal DIS returns to a high resistance state. By constantly cycling through the charge-discharge process described above, the timer 2411 may send a square wave to the boost circuit 242 through the output terminal OUT.

In the above cycle, during the charging phase, the first diode D1 is turned on, the second diode D2 is turned off, and the charging of the first capacitor C1 is completed through the first resistor R1; in the discharging phase, the first diode D1 is turned off, the second diode D2 is turned on, and the discharging of the first capacitor C1 is completed through the second diode R2.

Therefore, the charging time t1=0.693×r1×c4 and the discharging time t2=0.693×r2×c4 of the first capacitor C1 can be arbitrarily chosen by selecting the first resistor R1 and the second resistor R2 with different resistances, so as to achieve the arbitrary value of the square wave duty ratio output by the timer 2411.

It will be appreciated that other forms of timing circuit 241 may be employed in practice.

After the timer 2411 sends a square wave to the boost circuit 242, the boost circuit 242 may boost the input voltage Vin of the power supply according to the square wave.

In one possible implementation, the boost circuit 242 includes a second capacitor C2 and a third capacitor C3, and a third diode D3 and a fourth diode D4.

Wherein the anode of the third diode D3 is coupled with the output end of the power supply; the cathode of the third diode D3 is coupled to the first end of the second capacitor C2 and the anode of the fourth diode D4; a second terminal of the second capacitor C2 is coupled to the output terminal of the timing circuit 241; the cathode D4 of the fourth diode is coupled to the first terminal of the third capacitor C3 and the first terminal of the transistor 231 in the first driving circuit 230; the second terminal of the third capacitor C3 is coupled to ground.

It can be understood that in the present embodiment, the first input terminal of the boost circuit 242 is the anode of the third diode D3, the second input terminal is the second terminal of the second capacitor C2, and the output terminal is the cathode of the diode D4.

The square wave output by the timing circuit 241 has a high level of 5V and a low level of 0V; the operation principle of the booster circuit 242 will be described with reference to the power input voltage Vin of 5V:

when the square wave signal is at a low level, namely 0V, the voltage of the second capacitor C2 and the voltage of the third capacitor C3 are increased to 5V through the power input voltage; when the square wave signal is changed to 5V, the voltage of the pulse signal is applied to the lower polar plate of the second capacitor C2, at the moment, the pulse voltage is superposed with the voltage of the second capacitor C2, the voltage of the second capacitor C2 is changed to 10V, the voltage of the third capacitor C3 is still 5V, therefore, charge sharing can occur on the two capacitors, and finally, the voltage of the two capacitors is 7.5V; when the square wave signal is changed to 0V again, the voltage of the second capacitor C2 is reduced to 2.5V and then is raised to 5V by the power supply, and the voltage of the third capacitor C3 is still 7.5V because the fourth diode D4 does not flow to the second capacitor C2; when the square wave signal is changed to 5V again, the voltage of the second capacitor C2 is changed to 10V and is shared with the third capacitor C3 again, and the voltage of the third capacitor C3 is raised to 8.8V; and the voltage of the third capacitor C3 can reach 10V finally after the process is circulated, namely the process of boosting the power input signal is completed.

It can be appreciated that the charging speed of the third capacitor C3 is greater than the speed at which the first driving circuit 230 consumes the electric energy from the charge pump 240, so as to ensure that the voltage output by the charge pump 240 is the maximum voltage obtained after the voltage boosting.

It will be appreciated that the third diode D3 is used to prevent the electrical signal of the second capacitor C2 from flowing to the power supply.

In this embodiment, by setting the timing circuit 241 and the booster circuit 242 to form a charge pump with a simple structure, the timing circuit 241 is used as a pulse signal source of the booster circuit 242, so that the cost can be reduced, and the occupation of the circuit design space can be reduced.

In one possible implementation, the charge pump includes a processor 250, a second drive circuit 243, and a boost circuit 242; referring specifically to fig. 9, fig. 9 is a schematic circuit diagram of another charge pump according to an embodiment of the present disclosure.

Wherein, the output end of the processor 250 is coupled to the input end of the second driving circuit 243; the first input terminal of the voltage boosting circuit 242 is coupled to the power source, the second input terminal of the voltage boosting circuit 242 is coupled to the output terminal of the second driving circuit 243, and the output terminal of the voltage boosting circuit 242 is coupled to the first terminal of the transistor 231 in the first driving circuit 230.

The processor 250 is configured to send a pulse signal to the second driving circuit 243; the second driving circuit 243 amplifies the pulse signal and outputs the amplified pulse signal to the booster circuit 242; the booster circuit 242 is configured to amplify the power supply input voltage Vin based on the amplified pulse signal.

In one possible implementation, the second driving circuit 243 includes a second power supply VDD and a driving chip 2431; the power supply end VDD of the driving chip 2431 is coupled to the second power supply VDD; the output end of the processor 250 is coupled to the input end INA of the driving chip 2431; the output terminal OUTA of the driving chip 2431 is coupled to the second input terminal of the boost circuit 242; ground GND of driving chip 2431 and the heat dissipation end SINK is coupled to the ground.

The driving chip 2431 may include an enable terminal ENA, an input terminal INA, an output terminal OUTA, a ground terminal GND, a power supply terminal VDD, and a heat SINK terminal SINK.

In one possible implementation, the driving chip 2431 receives, through the power supply terminal VDD, the electric energy output by the second power supply VDD to perform operation, where the second power supply VDD may be a power supply coupled to the slow start circuit, or may be an external power supply independently used for supplying power to the driving chip 2431; the input terminal INA is used for receiving the pulse signal sent by the processor 250, and the output terminal OUTA is used for outputting the amplified pulse signal; the enable end ENA can be suspended to enable the driving chip 2431 to work normally and output signals; the heat dissipation end SINK is used for grounding; the ground GND is for grounding.

In the present embodiment, the input terminal INA of the driving chip 2431 is the input terminal of the second driving circuit 243, and the output terminal OUTA is the output terminal of the second driving circuit 243.

Alternatively, the processor 250 may be a processor on a circuit board where the slow start circuit is located for performing other functions. The external driving chip 2431 and the booster circuit 242 form a charge pump on the basis of the processor 250, so that the cost and the circuit design space can be saved.

Alternatively, the processor 250 may be a Microcontroller (MCU), a Complex Programmable Logic Device (CPLD), or a digital signal processor (Digitalsignal processor), but may also be other types of processors. The present application is not limited in this regard.

The processor 250 is configured to send a pulse signal to the driving chip 2431. Optionally, the pulse signal is a square wave.

The driving chip 2431 is configured to amplify the pulse signal sent by the processor 250 and drive the booster circuit 242 by transmitting the amplified pulse signal.

The operation principle of the booster circuit 242 in this embodiment is similar to that of the booster circuit 242 in the embodiment shown in fig. 8, and will be understood by referring to the corresponding description in the embodiment shown in fig. 8 without further description.

It will be appreciated that the processor 250 emits a relatively weak pulse signal that is insufficient to fully turn on the power devices in the circuit, and that if the power devices are directly driven by the processor 250, the processor 250 may be damaged by overheating. Therefore, a driving chip 2431 is required to be connected to the processor 250 to amplify the post-pulse signal to drive the power device with a stronger driving capability.

In this embodiment, the processor 250 on the circuit board where the slow start circuit is located is externally connected with the driving chip 2431 and the boost circuit 242 to form the charge pump 240, and the existing processor 250 on the circuit board is used as the pulse signal source of the charge pump 240 to control the charge pump 240 to work, so that the cost and the circuit design space can be saved.

Embodiments of the present application also provide a computing device including a cabinet and a computing node as shown in fig. 3; the computing node is arranged in the cabinet.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or, what contributes to the prior art, or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RandomAccessMemory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

Claims

1. A computing node, the computing node comprising a power supply, a slow start circuit, and a load;

the slow start circuit comprises a first switch tube, a charge pump, a first driving circuit and a hot plug controller; wherein the first driving circuit includes a transistor;

The first end of the first switch tube and the input end of the charge pump are coupled with the output end of the power supply; the second end of the first switching tube is coupled with a load; the output end of the charge pump is coupled with the first end of the transistor; the second end of the transistor is coupled with the third end of the first switch tube; the third end of the transistor is coupled with the control signal output end of the hot plug controller;

the hot plug controller is used for outputting a first control signal to the first driving circuit;

the charge pump is used for amplifying the power supply input voltage to obtain a driving voltage and outputting the driving voltage to the first driving circuit;

the first driving circuit is used for outputting a second control signal to the first switching tube according to the first control signal; the second control signal is used for controlling the working state of the first switching tube.

2. The compute node of claim 1, wherein the charge pump comprises a timing circuit and a boost circuit; the first input end of the boost circuit is coupled with the power supply, the second input end of the boost circuit is coupled with the output end of the timing circuit, and the output end of the boost circuit is coupled with the first end of the transistor;

The timing circuit is used for sending pulse signals to the boost circuit; the boost circuit is used for amplifying the power supply input voltage according to the pulse signal.

3. The computing node of claim 2, wherein the timing circuit comprises a first power supply, a timer, a first resistor, a second resistor, a first diode, a second diode, and a first capacitor; wherein, the first end of the first resistor is coupled with the first power supply; the second end of the first resistor, the first end of the second resistor and the anode of the first diode are coupled with the discharge end of the timer; a second end of the second resistor is coupled with the cathode of the second diode; the cathode of the first diode, the anode of the second diode and the first end of the first capacitor are coupled with the input end of the timer; the second end of the first capacitor and the ground end of the timer are coupled to ground; the output of the timer is coupled to the second input of the boost circuit.

4. The compute node of claim 1, wherein the charge pump comprises a processor, a second drive circuit, and a boost circuit; the output end of the processor is coupled with the input end of the second driving circuit; the first input end of the boost circuit is coupled with the power supply, the second input end of the boost circuit is coupled with the output end of the second driving circuit, and the output end of the boost circuit is coupled with the first end of the transistor;

The processor is used for sending pulse signals to the second driving circuit;

the second driving circuit is used for amplifying the pulse signal and outputting the amplified pulse signal to the boosting circuit;

the booster circuit is used for amplifying the power supply input voltage according to the amplified pulse signal.

5. The computing node of claim 4, wherein the second drive circuit comprises a second power supply and a drive chip; the power supply end of the driving chip is coupled with the second power supply; the output end of the processor is coupled with the input end of the driving chip; the output end of the driving chip is coupled with the second input end of the booster circuit; the grounding end and the heat dissipation end of the driving chip are coupled to the ground.

6. The computing node of any of claims 2-5, wherein the boost circuit comprises a third diode, a fourth diode, a second capacitance, and a third capacitance; wherein the anode of the third diode is coupled with the output end of the power supply; the cathode of the third diode is coupled with the first end of the second capacitor and the anode of the fourth diode; the second end of the second capacitor is coupled with a pulse signal source; a cathode of the fourth diode is coupled with the first end of the third capacitor and the first end of the transistor; the second end of the third capacitor is coupled to ground.

7. The computing node of any of claims 1-6, wherein the transistor is any of: a transistor, a MOS transistor, a gallium nitride transistor, or a silicon carbide transistor.

8. The computing node of any of claims 1-7, wherein the first drive circuit further comprises a transient voltage suppression diode; the first end of the transient voltage suppression diode is coupled with the second end of the transistor, and the second end of the transient voltage suppression diode is coupled with the third end of the transistor.

9. The computing node of any of claims 1-8, further comprising a fourth capacitance and a zener diode; the first end of the fourth capacitor and the cathode of the zener diode are coupled with the second end of the first switch tube; the second end of the fourth capacitor and the anode of the zener diode are coupled to ground.

10. A computing device comprising a cabinet and a computing node of any of claims 1-9; wherein the compute node is disposed in the cabinet.