CN116525466A

CN116525466A - Wafer bonding method and bonded device structure

Info

Publication number: CN116525466A
Application number: CN202210854969.XA
Authority: CN
Inventors: 庄学理; 李元仁; 朱芳兰; 吴伟成; 许诺
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-03-18
Filing date: 2022-07-19
Publication date: 2023-08-01

Abstract

The present disclosure relates generally to wafer bonding methods and bonded device structures. In one embodiment, a structure comprises: a first device comprising a first dielectric layer and a first alignment mark in the first dielectric layer, the first alignment mark comprising a first magnetic cross having a first north pole and a first south pole; and a second device including a second dielectric layer and a second alignment mark in the second dielectric layer, the second alignment mark including a second magnetic cross having a second north pole and a second south pole, the first north pole aligned with the second south pole, the first south pole aligned with the second north pole, the first dielectric layer bonded to the second dielectric layer by a dielectric-dielectric bond, the first alignment mark bonded to the second alignment mark by a metal-metal bond.

Description

Wafer bonding method and bonded device structure

Technical Field

The present disclosure relates to the field of semiconductors, and more particularly, to wafer bonding methods and bonded device structures.

Background

Due to the development of Integrated Circuits (ICs), the semiconductor industry has experienced a continual increase due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, these improvements in integration density result from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed, greater bandwidth, and lower power consumption and delay increases, so does the demand for smaller and more creative techniques for packaging semiconductor dies.

Stacked semiconductor devices have become an effective technique for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic and memory circuits are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be bonded together by suitable bonding techniques to further reduce the form factor of the semiconductor device.

Disclosure of Invention

According to a first embodiment of the present disclosure, there is provided a method of manufacturing a semiconductor structure, including: forming a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first magnetic cross, the first magnetic cross including a first north pole and a first south pole, the first north pole including a first adjacent arm of the first magnetic cross, the first south pole including a second adjacent arm of the first magnetic cross, the second wafer including a second alignment mark, the second alignment mark including a second magnetic cross, the second magnetic cross including a second north pole and a second south pole, the second north pole including a first adjacent arm of the second magnetic cross, the second south pole including a second adjacent arm of the second magnetic cross; aligning the first alignment mark with the second alignment mark in an optical alignment process; aligning the first alignment mark with the second alignment mark in a magnetic alignment process after the optical alignment process, wherein the first north pole is aligned with the second south pole and the first south pole is aligned with the second north pole; and forming a bond between the first wafer and the second wafer.

According to a second embodiment of the present disclosure, there is provided a method of manufacturing a semiconductor structure, including: applying a first magnetic field to a first wafer to magnetize first alignment marks of the first wafer, the first alignment marks each comprising a plurality of first magnetic crosses, the first magnetic field forming a first non-zero angle with first arms of the plurality of first magnetic crosses; applying a second magnetic field to a second wafer to magnetize second alignment marks of the second wafer, the second alignment marks each comprising a plurality of second magnetic crosses, the second magnetic field forming a second non-zero angle with a second arm of the plurality of second magnetic crosses, the first magnetic field having an opposite polarity than the second magnetic field; moving the first wafer toward the second wafer until the first and second alignment marks apply horizontal and vertical forces to the first and second wafers; and forming a bond between the first wafer and the second wafer.

According to a third embodiment of the present disclosure, there is provided a semiconductor structure including: a first device comprising a first dielectric layer and a first alignment mark in the first dielectric layer, the first alignment mark comprising a first magnetic cross having a first north pole and a first south pole; and a second device comprising a second dielectric layer and a second alignment mark in the second dielectric layer, the second alignment mark comprising a second magnetic cross having a second north pole and a second south pole, the first north pole aligned with the second south pole, the first south pole aligned with the second north pole, the first dielectric layer bonded to the second dielectric layer by a dielectric-dielectric bond, the first alignment mark bonded to the second alignment mark by a metal-metal bond.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of a wafer according to some embodiments.

Fig. 2A-4B are views of intermediate steps during a process for forming alignment marks for a wafer, according to some embodiments.

Fig. 5 is a diagram of a wafer bonding method according to some embodiments.

Fig. 6-14 are various views of intermediate steps during a wafer bonding method according to some embodiments.

Fig. 15A-15H are top views of alignment marks according to various embodiments.

Fig. 16-17 are views of intermediate steps during a process for forming alignment marks for wafers according to some other embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "lower," "above," "upper," etc.) may be used herein to facilitate describing a relationship of one element or feature to another element(s) or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to various embodiments, magnetic alignment marks are formed in the wafer and are used in an alignment process during bonding of the wafer. Specifically, the two wafers may be formed with alignment marks of opposite magnetic polarities. As a result, when the wafers are bonded together, the alignment marks of the wafers are magnetically attracted to each other. Thus, the wafers may be magnetically self-aligned during bonding, which may reduce misalignment between bonded wafers.

Fig. 1 is a cross-sectional view of a wafer 70 according to some embodiments. The two wafers 70 are bonded in subsequent processing to form a bonded wafer structure. Wafer 70 includes semiconductor substrate 72, interconnect structure 74, conductive via 76, dielectric layer 78, bond pad 82, and alignment mark 84.

Wafer 70 has a plurality of device regions 72D, each of which includes features for a semiconductor die. The semiconductor die may be an integrated circuit die or interposer (interposer), or the like. Each integrated circuit die may be a logic device (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a microcontroller, etc.), a memory device (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management device (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) device, a sensor device (e.g., an image sensor die), a microelectromechanical system (MEMS) device, a signal processing device (e.g., a Digital Signal Processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc., or a combination of the foregoing (e.g., a system on chip (SoC) die).

In the illustrated embodiment, the wafer 70 also has a plurality of alignment mark regions 72A, and one or more alignment marks 84 are located in each alignment mark region 72A. Alignment mark regions 72A (including alignment marks 84) may be provided at the edge of wafer 70 such that they surround device region 72D (including bond pads 82). In another embodiment, alignment marks 84 are located in device region 72D, and wafer 70 does not have a separate region for alignment marks 84.

The semiconductor substrate 72 may be an active layer of a doped or undoped silicon substrate, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 72 may include: other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination of the foregoing. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. The semiconductor substrate 72 has an active surface (e.g., the surface facing upward in fig. 1) sometimes referred to as the front side, and an inactive surface (e.g., the surface facing downward in fig. 1) sometimes referred to as the back side.

Devices (not separately shown) may be formed at the active surface of semiconductor substrate 72. These devices may be active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.). Interconnect structure 74 is located over the active surface of semiconductor substrate 72. Interconnect structures 74 interconnect these devices to form an integrated circuit. The interconnect structure may be formed by, for example, a metallization pattern in the dielectric layer, and may be formed by a damascene process (e.g., a single damascene process or a dual damascene process, etc.). These metallization patterns include metal lines and vias formed in one or more dielectric layers. The metallization pattern of interconnect structure 74 is electrically coupled to these devices.

Conductive vias 76 extend into interconnect structure 74 and/or semiconductor substrate 72. Conductive via 76 is electrically coupled to the metallization pattern of interconnect structure 74. The conductive via 76 may be a via through the substrate, such as a via through silicon. As an example of forming the conductive via 76, a recess may be formed in the interconnect structure 74 and/or the semiconductor substrate 72 by, for example, etching, grinding, laser techniques, combinations of the foregoing, and the like. The thin barrier layer may be conformally deposited in the recess, for example, by CVD, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), thermal oxidation, combinations of the foregoing, or the like. The barrier layer may be formed of an oxide, nitride, carbide, combinations of the foregoing, or the like. A conductive material may be deposited over the barrier layer and in the recess. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, a combination of the foregoing, or the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, combinations of the foregoing, or the like. Excess conductive material and barrier layer are removed from the surface of interconnect structure 74 or semiconductor substrate 72 by, for example, CMP. The remaining portion of the barrier layer and the remaining portion of the conductive material in the recess form a conductive via 76.

Dielectric layer 78 is located at front side 70F of wafer 70. A dielectric layer 78 is in the interconnect structure 74 and/or on the interconnect structure 74. In some embodiments, dielectric layer 78 is an upper dielectric layer of interconnect structure 74. In some embodiments, the dielectric layer 78 is a passivation layer on the interconnect structure 74. The dielectric layer 78 may be formed of silicon oxide, silicon nitride, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymer, or the like, or a combination of the foregoing, which may be formed, for example, by Chemical Vapor Deposition (CVD), spin coating, or lamination, or the like.

The bond pads 82 are located at the front side 70F of the wafer 70. The bond pad 82 is a conductive post or pad or the like that can be externally connected. Bond pads 82 are located in interconnect structure 74 and/or on interconnect structure 74. In some embodiments, the bond pad 82 is part of the upper metallization pattern of the interconnect structure 74. In some embodiments, the bond pad 82 includes a post-passivation interconnect (post-passivation interconnect) electrically coupled to the upper metallization pattern of the interconnect structure 74. The bond pads 82 may be formed of a conductive material, such as a metal (e.g., copper or aluminum, etc.), which may be formed by, for example, plating, etc. A dielectric layer 78 is disposed laterally around bond pad 82.

Alignment marks 84 are located at the front side 70F of the wafer 70. Alignment marks 84 are located in interconnect structure 74 and/or on interconnect structure 74. In some embodiments, the alignment marks 84 are part of the upper metallization pattern of the interconnect structure 74. In some embodiments, alignment marks 84 are formed in dielectric layer 78 independently of bond pads 82. Dielectric layer 78 is disposed laterally around alignment marks 84. The planarization process may be applied to the various layers such that the top surface of dielectric layer 78, the top surface of bond pad 82, and the top surface of alignment mark 84 are substantially coplanar (within process variations) and exposed at front surface 70F of wafer 70. The planarization process may be Chemical Mechanical Polishing (CMP), etch-back (etch-back), a combination of the foregoing, or the like.

As will be described in greater detail later, the planarized front faces 70F of the two wafers 70 will be bonded in a face-to-face manner. The alignment marks 84 have a predetermined shape and/or pattern that can be identified using a camera such that the alignment marks 84 can be used to optically align the wafer 70 during wafer bonding. In addition, as will be described in more detail later, the alignment marks 84 are formed of a magnetic material such that the alignment marks 84 of the wafer 70 are magnetically attracted to each other during alignment, thereby improving the accuracy of wafer alignment. Further, the magnetic material of the alignment mark 84 has high transparency at the wavelength of light used during optical alignment, for example, infrared light, for example, light having a wavelength of about 1.1 μm (for example, in the range of 0.3 μm to 3 μm). Forming the alignment marks 84 from a material having high transparency may increase the accuracy of optical alignment.

In some embodiments, the magnetic material of the alignment marks 84 is different than the conductive material of the bond pads 82. The magnetic material of the alignment marks 84 may have a greater resistivity than the conductive material of the bond pads 82 and may have a greater transparency than the conductive material of the bond pads 82. In such an embodiment, the alignment marks 84 have a stronger magnetization than the bond pads 82.

In other embodiments, the alignment marks 84 and the bond pads 82 are formed of the same magnetic material. Thus, the bond pads 82 are also magnetic. Forming the bond pads 82 to be also magnetic may help increase the magnetic attraction between the wafers during alignment, thereby improving the accuracy of wafer alignment. In such an embodiment, the alignment marks 84 may have the same intensity magnetization as the bond pads 82.

Depending on the design of the semiconductor die, alignment marks 84 may be formed where additional bond pads 82 would otherwise be formed. Thus, alignment marks 84 are located in the same device layer (e.g., dielectric layer 78) as bond pads 82. Accordingly, the patterns of the bond pads 82 and the alignment marks 84 may have increased design flexibility.

Fig. 2A-4B are views of intermediate steps during a process for forming alignment marks 84 of wafer 70, according to some embodiments. Fig. 2A, 3A and 4A are top views. Fig. 2B, 3B and 4B are sectional views shown along the cross-section A-A' in fig. 2A, 3A and 4A, respectively. The alignment marks 84 (see fig. 4A) include one or more magnetic features 96 having a predetermined shape. In this embodiment, the alignment mark 84 is a single magnetic feature 96, the single magnetic feature 96 being a magnetic cross. According to various embodiments (described later with respect to fig. 15A-15H), alignment mark 84 may be a single magnetic cross, alignment mark 84 may be a single magnetic stripe, or alignment mark 84 may include multiple magnetic crosses/stripes.

In fig. 2A-2B, trenches 92 for magnetic features are patterned in dielectric layer 78. Trench 92 may be a recess extending into dielectric layer 78 or may be an opening extending through dielectric layer 78. Dielectric layer 78 may be patterned by any acceptable process, such as by exposing dielectric layer 78 to light and developing it when dielectric layer 78 is a photosensitive material, or by etching using, for example, anisotropic etching. A timed etch process may be used to stop etching of trench 92 after trench 92 reaches a desired depth. The depth of the trench 92 determines the thickness of the resulting magnetic feature 96 (see fig. 4B), which will be described in more detail below.

In fig. 3A-3B, a ferromagnetic feature 94 is formed in the trench 92. The ferromagnetic feature 94 is formed of a ferromagnetic material that is capable of being magnetized to form a permanent magnet. Examples of ferromagnetic materials include iron (Fe), cobalt (Co), nickel (Ni), alloys thereof (e.g., cobalt-iron-nickel (Co) _x Fe _y Ni _z Where x, y, and z are each in the range of 0 to 100), or a plurality of layers thereof, etc., which may be formed by techniques such as deposition (e.g., PVD), plating (e.g., electroplating or electroless plating), etc. The ferromagnetic material may be doped or undoped. For example, the ferromagnetic material may be cobalt-iron-nickel doped with boron, silicon, molybdenum, combinations of the foregoing, or the like. In some embodiments, the ferromagnetic feature 94 is a single continuous layer of ferromagnetic material. In some embodiments, the ferromagnetic feature 94 is an electrically conductive material doped with a ferromagnetic material.

As an example for forming ferromagnetic features 94, a layer of ferromagnetic material may be conformally formed in trench 92 and on dielectric layer 78. A removal process is performed to remove excess portions of the ferromagnetic material above the top surface of the dielectric layer 78 to form the ferromagnetic features 94. After the removal process, the ferromagnetic material has portions that remain in the trenches 92 (thereby forming the ferromagnetic features 94). In some embodiments, a planarization process such as a Chemical Mechanical Polishing (CMP), an etchback process, or a combination thereof, or the like, may be employed. After the planarization process, the top surface of the dielectric layer 78, the top surface of the bond pad 82 (see fig. 1), and the top surface of the ferromagnetic feature 94 are substantially coplanar (within process variations). The substantially coplanar top surfaces of these features are at the front side 70F of the wafer, and the resulting planar surface may be the surface that is subsequently used for wafer bonding.

In fig. 4A-4B, ferromagnetic feature 94 is magnetized to form magnetic feature 96. The magnetic feature 96 is a permanent magnet having a north pole 96N and a south pole 96S. The magnetic feature 96 has a stronger magnetization than the ferromagnetic feature 94. In some embodiments, the magnetic feature 96 has a magnetic field of about 750emu/cm ³ (e.g. at 250 emu/cm) ³ To 2000emu/cm ³ In (2) the magnetization (M, magnetic moment per volume). By exposing the ferromagnetic feature 94 to a magnetic field 102 (withDescribed later) to magnetize the ferromagnetic features 94.

In this embodiment, where the magnetic feature 96 is a magnetic cross, the magnetic cross includes four arms 98 protruding from a central portion. The first pair of adjacent arms 98N form the north pole 96N of the magnetic cross. The arm 98N includes one arm 98N extending in a first direction (e.g., Y-direction) and one arm 98N extending in a second direction (e.g., X-direction). The second pair of adjacent arms 98S form a south pole 96S of the magnetic cross. The arm 98S includes one arm 98S extending in a first direction (e.g., Y-direction) and one arm 98S extending in a second direction (e.g., X-direction). The width and length of the arm 98 will be described with respect to fig. 15A to 15B. The magnetic feature 96 has a thickness T along a third direction (e.g., Z-direction) ₁ . In some embodiments, thickness T ₁ About 0.5 μm (e.g., in the range of 0.3 μm to 0.7 μm). In some embodiments, the total length of the alignment marks 84 (e.g., magnetic cross) along a first direction (e.g., Y-direction) is about 50 μm (e.g., in the range of 10 μm to 100 μm) and the total width along a second direction (e.g., X-direction) is about 50 μm (e.g., in the range of 10 μm to 100 μm).

Although not shown separately in fig. 2A-4B, it should be appreciated that a plurality of alignment marks 84 may be formed simultaneously. For example, a plurality of trenches 92 may be patterned in the dielectric layer 78, the trenches 92 may be filled with corresponding ferromagnetic features 94, and the ferromagnetic features 94 may be magnetized to form magnetic features 96. Alignment marks 84 (including magnetic feature 96 of each alignment mark 84) may be spaced apart by a distance of about 5 μm (e.g., in the range of 1 μm to 20 μm).

The magnetic field 102 used to magnetize the magnetic features 96 has a direction parallel to the front surface 70F (see fig. 4B) of the wafer and forms a non-zero angle with each arm 98 of the magnetic features 96. The non-zero angle is between 0 degrees and 90 degrees. In some embodiments, the non-zero angle is a 45 degree angle. Thus, the magnetization direction induced in the magnetic feature 96 is at a 45 degree angle to the arm 98 of the magnetic feature 96. The magnetic field 102 may be generated by an electromagnet. In some embodiments, the magnetic field 102 has a magnetic field strength of about 1 Tesla (Tesla) (e.g., in the range of 0.01 Tesla to 2 Tesla) and is applied for a duration of about 5 seconds (e.g., in the range of 0.01 seconds to 60 seconds).

Fig. 5 is a diagram of a wafer bonding method 500 according to some embodiments. The wafer bonding method 500 will be described in conjunction with fig. 6-14, with fig. 6-14 being various views of intermediate steps during the wafer bonding method 500 according to some embodiments. In wafer bonding method 500, two wafers 70 (including a first wafer 70A and a second wafer 70B, see fig. 6) are bonded in a face-to-face manner. In this embodiment, the wafers 70 are bonded in a face-to-face manner by hybrid bonding such that the front side of the first wafer 70A is bonded to the front side of the second wafer 70B by dielectric-dielectric bonding and metal-metal bonding. Hybrid bonding allows the wafers 70A, 70B to be bonded without using any adhesive material (e.g., die attach film) or eutectic material (e.g., solder).

In step 502, a first wafer 70A and a second wafer 70B are formed that include a first alignment mark 84A and a second alignment mark 84B (described later with respect to fig. 7), respectively. When the wafers 70 are bonded to each other, one of the wafers 70 will be flipped. Thus, wafers 70A, 70B are formed with alignment marks 84A, 84B, with alignment marks 84A, 84B including magnetic features 96A, 96B having opposite magnetic polarities. More specifically, first magnetic feature 96A has an opposite magnetic polarity to second magnetic feature 96B. Thus, when the wafers 70A, 70B are placed face-to-face, they will magnetically attract each other.

Referring to fig. 6 (simplified top view of wafers 70A, 70B) and fig. 7 (top view of alignment marks 84A, 84B), wafers 70A, 70B are shown in a similar processing step as described with respect to fig. 4A-4B, in which magnetic features 96A, 96B are magnetized. When magnetizing the magnetic features 96A, 96B, different magnetic fields 102A, 102B are applied to the wafers 70A, 70B. Specifically, a first magnetic field 102A is applied to the first wafer 70A to magnetize the first magnetic feature 96A of the first wafer 70A, and a second magnetic field 102B is applied to the second wafer 70B to magnetize the second magnetic feature 96B of the second wafer 70B. The first magnetic field 102A may (or may not) have the same strength as the second magnetic field 102B, and the first magnetic field 102A is antiparallel (anti-parallel) to the second magnetic field 102B such that the first magnetic field 102A has an opposite polarity (e.g., opposite direction) than the second magnetic field 102B. As a result, the magnetization of the first magnetic feature 96A may (or may not) have the same strength as the magnetization of the second magnetic feature 96B, but the magnetization of the first magnetic feature 96A has an opposite polarity than the magnetization of the second magnetic feature 96B. Thus, when the wafers 70A, 70B are placed face-to-face, the first magnetic feature 96A will be attracted to the second magnetic feature 96B. The direction of the magnetic fields 102A, 102B is relative to the respective wafer 70A, 70B. In some embodiments, the direction of the magnetic fields 102A, 102B is relative to the notch 88 in the wafer 70A, 70B.

In step 504, the wafers 70A, 70B are roughly aligned in a first alignment process. Referring to fig. 8-10, wafers 70A, 70B are shown during steps of a first alignment process. Each of the alignment marks 84A, 84B is schematically illustrated, but as previously described, each of the wafers 70A, 70B may include a plurality of alignment marks. The first alignment process is an optical alignment process that utilizes cameras 106A, 106B, such as infrared cameras. The first wafer 70A is placed on the lower chuck 104A and the second wafer 70B is placed on the upper chuck 104B. The chucks 104A, 104B are operable to move the wafers 70A, 70B horizontally (e.g., in the X/Y plane) and to move the wafers 70A, 70B vertically (e.g., along the Z direction). During the first alignment process, the chucks 104A, 104B are positioned far enough apart that the magnetic attraction between the alignment marks 84A, 84B is insufficient to move the wafers 70A, 70B. In some embodiments, the chucks 104A, 104B are positioned such that the gap G between the wafers 70A, 70B (e.g., between the alignment marks 84A, 84B) ₁ (see FIG. 10) is about 3mm (e.g., in the range of 0.1mm to 10 mm).

The first alignment process includes searching for a first alignment mark 84A of the first wafer 70A using the upper camera 106B, as shown in fig. 8. The upper camera 106B is set at a fixed position and the lower chuck 104A is moved horizontally in the X/Y plane until the upper camera 106B detects that the first alignment mark 84A is located at a desired position indicating proper wafer alignment. The position of the lower chuck 104A (the aligned position of the lower chuck 104A) is then measured using the positioning sensor 108. The alignment position of chuck 104A is recorded. The lower chuck 104A may then be withdrawn to clear the line of sight of the cameras 106A, 106B.

As shown in fig. 9, the first alignment process further includes searching for a second alignment mark 84B of the second wafer 70B using the lower camera 106A. The lower camera 106A is set at a fixed position and the upper chuck 104B is moved horizontally in the X/Y plane until the lower camera 106A detects that the second alignment mark 84B is located at a desired position indicating proper wafer alignment. The position of the upper chuck 104B (which is the aligned position of the upper chuck 104B) is then measured using the positioning sensor 108. The alignment position of the upper chuck 104B is recorded.

The first alignment process also includes horizontally moving the chucks 104A, 104B in the X/Y plane to their aligned positions (as determined by the positioning sensor 108). When the chucks 104A, 104B are in their aligned position, the first wafer 70A is coarsely aligned with the second wafer 70B. After the wafers 70A, 70B are roughly aligned, the amount of misalignment between them may be large. In some embodiments, the wafers 70A, 70B have a misalignment greater than about 0.2 μm (e.g., in the range of 0.2 μm to 0.4 μm misalignment).

In step 506, the wafers 70A, 70B are finely aligned in a second alignment process. Referring to fig. 11, wafers 70A, 70B are shown during a second alignment process. The second alignment process is a magnetic alignment process using the alignment marks 84A, 84B. The second alignment process is a self-alignment process. During the second alignment process, the chucks 104A, 104B are positioned close enough together such that the magnetic attraction between the alignment marks 84A, 84B is sufficient to move the wafers 70A, 70B. In some embodiments, the chucks 104A, 104B are positioned such that the gap G between the wafers 70A, 70B (e.g., between the alignment marks 84A, 84B) ₂ About 0.2 μm (e.g., in the range of 0.01 μm to 0.5 μm). The chucks 104A, 104B are closer together during the second alignment process than during the first alignment process.

Referring to FIG. 12, some magnetic features 96A, 96B of two alignment marks 84A, 84B are shown. Because the magnetic features 96A, 96B are magnetically attracted, the alignment marks 84A, 84B apply two forces to the wafers 70A, 70B (see fig. 11): horizontal force F _H (e.g. in the X/Y plane) and vertical force F _V (e.g., along the Z-direction). Vertical force F _V The wafers 70A, 70B are pulled toward one another. Horizontal force F _H The north pole 96N of the magnetic features 96A, 96B is pulled toward the south pole 96S of the magnetic features 96A, 96B. Horizontal force F _H Strong enough to move the wafers 70A, 70B in the X/Y plane. As described above, the magnetic features 96A, 96B of the alignment marks 84A, 84B have opposite magnetic polarities. Thus, as the wafers 70A, 70B move in the X/Y plane, the north pole 96N of the first magnetic feature 96A aligns with the south pole 96S of the second magnetic feature 96B, and the south pole 96S of the first magnetic feature 96A aligns with the north pole 96N of the second magnetic feature 96B.

The second alignment process includes vertically moving chucks 104A, 104B (see fig. 11) toward each other in the Z-direction until alignment marks 84A, 84B generate a desired horizontal force F _H And vertical force F _V . This begins to move the alignment marks 84A, 84B to the aligned position. Movement of the chucks 104A, 104B is then stopped and a wait is performed (during which the chucks 104A, 104B remain in the desired position) until the wafers 70A, 70B finish moving to their aligned positions (e.g., until the north pole 96N is aligned with the south pole 96S). In some embodiments, the second alignment process includes waiting for a duration of about 500 μs (e.g., in the range of 10 μs to 5000 μs) while the chucks 104A, 104B remain in the desired positions. When north pole 96N is aligned with south pole 96S, first wafer 70A is finely aligned with second wafer 70B. After the wafers 70A, 70B are finely aligned, the amount of misalignment between them is small. In some embodiments, the wafers 70A, 70B have a misalignment of less than about 0.1 μm (e.g., in the range of 0.01 μm to 0.5 μm misalignment). Performing a second alignment process (e.g., magnetic self-alignment) in addition to the first alignment process (e.g., optical alignment) allows for misalignment between the wafers 70A, 70B to be less than if the first alignment process alone was used.

In step 508, a pre-bonding process is performed by bringing the front sides of the wafers 70A, 70B into contact with each other. Referring to fig. 13, the wafers 70A, 70B are shown after the wafers 70A, 70B are contacted. During pre-bonding, a small pressure is applied by moving chucks 104A, 104B vertically toward each other to press first wafer 70A against second wafer 70B. Fig. 14 is a cross-sectional view of wafers 70A, 70B during bonding. When the wafers 70A, 70B are pressed together, the dielectric layers 78A, 78B enter a contact state. The pre-bonding is performed at a low temperature (e.g., about room temperature (e.g., in the range of 15 ℃ to 30 ℃), and the dielectric layers 78A, 78B are bonded to each other after the pre-bonding.

In step 510, an annealing process is performed to improve the bond strength between the wafers 70A, 70B. During the annealing process, the dielectric layers 78A, 78B; bond pads 82A, 82B; and the alignment marks 84A, 84B are annealed at a high temperature (e.g., a temperature in the range of 100 ℃ to 450 ℃). After annealing, a bond (e.g., a fusion bond) is formed to bond the dielectric layers 78A, 78B. For example, the bonding may be covalent bonding between the material of dielectric layer 78A and the material of dielectric layer 78B. The bond pads 82A, 82B are connected to each other in a one-to-one correspondence. The bond pads 82A, 82B may be in physical contact after pre-bonding, or may be expanded during annealing to enter a state of physical contact. Furthermore, during annealing, the materials (e.g., copper) of the bond pads 82A, 82B intermix such that metal-to-metal bonds are also formed. The alignment marks 84A, 84B are also connected to each other in a one-to-one correspondence, and metal-to-metal bonds may be formed between the alignment marks 84A, 84B in a similar manner as the bond pads 82A, 82B. Thus, the resulting bond between wafers 70A, 70B is a hybrid bond, which includes both dielectric-dielectric bonds and metal-metal bonds.

After the wafers 70A, 70B are bonded, additional processing may be performed. For example, referring again to fig. 14, the bonded wafer structure may be singulated by sawing along scribe line regions, such as between device regions 72D. Sawing singulates the bonded devices in each device region 72D to form bonded device structures. In embodiments in which alignment marks 84 are formed in device region 72D, the bonded device structure may include alignment marks 84. In embodiments where alignment marks 84 are formed in separate alignment mark regions 72A, the bonded device structure may not include alignment marks 84.

Fig. 15A-15H are top views of alignment marks 84 according to various embodiments. As described above, each alignment mark 84 includes one or more magnetic features 96. Any combination of alignment marks 84 described with respect to fig. 15A-15H may be formed for a single wafer 70.

As shown in fig. 15A-15B, the alignment mark 84 may be a single magnetic feature 96, wherein the magnetic feature 96 is a magnetic cross. As described previously with respect to fig. 4A-4B, the magnetic cross is formed by applying a magnetic field 102 (see fig. 4A) to the ferromagnetic feature, thereby forming the magnetic feature. When the magnetic feature 96 is a magnetic cross, the magnetic field 102 (see fig. 4A) used to magnetize the magnetic cross has a direction that forms a non-zero angle with each arm 98 of the magnetic cross. The non-zero angle is between 0 degrees and 90 degrees.

In some embodiments, as shown in FIG. 15A, the plurality of arms 98 of the magnetic cross have equal widths W ₁ And equal length L ₁ Wherein the length L ₁ Greater than width W ₁ . Specifically, each arm 98 has a length L in a direction radiating from the central portion ₁ And has a width W in a direction perpendicular to the direction of radiation from the central portion ₁ . In some embodiments, length L ₁ In the range of 15 μm to 20 μm, and a width W ₁ In the range of 15 μm to 20 μm. In other embodiments (not separately shown), the plurality of arms 98 of the magnetic cross have different widths W ₁ And/or different lengths L ₁ 。

In some embodiments, as shown in FIG. 15B, the plurality of arms 98 of the magnetic cross have equal widths W ₁ And equal length L ₁ Wherein the length L ₁ Less than width W ₁ . Specifically, each arm 98 has a length L in a direction radiating from the central portion ₁ And has a width W in a direction perpendicular to the direction of radiation from the central portion ₁ . Width W in the embodiment of fig. 15B ₁ Greater than width W in the embodiment of fig. 15A ₁ . In some embodiments, length L ₁ In the range of 15 μm to 20 μm, and a width W ₁ In the range of 15 μm to 20 μm. In other embodiments (not separately shown), the plurality of arms 98 of the magnetic cross have different widths W ₁ And/or different lengths L ₁ 。

Bonding on waferDuring which the vertical force F generated by the magnetic cross _V (see FIG. 12) the strength is determined by the thickness T of the arm 98 ₁ (previously described) and width W thereof ₁ And (5) determining. Table 1 lists the vertical forces F generated by magnetic crosses of various thicknesses and arm widths _V . As shown in Table 1, given the same thickness T ₁ A magnetic cross with a wider arm (e.g., as shown in fig. 15B) generates a greater vertical force F than a magnetic cross with a narrower arm (e.g., as shown in fig. 15A) _V 。

	W of 15 μm ₁	W of 20 μm ₁
			T of 0.3 μm ₁	7.2E-7N	9.5E-7N
T of 0.5 μm ₁	1.5E-6N	2.2E-6N
			T of 0.7 μm ₁	2.6E-6N	3.8E-6N

Table 1

As shown in fig. 15C-15D, the alignment mark 84 may be a single magnetic feature 96, wherein the magnetic feature 96 is a magnetic stripe. Similar to the embodiments described above with respect to fig. 4A-4B, the magnetic stripe is formed by applying a magnetic field 102 (see fig. 4A) to the ferromagnetic feature. When the magnetic feature 96 is a magnetic stripe, the magnetic field 102 (see fig. 4A) used to magnetize the magnetic stripe has a direction along the longitudinal direction (e.g., the Y-direction) of the magnetic stripe.

In some embodiments, as shown in fig. 15C, the magnetic stripe has a rectangular shape. Specifically, the magnetic stripe has a length L along a first direction (e.g., Y-direction) ₁ And a width W along a second direction (e.g., X direction) ₁ Wherein the length L ₁ Greater than width W ₁ . In some embodiments, length L ₁ In the range of 15 μm to 20 μm, and a width W ₁ In the range of 15 μm to 20 μm. The magnetization direction of the magnetic stripe is along its longitudinal direction (e.g., Y-direction).

In some embodiments, as shown in fig. 15D, the magnetic stripe has a square shape. Specifically, the magnetic stripe has a length L along a first direction (e.g., Y-direction) ₁ And a width W along a second direction (e.g., X direction) ₁ Wherein the length L ₁ Equal to width W ₁ . Width W in the embodiment of fig. 15D ₁ Greater than width W in the embodiment of fig. 15C ₁ . In some embodiments, length L ₁ In the range of 15 μm to 20 μm, and a width W ₁ In the range of 15 μm to 20 μm. The magnetization direction of the magnetic stripe may be along either direction (e.g., the X-direction or the Y-direction).

Vertical force F generated by the magnetic stripe during wafer bonding _V (see FIG. 12) from its thickness T ₁ (previously described) and width W thereof ₁ And (5) determining. Table 2 lists the vertical forces F generated by magnetic strips of various thicknesses and widths _V . As shown in Table 2, given the same thickness T ₁ A magnetic stripe having a larger width (e.g., as shown in fig. 15D) generates a greater vertical force F than a magnetic stripe having a smaller width (e.g., as shown in fig. 15C) _V 。

	W of 15 μm ₁	W of 20 μm ₁
			T of 0.3 μm ₁	7.3E-7N	1.0E-6N
T of 0.5 μm ₁	1.5E-6N	2.1E-6N
			T of 0.7 μm ₁	2.6E-6N	3.8E-6N

Table 2

As shown in fig. 15E-15H, alignment mark 84 may include a plurality of magnetic features 96. The magnetic feature 96 may be a magnetic cross or a magnetic stripe. The use of multiple magnetic features 96 for each alignment mark 84 may increase the vertical force F generated by the alignment mark 84 during wafer bonding _V (see fig. 12).

In some embodiments, as shown in FIG. 15E, the alignment mark 84 includes two magnetic features 96 (which are magnetic strips). The magnetic features 96 are arranged side by side such that their end sides are aligned. In this embodiment, the longitudinal direction of both magnetic features 96 is parallel to the first direction (e.g., the Y-direction). In another embodiment, the longitudinal direction of both magnetic features 96 is parallel to the second direction (e.g., the X-direction).

In some embodiments, as shown in fig. 15F, the alignment mark 84 includes two magnetic features 96 (which are magnetic strips). The magnetic features 96 are arranged in different directions. Specifically, the longitudinal direction of the first magnetic feature 96 is parallel to a first direction (e.g., the Y-direction) and the longitudinal direction of the second magnetic feature 96 is parallel to a second direction (e.g., the X-direction).

In some embodiments, as shown in FIG. 15G, the alignment marks 84 include magnetic features 96 as magnetic strips arranged in a grid including rows of magnetic strips. The magnetic stripe has a high density in each grid. In some embodiments, each alignment mark 84 includes 1 to 500 magnetic strips. The magnetic strips in the grid may be smaller than the magnetic strips described for fig. 15C-15F. The magnetic stripe has a length L along a first direction (e.g., Y-direction) ₁ And a width W along a second direction (e.g., X direction) ₁ Wherein the length L ₁ Greater than width W ₁ . In some embodiments, the length L of each magnetic stripe ₁ In the range of 0.2 μm to 20 μm (e.g., in the range of 0.2 μm to 10 μm), and the width W of each magnetic stripe ₁ In the range of 0.2 μm to 20 μm (e.g. in the range of 0.2 μm to 10 μm). The longitudinal axes of the magnetic strips are all aligned along their longitudinal direction (e.g., Y-direction).

The magnetic strips in a row are separated by a distance D along a first direction (e.g., Y-direction) ₁ And the rows of magnetic strips are separated by a distance D along a second direction (e.g., X-direction) ₂ . In some embodiments, distance D ₁ In the range of 0.1 μm to 0.4 μm, and a distance D ₂ In the range of 0.1 μm to 0.4 μm. Within the grid, alternating rows of magnetic strips are offset from each other along their longitudinal direction (e.g., Y-direction) by a distance D ₃ And every other row of magnetic strips is aligned along their longitudinal direction (e.g., Y-direction). In some embodiments, distance D ₃ In the range of 0.4 μm to 9.6 μm. Offsetting alternating rows of magnetic stripes may improve the accuracy of the alignment process utilizing alignment marks 84.

In some embodiments, as shown in fig. 15H, the alignment marks 84 include magnetic features 96 that are magnetic crosses arranged in a grid of rows that include the magnetic crosses. The magnetic cross has a high density in each grid. In some embodiments, each alignment mark 84 includes 1 to 500 magnetic crosses. The magnetic cross in the grid may be smaller than the magnetic described for fig. 15A-15B A cross. In some embodiments, the length L of each arm 98 ₁ In the range of 0.4 μm to 5 μm, and the width W of each arm 98 ₁ In the range of 0.4 μm to 5 μm.

The magnetic crosses in a row are spaced apart along a first direction (e.g., Y-direction) by a distance D ₁ . In some embodiments, distance D ₁ In the range of 0.1 μm to 5 μm. The arms 98 of adjacent rows of magnetic crosses may overlap each other along the longitudinal axis of these arms 98. Within the grid, alternating rows of magnetic crosses are offset from each other along their longitudinal direction (e.g., Y-direction) by a distance D ₃ And every other row of the magnetic cross is aligned along their longitudinal direction (e.g., Y-direction). In some embodiments, distance D ₃ In the range of 0.2 μm to 10 μm. Offsetting alternating rows of magnetic crosses may improve the accuracy of an alignment process utilizing alignment marks 84.

Fig. 16-17 are views of intermediate steps during a process for forming alignment marks for wafers according to some other embodiments. As previously described, different wafers may be formed with alignment marks that include magnetic features having opposite magnetic polarities. Fig. 16-17 show the alignment marks 84 of fig. 15G-15H, respectively, during a magnetization process (previously described with respect to fig. 4A-4B) for the alignment marks 84. The first magnetic field 102A is used to magnetize the first magnetic feature 96A of the first alignment mark 84A of the first wafer. The second magnetic field 102B is used to magnetize the second magnetic feature 96B of the second alignment mark 84B of the second wafer. The first magnetic field 102A has an opposite magnetic polarity to the second magnetic field 102B. When the magnetic features 96A, 96B are magnetic crosses, as shown in fig. 17, the first magnetic field 102A forms a first non-zero angle with each arm of the first magnetic feature 96A and the second magnetic field 102B forms a second non-zero angle with each arm of the second magnetic feature 96B.

Embodiments may achieve a number of advantages. Forming magnetic alignment marks 84 in wafer 70 may improve the accuracy of the alignment process during bonding of wafer 70. Specifically, the two wafers 70A, 70B are formed with alignment marks 84A, 84B having opposite magnetic polarities. As a result, when wafers 70A, 70B are bonded together, first alignment mark 84A is magnetically attracted to second alignment mark 84B. The magnetic attraction between the alignment marks 84A, 84B generates a horizontal force in a horizontal plane (parallel to the front surface 70F of the wafer 70A, 70B) and is large enough to move the wafer in the horizontal plane such that the first alignment mark 84A is aligned with the second alignment mark 84B. Magnetic self-alignment between the wafers 70A, 70B may be achieved and utilized during bonding may reduce misalignment between the bonded wafers 70A, 70B.

In one embodiment, a method includes: forming a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first magnetic cross, the first magnetic cross including a first north pole and a first south pole, the first north pole including a first adjacent arm of the first magnetic cross, the first south pole including a second adjacent arm of the first magnetic cross, the second wafer including a second alignment mark, the second alignment mark including a second magnetic cross, the second magnetic cross including a second north pole and a second south pole, the second north pole including a first adjacent arm of the second magnetic cross, the second south pole including a second adjacent arm of the second magnetic cross; aligning the first alignment mark with the second alignment mark in an optical alignment process; aligning the first alignment mark with the second alignment mark in a magnetic alignment process after the optical alignment process, wherein the first north pole is aligned with the second south pole and the first south pole is aligned with the second north pole; and forming a bond between the first wafer and the second wafer. In some embodiments of the method, the first alignment mark comprises a first grid of a plurality of first magnetic crosses, the first magnetic cross being one of the plurality of first magnetic crosses, wherein alternating rows of the plurality of first magnetic crosses within the first grid are offset from each other. In some embodiments of the method, every other row of the first plurality of magnetic crosses is aligned. In some embodiments of the method, the first magnetic cross and the second magnetic cross each comprise cobalt-iron-nickel doped with boron, silicon, or molybdenum. In some embodiments of the method, the first wafer further includes a first dielectric layer and a first bond pad, the first alignment mark and the first bond pad are formed in the first dielectric layer, the second wafer further includes a second dielectric layer and a second bond pad, the second alignment mark and the second bond pad are formed in the second dielectric layer, and the first bond pad, the second bond pad, the first alignment mark, and the second alignment mark are formed of the same magnetic material. In some embodiments of the method, the first wafer further includes a first dielectric layer and a first bond pad, the first alignment mark and the first bond pad are formed in the first dielectric layer, the second wafer further includes a second dielectric layer and a second bond pad, the second alignment mark and the second bond pad are formed in the second dielectric layer, the first bond pad and the second bond pad are formed of a conductive material, the first alignment mark and the second alignment mark are formed of a magnetic material, and the conductive material is different from the magnetic material. In some embodiments of the method, the first wafer further comprises a first dielectric layer, the first alignment mark is formed in the first dielectric layer, the second wafer further comprises a second dielectric layer, the second alignment mark is formed in the second dielectric layer, and forming a bond between the first wafer and the second wafer comprises: forming a dielectric-dielectric bond between the first dielectric layer and the second dielectric layer; and forming a metal-to-metal bond between the first alignment mark and the second alignment mark.

In one embodiment, a method includes: applying a first magnetic field to a first wafer to magnetize first alignment marks of the first wafer, the first alignment marks each comprising a plurality of first magnetic crosses, the first magnetic field forming a first non-zero angle with first arms of the plurality of first magnetic crosses; applying a second magnetic field to a second wafer to magnetize second alignment marks of the second wafer, the second alignment marks each comprising a plurality of second magnetic crosses, the second magnetic field forming a second non-zero angle with a second arm of the plurality of second magnetic crosses, the first magnetic field having an opposite polarity than the second magnetic field; moving the first wafer toward the second wafer until the first and second alignment marks apply horizontal and vertical forces to the first and second wafers; and forming a bond between the first wafer and the second wafer. In some embodiments of the method, the first magnetic field has a different strength than the second magnetic field. In some embodiments of the method, the first magnetic field has the same strength as the second magnetic field. In some embodiments of the method, each of the first arms has a first width, each of the first arms has a first length, and the first length is greater than the first width. In some embodiments of the method, each of the first arms has a first width, each of the first arms has a first length, and the first length is less than the first width. In some embodiments of the method, the plurality of first magnetic crosses of each of the first alignment marks are arranged in a first grid, and first arms of the plurality of first magnetic crosses in adjacent rows of the first grid overlap. In some embodiments of the method, moving the first wafer toward the second wafer begins to move the first alignment mark and the second alignment mark to an aligned position, the method further comprising: after moving the first wafer toward the second wafer, waiting until the first alignment mark and the second alignment mark finish moving to the alignment position. In some embodiments of the method, waiting until the first alignment mark and the second alignment mark finish moving to the alignment position comprises waiting for a duration in the range of 10 μs to 5000 μs. In some embodiments of the method, forming a bond between the first wafer and the second wafer comprises: contacting a first dielectric layer of the first wafer with a second dielectric layer of the second wafer; contacting a first alignment mark of the first wafer with a second alignment mark of the second wafer; and annealing the first wafer and the second wafer.

In one embodiment, a structure comprises: a first device comprising a first dielectric layer and a first alignment mark in the first dielectric layer, the first alignment mark comprising a first magnetic cross having a first north pole and a first south pole; and a second device comprising a second dielectric layer and a second alignment mark in the second dielectric layer, the second alignment mark comprising a second magnetic cross having a second north pole and a second south pole, the first north pole aligned with the second south pole, the first south pole aligned with the second north pole, the first dielectric layer bonded to the second dielectric layer by a dielectric-dielectric bond, the first alignment mark bonded to the second alignment mark by a metal-metal bond. In some embodiments of the structure, the first alignment mark comprises a first grid of a plurality of first magnetic crosses, the first magnetic cross being one of the plurality of first magnetic crosses, wherein alternating rows of the plurality of first magnetic crosses within the first grid are offset from one another. In some embodiments of the structure, the plurality of first magnetic crosses include first arms, and the first arms of the plurality of first magnetic crosses in adjacent rows of the first grid overlap. In some embodiments of the structure, the first north pole comprises a first adjacent arm of the first magnetic cross and the first south pole comprises a second adjacent arm of the first magnetic cross.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a method of fabricating a semiconductor structure, comprising: forming a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first magnetic cross, the first magnetic cross including a first north pole and a first south pole, the first north pole including a first adjacent arm of the first magnetic cross, the first south pole including a second adjacent arm of the first magnetic cross, the second wafer including a second alignment mark, the second alignment mark including a second magnetic cross, the second magnetic cross including a second north pole and a second south pole, the second north pole including a first adjacent arm of the second magnetic cross, the second south pole including a second adjacent arm of the second magnetic cross; aligning the first alignment mark with the second alignment mark in an optical alignment process;

Aligning the first alignment mark with the second alignment mark in a magnetic alignment process after the optical alignment process, wherein the first north pole is aligned with the second south pole and the first south pole is aligned with the second north pole; and forming a bond between the first wafer and the second wafer.

Example 2 is the method of example 1, wherein the first alignment mark comprises a first grid of a plurality of first magnetic crosses, the first magnetic cross being one of the plurality of first magnetic crosses, wherein alternating rows of the plurality of first magnetic crosses within the first grid are offset from one another.

Example 3 is the method of example 2, wherein every other row of the first plurality of magnetic crosses is aligned.

Example 4 is the method of example 1, wherein the first magnetic cross and the second magnetic cross each comprise cobalt-iron-nickel doped with boron, silicon, or molybdenum.

Example 5 is the method of example 1, wherein the first wafer further comprises a first dielectric layer and a first bond pad, the first alignment mark and the first bond pad are formed in the first dielectric layer, the second wafer further comprises a second dielectric layer and a second bond pad, the second alignment mark and the second bond pad are formed in the second dielectric layer, and the first bond pad, the second bond pad, the first alignment mark, and the second alignment mark are formed of the same magnetic material.

Example 6 is the method of example 1, wherein the first wafer further comprises a first dielectric layer and a first bond pad, the first alignment mark and the first bond pad are formed in the first dielectric layer, the second wafer further comprises a second dielectric layer and a second bond pad, the second alignment mark and the second bond pad are formed in the second dielectric layer, the first bond pad and the second bond pad are formed of a conductive material, the first alignment mark and the second alignment mark are formed of a magnetic material, and the conductive material is different from the magnetic material.

Example 7 is the method of example 1, wherein the first wafer further comprises a first dielectric layer, the first alignment mark is formed in the first dielectric layer, the second wafer further comprises a second dielectric layer, the second alignment mark is formed in the second dielectric layer, and forming a bond between the first wafer and the second wafer comprises: forming a dielectric-dielectric bond between the first dielectric layer and the second dielectric layer; and forming a metal-to-metal bond between the first alignment mark and the second alignment mark.

Example 8 is a method of fabricating a semiconductor structure, comprising: applying a first magnetic field to a first wafer to magnetize first alignment marks of the first wafer, the first alignment marks each comprising a plurality of first magnetic crosses, the first magnetic field forming a first non-zero angle with first arms of the plurality of first magnetic crosses; applying a second magnetic field to a second wafer to magnetize second alignment marks of the second wafer, the second alignment marks each comprising a plurality of second magnetic crosses, the second magnetic field forming a second non-zero angle with a second arm of the plurality of second magnetic crosses, the first magnetic field having an opposite polarity than the second magnetic field; moving the first wafer toward the second wafer until the first and second alignment marks apply horizontal and vertical forces to the first and second wafers; and forming a bond between the first wafer and the second wafer.

Example 9 is the method of example 8, wherein the first magnetic field has a different strength than the second magnetic field.

Example 10 is the method of example 8, wherein the first magnetic field has the same strength as the second magnetic field.

Example 11 is the method of example 8, wherein each of the first arms has a first width, each of the first arms has a first length, and the first length is greater than the first width.

Example 12 is the method of example 8, wherein each of the first arms has a first width, each of the first arms has a first length, and the first length is less than the first width.

Example 13 is the method of example 8, wherein the plurality of first magnetic crosses of each of the first alignment marks are arranged in a first grid, and first arms of the plurality of first magnetic crosses in adjacent rows of the first grid overlap.

Example 14 is the method of example 8, wherein moving the first wafer toward the second wafer begins moving the first alignment mark and the second alignment mark to an aligned position, the method further comprising: after moving the first wafer toward the second wafer, waiting until the first alignment mark and the second alignment mark finish moving to the alignment position.

Example 15 is the method of example 14, wherein waiting until the first alignment mark and the second alignment mark finish moving to the aligned position comprises waiting a duration in a range of 10 μs to 5000 μs.

Example 16 is the method of example 8, wherein forming a bond between the first wafer and the second wafer comprises: contacting a first dielectric layer of the first wafer with a second dielectric layer of the second wafer; contacting a first alignment mark of the first wafer with a second alignment mark of the second wafer; and annealing the first wafer and the second wafer.

Example 17 is a semiconductor structure, comprising: a first device comprising a first dielectric layer and a first alignment mark in the first dielectric layer, the first alignment mark comprising a first magnetic cross having a first north pole and a first south pole; and a second device comprising a second dielectric layer and a second alignment mark in the second dielectric layer, the second alignment mark comprising a second magnetic cross having a second north pole and a second south pole, the first north pole aligned with the second south pole, the first south pole aligned with the second north pole, the first dielectric layer bonded to the second dielectric layer by a dielectric-dielectric bond, the first alignment mark bonded to the second alignment mark by a metal-metal bond.

Example 18 is the structure of example 17, wherein the first alignment mark comprises a first grid of a plurality of first magnetic crosses, the first magnetic cross being one of the plurality of first magnetic crosses, wherein alternating rows of the plurality of first magnetic crosses within the first grid are offset from one another.

Example 19 is the structure of example 18, wherein the plurality of first magnetic crosses includes first arms, and the first arms of the plurality of first magnetic crosses in adjacent rows of the first grid overlap.

Example 20 is the structure of example 17, wherein the first north pole comprises a first adjacent arm of the first magnetic cross and the first south pole comprises a second adjacent arm of the first magnetic cross.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first magnetic cross, the first magnetic cross including a first north pole and a first south pole, the first north pole including a first adjacent arm of the first magnetic cross, the first south pole including a second adjacent arm of the first magnetic cross, the second wafer including a second alignment mark, the second alignment mark including a second magnetic cross, the second magnetic cross including a second north pole and a second south pole, the second north pole including a first adjacent arm of the second magnetic cross, the second south pole including a second adjacent arm of the second magnetic cross;

Aligning the first alignment mark with the second alignment mark in an optical alignment process;

aligning the first alignment mark with the second alignment mark in a magnetic alignment process after the optical alignment process, wherein the first north pole is aligned with the second south pole and the first south pole is aligned with the second north pole; and

a bond is formed between the first wafer and the second wafer.

2. The method of claim 1, wherein the first alignment mark comprises a first grid of a plurality of first magnetic crosses, the first magnetic cross being one of the plurality of first magnetic crosses, wherein alternating rows of the plurality of first magnetic crosses within the first grid are offset from one another.

3. The method of claim 2, wherein every other row of the first plurality of magnetic crosses is aligned.

4. The method of claim 1, wherein the first and second magnetic crosses each comprise cobalt-iron-nickel doped with boron, silicon, or molybdenum.

5. The method of claim 1, wherein the first wafer further comprises a first dielectric layer and a first bond pad, the first alignment mark and the first bond pad are formed in the first dielectric layer, the second wafer further comprises a second dielectric layer and a second bond pad, the second alignment mark and the second bond pad are formed in the second dielectric layer, and the first bond pad, the second bond pad, the first alignment mark, and the second alignment mark are formed of the same magnetic material.

6. The method of claim 1, wherein the first wafer further comprises a first dielectric layer and a first bond pad, the first alignment mark and the first bond pad are formed in the first dielectric layer, the second wafer further comprises a second dielectric layer and a second bond pad, the second alignment mark and the second bond pad are formed in the second dielectric layer, the first bond pad and the second bond pad are formed of a conductive material, the first alignment mark and the second alignment mark are formed of a magnetic material, and the conductive material is different from the magnetic material.

7. The method of claim 1, wherein the first wafer further comprises a first dielectric layer, the first alignment mark is formed in the first dielectric layer, the second wafer further comprises a second dielectric layer, the second alignment mark is formed in the second dielectric layer, and forming a bond between the first wafer and the second wafer comprises:

forming a dielectric-dielectric bond between the first dielectric layer and the second dielectric layer; and

a metal-to-metal bond is formed between the first alignment mark and the second alignment mark.

8. A method of fabricating a semiconductor structure, comprising:

applying a first magnetic field to a first wafer to magnetize first alignment marks of the first wafer, the first alignment marks each comprising a plurality of first magnetic crosses, the first magnetic field forming a first non-zero angle with first arms of the plurality of first magnetic crosses;

applying a second magnetic field to a second wafer to magnetize second alignment marks of the second wafer, the second alignment marks each comprising a plurality of second magnetic crosses, the second magnetic field forming a second non-zero angle with a second arm of the plurality of second magnetic crosses, the first magnetic field having an opposite polarity than the second magnetic field;

moving the first wafer toward the second wafer until the first and second alignment marks apply horizontal and vertical forces to the first and second wafers; and

a bond is formed between the first wafer and the second wafer.

9. The method of claim 8, wherein the first magnetic field has a different strength than the second magnetic field.

10. A semiconductor structure, comprising:

a first device comprising a first dielectric layer and a first alignment mark in the first dielectric layer, the first alignment mark comprising a first magnetic cross having a first north pole and a first south pole; and

A second device comprising a second dielectric layer and a second alignment mark in the second dielectric layer, the second alignment mark comprising a second magnetic cross having a second north pole and a second south pole, the first north pole aligned with the second south pole, the first south pole aligned with the second north pole, the first dielectric layer bonded to the second dielectric layer by a dielectric-dielectric bond, the first alignment mark bonded to the second alignment mark by a metal-metal bond.