CN116521236A - Pipelined decoding method based on RISC-V instruction set - Google Patents
Pipelined decoding method based on RISC-V instruction set Download PDFInfo
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- CN116521236A CN116521236A CN202310524664.7A CN202310524664A CN116521236A CN 116521236 A CN116521236 A CN 116521236A CN 202310524664 A CN202310524664 A CN 202310524664A CN 116521236 A CN116521236 A CN 116521236A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a pipeline decoding method based on RISC-V instruction set, comprising the following steps: the first stage, after the instruction is read out from the instruction cache, decoding is carried out aiming at the program flow control instruction and the AUIPC instruction, and decoding of the instruction branch type and calculation of the target address are completed; the second stage, each field of the instruction is split and decoded, and each field attribute is decoded, including register addresses of a source operand and a destination operand, a fixed floating point type and an immediate effective identifier; thirdly, completing decoding of the instruction execution unit type according to decoding information of each field of the instruction in the previous stage; and the fourth stage, completing decoding of the operation type. Aiming at the characteristics of different pipeline stages in the high-performance processor, the invention obtains necessary instruction information by stage decoding so as to realize pipelining of a control path, optimize the time sequence of individual decoding stages and further improve the performance of the processor.
Description
Technical Field
The invention relates to the technical field of instruction pipeline decoding, in particular to a pipeline decoding method based on a RISC-V instruction set.
Background
RISC-V is a fifth generation reduced instruction set, and is favored by industry and academia due to its stable, open, and compatible properties. The RISC-V instruction set is in a modularized instruction set structure, in a certain high-performance processing design, an RV64G subset is selected, the instruction length is 32 bits, and the lowest two bits are fixed to be 11 with 2 bits. The instruction coding formats are 6 types, and are respectively: r-type instructions are used for register-to-register operations; type I instructions are used for short immediate and memory load operations; the S type instruction is used for accessing the memory store operation; the type B instruction is used for conditional jump operation; the U-type instruction is used for long immediate operations; type J instructions are used for unconditional jump operations. In the conventional processor design, the decoding logic is often placed on the first-stage pipeline, and in this way, the decoding circuit is mostly a combinational logic, which causes time sequence tension.
Disclosure of Invention
Aiming at the characteristics of different pipeline stages in a high-performance processor, the invention provides a pipeline decoding method based on a RISC-V instruction set, which obtains necessary instruction information by stage decoding so as to realize pipelining of a control path, optimize the time sequence of individual decoding stages and further improve the performance of the processor.
The technical scheme of the invention is as follows:
a pipelined decoding method based on a RISC-V instruction set, for decoding the RISC-V instruction set, comprising:
the first stage, after the instruction is read out from the instruction cache, decoding is carried out aiming at the program flow control instruction and the AUIPC instruction, the decoding of the instruction branch type and the calculation of the target address are completed, and the instructions of other types are continuously and downwards entered into the next stage;
the second stage, each field of the instruction is split and decoded, and each field attribute is decoded, including register addresses of a source operand and a destination operand, a fixed floating point type and an immediate effective identifier;
the third stage, according to the decoding information of each field of the instruction of the previous stage, the decoding of the instruction execution unit type is completed, including RISC-V instruction operation code decoding, operation code compression and abnormality detection logic, the operation code of the instruction describes the operation of the execution unit corresponding to the instruction, and at the same time, the instruction abnormality identification and the abnormality operation code are obtained through the abnormality detection in the decoding;
and in the fourth stage, decoding of the operation type is completed, namely, splicing and expanding operation of the immediate is completed according to the compressed operation code, operand type and operand value, and meanwhile, decoding and transmitting of the execution code of the instruction to each execution unit are completed according to the execution code of the instruction.
Further, in the second stage, first, the fetched instruction information is cached at a first pipeline stage.
Further, in the third stage, decoding of the ROB opcode in the reorder buffer within the instruction is completed.
Further, in the third stage, the instruction exception flag is triggered when an illegal instruction exception or breakpoint exception is detected by the instruction.
Further, in the fourth stage, an instruction execution unit function code is assigned to the instruction, the instruction execution unit function code corresponding to the execution unit of the instruction, and the instruction is issued to a different execution unit according to the instruction execution unit function code.
The invention also provides a pipeline decoding module based on RISC-V instruction set, which is characterized in that the pipeline decoding module is used for decoding the RISC-V instruction set and comprises the following components:
the pre-decoding module decodes the program flow control type instruction and the AUIPC instruction after the instruction is read from the instruction cache, finishes decoding of the instruction branch type and calculation of the target address, and continuously and downwards enters the next stage for other types of instructions;
the decoding module is used for splitting and decoding each field of the instruction to obtain each field attribute, wherein each field attribute comprises a register address of a source operand and a destination operand, a fixed floating point type and an immediate effective identifier;
the post-decoding module is used for finishing decoding of the instruction execution unit type according to the decoding information of each field of the instruction at the previous stage, and comprises RISC-V instruction operation code decoding, operation code compression and abnormality detection logic, wherein the operation code of the instruction describes the operation of the execution unit corresponding to the instruction, and meanwhile, the instruction abnormality identification and the abnormality operation code are obtained through abnormality detection in decoding;
and the transmitting module is used for completing decoding of the operation type, namely completing splicing and expanding operation of the immediate number according to the compressed operation code, operand type and operand value, and simultaneously transmitting the operation code decoded by the instruction to each executing unit.
Further, in the decoding module, first, the fetched instruction information is cached at a first pipeline stage.
Further, in the post-decoding module, decoding of the ROB operation code in the reorder buffer in the instruction is completed.
Further, in the post-decoding module, an instruction exception identifier is triggered when an instruction is detected as an illegal instruction exception or a breakpoint exception.
Further, in the transmitting module, an instruction execution unit function code is allocated to the instruction, the instruction execution unit function code corresponds to an execution unit of the instruction, and the instruction is transmitted to different execution units according to the instruction execution unit function code.
The invention also provides a superscalar processor which is characterized by being used for executing any of the pipeline decoding methods based on the RISC-V instruction set when the instruction is decoded in a pipeline.
In summary, the beneficial effects of the invention are as follows: for the high-performance superscalar processor, the decoding logic unit is always used as a key path, the time sequence of the decoding logic is optimized, the decoding logic is split into different pipeline segments for execution according to the pipeline control logic, and the time sequence pressure of the decoding module is shared, so that the decoding logic unit is not used as a frequency bottleneck of the processor to influence the performance of the processor.
Drawings
FIG. 1 is a schematic diagram of RISC-V instruction set encoding type one;
FIG. 2 is a schematic diagram II of the RISC-V instruction set encoding type;
FIG. 3 is a schematic diagram of the division and naming of the fields of a RISC-V instruction;
FIG. 4 is a flow chart of pipeline decode logic of the present invention.
Detailed Description
The following describes in detail the embodiments of the present invention with reference to the drawings.
Examples: a pipeline decoding method based on RISC-V instruction set is used for decoding RISC-V instruction set.
As previously mentioned, the RISC-V instruction set instruction encoding format is of 6 types, respectively: r-type instructions are used for register-to-register operations; type I instructions are used for short immediate and memory load operations; the S type instruction is used for accessing the memory store operation; the type B instruction is used for conditional jump operation; the U-type instruction is used for long immediate operations; type J instructions are used for unconditional jump operations. The field partitioning of various types of instructions is shown in fig. 1-3, where the R4 type is a variation of the R format, primarily for floating point 4 operand class instructions, such as multiply-add instructions.
The method comprises four stages.
In the first stage, after the instruction is read out from the instruction cache, decoding is carried out for the program flow control instruction and the AUIPC instruction, decoding of the instruction branch type and calculation of the target address are completed, and the other types of instructions are continuously and downwards entered into the next stage.
And the second stage is used for caching the fetched instruction information into a first pipeline stage, so as to avoid the execution unit from executing slower blocking instruction fetching, and enable the instruction energy to be continuously supplied to the execution stage. Meanwhile, all fields of the instruction are split and decoded at the stage, and all field attributes including register addresses of source operands and destination operands, fixed floating point types and effective identification of immediate are decoded; this information needs to be provided to the register renaming so decoding needs to be done at this stage.
The third stage, according to the decoding information of each field of the instruction of the previous stage, the decoding of the instruction execution unit type is completed, including RISC-V instruction operation code decoding, operation code compression and abnormality detection logic, the operation code of the instruction describes the operation of the execution unit corresponding to the instruction, and at the same time, the instruction abnormality identification and the abnormality operation code are obtained through the abnormality detection in the decoding; the instruction exception identifier is triggered when an illegal instruction exception or a breakpoint exception is detected by the instruction. And the decoding of the ROB operation code is completed at this stage, and the ROB operation code is used by an instruction dispatch unit and the ROB for distinguishing each non-execution type instruction.
And a fourth stage, in a transmitting stage before the executing stage, the decoding of the operation type is finished, namely, the splicing and expanding operation of the immediate number is finished according to the compressed operation code, operand type and operand value, and meanwhile, the decoding and transmitting of the execution code of the instruction to each execution unit are finished. In the fourth stage, an instruction execution unit function code is assigned to an instruction, the instruction execution unit function code corresponding to an execution unit of the instruction, the instruction being issued to a different execution unit according to the instruction execution unit function code.
The instruction is pipelined decoded by the stages described above, and the decoding logic flow diagram is shown in FIG. 4.
In fig. 4, the operation format code is a hybrid code in which an operation code (opcode) of an instruction and a coding format (function) of the instruction are combined. Wherein the fields of the instruction and the attributes of the fields are information necessary for renaming logic, require earlier translations. The type of execution unit of the instruction is the necessary logic for dispatch and may be decoded later. Pipeline each stage noun interpretation:
branch type opcode: the method comprises the steps of obtaining branch instruction information by decoding instruction operation codes of a branch instruction, JAL, JALR and AUIPC changing program flow, and pre-decoding branch prediction to jump to a corresponding destination address in advance;
destination address: the destination address of the branch jump instruction is the PC address corresponding to the next instruction;
branch and other types of instruction distinction: other non-jump instructions are distinguished through operation codes of the branch instructions, so that the non-jump instructions can enter a next stage pipeline for sequential decoding;
splitting each field of the instruction: splitting the fields of the RISC-V instruction of FIG. 2
The attribute identification of each field of the instruction: decoding attributes represented in RISC-V instruction field to identify whether it is a general purpose register index or an immediate field, and if it is a general purpose register index, whether it is a scalar register or a floating point register
Execution unit type: the execution unit includes: the fixed point operation unit, the floating point operation unit, the memory access unit and the like are used for distinguishing different types of instructions through instruction operation format codes and entering different execution units for processing;
and (3) anomaly identification: in the decoding process, the instruction is subjected to abnormality detection, and if illegal instruction abnormality occurs, the breakpoint abnormality triggers an abnormality mark;
instruction execution unit function code: corresponding to the execution units of the instructions, different execution unit functional codes are allocated to several types of instructions in the instructions entering a certain execution unit, and the subsequent transmitting stage transmits the instructions to different execution units according to the unit functional codes of the instructions.
The invention also provides a pipeline decoding module based on RISC-V instruction set, which is characterized in that the pipeline decoding module is used for decoding the RISC-V instruction set and comprises the following components:
the pre-decoding module decodes the program flow control type instruction and the AUIPC instruction after the instruction is read from the instruction cache, finishes decoding of the instruction branch type and calculation of the target address, and continuously and downwards enters the next stage for other types of instructions;
the decoding module caches the fetched instruction information into a first-level pipeline stage, and decodes each field of the instruction into each field attribute including register addresses of source operands and destination operands, fixed floating point types and effective identification of immediate numbers;
the post-decoding module is used for finishing decoding of the instruction execution unit type according to the decoding information of each field of the instruction at the previous stage, and comprises RISC-V instruction operation code decoding, operation code compression and abnormality detection logic, wherein the operation code of the instruction describes the operation of the execution unit corresponding to the instruction, and meanwhile, the instruction abnormality identification and the abnormality operation code are obtained through abnormality detection in decoding; in the post-decoding module, triggering an instruction exception identifier when an instruction is detected to be illegal or a breakpoint is abnormal; in the post-decoding module, the decoding of the ROB operation code in the reorder buffer in the instruction is completed;
the transmitting module is used for completing decoding of operation types, namely completing splicing and expanding operation of immediate numbers according to compressed operation codes, operand types and operand values, and simultaneously decoding and transmitting the execution codes of the instructions to each execution unit; in the transmitting module, an instruction execution unit function code is allocated to the instruction, the instruction execution unit function code corresponds to the execution unit of the instruction, and the instruction is transmitted to different execution units according to the instruction execution unit function code.
The invention also provides a superscalar processor which is characterized by being used for executing the pipeline decoding method based on the RISC-V instruction set when the instruction is decoded in a pipeline.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and improvements could be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the present invention.
Claims (10)
1. A pipelined decoding method based on a RISC-V instruction set, for decoding the RISC-V instruction set, comprising:
the first stage, after the instruction is read out from the instruction cache, decoding is carried out aiming at the program flow control instruction and the AUIPC instruction, the decoding of the instruction branch type and the calculation of the target address are completed, and the instructions of other types are continuously and downwards entered into the next stage;
the second stage, each field of the instruction is split and decoded, and each field attribute is decoded, including register addresses of a source operand and a destination operand, a fixed floating point type and an immediate effective identifier;
the third stage, according to the decoding information of each field of the instruction of the previous stage, the decoding of the instruction execution unit type is completed, including RISC-V instruction operation code decoding, operation code compression and abnormality detection logic, the operation code of the instruction describes the operation of the execution unit corresponding to the instruction, and at the same time, the instruction abnormality identification and the abnormality operation code are obtained through the abnormality detection in the decoding;
and in the fourth stage, decoding of the operation type is completed, namely, splicing and expanding operation of the immediate is completed according to the compressed operation code, operand type and operand value, and meanwhile, decoding and transmitting of the execution code of the instruction to each execution unit are completed according to the execution code of the instruction.
2. The method of claim 1, wherein in the second stage, first a first pipeline stage is cached for fetched instruction information.
3. The method of claim 1, wherein in the third stage, the instruction is decoded with a ROB operation code of a reorder buffer.
4. The RISC-V instruction set based pipeline decoding method of claim 1, wherein in the third stage, instruction exception identification is triggered when an instruction is detected as an illegal instruction exception or a breakpoint exception.
5. The method of claim 1, wherein in the fourth stage, an instruction execution unit function code is assigned to an instruction, the instruction execution unit function code corresponding to an execution unit of the instruction, and wherein the instruction is issued to a different execution unit based on the instruction execution unit function code.
6. A pipeline decode module based on a RISC-V instruction set, for decoding the RISC-V instruction set, comprising:
the pre-decoding module decodes the program flow control type instruction and the AUIPC instruction after the instruction is read from the instruction cache, finishes decoding of the instruction branch type and calculation of the target address, and continuously and downwards enters the next stage for other types of instructions;
the decoding module is used for splitting and decoding each field of the instruction to obtain each field attribute, wherein each field attribute comprises a register address of a source operand and a destination operand, a fixed floating point type and an immediate effective identifier;
the post-decoding module is used for finishing decoding of the instruction execution unit type according to the decoding information of each field of the instruction at the previous stage, and comprises RISC-V instruction operation code decoding, operation code compression and abnormality detection logic, wherein the operation code of the instruction describes the operation of the execution unit corresponding to the instruction, and meanwhile, the instruction abnormality identification and the abnormality operation code are obtained through abnormality detection in decoding;
and the transmitting module is used for completing decoding of the operation type, namely completing splicing and expanding operation of the immediate number according to the compressed operation code, operand type and operand value, and simultaneously transmitting the operation code decoded by the instruction to each executing unit.
7. The RISC-V instruction set based pipeline decode module according to claim 6, wherein the decode module first caches fetched instruction information by a first pipeline stage.
8. The RISC-V instruction set based pipeline decode module of claim 6, wherein in the post decode module, the decoding of the ROB opcode in the instruction is completed.
9. The RISC-V instruction set based pipeline decode module according to claim 6, wherein in the post-decode module, the instruction exception flag is triggered when an illegal instruction exception or a breakpoint exception is detected by the instruction.
10. The RISC-V instruction set based pipeline decode module of claim 6, wherein in the issue module, an instruction execution unit function code is assigned to an instruction, the instruction execution unit function code corresponding to an execution unit of the instruction, the instruction being issued to a different execution unit based on the instruction execution unit function code.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116991477A (en) * | 2023-08-03 | 2023-11-03 | 上海合芯数字科技有限公司 | Rotary instruction execution method, system and execution unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116991477A (en) * | 2023-08-03 | 2023-11-03 | 上海合芯数字科技有限公司 | Rotary instruction execution method, system and execution unit |
| CN116991477B (en) * | 2023-08-03 | 2024-01-30 | 上海合芯数字科技有限公司 | Rotary instruction execution method, system and execution unit |
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