CN116520613A

CN116520613A - Display substrate, display panel and display device

Info

Publication number: CN116520613A
Application number: CN202310638336.XA
Authority: CN
Inventors: 蒲巡; 王小元; 陈俊明; 刘艳; 杨国栋; 万彬
Original assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Priority date: 2023-05-31
Filing date: 2023-05-31
Publication date: 2023-08-01

Abstract

The embodiment of the invention discloses a display substrate, a display panel and a display device, wherein the display substrate comprises a display area and a fan-out area, and the fan-out area comprises a plurality of fan-out subareas; the fan-out subarea comprises a first group of pins and a second group of pins, the first group of pins comprises m first pins, the second group of pins comprises m second pins, m is more than 1, in the first direction, the first pins and the second pins in the nth fan-out subarea are alternately arranged, the second pins and the first pins in the (n+1) th fan-out subarea are alternately arranged, and n is a positive odd number; the first pin is connected with a first switching pin arranged on the same layer as the second pin, and the second pin is connected with a second switching pin arranged on the same layer as the first pin; the first pin in the nth fan-out subarea is led out to the display area through the first lead wire, the second pin is led out to the display area through the second lead wire, and the second pin in the (n+1) th fan-out subarea is led out to the display area through the first lead wire, and the first pin is led out to the display area through the second lead wire.

Description

Display substrate, display panel and display device

Technical Field

The invention relates to the technical field of display. And more particularly, to a display substrate, a display panel, and a display device.

Background

With the development of information technology, electronic devices are widely used in daily life of people, and the development of the technology is rapidly shown.

In a conventional Panel (Panel) design, a fan-out area of most panels includes a plurality of fan-out sub-areas, and pins of each fan-out sub-area are arranged in a double row, and in order to eliminate display defects caused by static discharge, pins of a first row and a second row are disposed in different metal layers. In addition, since the starting and ending positions of the pins are determined by the IC channel, the cycle order of the pins of the adjacent two fan-out subareas of the display panel is not consistent, and the metal layers of the pins adjacent to the left fan-out subarea and the right fan-out subarea are the same, so that the split screen phenomenon can occur when a specific picture is displayed.

Disclosure of Invention

The invention aims to provide a display substrate, a display panel and a display device, which are used for solving at least one of the problems of the related art.

In order to achieve the above purpose, the invention adopts the following technical scheme:

the first aspect of the invention provides a display substrate, which comprises a display area and a fan-out area positioned at one side of the display area, wherein the fan-out area comprises a plurality of fan-out subareas arranged along a first direction;

the fan-out subarea comprises a first group of pins and a second group of pins which are arranged along a second direction, the second direction is orthogonal to the first direction, the first group of pins comprises m first pins which are arranged along the first direction, the second group of pins comprises m second pins which are arranged along the first direction, m is more than 1, the first pins and the second pins are alternately arranged in the nth fan-out subarea in the first direction, the second pins and the first pins are alternately arranged in the (n+1) th fan-out subarea, and n is a positive odd number;

the first pin is connected with a first transfer pin arranged in the same layer as the second pin, and the second pin is connected with a second transfer pin arranged in the same layer as the first pin;

the first pin in the nth fan-out subarea is led out to the display area through a first lead wire, the second pin is led out to the display area through a second lead wire, the second pin in the (n+1) th fan-out subarea is led out to the display area through a first lead wire, and the first pin is led out to the display area through a second lead wire;

wherein the first lead is arranged in a same layer as one of the first pin and the second pin, and the second lead is arranged in a same layer as the other of the first pin and the second pin.

Optionally, the display area includes thin film transistors arranged in an array, and a source electrode and a drain electrode of the thin film transistors are formed on the source-drain metal layer;

one of the first pin and the second pin is arranged on the same layer as the grid electrode of the thin film transistor, and the other pin is arranged on the same layer as the source drain metal layer.

Optionally, the first transfer pin is located at a side of the first pin near the display area, and the second transfer pin is located at a side of the second pin near the display area.

Optionally, the line widths of the plurality of first leads are the same, and the line widths of the plurality of second leads are the same.

Optionally, the first pin is connected with a first transfer pin arranged on the same layer as the second pin through a first via hole;

the second pin is connected to a second transfer pin arranged on the same layer as the first pin through a second via hole.

Optionally, the display substrate further comprises an insulating layer comprising a first insulating layer and a second insulating layer,

the first insulating layer is positioned between the first pin and the second pin;

the second insulating layer is positioned at one side of the second pin, which is away from the first pin;

the first via hole comprises a third via hole exposing the first pin and a fourth via hole exposing the first transfer pin, and the second via hole comprises a fifth via hole exposing the second pin and a sixth via hole exposing the second transfer pin;

the fan-out sub-section further comprises a first switching electrode and a second switching electrode,

the first transfer electrode is electrically connected with the first pin through the third via hole and is electrically connected with a first transfer pin corresponding to the first pin through the fourth via hole;

the second transfer electrode is electrically connected with the second pin through the fifth via hole and is electrically connected with a second transfer pin corresponding to the second pin through the sixth via hole.

Optionally, the first transfer electrode and the second transfer electrode are indium tin oxide electrodes.

A second aspect of the present invention provides a display panel comprising the display substrate provided in the first aspect of the present invention.

Optionally, the display panel further includes:

an opposite substrate arranged opposite to the display substrate;

and the liquid crystal layer is positioned between the display substrate and the opposite substrate.

A third aspect of the present invention provides a display device comprising the display panel provided in the second aspect of the present invention.

The beneficial effects of the invention are as follows:

the display substrate provided by one embodiment of the invention is provided with a first group of pins and a second group of pins which are arranged in a second direction, wherein the first group of pins and the second group of pins are led out to a display area through first leads and second leads which are alternately arranged, and transfer pins are arranged, and the first pins in the first group of pins are connected with first transfer pins which are arranged in the same layer with the second pins in the second group of pins; the second pins in the second group of pins are connected with the second transfer pins which are arranged on the same layer as the first pins in the first group of pins, so that the pins can be connected to the display area through leads in the same sequence no matter how the IC channels are selected, the fan-out area can not have the condition that two adjacent leads are arranged on the same layer, the driving sequences of different fan-out subareas are consistent in a specific picture, no obvious difference exists in brightness, and the problem of split screen of the display substrate is solved.

Drawings

The following describes the embodiments of the present invention in further detail with reference to the drawings.

Fig. 1 shows a schematic structure of a fan-out area of the prior art.

Fig. 2 is a schematic structural view of a display substrate according to the prior art.

Fig. 3 shows a cross-sectional view of R-R' of fig. 1 as set forth in one embodiment of the prior art.

Fig. 4 is a schematic structural diagram of a display substrate according to an embodiment of the prior art.

Fig. 5 is a schematic diagram of a display substrate according to an embodiment of the prior art.

Fig. 6 is a schematic structural diagram of a display substrate according to an embodiment of the invention.

Fig. 7 shows a schematic diagram of a structure of a fan-out area according to an embodiment of the present invention.

Fig. 8 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.

Fig. 9 is a schematic diagram of a display substrate according to an embodiment of the invention.

Fig. 10-13 show schematic structural diagrams of a fan-out area according to an embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the present invention, the present invention will be further described with reference to examples and drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.

It should be appreciated that although the terms "first," "second," etc. may be used herein to describe various elements, these should not be interpreted as implying any order, number, or importance, but rather merely to distinguish between different components. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present disclosure. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In the description of the embodiments of the present disclosure, the azimuth or positional relationship indicated by the technical terms "center", "edge", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience in describing the embodiments of the present disclosure and to simplify the description, rather than to indicate or imply that the devices or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the embodiments of the present disclosure.

In conventional panel designs, when a display substrate is designed at a glass end, an integrated circuit Output pin (IC Output pad) of a fan-out area is generally designed in a double row, and in a specific example, as shown in fig. 1, the fan-out area includes a fan-out sub-area P and a fan-out sub-area Q disposed at left and right sides; since the power line C needs to be provided under the output pin of the integrated circuit and the impedance of the power line C needs to be low, the power line needs to be designed to be wide. In addition, in order to avoid the problem of static electricity discharge, the distance D between the power line C prepared in the same layer as the gate and the output pin a prepared in the same layer as the gate cannot be too small, and the distance D between the power line C and the output pin a prepared in the same layer as the gate needs to be set to be 50 micrometers or more; based on the above consideration, the first row of the fan-out area integrated circuit is a first type output pin A which is in the same layer as the grid electrode, and the second row is a second type output pin B which is in the same layer as the source electrode and the drain electrode; the third row is provided with a power line C, and the fan-out wiring connected with the output pins and the corresponding output pins are arranged in the same layer.

As shown in fig. 2, the output pins on the right side of the fan-out subarea P end with the second type of output pins B, and the output pins on the left side of the fan-out subarea Q also start with the second type of output pins B, so that two adjacent fan-out wires corresponding to the fan-out subarea P are made of the same layer of metal, and the circulation modes of the fan-out subarea P and the fan-out subarea Q are inconsistent.

Specifically, the first fan-out subarea corresponds to the 1 st output pin to the 720 nd output pin which are sequentially arranged, and the circulation is started by the first type of output pins; the 721 th output pins to 1440 th output pins of the second fan-out subarea are correspondingly arranged in sequence, and the second class output pins start to circulate; the 720 th output pin and the 721 th output pin are both second-class output pins, the circulation modes of the first fan-out subarea and the second fan-out subarea are inconsistent, and the first fan-out subarea is formed by circulating the first-class output pins A and the second-class output pins B, namely AB is alternately arranged; the second fan-out subarea is formed by cycling the second type of output pins B and the first type of output pins A, namely BA is alternately arranged. Correspondingly, as shown in fig. 3, a cross-sectional view along the line R-R' is shown, wherein the first lead 103 connected to the first type of output pins and the second lead 203 connected to the second type of output pins are respectively disposed on different film layers.

In a specific example, as shown in fig. 4, the fan-out area includes a fan-out subarea P, a fan-out subarea Q, a fan-out subarea W, and a fan-out subarea U, which are sequentially arranged from left to right, and the display effect of the fan-out subarea is shown in fig. 5, so that an obvious split-screen phenomenon can be seen, and the brightness difference between two adjacent fan-out subareas is obvious.

The inventors have found by analysis that the main cause of this phenomenon is: in the actual production process, since the first type output pins and the second type output pins are arranged on different layers and are prepared by a film deposition process at different times, even prepared by different equipment and different factories, the difference between the widths and the film thicknesses of the first type output pins and the second type output pins is caused, and the difference is amplified when the charging is insufficient, so that the split screen phenomenon shown in fig. 5 with obvious brightness difference occurs.

Specifically, through actual measurement of the resistance, the routing resistance of the brighter region is smaller than that of the darker region, and the thickness of the film layer is thicker, and the specific relation is as follows: the film layer is thicker/the line width is wider, the resistance is smaller, the charging rate is higher, and the display brightness is brighter.

Based on the above considerations, one embodiment of the present invention provides a display substrate, as shown in fig. 6, 7, 8, and 9, which includes a display Area (Active Area, AA) and a Fan-out Area (Fan-out Area) located at one side of the display Area, the Fan-out Area including a plurality of Fan-out sub-areas arranged along a first direction x.

The fan-out subarea comprises a first group of pins 10 and a second group of pins 20 which are arranged along a second direction y, the second direction y is orthogonal to the first direction x, the first group of pins 10 comprises m first pins 101 which are arranged along the first direction x, the second group of pins 20 comprises m second pins 201 which are arranged along the first direction x, m is more than 1, the first pins and the second pins are alternately arranged in the nth fan-out subarea in the first direction, the second pins and the first pins are alternately arranged in the (n+1) th fan-out subarea, and n is a positive odd number;

the first pin 101 is connected to a first switching pin 102 arranged in the same layer as the second pin 201, and the second pin 201 is connected to a second switching pin 202 arranged in the same layer as the first pin 101;

the first pin 101 in the nth fan-out sub-area is led out to the display area through a first lead 103 and the second pin 201 is led out to the display area through a second lead 203, the second pin 201 in the (n+1) th fan-out sub-area is led out to the display area through a first lead 103 and the first pin 101 is led out to the display area through a second lead 203;

wherein the first lead 103 is disposed in a same layer as one of the first pin 101 and the second pin 201, and the second lead 203 is disposed in a same layer as the other of the first pin 101 and the second pin 201.

The first group of pins 10 and the second group of pins 20 arranged in the second direction are arranged, the first group of pins 10 and the second group of pins 20 are led out to a display area through first leads 103 and second leads 203 which are alternately arranged, and transfer pins are arranged, and a first pin 101 in the first group of pins 10 is connected with a first transfer pin 102 which is arranged in the same layer as a second pin 201 in the second group of pins 20; the second pins 201 in the second group of pins 20 are connected to the second transfer pins 202 arranged on the same layer as the first pins 101 in the first group of pins 10, so that the pins can be connected to the display area by the leads in the same order no matter how the IC channels are selected, the fan-out area is free from the situation that two adjacent leads are arranged on the same layer, and therefore, under a specific picture, the driving sequences of different fan-out subareas are consistent, no obvious difference exists in brightness, and the problem of split screen of the display substrate is solved. As shown in fig. 9, the display substrate in the present disclosure has an actual display effect, uniform display brightness, and no split screen phenomenon.

In a specific example, the display substrate further includes a plurality of scan lines and data lines disposed in the display area, the plurality of scan lines and data lines being disposed to cross each other, the plurality of scan lines and data lines dividing the display area into a plurality of sub-pixels, each sub-pixel including a thin film transistor and a pixel electrode.

In a specific example, the display region includes thin film transistors arranged in an array, and source and drain electrodes of the thin film transistors are formed on the source and drain metal layer.

One of the first pin 101 and the second pin 201 is arranged in the same layer as the gate electrode of the thin film transistor, and the other is arranged in the same layer as the source drain metal layer.

The grid electrode of the thin film transistor is arranged on the same layer as the scanning line and the corresponding lead wire and is electrically connected with the scanning line, the source electrode and the drain electrode of the thin film transistor are arranged on the same layer as the data line and the corresponding lead wire of the fan-out area, the source electrode of the thin film transistor is electrically connected with the data line, and the drain electrode of the thin film transistor is electrically connected with the pixel electrode.

Specifically, the thin film transistor may be a top gate structure or a bottom gate structure, where the top gate structure, i.e., the active layer, is located between the gate and the substrate, and the bottom gate structure, i.e., the active layer, is located between the gate and the drain and the source.

In a specific example, a display substrate shown in fig. 6 is taken as an example to explain in detail: the fan-out area comprises a first fan-out subarea K and a second fan-out subarea L, wherein pins of the first fan-out subarea K are connected to data lines of the display area through leads, the first fan-out subarea K corresponds to 1 st data line D1-720 th data line D720, and the second fan-out subarea L corresponds to 721 th data line D721-1440 th data line D1440.

Each fan-out sub-section comprises a first group of pins 10 and a second group of pins 20 arranged in a second direction y, the first group of pins 10 of the first fan-out sub-section K comprising 360 first pins 101 arranged in a first direction x, the second group of pins 20 of the first fan-out sub-section K comprising 360 second pins 201 arranged in the first direction x; the first set of pins 10 of the second fan-out sub-section L comprises 360 first pins 101 arranged in the first direction x, and the second set of pins 20 of the second fan-out sub-section L comprises 360 second pins 201 arranged in the first direction x.

Specifically, each first pin 101 in the first group of pins 10 in the first fan-out sub-area K is led out to the display area through a first lead 103, that is, through the first lead 103 and a data signal line of the display area; each second pin 201 in the second group of pins 20 in the first fan-out sub-area K is led out to the display area through a second lead 203, that is, is connected to a data signal line arranged in the display area through the second lead 203;

contrary to the first fan-out sub-area K, each first pin 101 in the first set of pins 10 in the second fan-out area L is led out to the display area through the second lead 203, that is, through the second lead 203 and the data signal line of the display area; each second pin 201 in the second set of pins 20 in the second fan-out sub-area L is led out to the display area through the first lead 103, that is, is connected to a data signal line disposed in the display area through the first lead 103.

Specifically, the invention is provided with the transfer pins, no matter whether the pins are arranged on the same layer as the leads or not, the pins can be electrically connected with the leads, the fan-out lines of the fan-out areas are alternately ordered, the circulation sequence of the fan-out lines of each fan-out area is consistent, the adjacent fan-out lines of the adjacent two fan-out areas, such as the first fan-out area K and the second fan-out area L, are positioned on different film layers, the condition that the adjacent two wires of the adjacent two fan-out areas are arranged on the same layer is avoided, and the leads connected with the adjacent pins between the different fan-out areas are not positioned on the same layer through design.

It should be noted that the drawings in the present invention are only for illustrating the structure of the substrate, and some parts are exaggerated in drawing for understanding, and the dimensional and proportional relationships in the drawings do not represent actual dimensional and proportional relationships.

In addition, for the area of the same layer of the fanout line and the output pin, the switching pin is not required, and the output pin is directly led out to the display area through the fanout line of the same layer.

In a specific embodiment, the display substrate correspondingly includes two driving chips, as shown in fig. 8, where a first driving chip is led out to the display area of the display substrate through a first fan-out sub-area and a second fan-out sub-area, and a second driving chip is led out to the display area of the display substrate through a third fan-out sub-area and a fourth fan-out sub-area.

It should be noted that the number of driving chips corresponding to the display substrate may be 1, 2 or 3, and may be set according to specific situations, which is not specifically limited herein.

In an alternative embodiment, the first lead is arranged in the same layer as the first lead, that is, in the same layer as the gate of the display area, and the second lead is arranged in the same layer as the second lead, that is, in the same layer as the source drain metal layer of the display area, and the first lead and the second lead may be linear or polygonal.

In another alternative embodiment, the first lead is disposed in a same layer as the second lead, i.e., in a same layer as the source drain metal layer of the display area, and the second lead is disposed in a same layer as the first lead, i.e., in a same layer as the gate of the display area.

In a specific embodiment, as shown in fig. 8, the first switch pin is located on a side of the first pin near the display area, the second switch pin is located on a side of the second pin near the display area, and the first lead and the second lead may be linear or polygonal.

According to the embodiment, the transfer pin which is electrically connected with the output pin is additionally arranged on the output pin, the transfer pin and the corresponding output pin are positioned on different film layers, whether the pins are arranged on the same layer as the lead or not can be electrically connected with the lead, the wiring design of the fan-out area can be carried out according to the unified sequence, sequential exchange can not occur at the interval part of the fan-out subarea, and the problems of large display brightness gap and display split screen are solved by adopting the above-mentioned design.

In a specific embodiment, the line widths of the plurality of first wires 103 are the same, and the line widths of the plurality of second wires 203 are the same.

According to the embodiment, the line widths of the plurality of first leads are set to be the same, the line widths of the plurality of second leads are set to be the same, so that the line widths of the first leads, the second leads and the corresponding data lines on the display substrate which are simultaneously arranged are also consistent, the resistances of the plurality of leads are consistent, the charging rates are consistent, the brightness displayed by the corresponding display substrate is also consistent, and the problem of split display is further solved.

In a specific embodiment, the film thicknesses of the plurality of first leads are the same, and the film thicknesses of the plurality of second leads are the same.

According to the embodiment, the film thicknesses of the first leads are set to be the same, the film thicknesses of the second leads are set to be the same, so that the film thicknesses of the first leads, the second leads and the corresponding data lines on the display substrate which are simultaneously arranged are consistent, the charging rates of the leads are consistent, the brightness of the corresponding display substrate is consistent, and the problem of split display is further solved.

In a specific embodiment, the first pin 101 is connected to a first switching pin 102 disposed on the same layer as the second pin 201 through a first via;

the second pin 201 is connected to a second transfer pin 202 disposed on the same layer as the first pin 101 through a second via.

In a specific example, as shown in fig. 10, which is a cross-sectional view taken along the line d-d' in fig. 7, the display substrate includes a first insulating layer 301 and a second insulating layer 302, the first lead 101 located in the first fan-out sub-area K is disposed in the same layer as the first lead 103, the first lead 101 and the first lead 103 are disposed between the first insulating layer 301 and the second insulating layer 302, and a first via penetrating to the first lead 101 is disposed on the first insulating layer; the first transfer pin 102 is electrically connected to the first pin 101 through the first via hole.

In a specific example, as shown in fig. 11, which is a cross-sectional view taken along the line e-e' in fig. 7, the display substrate includes a first insulating layer 301 and a second insulating layer 302, the second pins 201 located in the first fan-out sub-area K are disposed on the same layer as the second wires 203, and the second pins 201 and the second wires 203 are disposed on the first insulating layer 301 and electrically connected to the second transfer pins through second vias disposed on the first insulating layer and penetrating to the second transfer pins 202.

It should be noted that the present invention is not limited in particular to the orthographic projection of the adapter pins onto the substrate and whether the orthographic projection of the pins onto the substrate is covered.

In a specific embodiment, the display substrate further comprises an insulating layer, the insulating layer comprising a first insulating layer 301 and a second insulating layer 302,

the first insulating layer 301 is located between the first pin 101 and the second pin 201;

the second insulating layer 302 is located on a side of the second pin 201 facing away from the first pin 101.

In a specific embodiment, the first via includes a third via exposing the first pin 101 and a fourth via exposing the first switch pin 102, and the second via includes a fifth via exposing the second pin 201 and a sixth via exposing the second switch pin 202;

the fan-out sub-region further comprises a transfer electrode 303, comprising a first transfer electrode and a second transfer electrode,

Specifically, as shown in fig. 12, which is a sectional view taken along a sectional line b-b' in fig. 7, the first pins 101 and the first transfer pins 202 located in the second fan-out sub-area L are located in different film layers; the third via hole is penetrated from the second insulating layer 302 to the first pin 101 to expose the first pin 101, the fourth via hole is penetrated from the second insulating layer to the first transfer pin 102 arranged in the same layer as the second pin to expose the first transfer pin 102, and after the third via hole and the fourth via hole are prepared, a conductive material is laid on the third via hole and the fourth via hole to form a first transfer electrode.

Specifically, as shown in fig. 13, as a section line along a section line c-c' in fig. 7, the second pins 201 and the second transfer pins 202 in the second fan-out sub-area L are located in different layers, the fifth via penetrates through the second insulating layer 302 to expose the second pins 201, the sixth via penetrates through the first insulating layer 301 and the second insulating layer 302 to expose the second transfer pins 202, and after the fifth via and the sixth via are formed, a transparent conductive material such as indium tin oxide is laid thereon to electrically connect the second pins 201 and the second transfer pins 202.

In a specific embodiment, the first and second switching electrodes are indium tin oxide electrodes.

An embodiment of the invention provides a display panel, which comprises the display substrate provided by the embodiment of the invention.

The display panel in the embodiment comprises a display substrate, the fan-out area of the display substrate is provided with transfer pins corresponding to the pins, and a first pin in a first group of pins is connected with a first transfer pin which is arranged in the same layer with a second pin in a second group of pins; the second pins in the second group of pins are connected with the second transfer pins arranged on the same layer as the first pins in the first group of pins, so that the pins can be connected to the display area through the leads in the same sequence no matter how the IC channels are selected, the fan-out area can not have the condition that two adjacent leads are arranged on the same layer, the driving sequences of different fan-out subareas are consistent under a specific picture, no obvious difference exists in brightness, and the split screen problem is solved.

Taking the display panel as a liquid crystal display panel as an example, the display panel further includes:

an opposite substrate arranged opposite to the display substrate;

Specifically, the display substrate, the opposite substrate and the liquid crystal layer are fixedly arranged through sealant.

It should be noted that the display panel is not limited to a liquid crystal display panel, and can be an organic light emitting diode display screen.

In a specific embodiment, the opposite substrate includes a color film and a black matrix, and the orthographic projection of the black matrix on the substrate covers the orthographic projection of the scanning line and the data line on the substrate; the opening area of the black matrix corresponds to the light emitting area of the sub-pixel.

The color film comprises an optical filter corresponding to the color of the sub-pixel, the sub-pixel comprises a red sub-pixel, a blue sub-pixel and a green sub-pixel, and correspondingly, the color film comprises a red optical filter, a blue optical filter and a green optical filter.

An embodiment of the present invention provides a display device, which includes the display panel provided by the embodiment of the present invention.

In a specific embodiment, the display device further includes a driving chip connected to the data lines in the display panel through the first and second sets of pins of the fan-out sub-region.

Specifically, the driving chip comprises a first driving chip and a second driving chip, and each driving chip corresponds to two fan-out subareas. It should be noted that the number of the driving chips can be set according to the requirement, and is not particularly limited herein.

In a specific embodiment, the display device further includes a backlight module, and the display panel is located on a light emitting side of the backlight module.

The display device provided by the embodiment of the invention comprises the following components: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., is an essential component of the display device, and those skilled in the art should understand that the product or component is not described herein, and should not be taken as a limitation of the present invention.

In the drawings, the size, proportion, or region of the constituent elements may be exaggerated for clarity. Accordingly, embodiments of the present disclosure are not necessarily limited to this dimension, and the shape and size of each component in the drawings do not reflect the true scale. Furthermore, the figures schematically illustrate some examples, and embodiments of the present disclosure are not limited to the shapes or values illustrated in the figures.

It should be apparent that the foregoing examples of the present disclosure are merely illustrative of the present disclosure and not limiting of the embodiments of the present disclosure, and that various other changes and modifications may be made by one of ordinary skill in the art based on the foregoing description, and it is not intended to be exhaustive of all embodiments, and all obvious changes and modifications that come within the scope of the present disclosure are intended to be embraced by the technical solution of the present disclosure.

Claims

1. A display substrate, comprising a display area and a fan-out area positioned at one side of the display area, wherein the fan-out area comprises a plurality of fan-out subareas arranged along a first direction;

2. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate,

the display area comprises thin film transistors which are arranged in an array manner, and a source electrode and a drain electrode of the thin film transistors are formed on the source-drain metal layer;

3. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate,

the first transfer pin is positioned on one side of the first pin, which is close to the display area, and the second transfer pin is positioned on one side of the second pin, which is close to the display area.

4. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate,

the line widths of the plurality of first leads are the same, and the line widths of the plurality of second leads are the same.

5. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate,

the first pin is connected with a first transfer pin arranged on the same layer as the second pin through a first via hole;

6. The display substrate according to claim 5, wherein,

the display substrate further includes an insulating layer including a first insulating layer and a second insulating layer,

7. The display substrate according to claim 6, wherein,

the first transfer electrode and the second transfer electrode are indium tin oxide electrodes.

8. A display panel comprising a display substrate according to any one of claims 1-8.

9. The display panel of claim 8, wherein,

the display panel further includes:

an opposite substrate arranged opposite to the display substrate;

10. A display device comprising the display panel of claim 9 and a driver chip connected to data lines within the display panel via a first set of pins, a second set of pins of a fan-out sub-region.