CN1165083C

CN1165083C - Write amplifier/read amplifier having vertical transistor used for DRAM memory

Info

Publication number: CN1165083C
Application number: CNB011162910A
Authority: CN
Inventors: A; A·弗雷; W·维贝尔; T·施勒泽尔
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2000-02-28
Filing date: 2001-02-28
Publication date: 2004-09-01
Anticipated expiration: 2021-02-28
Also published as: DE10009346B4; KR20010085740A; JP2001298166A; JP3787500B2; CN1311532A; US6822916B2; EP1128389A1; TW501133B; US20010030884A1; KR100450073B1; DE10009346A1

Abstract

As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by 'vertical transistors' in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

Description

Amplifier/the sense amplifier that writes that has vertical transistor that is used for the DRAM memory

Technical field

The present invention relates to a kind of amplifier/sense amplifier that writes that is used for dynamic random access memory DRAM, be furnished with vertical transistor on it.

Background technology

Dynamic random access memory (DRAM memory) is a kind of most important memory of storing digital information, each DRAM memory comprises a transistor, be used for the unit and the capacitor of control store electric charge, described electric charge is meant the information that deposits memory cell in.

Described each memory cell is pressed matrix arrangement and is connected, each memory cell has a so-called word line and a bit line, the delegation of all memory cells has same word line, or have two word lines, they are connected with per two unit, and every row of matrix of memory cells is connected with one or two bit line.By activating a specific word line, all memory cells that are connected are read by its bit line, write or refresh the information content of (renewal) memory cell.It is necessary refreshing for the DRAM memory, because the existence of leakage current, particularly on integrated assembly, tends to lose along with the time at the electric charge of capacitor stored.

In order to read the information that deposits memory cell in, perhaps refreshing information is provided with and writes or reading circuit, and each in them generally is connected with two bit lines, the difference that can compare charge information that is connected of this and two bit lines, and simplify computing to the memory cell content.

Fig. 1 is an example that reads the writing of DRAM memory cell/read-out device of prior art.Sort circuit mainly comprises a multiplier A, an operator circuit B and a precharge/balanced electronic circuit C.The core of this circuit is the operator circuit B that has a trigger, it by two transistors to constitute i.e. nMOS transistor T 1 and T2, or pMOS transistor T 4 and T5 with the homopolar crystal pipe.Be connected with two bit lines at writing described in this example/sense amplifier device, one is bit line BL, one is reference bit line BBL, and BBL is connected by the grid of interface 10 with transistor T 1 here, and BL is connected by the grid of interface 12 with transistor T 2.In addition, BBL is connected by the source/drain region of interface 11 with transistor T 2, and BL is connected by the source/drain region of interface 13 with transistor T 1.Two transistorized another source/drain regions then are connected with transistor T 3 by a SAN interface 14, transistor T 3 is connected with lead 17 by interface 15, the latter is the holding wire of transmission NSET signal, and this transistor can switch between ground connection (GND) and NSET signal.By ground wire 18 and interface 16, another source/drain region ground connection of transistor T 3.The transistor seconds that is made of transistor T 4 and T5 is to being connected with BBL with bit line BL in aforesaid same mode, yet on transistor T 6, replaced ground connection by VDD.The circuit of this prior art plays and possible signal condition is segregated into clear and definite signal level carries out computing, and the content of described memory cell is represented with logical one or logical zero.

Multiplier A comprises two transistor Ts 7 and T8, and the former is used for bit line BL, and the latter is used for bit line BBL, and bit line BL is connected by the source/drain region of interface 34 with transistor T 7, and bit line BBL is connected with transistor T 8 by interface 31.Multiplier signal is transferred to the

interface

33 and 30 of transistor T 7 and T8 by MUX line 36, so transistor turns, in conduction period, the voltage on BL or BBL transmits by

interface

35 and 32.

Precharge/balanced electronic circuit C comprises three transistor Ts 9, T10 and T11, and BBL is connected with the source/drain region of transistor T 10 by an interface 40, and BL is connected by the source/drain region of interface 42 with transistor T 9.Another source/drain region of two transistor Ts 9 and T10 is connected with VBLEQ holding wire 46 by interface 44, source/the drain region of transistor T 11 is connected with BBL by interface 41, and be connected with BL by interface 43, these three transistor Ts 9, each gate regions of T10 and T11 all is connected with EQ line 47 by interface 45.Circuit described here is as writing/case illustrated of reading circuit, and is not used in qualification the present invention, can derive many mutation circuit thus.

The manufacturing of DRAM memory needs higher expenditure cost, current DRAM memory is in fact mainly made by integrated semiconductor, the layout of memory cell wherein, word line comprises word line control and bit line and comprises bit line control etc. and be integrated in the circuit, and this circuit is molded on the silicon crystalline structure.Principal element in the expenditure of making integrated circuit consumption is the size of silicon crystal usable surface.How maximum at present cost holds definite number of memory cells and storage support logic thereof on as far as possible little chip surface if being dropped in, this more and more littler desired cost of demand is actually a kind of lasting requirement, needs to optimize constantly the internal structure design of DRAM memory for this reason.The structural design of this DRAM memory can reach less than 8F ²Available crystal face on generate 1G bit magnitude, wherein F is meant half of a mesh width forming in proper order with the minimum scantling of photoetching technique manufacturing or by parallel bit line.Respond the trend of the more and more littler change in above-mentioned surface, described bit line design has produced the transition from " stacking formula " notion to " open " notion, the former general two adjacent drawing of word line, each is all corresponding with two memory cells, and the latter only adopts a word line, and this word line is corresponding with each memory cell in the delegation.Adopt this mode, the quantity of electric charge of two adjacent bit lines of disposable comparison is impossible, and a parallel reference bit line is not used as benchmark for this reason.On the contrary, a reference bit line is guided to other cell array, and purpose is that the voltage of a corresponding bit line can be compared with a non-corresponding reference bit line.By cancelling the 2nd parallel bit line, dwindled writing/the idle face width degree that can arrange of sense amplifier.In order to make the DRAM memory cell littler, the word line of the available idle face of conventional writing/sense amplifier and the width that bit line is arranged can be from 8F to 4F, in another example, two bit lines stack mutually to be put, and they are introduced on the cell array of different for example bar shaped placed adjacent.

Existing known writing/sense amplifier may cause there are not enough idle faces owing to reduce size, also can not make at present to have writing/sense amplifier of new-type DRAM memory cell placed adjacent at interval for this reason.So write/layout of reading circuit on chip should make great efforts to be complementary with the situation of littler cell size, this layout has improved again to settle and has write/area requirements of reading circuit, so total input of making each DRAM means of storage is increased.

Summary of the invention

The purpose of this invention is to provide a kind of writing/reading circuit of new-type modern DRAM memory that comprise, it has the littler grid that width only has 4F.

The object of the present invention is achieved like this, and a kind of integrated writing/reading circuit is used at least one bit line of computing DRAM memory, it is characterized in that having an employed transistor in described writing/reading circuit at least is vertical transistor.

The present invention also comprises the useful expansion based on technique scheme.

Other useful designs of the present invention, scheme and details are embodied in the content of various useful expansions, specification and accompanying drawing thereof.

According to principle of the present invention, write/have at least in the reading circuit the employed conventional transistor of a part and replaced by so-called vertical transistor, their the stacked placement of different doped regions, perhaps stacked basically.Adopt vertical transistor and adopt traditional transistor to compare, can save considerable space, purpose is to guarantee that writing in grid/reading circuit device has littler mesh width.

Integrated writing of the present invention/reading circuit is used at least one bit line of computing DRAM memory, and at least one transistor is to adopt vertical transistor in described writing/reading circuit.

Said write/reading circuit such as traditional circuit adopt at least two different channel type transistors to carrying out computing, and the transistor of used pair of transistors can be to adopt vertical transistor in described writing/reading circuit.Because described transistor writes/core of reading circuit one of general formation, adopt vertical transistor, they only cover enough little space, can realize purpose of the present invention thus.

In order to save the used space of the internal vertical transistor devices of transistor as far as possible, transistor has a shared source/drain region, (the SAN input of the voltage that can accept to supply with on it, the SAP input), because each transistor is to respectively there being a source transistor/drain region, a their shared voltage, so silicon areas of the necessity that can on chip, further be simplified.

Driver transistor to conducting transistor on the voltage of necessity (VDD GND) also utilizes transistor to realize, these transistors also can be vertical transistors in the present invention.

Can also realize the circuit further simplified, the right vertical transistor of transistor or supply with the vertical transistor of these vertical transistors to voltage arbitrarily has a shared source/drain region.

As shown in Figure 1, right source/the drain region of described transistor is connected with relevant switching transistor, therefore this equipment has a shared source/drain region groove, common source/the drain region of this vertical transistor can be connected by a SET lead with a voltage source (VDD or GND), according to transistorized type, determine or and NSET, perhaps be connected with the PSET lead.

In order to realize space-saving purpose, described transistor is to preferably adopting vertical transistor, its width has a bit line in the horizontal at least, purpose is that the mesh width with described bit line adapts, the mesh width of a bit line extends, and the width of a bit line comprises and the nearest spacing of necessity of bit line, for this reason, need to guarantee that each transistor can placed adjacent to desired two transistors, for example adopt the reduced form in common source/drain region.

Of the present invention writing/reading circuit preferably also has a multiplier circuit that connects at least one bit line, wherein the used transistor of multiplier circuit is a vertical transistor, can save total space by means of other assemblies of writing of realizing of vertical transistor/reading circuit.And multiplier circuit also is to mate fully with predetermined grid.

Make all bit lines of a common polysilicon gate polar region of at least a portion connection of vertical transistor, further conserve space, here all bit lines " owning " is meant and all bit lines that definite writing/reading circuit is relevant, is not meant all bit lines that use in described DRAM memory.

The common polysilicon gate polar region of vertical transistor preferably can be connected with a multiplier signal source, can change on off operating mode by these transistorized gate regions like this.Of the present invention writing/reading circuit can also have a precharge/balanced electronic circuit, and the transistor of using in wherein precharge/balanced electronic circuit also can be a vertical transistor.

Of the present invention have all of the writing of vertical transistor/reading circuit three electronic circuits be discrete at least make, particularly ought wholely write/all electronic circuits in the reading circuit adopt vertical transistors to make, can realize having the modern DRAM memory of predetermined narrow grid.

The vertical transistor of described precharge/balanced electronic circuit preferably have a common polysilicon gate polar region to small part, according to the background science principle, the adjacent area of different crystal pipe is made in silicon by common structure, can make general construction simple and space requirement is reduced.

The shared polysilicon gate polar region of the vertical transistor of described precharge/balanced electronic circuit preferably is connected with an equalizing signal source (EQ).

Described precharge/balanced electronic circuit has a transistor corresponding at least one bit line in each bit lines, and a described transistorized source/drain region is connected with a voltage source, and described transistorized these sources/drain region constitutes a shared source/drain region.

Speak of its structure, vertical transistor preferably has a protuberance that is positioned on the substrate material, its sidewall is as raceway groove, on described protuberance, form one deck as first source/drain region, this aspect is material doped to the back side of substrate, the aspect that forms near described protuberance on substrate is material doped to the back side of substrate, as second source/drain region, and on the sidewall of described protuberance and form the gate regions of polycrystalline silicon material to the transition portion in second source/drain region from the sidewall of protuberance.Described polysilicon can form a polysilicon contact zone, can contact with gate regions.

Adopt the example of above-mentioned preferred vertical transistor, circuit of the present invention is compared with the circuit that the transistor that utilizes horizontal arrangement of routine constitutes, significantly conserve space.Described protuberance can form like this, the right transistor of described transistor has a width, it allows transistor to go in the width grid interpolation of bit line, that is to say, a protuberance width approximately suitable (because must exist at interval) with half mesh width of bit line, here people also can adopt the small technology of photoetching to make desired structure, other transistors can have a protuberance, its the width approximately mesh width with a bit line is suitable, therefore protuberance has common mesh width, through next bit line, and, match with two mesh widths.If for each bit line or set of bit lines, transistor is not a placed adjacent in twos, but transistor only so preferably is made of two bit lines.

The recommendable characteristics of of the present invention writing/reading circuit are that this circuit is connected with two bit lines.A device that has two bit lines can match with the layout of the disclosed writing/reading circuit that has had at present, and has simplified the right utilization of existing transistor, because they realize operation by two bit lines.Described set of bit lines can cause the different memory side in the DRAM memory.The suggestion of this example, described two bit lines cause a memory side, in this case, two bit lines on said write/reading circuit stack up and down with the primary flat of relevant DRAM memory, described set of bit lines realizes that by the lead of perpendicular this lead is stretched out up to described transistor by set of bit lines with being connected preferably of vertical transistor downwards.

The present invention constitutes a DRAM integrated memory by adopting vertical transistor as writing/transistor of reading circuit.The advantage of this scheme of the present invention will be by the description to the preferred embodiment of of the present invention writing/reading circuit, and the clearer and more definite and easy people of being understands.

Description of drawings

To make detailed description to the present invention according to specific embodiment below, these embodiment all adopt diagramatic way to assist and are illustrated.Accompanying drawing is as follows:

Fig. 1 is aforesaid common a writing/reading circuit that is used for the bit line in DRAM memory of computing;

Fig. 2 is the preferred embodiment of an operator circuit of of the present invention writing/reading circuit;

Fig. 3 and 4 is respectively the cutaway view along hatching line III and IV of integrated circuit view shown in Figure 2;

Fig. 5 is two bit line and the 3-D view of a transistor to being connected that the embodiment that recommends according to the present invention realizes;

Fig. 6 is the view according to a multiplier electronic circuit of preferred embodiment realization of the present invention;

Fig. 7 is the cutaway view along hatching line VII of vertical transistor view in the multiplier electronic circuit shown in Figure 6;

Fig. 8 is the cutaway view along hatching line VIIIa and VIIIb of the interior set of bit lines of multiplier electronic circuit shown in Figure 6 and two vertical transistor collapsed view;

Fig. 9 is a preferred embodiment of precharge of the present invention/balanced electronic circuit;

Figure 10 is the transistorized cutaway view along hatching line X of precharge/balanced electronic circuit shown in Figure 9.

Embodiment

In Fig. 2, showed major part according to operator circuit of the present invention and writing/reading circuit.This accompanying drawing has been showed two zoness of different that transistor is right, and transistorized internal placement reaches the difference at different doped layers.The circuit of the polysilicon region of the device shown in Fig. 2 is consistent with computing circuit B shown in Figure 1, and therefore identical structure adopts identical symbolic representation in each figure.Stretch out the bit line BL and the BBL of two vertical pile among Fig. 2 from top zone, they are by transistor T 1 and T4 and be parallel to the flat formation of DRAM memory, are connected downward vertically respectively by two bit lines.Transistor T 1 to T4 shown in Figure 2 and the polysilicon region of T3 and T6 are positioned at the surface portion of hatching, not having the zone 56 of the T1 of hatching, the zone 57 of T2, the zone 60 of T4 and the zone 61 of T5 is n (56,57) mix, perhaps p (60,61) territory, doped crystal area under control, they are as transistorized source/drain region.The common Plane n doped layer that is formed on T1, T2 and T3 (59) that embeds of source/drain region and the polysilicon region around it perhaps is formed on the p doped layer of T4, T5 and T6 (63).The three-dimensional structure of this different multi-crystal silicon areas can be further from Fig. 3 with Fig. 4 is clear finds out that wherein Fig. 3 is the cutaway view along bit line direction, Fig. 4 is the cutaway view along the orthogonal direction of bit line.As shown in the figure, transistor T 1 and T2 have the p doped layer on substrate 64, are positioned under other structural members that prepared.Stretch out a protuberance 64a by described substrate, its existence has guaranteed transistorized being arranged vertically of realizing according to the present invention.Have a transoid doped layer 56 (being the n doped layer in Fig. 3) on described protuberance, it is as transistorized source/drain region.Described protuberance is formed between polysilicon gate polar region 50a and protuberance 64a or the layer 56 round all sides of polysilicon 50, forms an oxide layer in addition, and is not shown.As shown in Figure 3, polysilicon gate polar region 50a changes over to from polysilicon contact zone 50b, is used for contacting with bit line.The structure of other transistor Ts 2, T4 and T5 is corresponding to, and a part is mixed, their structure transistor T 1 as shown in Figure 3.

Fig. 2 and Fig. 3 represent vertical transistor T3 and T6, and they and voltage VDD or connect with ground electrode GND are as vertical transistor.Voltage is supplied with the

contact

16 or 26 on source/

drain region

58 or 62 of transistor T 3 or T6 by ground wire 18 or lead VDD28.The polysilicon gate polar region 54 of transistor T 3 and T6 or 55 vertical being placed on the protuberance, by

contact

15 or 25 and lead 17 or 27 and holding wire NSET or PSET connect or disconnect, can realize that the SAN or the SAP of the circuit of Fig. 1 connect 14 or 24 in simple mode thus.As shown in Figure 1, connect

contact

10,12,20 and the gate regions of bit line with transistor T 1, T2, T4 and T5 is connected, similarly, connect

contact

11,13,21 and bit line is connected with first source/drain region of transistor T 1, T2, T4 and T5 with 23 with 22.

The concrete syndeton that bit line is connected with transistor is represented in Fig. 5 in the 3-D view mode Fig. 5 has showed the embodiment of transistor to T1/T2.Equally, identical label is represented identical technical characterictic in each accompanying drawing.As shown in the figure,

multi-crystal silicon area

50 and 51 forms round substrate extension 64a and

layer

56,57, and zone behind forms the independently piece 50b with a upper surface in the drawings, and 51b can form

contact

10 and 12 on this

upper surface.Contact

11 and 13 is formed on the

layer

57 or 56, as clearly shown in Figure 5, the structure of the vertical transistor that the present invention uses is the doping that

layer

56,57 is scheduled to, protuberance 64a in formation on the transoid doped substrate 64 is formed on the described

layer

56,57, between protuberance, form raceway groove, by cambium layer 59 between the side of protuberance, also comprise first orienting device and protuberance and the

multi-crystal silicon area

50 or 51 of

part surrounding layer

56,57 in case of necessity.

Fig. 5 has also showed two the bit line BL and the BBL that stack up and down, and their a part of horizontal-extendings then vertically turn round, and a part directly stands vertically as joint pin 10-13.

The following describes the connection contact of employing multi-stage process realization and the structure of bit line, it is formed by different metallized plane depositions.At first we see three metallized planes 80,81 and 82, their each horizontal-extendings, used material for example is a tungsten, described bit line also is to be made by tungsten, in non-metallic areas, metallized plane by insulating material for example oxide make, between three major metal planes, be insulating barrier, oxide layer for example.To be protected being communicated with between contact and the transistor in order making to connect, in this insulating barrier, to be pre-formed contact hole, in the hole with metal filled.As shown in the figure, one first insulating barrier represents that with label 83 one second insulating barrier represents that with label 84 one the 3rd insulating barrier is represented with label 85.

Fig. 6 is the possible silicon wafer design cutaway view of a multiplier circuit of writing of realizing according to the present invention/reading circuit, and here two transistor Ts 7 and T8 have a common polysilicon gate polar region 65, and its source/drain region 66,67 or 68,69 is spaced from each other.Two bit line BL and BBL draw by transistor, and with the contact 31 of transistor T 8 with 32 or the contact 34 of transistor T 7 be connected with source/drain region of 35.Two bit lines interrupt, its neutrality line BL interrupts by transistor T 7, and bit line BBL interrupts by transistor T 8, if transistor by holding wire 36 and contact 30/33 not by the MUX signal activation, then not having electric current to flow through between the

contact

34 and 35 of transistor T 7 or between the

contact

31 and 32 at transistor T 8, so bit line all interrupts.

Fig. 7 is the cutaway view along hatching line VII of vertical transistor view in the multiplier electronic circuit shown in Figure 6.From then on scheme still can know and find out transistorized vertical stratification, near a substrate 70, form a protuberance 70a, on protuberance, comprise 67 and transoid doped layer 69 of layer that a transoid is mixed near protuberance 70a.Multi-crystal silicon area 65 is separated by the oxide layer of a (not shown) by substrate 70.

Fig. 8 is the cutaway view along hatching line VIIIa and VIIIb of the interior set of bit lines of multiplier electronic circuit shown in Figure 6 and two vertical transistor collapsed view; The n doped region 66 of the transistor T 7 of contact 34 below bit line BL directly reaches, bit line BL interrupts in this contact back.In Fig. 8 b, showed another contact 35 of bit line BL, it is guided on the bit line BL that connects once more by another n doped region of transistor T 7.Fig. 8 c and 8d have showed the similar situation about bit line BBL and contact 31 and 32, are noted that especially here according to the quantity of idle available metalized surface (right side) and the quantity of passing the contact hole of insulating barrier, the possible design of contact.

Fig. 9 is a preferred embodiment of precharge of the present invention/balanced electronic circuit; As shown in the figure, all three transistor Ts 9, T10 and T11 interconnect by a common multi-crystal silicon area 71, and are connected with the transfer wire 49 of signal EQ by contact 45.Transistor T 9 and T10 also comprise a total source/drain region 74, and it is connected with the transfer wire 48 of signal VBLQ by contact 44.Described bit line BL and BBL through circuit transmission separately lays downwards, bit line BL is connected with the second source/drain region 72 of transistor T 9 by contact 42, and bit line BBL is connected with the second source/drain region 73 of transistor T 10 by contact 40, bit line BL then is connected with a source/drain region 75 of transistor T 11 by contact 43, and bit line BBL is connected with another source/drain region 76 of transistor T 11 by contact 41.

Figure 10 is the transistorized cutaway view along hatching line X of precharge/balanced electronic circuit shown in Figure 9.As shown in the figure, transistor is to form in pairs here, its width identical with in other embodiments.As previously mentioned, owing to adopt the realization of the transistor unit of three transistor series formations to have very much practical value, wherein each transistor can use whole mesh width (for example 4F), therefore can on the basis of existing embodiment, expand and conversion, for example two bit lines need not just can realize being connected with the last source/drain region of vertical transistor of the present invention with the staggered of contact, form a protuberance 77a in the transistorized substrate 77.

In the described in front accompanying drawing, respectively draw two grids and two bit lines are right, for the sake of clarity, in the DRAM memory, be mounted with a plurality of bit lines that adjoin each other, wherein the structure of the structure of second device and first device is identical, by adopting as shown in the figure two of the present invention to write/reading circuit, in fact signal line of determining that has by all writing/reading circuit or the definite transistor device (multi-crystal silicon area among Fig. 2 54 for example, 55 or source/drain region 59,63) can be integrated in a certain common area of a DRAM memory, realize the summation result of use.

In order to make modern DRAM memory can have narrower grid, the present invention adopts the vertical transistor arrangement, is the good technical characteristic of vertical transistor of the present invention below:

-vertical transistor only needs to occupy few plane;

The selection of-its channel length and employed photoetching technique are irrelevant;

-all writing/sense amplifier of being used for a device can adopt unified signal, for example SAN, SAP or VBLEQ, and this is not called and isolates, and promptly in one plane forms a common source/drain region.

Compare with the memory of routine, the present invention can realize the minimum compact mechanism F of unit grid, at peripheral part, and writing/zone of sense amplifier in, only need occupy the physical dimension of about 1.5-2F.Owing to adopt vertical transistor can realize high periodicity, can realize at present writing/the minimum lithographic dimensions F of reading circuit.

In existing DRAM matrix storage zone, adopt of the present invention writing/sense amplifier, insert the manufacturing of the memory cell design of settling vertical transistor, can only need very little technology and technology to drop into expense, can be according to the memory cell mesh width, simply make vertical structure, for example separate conversion and multiple-separation-word line etc.

Adopt vertical stratification,,, can form a general layout layout along the length direction of of the present invention writing/sense amplifier on a 4F grid next door.So, can adopt the transistorized embodiment of vertical stratification aforesaid annular or surrounding layer, its channel width is exaggerated according to the geometric widths in double at least source/drain region.

Below how simple declaration is made the method for of the present invention writing/reading circuit.

The n that at first carries out corresponding number material on the substrate of bottom in advance mixes or the p doping treatment, then carry out photoetching process, and between the protuberance of each vertical transistor, form groove or ditch by the corrosion etch process, then, on the new surface that forms, mix by grafting.At next step, the gate regions of vertical transistor is carried out oxidation, thereby form an oxide layer.Then, deposition forms a polysilicon layer, and it covers whole established structure, afterwards, carry out photoetching, can determine the outline of expectant control bonding pad (for example among Fig. 5 clear show and for example as shown in Figure 2 the hatching part of extension) backward thus, carry out the anisotropy dry corrosion then, form multi-crystal silicon area as shown in the figure, generally have separator on multi-crystal silicon area, constitute the protuberance that is positioned at on-chip vertical transistor, the setting structure of Xing Chenging as shown in Figure 3 thus.

For different electronic devices is kept apart, vertical transistor is filled the groove that all have formed with oxide, then after handling through necessary planarization technology, for example adopt the CMP method, can on the flat surfaces that forms, further adopt photoetching process processing,, form contact hole 83 by means of photoetching treatment, in these contact holes with metal for example tungsten fill, described tungsten is obtained by the tungsten fluoride segregation.

Next step is the planar technique processing by a chemical mechanical polishing, isolate first metallized plane 80, adopt the processing of photoetching process and corrosion step to obtain required lead bar structure afterwards, then with method new contact hole/oxide layer and metallized plane stack are formed in the above-mentioned first that has formed in the same way.

Described metallized plane also can be guided reverse direction into, is not to isolate metallized plane earlier here, but oxide layer.In case of necessity, adopt two step method, promptly handle, lead bar and contact hole structure are immersed in the oxide by photoetching treatment and etch, with the trench fill of proper metal material, can use a kind of big Ma Shigang working system here then with contact hole and the generation of lead bar.

Write with formation with the manufacturing of routine/reading circuit needs necessary a plurality of additional steps to compare, make vertical transistor and the labyrinth of preparation metal flat is had relatively high expectations on transistor expense, yet the raising institute of this to be people win microminiaturized degree must pay.

Claims

1. integrated writing/reading circuit, (BL BBL), is characterized in that, having an employed transistor in described writing/reading circuit at least is vertical transistor to be used at least one bit line of computing DRAM memory.

2. according to claim 1 writing/reading circuit, it is characterized in that, it has at least two transistors to (T1/T2, T4/T5), each transistor constitutes the transistor that is used for computing by same channel type, and the transistor that uses in said write/reading circuit is to (T1/T2, T4/T5) be vertical transistor (T1, T2, T4, T5).

3. according to claim 2 writing/reading circuit is characterized in that, each transistor is to (T1/T2, described vertical transistor T4/T5) has a shared source/drain region (59,63).

4. according to claim 2 or 3 described writing/reading circuits, it is characterized in that, be used for that (VDD GND) is switched to transistor to (T1/T2, (T3 T6) is vertical transistor to transistor T4/T5) with a voltage source.

5. according to claim 4 writing/reading circuit, it is characterized in that, each transistor is to (T1/T2, T4/T5) vertical transistor (T1, T2, T4, T5) and be used for and described voltage source (VDD, GND) (T3 T6) has a shared source/drain region (59,63) to the vertical transistor of Jie Tonging.

6. according to claim 5 writing/reading circuit is characterized in that, and vertical transistor (T1, T2, T4, T5, T3, (VDD GND) is connected with described voltage source by a lead (17,27) in shared source/drain region (59,63) T6).

7. according to claim 2 or 3 described writing/reading circuits, it is characterized in that transistor is to (T1/T2, T4/T5) vertical transistor (T1, T2, T4, T5) towards at least one bit line (BL, BBL) have in a lateral direction one with the mesh width equal widths.

8. according to any described writing/reading circuit among the claim 1-3, it is characterized in that, also comprise a multiplier circuit (A), with at least one bit line (BL, BBL) be connected, the transistor that in described multiplier circuit (A), uses be vertical transistor (T7, T8).

9. according to claim 8 writing/reading circuit is characterized in that, (T7, at least a portion T8) has a shared polysilicon gate polar region (65) to the vertical transistor of described multiplier circuit (A).

10. according to claim 9 writing/reading circuit is characterized in that, (T7, shared polysilicon gate polar region (65) T8) is connected with a multiplier signal source (MUX) vertical transistor.

11., it is characterized in that also having a precharge/balanced electronic circuit (C) according to any described writing/reading circuit among the claim 1-3, the transistor that in described precharge/balanced electronic circuit (C), uses be vertical transistor (T9, T10, T11).

12. according to claim 11 writing/reading circuit is characterized in that, (at least a portion T11) has a shared polysilicon gate polar region (71) to the vertical transistor of described precharge/balanced electronic circuit (C) for T9, T10.

13. according to claim 12 writing/reading circuit is characterized in that, the shared polysilicon gate polar region (71) of vertical transistor is connected with the signal source (EQ) of an equalizer.

14. according to claim 11 writing/reading circuit, it is characterized in that, described precharge/balanced electronic circuit (C) has a transistor (T9 corresponding at least one bit line, T10), its source/drain region is connected with a voltage source (VBLEQ), and this source/drain region constitutes a shared source/drain region (74).

15. according to any described writing/reading circuit among the claim 1-3, it is characterized in that, be formed with a protuberance (64a on the substrate material of described vertical transistor, 70,77), as channel region, a layer (56 of going up formation at described protuberance (64a, 70,77), 57,58,60,61,62,66,67,72,73) material is through transoid doping treatment on substrate, week is done first source/drain region, one on substrate near described protuberance (64a, 70,77) locate the layer (59,63,69 that forms, 74,76) material is through transoid doping treatment on substrate, as second source/drain region, also comprise one on the sidewall of protuberance (64a, 70,77) and from protuberance (64a, 70,77) sidewall to second source/multi-crystal silicon area (50,52 of the transition in drain region, 54,65,71).

16. according to claim 15 writing/reading circuit is characterized in that, transistor is to (T1/T2, the width of the protuberance on transistor T4/T5) (64a, 70,77) and the mesh width of a bit line are complementary.

17. according to claim 15 writing/reading circuit is characterized in that, the width of the protuberance on the described transistor (64a, 70,77) and the mesh width of a bit line are complementary.

18., it is characterized in that (BL BBL) is connected for said write/reading circuit and two bit lines according to any described writing/reading circuit among the claim 1-3.

19. according to claim 18 writing/reading circuit is characterized in that, described two bit lines (BL, BBL) writing/reading circuit on, and the primary flat of described DRAM memory stacks up and down.

20., it is characterized in that described bit line and vertical transistor are connected by contact (10,11,12,13,20,21,22,23,31,32,34,35,40,41,42,43) according to any described writing/reading circuit among the claim 1-3.