CN116508317A

CN116508317A - 3D display

Info

Publication number: CN116508317A
Application number: CN202180064044.9A
Authority: CN
Inventors: S·S·克莱纳-伊文森
Original assignee: Rierfixon Laboratories LLC
Current assignee: Rierfixon Laboratories LLC
Priority date: 2020-09-17
Filing date: 2021-09-17
Publication date: 2023-07-28

Abstract

A display for controlling the directionality of an image of an observer who observes from an observer's point of view in front of the display. The display includes a plurality of pixels including a first pixel that constitutes an image pixel. The pixels are arranged in a plane and in a first segment covering a segment area of the display. Each pixel defines a pixel region having a plurality of sub-pixels, and the first pixel has a first plurality of sub-pixels including a first sub-pixel. Each sub-pixel defines a direction from the display to a view point or an angle between a normal to the display and a view point. The display also includes a front optic having at least one optical element with optical power and a first focus and a second focus, the first focus being located at the plane, the second focus being between the front optic and a point located in front of the front optic and not distant from the front optic. The display includes circuitry implemented in a first film, and address lines for transmitting address control signals to the circuitry for addressing respective sub-pixels of the first plurality of sub-pixels. The display further comprises a control system for controlling the light intensity and the angle or direction of the emitted light from the plurality of pixels such that the emitted light is visible from the observer's point of view. The control system is configured to output a set of input luminance values to the circuit such that segments of emitted light have a luminance corresponding to the values in the set of input luminance values; and outputting the address control signal defining a sub-pixel of each of the plurality of pixels to be addressed to emit light such that the pixels in the segment emit light at an angle such that the pixels are visible from the observer's point of view.

Description

3D display

The present invention relates to a light field display that can produce a composite light field that can provide one or more observers with a stereoscopic reproduction of an object or scene while providing a look-around capability, i.e., the viewing angle and perspective experienced by the observer as they move around the display change in a manner similar to a natural light field so as to appear as if the scene or object were truly there. The light field display is generally horizontally oriented so that the viewer can walk around it, which benefits entirely from the look-around capability, although it can be positioned in many orientations.

Light field displays rely on the basic principle of directional pixels (sometimes referred to as holographic pixels). The directional pixels are capable of emitting light of different intensities and colors at different angles. It typically includes an array of microlenses and non-Chang Xiaozi pixels. The lenses focus the light of the individual sub-pixels in the corresponding emission directions. Light field displays are typically constructed as very high resolution displays with an array of superimposed microlenses.

Conventional light field displays emit light from each pixel at multiple angles, whether or not the eye under observation is positioned in any angular direction. In practice, only a small portion of the emitted light is typically received by the eye. Such non-observed rays are of little value, but they result in very complex subpixel circuits and image rendering hardware.

The light field display may operate in a mode in which a separate system tracks the observer's head position and only renders views that are emitted towards the observer's eye, i.e. the views that are not observed are not rendered or sent to the display. Such a configuration is referred to as an automatic multi-view display. This may simplify the way in which the image is generated to provide a still or moving image to the display, but it does not necessarily reduce the complexity of the display itself, as it still has to provide the ability to emit light of the required intensity and possible colour in any direction in which the eye may be positioned.

Autostereoscopic displays with head tracking functionality can have significantly lower complexity while maintaining high resolution for a single observer located in a restricted viewing area. This may be useful for some applications, but is not included in many situations such as social activities, group presentations, and professional work together.

A high angular resolution of the light field display, i.e. the number of discrete "views" (solid angular spacing of substantially uniform irradiance from pixels) is desirable because it can reduce the viewing angle difference for each view, thereby dispersing abrupt changes in the observer's pupil as it moves from view to adjacent view. Furthermore, when the observer's pupil is located at the boundary between views, it may reduce perceived blurring of the object such that light from both views enters the pupil. Furthermore, the high angular resolution increases the distance from which stereoscopic effects can be observed and/or the field of view of the display.

One problem is that the angular resolution is at the cost of extreme complexity and complexity is proportional to the square of the angular resolution. Consider a display that must be capable of viewing within a distance of 5 meters and that the pixels should have a field of view of 90 degrees. Assuming that the minimum eye distance of the observer is 55mm, the angular resolution of the display must be 2x tan-1 ((55 mm/2)/5000 mm degrees) =0.63 degrees to ensure that each eye sees a different view. If perfect optics are used, this would require a minimum of 143 views in the horizontal direction and a minimum of 143 views in the vertical direction, amounting to a minimum theoretical number of 1432= 20,449 views, corresponding to 20.449 subpixels per pixel. This is three times the number that would be required for a color display having one subpixel for each primary color of each pixel, i.e., 61.347 subpixels per pixel. For a full HD display this corresponds to 1920x 1080x61.347 =more than 1270 hundred million sub-pixels. In contrast, the highest resolution display (8K display) currently on the market has about 1 hundred million sub-pixels, more than a thousand times less.

One way to achieve very high resolution is to tile multiple high resolution microdisplays. Since each microdisplay requires a high bandwidth connector, it is in practice required to place the microdisplays at a small distance, resulting in a dark space between the microdisplays. Optical structures, such as relay optics, located on top of a microdisplay can reduce the visibility of dark gaps to some extent, but in practice such displays are not completely seamless, and relay optics are complex and render the display non-thin-profile.

Optionally, infrared light may be used to select the subpixels while all subpixels in one pixel receive the same electrical signal to control the pixel color value. For example, the sub-pixels may be sensitive to infrared light such that they are only activated when illuminated by infrared light, and the infrared light may be focused onto the sub-pixels by an optical illumination system controlled by a control system connected to the eye-tracking system. Such configurations include an infrared up-conversion layer in an organic stack that includes an OLED layer. Such a configuration may significantly reduce the complexity of the circuit, but at the cost of including an infrared illumination and focusing system that is capable of focusing infrared light on each sub-pixel, and optical tolerances and diffraction phenomena may limit the manner in which small sub-pixels are addressed, thereby limiting the final resolution.

The above-described drawbacks of the prior art mean that even the best light field displays and automatic multi-view displays today require a significant compromise in terms of resolution, viewing distance, field of view, color reproduction, viewing area and/or number of viewers, while still exhibiting distracting artifacts such as abrupt changes between discrete views as the display is being viewed while moving around and/or blurring of the borders of the viewing position on the viewing boundary. Nevertheless, natural depth perception and look around capability are very important factors for certain use cases, although quality is limited, in fact there is a market for light fields and automatic multi-view displays in certain applications. Significant improvements in performance parameters are required to achieve a wider market acceptance.

The display according to the present disclosure has the ability to display an image within a specific angle/direction or narrow angle range such that the image is visible, for example, by the left eye of an observer instead of the right eye of the observer. In this way, the display may display the image at an angle such that the image is visible to the left eye of the observer during a first time slot or time window and at an angle such that the image is visible to the right eye of the observer during a second time slot. The two images may enable a viewer to perceive a three-dimensional image. Such displays have an automatic stereoscopic capability so that the viewer does not need to use glasses. Such displays may also be used to save energy, for example, to illuminate a room only at an angle towards the viewer. Such displays may also be used to display personal information to a viewer of the display.

In order to emit light at different angles according to the position of the observer, each image pixel is divided into a plurality of sub-pixels, and the light of the sub-pixels is divided into different angles/directions by lenses in front of the pixel plane. For each image pixel, a sub-pixel within the image pixel is selected to emit light having a position that means visible to an observer from the point of view of the observer. In this way, light from one sub-pixel is traced from the sub-pixel to the lens where it is refracted and continues from the lens to the viewer. Light from another sub-pixel having a different position within its image pixel than the position of the first sub-pixel is traced from the sub-pixel to the lens where it is refracted and continues from the lens to the viewer.

Pixels in the display may be grouped into groups of pixels forming segments of the display. The pixels in the segment may emit light at substantially the same angle. Thus, the subpixel selections for all pixels in a segment may be the same. This has the advantage of further reducing complexity, since a single common sub-pixel selection signal may be provided to the entire segment instead of providing multiple sub-pixel selection signals, one for each sub-pixel. The size of the segment into which the beam of emitted light is diverted may be selected such that, for any first point within the desired eye movement range of the display, beams of light emitted at substantially the same angle from substantially all pixels in the segment may be directed to illuminate the first point and at the same time not illuminate a second point located farther from the first point than the typical inter-pupillary distance.

For example, the subpixel size and refractive lens may be selected to steer a beam having a beam steering angle of 0.5 degrees. The segment size may be, for example, 6x6mm. For example, the number of pixels in a segment may be 64 pixels arranged in an 8x8 pixel grid. Each pixel may have a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The subpixels of each color may include a plurality of directional subpixels, for example 1200 directional subpixels arranged in a grid of horizontal 100 and vertical 12.

The display may be made up of a plurality of such segments that may have the same size and number and arrangement of pixels. The segments may be, for example, quadratic or rectangular.

The absence of such segments means that more data processing and data transmission is required.

All image pixels within the first segment emit light at a first angle and all image pixels within the second segment emit light at a second angle different from the first angle.

Thus, each segment receives a data signal for addressing the same sub-pixel in each image pixel of the segment without having to render an image with information about the light intensity of each sub-pixel in all image pixels of the display.

This reduces the requirements for data processing and data transfer as well as the number of transistors required in the display circuitry, i.e. if there are two transistors per sub-pixel in a non-segmented display, the number of transistors can be halved by collecting every other image pixel in a segment.

The above objects and advantages and many other objects and advantages which will be apparent from the description of the present invention are obtained according to a first aspect of the present invention by:

a display for displaying an image to a viewer at a first point of view, the display comprising:

A plurality of pixels constituting image pixels, each image pixel comprising a group of sub-pixels and displaying a sample of the image during an intended operation of the display,

a circuit comprising a plurality of pixel circuits, each pixel circuit being arranged for driving said set of sub-pixels of each image pixel,

the circuit comprises a plurality of control circuits for addressing respective sub-pixels of the sub-pixel group,

each control circuit has a memory component, an address signal input and a select input,

the control circuit is arranged such that the address signal is input into the memory component when the control circuit is selected by the selection input.

According to a second aspect of the invention, the above objects and advantages are obtained by:

each subpixel group has a first number of subpixels such as subpixel rows oriented substantially horizontally and a second number of subpixels such as subpixel columns oriented substantially vertically,

a control system for outputting address signals for addressing the respective sub-pixels of each pixel circuit and a set of luminance values comprising luminance values for each pixel circuit,

the circuit is connected to the control system by a plurality of electrode wires,

the plurality of electrode lines is smaller than a sum of the first number of sub-pixels and the second number of sub-pixels.

According to a third aspect of the invention, the above objects and advantages are obtained by:

a circuit comprising a plurality of pixel circuits, each pixel circuit being arranged for driving the plurality of sub-pixels of each image pixel,

the plurality of pixel circuits includes:

-a first pixel circuit having a first pixel driver for driving a first sub-pixel group comprising a first sub-pixel, and

A second pixel circuit having a second pixel driver for driving a second sub-pixel group comprising a second sub-pixel,

-the first sub-pixel is connected by a first switch to the first pixel driver for driving the first sub-pixel such that the first sub-pixel outputs light having a first brightness, and

the second sub-pixel is connected to the second pixel driver for driving the second sub-pixel by a second switch such that the second sub-pixel outputs light having a second brightness,

the first switch having a first input for switching the first switch and the second switch having a second input for switching the second switch,

the circuit comprising a control circuit for switching the first switch and the second switch by a control signal output at an output by the control circuit,

the output is connected to the first input and the second input.

The invention will now be explained in more detail below by way of example with reference to the accompanying drawings. The present invention may, however, be embodied in forms other than described below and should not be construed as limited to any of the examples set forth herein. But rather provides any examples so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. Therefore, in the description of each drawing, similar elements will not be described in detail.

Fig. 1 shows a schematic diagram of a display system.

The display 1 is observed by a first observer (having a first eye 2 and a second eye 3, i.e. a left eye and a right eye) and from a first point of view.

The display is arranged to display an image to a viewer.

The tracking system 4, such as an eye movement tracking system, may determine the position of the first eye 2.

The tracking system may also determine the position of the second eye by measuring or inferring the position of the second eye as a function of the position of the first eye and the average inter-pupillary distance.

In general, the tracking system may track any number of viewers in front of the display.

The position may be input to the control system 5 for controlling the display to display an image viewable by the first observer at the first point of view, i.e. output light in a direction towards the first observer.

At other viewpoints than the first viewpoint, the display may be arranged to appear dark, i.e. the displayed image is directed only to the viewer (or only to the first eye of the viewer).

The first image may be displayed to the left eye and the second image may be displayed to the right eye (e.g., in two different time slots). When the two images have slightly offset viewing angles, the viewer can perceive a 3D effect. The display may operate in a time multiplexing operation having at least two time slots.

The display may be autostereoscopic (i.e. a multi-view autostereoscopic 3D display) and therefore does not require any head-mounted equipment.

The display may also display the same image to both eyes, which may achieve power saving but no 3D effect. Thus, the display is also capable of displaying 2D images.

The controller 5 may be arranged to control an image generator 6, which may be arranged to output images (image data) to a display driver circuit 7, which may be arranged to drive the display 1 to display images.

In a first time slot, the controller may instruct the image generator 6 to output a first image for the first eye 2, e.g. a perspective view of a position corresponding to the first eye 2, and in a second time slot, the controller may instruct the image generator 6 to output a second image for the second eye 3, e.g. a perspective view of a position corresponding to the second eye 3.

Image generator 6 may include an image rendering system capable of computing perspective views of a representation of a 3D object or 3D scene. Thus, an observer having the first eye 2 and the second eye 3 can move around and observe objects or scenes from different angles.

Alternatively or additionally, the image generator 6 may comprise a playback system capable of outputting a first perspective image of the stereoscopic image in a first time slot and a second perspective image of the stereoscopic image in a second time slot. The stereoscopic image may be an image in a sequence of images in a movie or transmission.

The frequency of the time multiplexing operation may be selected such that the multiplexing is substantially unnoticeable to the human visual system, e.g. the multiplexing may comprise 60 or more complete duty cycles per second, e.g. 72 duty cycles per second, so that the first eye 2 may perceive the first image as substantially stable and flicker free, while the second eye 3 may perceive the second image as substantially stable and flicker free. Thus, an observer having the first eye 2 and the second eye 3 can perceive a stereoscopic image that is substantially free of flicker.

In the multiview autostereoscopic mode the eye tracking system is able to detect more than two eye positions and the controller 5 is able to instruct the display to illuminate in a direction such that more than one eye is able to see the image displayed on the display in one time slot. Thus, for example, a left eye group belonging to a group of observers can see a first image, and a right eye group belonging to the group of observers can see a second image. Thus, a group of viewers can perceive stereoscopic images at the same time.

One advantage of the disclosed invention is that the display can be quickly switched between emitting light in different directions in synchronization with displaying the corresponding image. It can therefore have a high multiplexing frequency, allowing more than two time slots in one duty cycle, while avoiding perceived flicker.

Thus, in contrast to prior art systems, in an automatic multi-view mode, multiple observers can perceive a single perspective depending on the observer's position. For example, the display can operate at a duty cycle of 60 times per second, where each duty cycle includes 10 time slots, so that a single perspective view can be provided to 10 eyes, thus providing a single stereoscopic perspective image to, for example, 5 viewers simultaneously, whereas the prior art is typically limited to only one stereoscopic perspective view.

This fast operation and multi-viewer advantage is achieved by an active matrix display configuration that includes a memory component for sub-pixel switching control in the active matrix display backplane and where the multiplexed data for sub-pixel switching/selection/addressing control is transmitted by the transmission lines in the backplane and synchronously demultiplexed by the demultiplexed circuits with pixel color values in the backplane, which significantly reduces the bandwidth required for the circuits in the active matrix backplane, thereby achieving a very fast response display configuration and also achieving good synchronization between the updating of pixels with respect to pixel color and emitted light direction, as described below.

Fig. 2a shows ray tracing of light output from a segment of a display arranged to display 9 image pixels, i.e. an image consisting of 9 pixels.

The segments may have a size that may be less than the interpupillary distance, in particular, the horizontal width of the segments may be less than a typical interpupillary distance, otherwise the right eye may observe the image displayed to the left eye, and vice versa. For example, one segment may be 6x 6mm.

The display has front optics such as a microlens array 8, i.e. lenses in front of each element are arranged to output light constituting one of the image pixels.

The element that outputs light constituting one of the image pixels may be an OLED or LCD element. It may be referred to as a pixel, but it consists of several individually addressable pixels (or "sub-pixels", each individually addressable pixel will be referred to hereinafter), i.e. the light constituting an image pixel will be output by one sub-pixel of a sub-pixel group, of which one sub-pixel will be addressed/selected to output light.

Thus, the segments of the display are arranged to have 9 groups of sub-pixels, each group having, for example, 100 sub-pixels. The subpixels may be distributed/laid out as a grid/matrix of subpixels.

The display may be composed of a plurality of segments, each segment having a plurality of sub-pixel groups (each group constituting one pixel), and each group (pixel) may have a plurality of sub-pixels.

The front optic has at least one optical element having optical power and a first focal point that lies substantially in a plane or layer and outputs light and a second focal point that is between the front optic and a point that is in front of the front optic and is not remote from the front optic. It may be located on the side facing the viewer (in front of the light output layer, between the light output layer and the viewer).

Fig. 2b shows a close-up of the ray tracing illustration of fig. 2, i.e. with the enlargement of the individual elements outputting the light constituting one of the image pixels during the first time slot.

A first front microlens 8A, comprised of a microlens array 8, may be located between the viewer and the subpixel set/group 46.

A first sub-pixel of the set/group of sub-pixels 46 may output light and the light from the first sub-pixel may be refracted by the micro-lens 8A in a first emission angle/direction, so that the first pixel has an emission direction substantially towards the first eye 2 of the viewer.

100 sub-pixels are shown, which means that light can be output towards 100 different viewpoints, i.e. depending on from which of the 100 viewpoints the observer observes, this particular sub-pixel can be addressed to output light.

Fig. 2c shows a close-up of the ray tracing diagram of fig. 2, i.e. with the enlargement of the individual elements outputting the light constituting one of the image pixels during the second time slot.

The second sub-pixel in the sub-pixel set/group 46 may be addressed to output light and this light may be refracted by the first front microlens 8A.

Since the second sub-pixel has a different position than the first sub-pixel within the area defined by the element outputting light constituting one of the image pixels, the light will be refracted in the second emission angle/direction such that the first "pixel" has an emission direction substantially towards the second point of view (e.g. the second eye 3 of the observer).

Fig. 3 shows ray tracing of light output from a display arranged to display 81 image pixels, i.e. an image which is a raster pattern/bitmap image consisting of 81 image elements/image pixels.

The display shown has 9 segments, with 9 sub-pixel groups in each segment. There are 100 subpixels per group (or pixel). There are a total of 8100 sub-pixels. The display may be a dot matrix display.

In one practical implementation, the display may have more pixels, e.g., about 200 ten thousand pixels arranged in a 64-pixel segment, but we will describe this configuration with 81 pixels for clarity of illustration.

Fig. 4a shows a front view/schematic of the 81 pixel display described in connection with fig. 3.

Each sub-pixel is displayed as a gray square, and the corresponding sub-pixel outputting light from each sub-pixel group is displayed as a white square.

Each lens in front of each pixel (sub-pixel group) is shown as a black circle.

The 9 sub-pixel groups in the first segment 1 are represented by squares with striped contours, i.e. the first segment is the upper left hand segment.

Each sub-pixel group is shown to constitute a rectangular area and is shown to have a distance from an adjacent sub-pixel group.

The sub-pixels outputting light from the sub-pixel groups in the segment are arranged/positioned to have the same relative position in one group.

Multiple/several sub-pixels in a sub-pixel group may be positioned such that there will be multiple substantially horizontally distributed views, i.e. the horizontal resolution of the views. Such a plurality of sub-pixels may be sub-pixel rows, i.e. sub-pixels arranged/positioned substantially horizontally. The subpixel group may have more rows of subpixels than columns of subpixels (columns are vertically arranged/positioned subpixels).

The sub-pixels of the sub-pixel group may be arranged/positioned in a 2-dimensional space, i.e. the position of the sub-pixels in the sub-pixel group may be characterized by a pair of coordinates (first coordinate X and second coordinate Y).

A cartesian coordinate system may be used, i.e. the X-coordinate designates the horizontal position of the sub-pixels within the sub-pixel group (1-10 in this figure) and the Y-coordinate designates the vertical position of the sub-pixels within the sub-pixel group (1-10 in this figure). The origin may be the upper left corner (row 1, column 1), i.e. subpixel (1, 1) is the upper left subpixel and subpixel (10, 10) is the lower right subpixel (last row, last column).

For one segment (i.e. within the segment), all light output sub-pixels (e.g. one per group) have the same relative position in all sub-pixel groups, i.e. the sub-pixel outputting light in the first sub-pixel group (upper left sub-pixel group) may have the same coordinate pair as the sub-pixel outputting light in the sub-pixel group to the right of the first sub-pixel group.

Or in other words, each subpixel group within a segment occupies an area (the subpixels in a subpixel group have a physical distribution over an area). The sub-pixels outputting light may have substantially the same position within each region, i.e. the sub-pixels outputting light in the first sub-pixel group (upper left group) have a first position within the region of the first sub-pixel group. The subpixels of the output light in the subpixel group (upper left second group) on the right side of the first subpixel group have a second position within the area of the second subpixel group. To reach the second position from the first position, a (linear) translation of the first position is performed.

In this way the addressing of the sub-pixels is much simpler than in the prior art, where the sub-pixels are addressed in the same way as the individual pixels are addressed in the active matrix drive scheme.

Simpler addressing means that the number of transistors can be reduced and/or the number of data lines can be reduced. For example, a single pixel value need not be transmitted to each sub-pixel, and only one coordinate pair need be determined per segment.

More than one sub-pixel may output light from a sub-pixel group, e.g. related sub-pixels of a measured/detected view point may be determined, and sub-pixels surrounding the sub-pixel may also be addressed to output light.

There may be subpixels in the subpixel group that are not used for any content.

The display may have a set(s) of data lines for transmitting luminance or gray-scale values/signals, each subpixel set receiving a luminance value (one or more subpixels will then output light at a luminance corresponding to the received luminance value (i.e., represented by a current or voltage)).

In the segment of FIG. 4a, the data lines constitute electrode lines arranged as column lines (B0-0 through B2-2).

The display may have a plurality of scan lines for scanning luminance values into each sub-pixel group, i.e. the display is preferably an active matrix display such that scanned luminance values are preserved/stored for each sub-pixel group, so each sub-pixel will output light corresponding to the scanned luminance values as long as the luminance values are stored.

In the segment of fig. 4a, the scan lines constitute electrode lines arranged as row lines (scan 0 to scan 8).

For clarity of description, the display is described as having this basic active matrix configuration for a gray scale display, however, the scope of the invention is contemplated to include modifications and additions well known in the art, such as RGB color masks to enable the display to display color images, as well as circuits and other means for enhancing, calibrating and compensating for variations in luminance over time and variations in the display surface in different parts, for example due to manufacturing tolerances, including but not limited to pre-charge lines, reset lines and look-up tables.

Row drivers (not shown) (sometimes also referred to as gate drivers) may be formed and may be connected to the scan/row lines.

The row driver may scan the display by sequentially outputting active row control signals, one scan line at a time, starting at scan line 0 and ending at scan line 8 in a scanning operation. This scanning operation may be repeated while the display is in an active state.

Column drivers (not shown) (sometimes also referred to as source drivers) may be formed and may be connected to the data/column lines.

The column driver may output column control signals, which may be analog brightness values on column lines synchronized with the row driver and update the display with new images during a scanning operation.

The pixels in the display (pixel circuits of each subpixel group) may include a sample-and-hold circuit (memory circuit) and may perform a sample-and-hold operation on the column control signals when the corresponding row control signals are in an active state.

The segments (pixel groups) may have a plurality of address lines, such as one, two or e.g. 15 address lines per segment, for transmitting address signals. The (maximum) number of sub-pixels in a sub-pixel group may be a power of the number of scan lines and the number of address lines, i.e. 1 address line and 9 scan lines means that (maximum) 9 sub-pixels may be addresses in a sub-pixel group. 2 address lines and 4 scan lines means that 16 sub-pixels can be addressed.

Fig. 4a shows 6 address lines (X0, Y0, X1, Y1, X2 and Y2). Segment 1 has two address lines, X0 and Y0.

The address lines may transmit address control signals for addressing the subpixels. For example, X0 and Y0 may transmit subpixel address control signals for the first segment (pixel group) in display segment 1.

The subpixel address control signal may define the position of the first front microlens 8A relative to the first subpixel in the subpixel set 46, thereby defining the first light emitting angle of the first pixel.

One advantage of this is that the direction data (emission angle data/sub-pixel addressing data) can be transmitted as multiplexed data and stored in the display, for example using a circuit similar to an active matrix circuit for pixel value control.

The other pixels (sub-pixel groups) in the display segment 1 may be configured such that they have substantially the same sub-pixels as the first sub-pixel, and thus they may emit light at substantially the same emission angle (direction towards the viewpoint). Therefore, almost all of the front microlenses in the display section 1 can emit light at the same light emission angle defined by X0 and Y0. The light emitting area of a subpixel may have an area >0, i.e., not a perfect mathematical point. Thus, the light beam emitted from the microlens may have a beam divergence >0, i.e., the light beam is not perfectly collimated. Therefore, even if the emission angles of all the microlenses in the display segment 1 are the same, the light emitted from almost all the front microlenses in the display segment 1 can reach the eyeball, provided that the beam divergence, segment size, and eyeball distance range are calculated (using well-known geometric algebra) such that the beam divergence is not too small, the segment size is not too large, and the display-to-eyeball distance is not too small. For example, the beam divergence may be about 0.5 degrees, the segment size may be about 6x 6mm, and the distance to the eyeball may be between 0.3 meters and 3 meters. Thus, the eyeball can observe that all the microlenses in the segment are illuminated, even though the microlenses are located at different positions and all emit light at the same angle.

In other words, the address control signals X0 and Y0 may control a common light emitting angle for the display section 1, and the column control signals B0-0 to B0-2 may control a brightness level of each pixel in the display section 1. Other display segments in the display may emit light at different angles, so for example the display may have a first emission angle from the upper right hand corner of the display towards the first eye 2 and a second emission angle from the lower left hand corner of the display towards the first eye 2, wherein the first and second angles are different.

The address electrode lines may be connected to the outputs of the column drivers. The outputs of the column drivers connected to the address electrode lines may operate as binary signals, e.g. they may be analog outputs, so that they are actually always at a high or low voltage level.

The column driver may comprise a digital-to-analog converter and the digital input value of the digital-to-analog converter corresponding to the output connected to the address electrode lines may be selected such that it is actually always a high digital value or a low digital value. The digital values may be stored, for example, in a video frame buffer, which may also store digital pixel brightness values for the column control signals.

In other words, the subpixel address control signal defining the light emitting angle of the display segment may be included in the same video frame buffer as the pixel value. One advantage of this configuration is that the existing standard active matrix external circuitry (row driver, column driver, timing controller, video frame buffer and video input interface) can be used to send direction data (emission angle data/subpixel addressing data) to the display.

For example, if segments are 100×100 pixels and each segment has 2 address electrode lines, a standard active matrix external component may be used, where only 2 of the 100 column lines are used for sub-pixel address data, thus 98% horizontal resolution and 100% vertical resolution may be maintained while supporting an angular resolution of 100×100=10,000 different emission angles per display segment.

In summary, this operation can also be described as follows: when the row driver scans the row electrode line scan 0 through scan 2, display segment 1 has been fully updated and has stored 6 binary subpixel address control signals (3 for X addressing and 3 for Y addressing) and 9 pixel brightness values.

The 9 pixel brightness values control the brightness of the illuminated sub-pixels in the respective pixels via a conventional pixel driver, while the 6 binary sub-pixel address control signal values control which sub-pixels are illuminated (output light), for example via a switching transistor.

The 6 binary subpixel addressing control signal values can be divided into 3X position values that control which subpixel column positions are active and 3Y position values that control which rows of subpixel positions are active. The sub-pixels in the position where both the column and row positions are in the active state will be illuminated.

In the update interval of updating the display segment 1, i.e., in the interval in which any of the row electrode line scans 0 to 2 is in an active state, the display segment 1 may hold an undesired combination of updated and non-updated sub-pixel address control signal values. Therefore, in the update interval, the display segment 1 may emit light in an undesired direction. It can be assumed that the update interval is short relative to the duration of the frame shown on the display and that the risk of light emitted in undesired directions reaching the eyes of the observer is very small. Thus, it can be assumed that the update interval is considered a dark interval that is too short to be noticed by the eye. For example, if a segment is 6mm high and the active display surface is 800mm high, the segment height is 0.75% of the display height and the segment update time will be substantially 0.75% of the display update time. Furthermore, during the update process the segments will emit light in different directions, so in the worst case where video frames are unlikely to occur, i.e. the light from a segment is received by another eye than the desired one, this will only be significantly shorter than 1% of the update period in a very short interval, and thus during a video frame an undesired crosstalk significantly lower than 1% of the pixel values in the segments will be maximally generated. In other words, it may be decided that no operation is performed on potentially unwanted transmission directions during the update interval and that less risk of being subject to less adverse obvious effects is experienced.

Optionally, additional circuitry may be included that is capable of turning off the sub-pixels during the update interval. The additional circuit may for example turn off the common voltage supply for all pixel driver circuits when scan 0 changes from an inactive state to an active state and turn on the common voltage supply again when scan 2 changes from an active state to an inactive state. Such circuit design may be accomplished using well known circuit design techniques and may include, for example, SR flip-flops.

The pixels in display segment 1 may store address control signals in a similar manner to the storage of column control signals, for example by a sample and hold operation controlled by row control signals. Alternatively, other storage devices known in the electronics arts, such as data latches or other flip-flop circuits, may be included. Optionally, for controlling the memory function by means of the row control signal, other means known in the electronic arts may be included, for example a clock signal may be included and the address control signal may be serial data.

The dimensions of the sub-pixels in the display section 1 may be calculated and selected such that the light from the front micro-lenses is emitted in a light beam having a divergent shape, e.g. a light cone, wherein the light cone may have a divergent nature such that the first eye 2 is located virtually inside and the second eye 3 is located virtually outside of all light cones, whereby the first eye 2 may see light emitted from substantially all front micro-lenses in the display section 1 and the second eye 3 may not see light emitted from substantially any front micro-lenses in the display section 1. Such calculation and selection of sub-pixel sizes is well known in the art of autostereoscopic displays and may take as input the size of the display segment 1, the interpupillary distance between the first eye 2 and the second eye 3, and the distance from the display segment 1 to the viewer.

Furthermore, the sub-pixel clusters may be illuminated together, effectively forming larger sub-pixels, resulting in a larger divergence of the emitted light cone, which may accommodate the approach of the viewer to the display segment 1. Also, the size calculation of such clusters is well known in the art of autostereoscopic displays. The electrode lines may transmit address data to address more than one subpixel, such that, for example, such clusters of subpixels may be addressed.

Fig. 4b shows a front view/schematic of a display with fewer pixels and fewer sub-pixels than the display shown in fig. 4 a.

Specifically, the display shown in fig. 4b has 9 segments and four pixels per segment and four sub-pixels per pixel.

Each lens in front of each pixel (sub-pixel group) is shown as a black circle.

The 4 sub-pixel groups in the first segment 1 are represented by squares with striped contours, i.e. the first segment is the upper left hand segment.

In the segment of FIG. 4B, the data lines constitute electrode lines arranged as column lines (B0-0 through B2-1).

In the segment of fig. 4b, the scan lines constitute electrode lines arranged as row lines (scan 0 to scan 5).

Fig. 4b shows 6 address lines (X0, Y0, X1, Y1, X2 and Y2).

Fig. 5a to 5g show circuits for displaying images.

The light emitting component may be an OLED.

The circuit has 4 pixels or 9 pixels and there may be multiple "subpixels" for each pixel. The figure shows 4 or 9 sub-pixels per pixel. The concept behind the circuits in fig. 5a to 5g is that the circuits constitute a segment in which an address control circuit is arranged for addressing the sub-pixels in all pixels for controlling the direction of the emitted light. Different components in the circuit can be used for this addressing.

The circuit may be implemented in thin film technology.

Fig. 5a shows a circuit for displaying an image consisting of 9 image pixels. The 9 image pixels are arranged in a 3x 3 matrix.

The circuit drives 81 addressable pixels. For purposes of this disclosure, each addressable pixel is referred to as a subpixel. The subpixels are arranged in 9 groups, i.e. 9 groups of 9 subpixels each.

Each image pixel is displayed by one of the 9 sub-pixels in the sub-pixel group, i.e. for each image pixel to be displayed, one of the 9 sub-pixels is addressed to output light, such that 9 of the total 81 sub-pixels output light.

The sub-pixels to be addressed depend on the point of view of the viewer, i.e. where the viewer views the display.

The tracking system detects the position of the observer such that the sub-pixels visible from that point of view are addressed to output light. There are 9 sub-pixels and therefore there will be 9 views. The display will appear dark when viewed from elsewhere than this point of view.

The circuits are arranged such that there is one pixel circuit per subpixel group. The pixel circuit is arranged to inject a current into the sub-pixel causing it to output light. Each pixel circuit may include a pixel driver 31 for outputting a current.

Each sub-pixel of the sub-pixel group is connected to the pixel driver by a first means and a second means, but the means for controlling the signal to the sub-pixel may be arranged in other ways, as shown in some other way in fig. 5a to 5 g.

Fig. 5a shows in total 12 components in a pixel circuit for addressing/switching pixel driver signals to a sub-pixel. Each component has a first input constituted by the pixel driver output or a signal derived therefrom (e.g. amplified), and a second input for addressing/controlling the component. The output is constituted by the pixel driver output or a signal derived therefrom. Hereinafter, a component is mentioned as a switch or a transistor, but it may also be implanted as a set of transistors arranged as a logic circuit/gate.

In general, when components constituting a pixel driver are not considered, a pixel circuit may have more sub-pixels than components.

In fig. 5a, there are 9 sub-pixels and 12 components. Generally, the number of components cannot be greater than the product of r (1+c) or c (1+r), where r is the number of rows and c is the number of columns. Alternatively, if there is only one row, the number of parts does not exceed the number of columns.

The circuit further includes a plurality of address control circuits. There are a total of 6 address control circuits (42 a, 42b, 42c, 43a, 43b, 43 c). The 6 address control circuits output 6 control signals for the 12 switches in each pixel circuit, i.e., the same 6 control signals are transmitted to each pixel circuit. This reduces the number of transistors in the circuit and reduces the number of data lines required to transmit control signals to the sub-pixels, i.e. 81 data lines are required if each sub-pixel has its own data line.

The circuit in fig. 5a has 8 data lines arranged as three Scan lines (scan_0, scan_1, scan_2), three luminance data lines (b_0, b_1, B2) and two address data lines (X, Y).

Thus, when Scan line Scan_0 is high, the luminance values transmitted by luminance value lines B_0, B_1, and B_2 can be read into the three pixel drivers connected to Scan_0 and B_0, B_1, and B_2. In addition, control signals transmitted through the address data lines X and Y may be read into two address control circuits connected to scan_0 and X and Y.

Specifically, when the row control signal scan 0 is in the active state and is also kept in the active state for the duration of one frame (memory), the first address control circuit 42a (sub-pixel address data sample-and-hold circuit) samples the high output or the low output on the address electrode line Y0.

The first subpixel 46a is connected to the pixel driver 31 through a first switch 47 a. The switch/component is part of the circuit shown in fig. 5 a.

The first switch has a first input for switching the first switch. The first input is connected to the second address control circuit 43a. The striped lines in fig. 5a show the signal paths.

The second subpixel 46b is connected to the second pixel driver 31b through a second switch 47b (or transistor or logic circuit). The second switch has a second input for switching the second switch. The second input is connected to a second address control circuit 43a. The dashed line represents the signal path, and at junction 49 the line from the first address control circuit is split into three parts.

All the subpixels in the first column are connected to the first pixel driver by switches and all these switches have their switch inputs connected to the first address control circuit 42a, generally all the subpixels in the first column in each subpixel group of a segment are connected to the corresponding pixel driver by switches and all these switches have their switch inputs connected to the first address control circuit, i.e. 27 switches are connected to the output of the first address control circuit, the first address control signal being used to select a subpixel column (for each "image" pixel).

The first address control circuit 42a is used to select a row of sub-pixels, i.e. all sub-pixels in the first row of the group of sub-pixels are connected to the pixel driver 31 via the third switch 48.

A subpixel group that arranges/positions subpixels in more than 1 dimension connects all its subpixels to the pixel driver through two switches.

As can be seen from the figure, the sub-pixels in the corresponding positions in the other pixels are similarly connected to the sub-pixel address sample-and-hold circuits 42A through switches and the sub-pixel address sample-and-hold circuits 43A are connected to their respective pixel drivers, so that the sub-pixels in the same position in different pixels will emit light, and the brightness of the emitted light will be controlled by the stored pixel value corresponding to each pixel in the pixel driver. The sub-pixels in the other locations are similarly connected to other sub-pixel address sample and hold circuits and corresponding pixel drivers.

In other words, the stored value recorded into the sub-pixel address sample-and-hold circuit controls which sub-pixel position emits light, thereby controlling the angle of light emitted from the segment, and the stored value in the pixel driver controls the brightness of light emitted from each pixel.

Therefore, when both the output of the sub-pixel address data sample-and-hold circuit 42A and the output of the sub-pixel address data sample-and-hold circuit 43A are high, both the switching transistor 48 and the switching transistor 47a are turned on, and a current can flow from the pixel driver 31 through the organic light emitting diode.

Looking now at the first set/group 46 of subpixels in the first pixel, we can see that it is arranged in columns and rows, also referred to as X-positions and Y-positions, and that the address control signals stored in sample-and-hold circuits/registers 43A, 43B, and 43C control which X-positions have active signals, and that the address control signals stored in sample-and-hold registers 42A, 42B, and 42C control which Y-positions have active signals, and that only subpixels located at active X-positions and active Y-positions are illuminated.

We can call the values stored in 43A, 43B, and 43C for the X bits and the values stored in 42A, 42B, and 42C for the Y bits, with the high voltage being considered a "1" value and the low voltage being considered a "0" value. Thus, for example, if the X bits are 0, 1, 0 and the Y bits are 0, 1, 0, then only the middle sub-pixel in each pixel will be "on", i.e., light up. The brightness will depend on the individual pixel driver. Likewise, if the X bit is 1, 0 and the Y bit is 1, 0, then the upper left subpixel will be on.

We can also see that more than one sub-pixel location, e.g. a cluster of sub-pixels, can be turned on. For example, if the X bit is 1, 0 and the Y bit is 1, 0, then the cluster comprising the four upper left sub-pixels will be on in the four pixels (upper left, upper middle, middle left, and middle). As can be seen from the figure, if more than one sub-pixel is on, the current in the pixel driver flows through more than one organic light emitting diode.

In other words, a group of 9 subpixels is arranged in a two-dimensional coordinate system, i.e., one subpixel is addressable by two control signals (a pair of address coordinates). Thus, the first control signal is for a sub-pixel address in a first dimension and the second control signal is for a sub-pixel address in a second dimension.

The 6 address circuits are arranged such that 3 of them are used for sub-pixel addresses in the first dimension and the other 3 are used for sub-pixel addresses in the second dimension.

The 12 switches of the pixel circuit are arranged in groups. Three of which are used for sub-pixel addresses in the first dimension. The three switches are connected to three address circuits of the first dimension, respectively. There are 9 switches left for the sub-pixel addresses in the second dimension.

The 9 switches are arranged in groups of three switches each, namely:

the first set of three switches is connected to a Scan0/Y0 address control circuit 42a for addressing in the second dimension,

a second set of three switches is connected to the Scan1/Y0 address control circuit,

the third set of three switches is connected to the Scan2/Y0 address control circuit.

This is the case for each pixel circuit, which will be exemplified below:

the circuit has a first pixel circuit including a first subpixel connected to the first pixel driver through a first pair of switches (a first X switch and a first Y switch), and a second pixel circuit including a second subpixel connected to the second pixel driver through a second pair of switches (a second X switch and a second Y switch).

The first pixel circuit is for outputting light of a first image pixel, and the second pixel circuit is for outputting light of a second image pixel.

The address of the first sub-pixel in the sub-pixel group in the first pixel circuit is the same as the address of the second sub-pixel in the sub-pixel group in the second pixel circuit. And the first sub-pixel is addressed by the same address coordinate pair that the second sub-pixel is addressed to, i.e. a first X switch (such as a switch/transistor preceding the upper left sub-pixel in the first pixel circuit, which is the upper left pixel circuit, in which there are 9X switches) is connected to Scan0/X0 address control circuits for the first dimension of the address circuit group.

The second X switch (upper left switch in the second pixel circuit, which is located directly below the first pixel circuit) is connected to the same address control circuit. Thus, the first X-switch and the second X-switch are connected in parallel to the same address circuit (which is a control input/terminal connected to the address control circuit). For transistors, the control input/terminal is often denoted as gate or base, depending on the transistor technology.

Similarly, a first Y switch is connected to a first address circuit of the address circuit group for a second dimension, and a second Y switch is connected to the same address circuit. Thus, the first Y-switch and the second Y-switch are connected in parallel to the same address circuit (which is a control input/terminal connected to the address control circuit).

The switch may be implemented as a transistor. Two transistors may also be used to form a switch.

The arrangement of the above-described circuits is an optimized implementation to minimize the number of transistors within, for example, a subpixel group. However, more transistors may be used, for example two transistors per sub-pixel, for a group of 9 sub-pixels, a total of 18 transistors (not including the transistors used in the driver circuits of the sub-pixel group).

Each subpixel group has a driver circuit to ensure that whichever subpixel is addressed/turned on to output light, light is output at a brightness controlled by the subpixel's driver circuit. Whichever sub-pixel outputs light, its brightness will be the same as the other sub-pixel that has been addressed, the purpose of which is to control the display of the image in a direction towards the intended viewpoint.

The pixel driver 31 may include a sample-and-hold circuit and a current source controlled by an output value of the sample-and-hold circuit.

The pixel driver 31 samples the analog column control signals B0-0 when the row control signal scan 0 is in an active state and remains substantially active for as long as a video frame is displayed.

The current intensity is controlled by the pixel driver 31. Thus, the first sub-pixel will emit light of a luminance controlled by the luminance value stored in the pixel driver 31.

The sub-pixels may be organic light emitting diodes fabricated in thin films and located in close proximity and thus have very similar characteristics such that the current is substantially equally distributed among the "on" sub-pixels. In one configuration, the pixel values stored in the pixel driver may compensate for the number of sub-pixels that are on, so that, for example, four sub-pixels are on, the calculated current is four times stronger than the current of a pixel having only one sub-pixel on and the same desired brightness.

In another configuration, the number of subpixels that are turned on in display segment 1 may be maintained at a constant number.

As described above, the size of the sub-pixel clusters may be calculated based on factors such as distance from the observer, such that the first eye 2 of the observer sees light from all pixels in the segment, and such that the second eye 3 of the observer does not see light from any pixels in the segment.

To keep the number of subpixels unchanged, subpixels in the "don't care" position can be turned on or off depending on the number of subpixels needed for the cluster. The "no-so" position may be calculated as a sub-pixel position corresponding to a light emitting direction not toward any eyes of any observer.

The switching transistor in fig. 5a is shown as a general FET transistor. In practice they may be thin film transistors and the transistor characteristics and structure (such as n-type or p-type) as well as other characteristics including voltage levels may in practice be designed such that the transistor operates as a bi-directional switch. Such thin film circuit designs are well known in the art of active matrix displays, thin film sample and hold circuits, such as gate driver circuits on thin film arrays, and the like.

The circuit is scalable in that one segment can be used for a much larger number of image pixels and there may be a much larger number of sub-pixels per image pixel.

Fig. 5b shows a high level circuit.

The circuit is used to display an image consisting of 4 image pixels. The 4 image pixels are arranged in a 2x 2 matrix.

The principle of the circuit in fig. 5b is the same as the circuit in fig. 5a, but discrete components are placed in logic gates or blocks. The pixel driver is shown as block 31 and a logic gate 50 (which may be an and gate) and a switch 52 control the signals to drive the sub-pixels.

The output of each logic gate turns on and off the associated switch. When the switch is turned on, a signal from the pixel driver drives the associated subpixel.

Each logic gate has two inputs, an output from the first address control circuit 42a and an output from the second address control circuit 43a, respectively.

When both inputs of the logic gate are high, switch 52 is turned on.

As for the circuit in fig. 5a, there are an address control circuit for controlling/addressing "rows" and an address control circuit for controlling/addressing columns. Since there are 2x 2 sub-pixels, there are 2 rows and 2 columns of sub-pixels. One address control circuit controls/addresses more than one pixel, i.e. in a segment of image pixels there is one subpixel per image pixel controlled by a single address circuit.

Fig. 5c shows a mid-level circuit.

The principle of the circuit in fig. 5c is the same as the circuit in fig. 5a and 5b, but the driver is shown as a block and the control is shown as a switch. The pixel driver is shown as block 31.

One associated switch per subpixel, i.e., the first switch 54 is located at/before the first subpixel 46 a. Each of these switches may be referred to as a column switch because the control input of each switch of each sub-pixel is connected to the output of an address control circuit for controlling column addressing, i.e. addressing in the X-direction or horizontal direction (when the display is arranged in its intended position).

The second set of switches may be referred to as row switches for controlling the column switches, i.e. the control inputs of the column switches are connected to the outputs of the address control circuit for controlling the addressing of the rows (row switches). When the row switch is on, the pixel driver signal is output from the addressed row switch and into the column switch.

Fig. 5d corresponds to fig. 5a, but is only used to display an image consisting of 4 image pixels, four sub-pixels in each pixel.

Fig. 5e shows that an amplifier 60 is added to each address control circuit, i.e. the output of the address control circuit is amplified.

The amplifier is shown as two transistors, i.e. a push-pull amplifier.

Each address control circuit (output) sees one capacitive load and one resistive load, as the output for each address control circuit can be directed/routed to multiple switches. The amplifier may provide compensation for this, i.e. the load may be so high that an address control circuit without an amplifier may not be able to drive the switch, since the output of the address control circuit has to go through many wires.

Fig. 5f also shows that one amplifier is added per address control circuit.

In fig. 5f, the amplifier return path enters signal ground through diode 62, such as an OLED.

Fig. 5g shows a circuit.

The circuit is used to display an image consisting of 9 image pixels. The 9 image pixels are arranged in a 3x 3 matrix.

The circuit corresponds to the type of circuit described in connection with the above figures and fig. 5g shows the addition of virtual or dummy pixels, such as the first dummy pixel 55, which are arranged to control the stability or balance of the light emission or current through the circuit.

For example, it may be desirable to turn on more than one sub-pixel per pixel/emit light, but only one sub-pixel is visible to the viewer.

Thus, the virtual subpixels may be arranged and have positions such that the virtual subpixels emit light that is not visible from any position defined by the subpixels within the subpixel grid.

In fig. 5g, a plurality of virtual sub-pixels (specifically three virtual sub-pixels per pixel) and a plurality of virtual address control circuits (specifically three virtual address control circuits) are shown.

In general, the circuit may have a plurality of sub-pixels, and the sub-pixels that are addressable to emit light in a direction toward the viewer constitute a number less than the total number of sub-pixels.

The pixel driver of each pixel circuit also drives virtual sub-pixels, i.e. each virtual sub-pixel is connectable to the pixel driver by means such as the first means 58 for addressing/switching the pixel driver signals to the virtual sub-pixels in the same way as the sub-pixels. The component may be a switch or a transistor or a general logic circuit.

The component/logic circuitry may receive control inputs from virtual address control circuitry, such as first virtual address control circuitry 56. The virtual address control circuit is used to address the virtual sub-pixels such that they emit light when the virtual sub-pixels are addressed.

Fig. 5g shows three virtual address control circuits.

The number of sub-pixels that can be turned on may depend on the distance the viewer is looking at the display.

If the observer is close to the display, it may be necessary to turn on more than one sub-pixel in a pixel so that the observer will still see the same image as the observer moves.

If the observer is far from the display it may be sufficient to turn on only one sub-pixel, since even if the observer moves it is unlikely to move so fast that the display cannot be updated to the new position of the observer.

For a position close to the display, if only one sub-pixel is on, it may be that the display update speed is not fast enough, so that the viewer moves out of the image, i.e. to a position where no image is pointing.

Since the number of sub-pixels (loads) that are turned on and off are so different, the virtual sub-pixels may provide a more uniform load over time, so that the same number of sub-pixels may be turned on for each image frame.

Fig. 6a shows another example of a circuit configuration for display segment 1.

In this example, the display segment 1 has 16 pixels, 4 sub-pixels each, arranged in a 2x 2 grid, and only one address electrode line XY0. The operation of this circuit is similar to that in fig. 5a, but here sample and hold circuits 42A and 42B are used for X-position addressing of the sub-pixels and sample and hold circuits 42C and 42D are used for Y-position addressing of the sub-pixels, and all sample and hold circuits 42A to 42D are connected to a single one of the address electrode lines XY0.

Fig. 6b shows another example of a circuit configuration for display segment 1.

In this example, the display segment 1 has 16 pixels, with 4 sub-pixels each arranged in a row. The sample and hold circuits 42A to 42D are all used for X-position addressing. In this configuration, the sub-pixels may be elongated and/or the front microlens array 8 may comprise cylindrical lenses.

Fig. 7 shows a circuit.

The circuit is used to display an image consisting of 4 image pixels to display a color image.

Generally, there are two techniques for displaying color.

One approach is to provide one red image pixel, one green image pixel, and one blue image pixel adjacent to each other. This is shown in fig. 7.

Another approach is to place a color mask between the pixels and the viewer such that a first image pixel has a red color filter that causes it to emit red light, a second image pixel has a green color filter that causes it to emit green light, and a third image pixel has a blue color filter that causes it to emit blue light. The first image pixel, the second image pixel, and the third image pixel are adjacent to each other.

Fig. 8 shows a configuration example of a display including 81 pixels arranged in 9 display segments of 9 pixels each, in which the sub-pixels are elongated.

In this configuration, the sub-pixels are arranged such that the distance of the sub-pixels of adjacent pixels is the same as the distance between the sub-pixels in the same pixel.

The advantage is that the micro-lens 8A can have a longer focal length and can transmit and refract the emitted light from the sub-pixels in the adjacent pixels, thus providing a large angle without requiring a very short focal length that can be difficult to manufacture with high quality.

Fig. 9a shows a color filter/mask of a color display.

The color mask is a pattern of three colors and has a first row of blue color filters for transmitting blue light, a second row (under the first row) of green color filters for transmitting green light, and a third row (under the second row) for transmitting blue light.

The first three rows cover the first line of image pixels.

The pattern in the first three rows repeats down the color mask. The pattern/color sequence in the vertical direction may be different, e.g. blue followed by green and then red.

Thus, the (three) different colors of the color mask are vertically ordered, i.e. in a consecutive order in the vertical direction.

The respective color filter may not necessarily have a color when the display is turned off, but when the display is viewed while the display is turned on, light from the respective color filter means that the respective color filter may be regarded as having a color.

The display may be a directional display as described above, i.e. a display with addressable sub-pixels for directing light to the viewer, in particular towards the left and right eyes of the viewer, such that the viewer perceives a 3D image (if a 3D image is to be perceived, both eyes may not see the same image, the left eye will see an image for the left eye and the right eye will see an image for the right eye).

The display uses light emitters that emit white light. Each light emitter may be an LED such as an OLED or an LCD for modulating the backlight.

Each pixel may be divided into three parts to generate colors, i.e., a first set of sub-pixels (within a pixel) may be for a first color, a second set of sub-pixels (within a pixel) may be for a second color, and a third set of sub-pixels (within a pixel) may be for a third color.

The color may be generated through a color mask.

The color mask is placed in front of the display pixels, arranged between the pixels and the viewer.

In front of the first portion of the pixel may be a first color filter for transmitting a first color of the incident spectrum, such as red, and filtering (reflecting or absorbing) other portions of the incident spectrum.

In front of the second portion of the pixels may be a second color filter for transmitting a second color of the incident spectrum, such as green.

In front of the third portion of pixels may be a third color filter for transmitting a third color of the incident spectrum, such as blue.

Fig. 9b is an enlargement of a single pixel.

The first color filter is arranged at an upper portion of the pixel/covers an upper portion of the pixel (indicated in red). The sub-pixel group arranged behind the first color filter constitutes a first "RGB sub-pixel".

The second color filter is arranged at/covers the middle part of the pixel. The third color filter is arranged at/covers the bottom part of the pixel. The sub-pixel group arranged behind the second color filter constitutes a second "RGB sub-pixel".

The second color filter is interposed between the first color filter and the third color filter. The sub-pixel group arranged behind the third color filter constitutes a third "RGB sub-pixel".

For each RGB sub-pixel, a single sub-pixel appears (shown brighter than the other sub-pixels).

Each RGB sub-pixel has a horizontal elongation, i.e., the number of sub-pixels in the horizontal direction is greater than the number of sub-pixels in the vertical direction, so as to have a higher horizontal resolution, with the eyes of the observer being arranged horizontally under normal viewing conditions.

Each color filter has an elongated shape with a width in a horizontal direction and a height in a vertical direction. The width is greater than the height, e.g., the width is greater than 25% of the height, such as 40%, 50%, 75%, or 100%.

Fig. 9c shows a perspective view of three image pixels.

Each of the three image pixels has three RGB sub-pixels, each in front of which a color filter is present.

An optical device, shown as an elongated optical lens, is arranged in front of each RGB sub-pixel. The optical lens is elongated in the horizontal direction, i.e. has a width (measured horizontally) that is larger than the height (measured vertically for the intended operating position of the display, i.e. suspended on a wall or standing on a stand).

Thus, the optics shape in front of the RGB sub-pixels follows the shape of the color filters in front of the RGB sub-pixels.

The following is a set of points that form aspects of the invention that may be considered to be patentable independently, and thus form the basis for a set of possible claims in the future:

1. a display for displaying an image to a viewer at a first point of view, the display comprising:

the plurality of pixels are arranged in a plane,

-a front optical device having at least one optical element with optical power and a first focus and a second focus, the first focus being located substantially at the plane, the second focus being between the front optical device and a point located in front of the front optical device and not distant from the front optical device.

2. A display for displaying an image to a viewer at a first point of view, the display comprising:

the plurality of pixel circuits includes:

the circuit includes a control circuit for switching the first switch and the second switch by a control signal output by the control circuit at an output, the output being connected to the first input and the second input.

3. A display for displaying an image to a viewer at a first point of view, the display comprising:

4. A display for displaying an image to a viewer at a first point of view, the display comprising:

5. A display according to any of the preceding points, each sub-pixel group having a first number of sub-pixels, such as sub-pixel rows, oriented substantially horizontally and a second number of sub-pixels, such as sub-pixel columns, oriented substantially vertically.

6. A display as claimed in any one of the preceding points, the number of control circuits being equal to the sum of the first number of sub-pixels and the second number of sub-pixels.

7. A display for displaying a color image, the display comprising:

a plurality of pixels constituting image pixels, each image pixel comprising a first RGB sub-pixel, a second RGB sub-pixel and a third RGB sub-pixel,

a color mask arranged in front of the plurality of image pixels,

the color mask forms a pattern of color filters, including a first color filter arranged in front of the first RGB sub-pixels,

a second color filter arranged in front of the second RGB sub-pixels,

a third color filter arranged in front of the third RGB sub-pixels,

the first color filter is arranged for transmitting a first color of an incident spectrum,

the second color filter is arranged for transmitting a second color of the incident spectrum,

the third color filter is arranged for transmitting a third color of the incident spectrum,

each color filter of the color mask has an elongated shape having a width in a horizontal direction and a height in a vertical direction, the width being greater than the height for reducing diffraction in a horizontal plane as compared to diffraction on a vertical plane.

8. A display according to any one of the preceding points, each image pixel comprising a first set of sub-pixels constituting the first RGB sub-pixel, a second set of sub-pixels constituting the second RGB sub-pixel and a third set of sub-pixels constituting the third RGB sub-pixel.

9. A display according to any of the preceding points, the width being greater than the height such that the display has a higher vertical resolution for a sub-pixel of a respective colour than a horizontal resolution for the sub-pixel of the respective colour.

10. A display according to any of the preceding points, the plurality of image pixels comprising a first image pixel comprising a first group of sub-pixels comprising a first sub-pixel.

11. A display according to any of the preceding points, the first sub-pixel group comprising a second sub-pixel.

12. The display of any of the foregoing points, the first subpixel defining a first direction or first angle relative to the viewer's point of view,

the second sub-pixel defines a second direction or second angle relative to the observer's point of view,

the first angle or direction is greater than 0% and less than 10%, such as a 5% difference, from the second angle or direction.

13. A display according to any of the preceding points, the plurality of image pixels comprising second image pixels comprising a second group of sub-pixels comprising a third sub-pixel.

14. A display according to any of the preceding points, the first and third sub-pixels being preferably addressed by a common or identical address control signal such that light emitted or propagating from the first and second sub-pixels is visible from the viewer point of view.

15. A display according to any of the preceding points, the third sub-pixel defining a third direction or second angle relative to the viewer's point of view.

16. A display according to any of the preceding points, the first angle or direction being substantially the same as the third angle or direction or differing from the third angle or direction by less than 10%, such as by 5%.

17. A display according to any of the preceding points, the display comprising a control system for controlling the light intensity and angle or direction of light emitted or propagated from the plurality of pixels such that light emitted or propagated from the plurality of pixels is visible from the viewer point of view.

18. A display according to any of the preceding points, the display being an active matrix display.

19. A display according to any of the preceding points, each sub-pixel constituting a light output element for outputting light.

20. A display as claimed in any one of the preceding points, the circuit comprising a first line connected to the first input and a second line connected to the second input.

21. A display as claimed in any one of the preceding points, the first and second lines constituting nodes of the circuit.

22. A display according to any of the preceding points, the circuit comprising a junction at which the first line is connected to the second line.

23. A display according to any of the preceding points, the electrode wire comprising:

a plurality of data lines for transmitting the luminance values,

a plurality of address lines for transmitting the address signals,

a plurality of scan lines for scanning the brightness value or the address signal.

24. A display as claimed in any one of the preceding points, the plurality of scan lines de-multiplexing the luminance values.

25. A display according to any of the preceding points, the circuitry constituting an active matrix backplane.

26. The display of any of the preceding points, the number of data lines being greater than one.

27. A display according to any of the preceding points, each sub-pixel of a respective image pixel defining a direction towards a viewpoint such that the image is visible from a first viewpoint when the first sub-pixel outputs light and the display is perceived as a dark screen from a viewpoint other than the first viewpoint.

% LCD backlight function

28. A display for controlling image directionality of an observer who observes the display from an observer's point of view in front of the display, the display comprising:

a liquid crystal layer sandwiched between the rear electrode layer and the front electrode layer for generating the image,

a plurality of pixels including a first pixel constituting a backlight pixel,

the plurality of pixels is arranged behind the layer,

each pixel defines a pixel region having a plurality of sub-pixels,

the first pixel has a first plurality of sub-pixels including a first sub-pixel,

each sub-pixel defines a direction from the display to a view point,

or the angle between the normal of the display and the viewpoint,

a front optical device having at least one optical element with optical power and a first focus and a second focus, the first focus being substantially on the layer, the second focus being between the front optical device and a point located in front of the front optical device and not distant from the front optical device,

A control system for controlling the light intensity and the angle or direction of the emitted light from the plurality of pixels,

the plurality of pixels are controlled such that for respective pixels emitting light, each pixel emits light having substantially the same light intensity such that the light intensity emitted by the respective first pixel differs from the light intensity emitted by the respective second pixel by no more than 20%.

29. A display according to any of the preceding points, the plurality of pixels being arranged in a first segment covering a segment area of the display.

30. The display according to any of the foregoing points,

the control system is configured such that

The light intensities of the plurality of pixels are individually controlled for each pixel in the first segment, and

the angles of the emitted light of the plurality of pixels are commonly controlled such that the plurality of pixels emit light at substantially the same angle such that the light emitted or propagated from the plurality of pixels is visible from the observer's point of view.

31. A display according to any of the preceding points, comprising circuitry comprising the plurality of pixels.

32. The display of point 31, the circuitry being implemented in the first film.

33. The display according to any of the foregoing points,

the control system is configured for

Outputting a set of input luminance values to the circuit such that the plurality of pixels in the segment emit light having a luminance corresponding to a value in the set of input luminance values, an

An address control signal defining a subpixel of each of the plurality of pixels to be addressed is output such that the plurality of pixels in the segment emit light at an angle such that the plurality of pixels are visible from the observer's point of view.

34. A display according to any of the preceding points, the first plurality of sub-pixels being arranged in a grid having rows and columns such as at least one row and more than one column.

35. A display according to any preceding claim, comprising address lines for transmitting address control signals to the circuitry for addressing respective sub-pixels in the first group of sub-pixels.

36. The display of point 35, the address lines connected to the outputs of the active matrix column driver.

37. The display according to point 35 or 36, the address lines constitute electrode lines.

38. The display according to any one of points 35 to 37, the address line being implemented in the first film or a second film different from the first film.

39. The display of any one of points 35 to 38, the address control signals comprising row control signals and column control signals.

40. A display according to any of the preceding points, comprising a first sub-pixel address line for transmitting sub-pixel row control signals to the first pixel for addressing a respective sub-pixel of the first plurality of sub-pixels.

41. The display of point 40, the first subpixel address line comprising an electrode line.

42. The display of point 40 or 41, the first subpixel address line being implemented in the first film or a second film different from the first film.

43. A display according to any of the preceding points, comprising a second sub-pixel address line for transmitting sub-pixel column control signals to the first pixel for addressing a respective sub-pixel of the first plurality of sub-pixels.

44. The display according to point 43, the second subpixel address line constitutes an electrode line.

45. The display of point 43 or 44, the second subpixel address line implemented in the first film or a second film different from the first film.

46. A display according to any of the preceding points, comprising a data line for transmitting light intensity values to the first sub-pixel.

47. The display of point 46, the data lines comprising electrode lines.

48. The display according to point 46 or 47, wherein the data line is implemented in the first film or a second film different from the first film.

49. A display according to any of the preceding points, comprising a scan line for drawing the image or updating the image.

50. The display according to point 49, wherein the scan lines constitute electrode lines.

51. The display according to point 49 or 50, wherein the scanning line is implemented in the first film or a second film different from the first film.

52. A display according to any of the preceding points, each sub-pixel constituting an electroluminescent device such as an LED or OLED or a light modulator such as a liquid crystal cell.

53. A display according to any of points 46 to 48, the first sub-pixel being connected to the data line by a pixel driver.

54. A display according to point 53, the pixel driver comprising a memory component or a circuit such as a sample and hold circuit.

55. A display according to any of points 49 to 51, the scan lines transmitting scan data for controlling the pixel drivers.

56. A display according to either point 53 or 54, the first sub-pixel being connected to the pixel driver at least by a first row of switches, such as transistors.

57. The display of point 56, the second subpixel is connected to the pixel driver at least through the first row switch.

58. The display of any one of points 35 to 42, the address line or the first sub-pixel address line transmitting the sub-pixel row control signal for switching the row switch.

59. A display according to any of points 46 to 48, the first sub-pixel being connected to the pixel driver at least through a first column switch such as a transistor.

60. The display of point 59, the second subpixel being connected to the pixel driver by at least a second column switch, such as a transistor.

61. The display of any one of points 35 to 39 or 43 to 45, the address line or the second sub-pixel address line transmitting the column control signal for switching the column switch.

62. The display according to any one of points 35 to 39, the address lines transmitting the address control signals to the first and second sub-pixels such that the first sub-pixel emits light and the second sub-pixel emits light.

63. The display according to any one of points 35 to 39,

the address line is connected to each of the plurality of pixels such that the first subpixel group and the second subpixel group are switched by the address control signal such that the first subpixel and the third subpixel are visible from the viewer's point of view when turned on by the address control signal.

64. The display according to any one of points 35 to 39,

the address lines are preferably connected to the first row switch and the second row switch by a memory component or circuit for switching the first row switch and the second row switch substantially simultaneously.

65. The display according to any of the foregoing points,

the first row of switches and the second row of switches are connected to outputs of the memory component or circuit, and the address lines are connected to inputs of the memory component or circuit.

66. The display according to any of the foregoing points,

the address lines are preferably connected to the first column switch and the second column switch by a memory component or circuit for switching the first column switch and the second column switch substantially simultaneously.

67. The display according to any of the foregoing points,

the first column switch and the second column switch are connected to an output of the memory component or circuit, and the address line is connected to an input of the memory component or circuit.

68. A display according to any of the preceding points, each sub-pixel having an input for a current and an output for the current.

69. A display according to any of the preceding points, the first and second sub-pixels being connected in parallel.

70. According to the display of point 68,

the output of each sub-pixel in a row of sub-pixels is connected to a memory component or circuit, and

the input of each sub-pixel in the sub-pixel column being connected to a second memory component or circuit, or

The output of each sub-pixel in a column of sub-pixels is connected to a memory component or circuit, and

the input of each sub-pixel in the sub-pixel row being connected to a second memory means or circuit, or

The input of each subpixel in a subpixel column is connected to a memory component or circuit, and

the output of each sub-pixel in the sub-pixel row being connected to a second memory component or circuit, or

The input of each sub-pixel in a row of sub-pixels is connected to a memory component or circuit, and

the output of each subpixel in a subpixel column is connected to a second memory component or circuit.

71. A display according to any of the preceding points, the memory component or circuit being a sample and hold circuit, a data latch or a flip-flop.

72. A display according to any of the preceding points, the control system being configured such that a plurality of sub-pixels are addressed for emitting light for each image frame such that the light intensity from the first pixel is uniform from one image frame to another.

73. A display according to any of the preceding points, the number of sub-pixels of the first sub-pixel group being addressed so that the difference in luminescence from one image frame to another does not exceed 25%, so that the current through the respective sub-pixels does not deviate by more than 25% from one image frame to another.

74. A display according to any of the preceding points, the number of sub-pixels of the first sub-pixel group being addressed for emitting constant light from one image frame to another.

75. A display according to any of the preceding points, the first sub-pixel group comprising virtual sub-pixels.

76. The display of point 75, the virtual sub-pixel being addressed for emitting light with the first sub-pixel and the virtual sub-pixel being positioned within the first pixel such that light emitted by the third sub-pixel is not visible from the viewer's point of view.

77. The display of points 75-76, the second sub-pixel being turned on with the first sub-pixel and the second sub-pixel being positioned proximate to the first pixel such that light emitted by the second sub-pixel is visible from the viewer's point of view.

78. A display according to any one of the preceding points, the angles of emitted light of the plurality of pixels being commonly controlled by an address control signal that defines the angles of emitted light of the plurality of pixels such that the first pixel receives the address control signal and the second pixel receives the address control signal.

79. A display according to any of the preceding points, the angle of the emitted light from the first sub-pixel and the angle of the emitted light from the second sub-pixel being not more than 25%, such as not more than 1 degree or 0.5 degree, from each other.

80. The display according to any of the preceding points, the first sub-pixel being arranged at a first position within the area of the first pixel, and the third sub-pixel being arranged at a second position within the area of the second pixel,

the second position essentially constitutes a translation of the first position such that

The light emitted by the first sub-pixel and the second sub-pixel is visible from the viewpoint, or

The first subpixel has a position within a pixel region of the first pixel that is substantially the same as a position the third subpixel has within a pixel region of the second pixel such that light emitted by the first subpixel and the third subpixel is visible from the viewpoint.

81. A display according to any one of the preceding points, the angle of light emitted by the respective pixels being controlled by the control system by optically or electronically addressing the sub-pixels.

82. A display according to any of the preceding points, the display being configured such that when the viewer views the display from the point of view

The control system transmits address control signals to the first and second sub-pixels such that the first and second sub-pixels emit light at an angle of the viewpoint.

83. The display of any of the preceding points, the segment region having a width of less than 10cm and greater than 0.5 cm.

84. A display according to any of the preceding points, the first segment having more than two pixels, such as 10 or 20 or 50 pixels.

85. A display according to any of the preceding points, the first segment having less than 50000 pixels.

86. A display for controlling image directionality of an observer who observes the display from an observer's point of view in front of the display, the display comprising:

a plurality of pixels including a first pixel constituting an image pixel,

the plurality of pixels are arranged in a plane,

each pixel defines a pixel region having a plurality of sub-pixels,

each sub-pixel defines a direction from the display to a view point,

or the angle between the normal of the display and the viewpoint,

Each subpixel is optically addressable and comprises:

a thin film stack of an electroluminescent layer and a photoactive layer,

the electroluminescent layer and the photoactive layer constituting an optical converter such that light incident on a respective sub-pixel causes a first current to be generated through the photoactive layer and through the electroluminescent layer, such that the electroluminescent layer emits light from a location of the respective sub-pixel within the pixel upon application of a voltage across the thin film stack,

a front optical device having at least one optical element with optical power and a first focus and a second focus, the first focus being located substantially at the plane, the second focus being between the front optical device and a point located in front of the front optical device and not distant from the front optical device,

-a control system for controlling the light intensity and the angle or direction of the emitted light from the plurality of pixels such that the light emitted by the plurality of pixels is visible from the observer's point of view.

87. A display according to any of the preceding points, comprising:

an addressing light element having a plurality of addressing pixels for emitting light from the respective addressing pixel towards the segment and optically addressing sub-pixels of the segment,

Each addressed pixel defines a direction from the segment towards the viewpoint.

88. A display according to any of the preceding points, comprising:

an optical device located between the addressing light element and the optical converter, the optical device structure comprising at least one optical element having an optical power,

the optical means are adapted to direct light from the respective addressed pixel to a sub-pixel of the segment such that the sub-pixel of the segment emits light visible from the viewpoint.

89. The display of any of the preceding points, light from the plurality of addressed pixels being modulated such that the thin film stack is illuminated at a first intensity in a first pattern defining an optical path between the thin film stack and a first eye of an observer, and such that a region of the thin film stack outside the first pattern is illuminated at a second intensity, wherein the second intensity is lower than the first intensity.

90. A display according to any of the preceding points, light from the plurality of light emitters or addressed pixels being modulated such that the thin film stack is illuminated at first time intervals in a first pattern defining an optical path between the thin film stack and a first eye of the first observer, and

The film stack is illuminated at a second time interval in a second pattern defining an optical path between the film stack and a second eye of the second viewer,

such that in the first time interval the first image for the first eye of the first observer is transmitted and in the second time interval the second image for the second eye of the second observer is transmitted.

91. A display according to any of the preceding points, comprising:

a circuit for generating a current through the electroluminescent layer, the current density of the current through the electroluminescent layer having a maximum 20% change in magnitude relative to the average magnitude of the current density.

92. A display according to any of the preceding points, the optical converter having a front face facing the viewer and a rear face opposite the front face.

93. A display according to any of the preceding points, the electroluminescent layer constituting an organic light emitting diode or an organic light emitter.

94. A display according to any of the preceding points, the optical means and the addressing light element being arranged behind the optical converter with respect to the point of view.

95. A display according to any of the preceding points, the optical means and the addressing light element being arranged in front of the optical converter with respect to the point of view.

96. A display according to any of the preceding points, the respective first addressed pixels defining a first direction from the first segment towards the view point and the respective second addressed pixels defining a second direction from the first segment towards a second view point, the first direction being different from the second direction.

97. A display according to any of the preceding points, comprising a second plurality of pixels arranged in a second segment of the area covering the display for emitting light visible from the point of view.

98. A display according to any of the preceding points, the second section being arranged alongside the first section.

99. The display of any of the preceding points, the second segment having a different viewing angle from the viewpoint to the second segment than from the viewpoint to the first segment.

100. A display according to any of the preceding points, comprising a second addressing light element having a second plurality of addressing pixels for emitting light from the respective addressing pixel to the second segment and optically addressing sub-pixels of the second segment.

101. A display according to any of the preceding points, the optical device comprising a plurality of optical elements.

102. A display as claimed in any one of the preceding points, the number of optical elements corresponding to the number of pixels.

103. A display according to any of the preceding points, the respective optical element being adapted to compensate for the off-axis position of the optical element relative to the central axis of the addressed light element.

104. A display according to any of the preceding points, the respective optical elements having prismatic properties and/or being tilted with respect to the plane of the addressing light element.

105. A display according to any of the preceding points, comprising compensation optics in the optical path between the respective optical element and the addressing light element, the compensation optics being adapted to compensate for the off-axis position of the optics relative to the central axis of the addressing light element.

106. A display according to any of the preceding points, the compensating optics being located in an optical path between more than one optical element comprised of the optics and an addressing light element.

107. A display according to any of the preceding points, the compensating optics being a collimating lens.

108. A display according to any of the preceding points, comprising a second optical device between the addressing light element and the optical converter, the second optical device having an optical power, the second optical device being adapted to direct light from a respective addressing pixel of the second plurality of addressing pixels to a sub-pixel of the second segment such that the sub-pixel of the segment emits light visible from the viewpoint.

109. A display according to any of the preceding points, comprising an addressed light element layer having a plurality of addressed pixels.

110. A display according to any of the preceding points, the respective optical element being a converging lens or a diffractive optical element.

111. A display according to any one of the preceding points, the addressed pixels being projected onto a surrounding area of an observer's eye and reflected towards the optical means.

112. A display according to any of the preceding points, comprising a plurality of segments for emitting light visible from the point of view.

113. A display according to any of the preceding points, comprising a second controller for addressing pixels of the plurality of segments such that voltages are applied to pixels of the plurality of segments constituting the image.

114. A display according to any of the preceding points, the second controller being synchronized with the first controller such that the addressed light elements are addressed at the same time as the pixels are addressed.

115. A display according to any of the preceding points, comprising:

a stack of at least a first set of first films, a second set of films and a third set of films,

the first set of films defines an electroluminescent layer comprising the plurality of pixels,

the second set of films defines a photosensitive layer,

the third set of film definitions comprising an addressing light layer of the addressing array for each pixel for emitting light from the respective addressed pixel and optically addressing the sub-pixels of the respective pixel,

-the control system is configured to address respective addressed pixels of each addressed array such that light from the respective addressed pixels is directed to respective sub-pixels of the respective pixels such that the image is visible from the viewpoint.

116. A display for controlling image directionality of an observer who observes the display from an observer's point of view in front of the display, the display comprising:

a plurality of pixels including a first pixel constituting an image pixel,

the plurality of pixels are arranged in a plane,

each pixel defines a pixel region having a plurality of sub-pixels,

each sub-pixel defines a direction from the display to a view point,

or the angle between the normal of the display and the viewpoint,

the first set of films defines an electroluminescent layer having a plurality of pixels including a first pixel comprising an image pixel,

Each pixel defines a pixel region having a plurality of sub-pixels,

each sub-pixel is optically addressable,

the second set of films defines a photosensitive layer,

the third set of film definitions comprising an addressing light layer of the addressing array for each pixel for emitting light from a respective addressed pixel and optically addressing a respective sub-pixel of the respective pixel, such that the respective sub-pixel emits light,

each addressed pixel defines an angle from the corresponding pixel towards the viewpoint,

-a controller for addressing a respective addressed pixel of each addressed array such that light from said respective addressed pixel is directed to a respective sub-pixel of a respective pixel such that said image is visible from said viewpoint.

117. A display for controlling the directionality of an image to an observer, the display comprising:

A plurality of pixels, each image pixel defining an area having a plurality of sub-pixels,

each subpixel is optically addressable and comprises:

a thin film stack of an electroluminescent layer and a photoactive layer,

the electroluminescent layer and the photoactive layer constituting an optical converter such that light incident on a respective sub-pixel causes a current to be generated through the photoactive layer and through the electroluminescent layer, such that the electroluminescent layer emits light from a location of the respective sub-pixel within the image pixel upon application of a voltage across the thin film stack,

the display includes:

an addressing light element having a plurality of addressing arrays, each addressing array having a plurality of addressing pixels for emitting light to the optical converter,

the plurality of addressing arrays are arranged such that each image pixel is addressed by an addressing array,

Each addressed pixel in the respective addressed array of respective image pixels defines a direction from said respective image pixel towards the viewpoint,

-a controller for addressing a respective addressed pixel of each addressed array such that light from said respective addressed pixel is directed to a respective sub-pixel of each image pixel such that said image is visible from said viewpoint.

118. A display according to any of the preceding points, the controller being remote from the display.

119. A display according to any of the preceding points, the controller being adapted to cause light from the addressed pixels to be modulated such that the optical converter is illuminated at first time intervals in a first pattern defining an optical path between the segment and the left eye of the observer and illuminated at second time intervals in a second pattern defining an optical path between the segment and the right eye of the observer, thereby displaying the image in 3D.

120. A display according to any of the preceding points, the optical converter having a front face facing the viewer and a rear face opposite the front face.

121. A display according to any of the preceding points, the addressing light element being arranged behind the optical converter with respect to the point of view.

122. A display according to any of the preceding points, the addressing light element being arranged in front of the optical converter with respect to the point of view.

123. A display as claimed in any one of the preceding points, the second focus being substantially at infinity.

124. A display according to any of the preceding points, the front optical device being arranged in front of the optical converter with respect to the point of view.

125. A display according to any of the preceding points, the first focus lying in a plane within +/-2cm, such as +/-100 micrometers (um), from the optical converter.

126. A display according to any of the preceding points, comprising a tracking system for tracking or detecting the position of the observer.

127. A display according to any of the preceding points, the tracking system constituting an eye movement tracking system for tracking or detecting the position of the eyes of the observer.

128. A display according to any of the preceding points, the tracking system comprising a visible or infrared camera or an illumination system capable of illuminating the viewer with structured or unstructured illumination or lidar and/or a passive infrared detector.

129. A display according to any of the preceding points, the controller being adapted to address respective addressed pixels as a function of the position of the viewer.

130. A display according to any of the preceding points, the thin film stack comprising a pair of terminals, one on each side of the thin film stack, for applying the voltage across the thin film stack.

131. A display as claimed in any one of the preceding points, the respective terminals having an area corresponding to the area of an image pixel.

132. A passive array display for controlling the directionality of an image of an observer viewing the display from an observer's point of view in front of the display, the display comprising:

a plurality of pixels comprising a first pixel constituting an image pixel, the plurality of pixels being arranged in a plane, each pixel defining a pixel area having a first plurality of sub-pixels comprising a first sub-pixel, each sub-pixel defining a direction from the display to a view point or an angle between a normal of the display and a view point,

a front optical device comprising a plurality of optical elements, wherein at least one optical element has an optical power and a first focus and a second focus, the first focus being located substantially at the plane, the second focus being between the front optical element and a point located in front of the front optical element and not distant from the front optical element,

-a thin film circuit comprising a plurality of pixels and being capable of receiving as inputs a plurality of scanning lines (row lines) and a plurality of data lines (column lines), wherein the thin film circuit is capable of receiving a set of gray signals on a first set of the plurality of data lines and a plurality of sub-pixel addressing signals on a second set of the plurality of data lines, wherein the thin film circuit is capable of illuminating a plurality of sub-pixels at positions according to the received sub-pixel addressing signals and illuminating the sub-pixels with light intensities according to corresponding gray signals in the set of received gray signals.

133. The display according to any of the foregoing points,

the received addressing signal comprises a single-heat-coded or multi-heat-coded binary signal for indicating a row or column of sub-pixels.

134. The display according to any of the foregoing points,

the binary signal is encoded by an analog voltage that is below a first voltage threshold or above a second voltage threshold.

135. The display according to any of the foregoing points,

the first voltage threshold is 20% of the maximum voltage and the second voltage threshold is 80% of the maximum voltage.

136. The display according to any of the foregoing points,

the plurality of data lines (column lines) are connected to active matrix column drivers (source driver/data driver).

137. A monoscopic display for displaying a picture and reducing power consumption while displaying the picture to a viewer, the monoscopic display comprising:

a plurality of image pixels arranged in a grid, each image pixel defining an area for emitting light from a portion of the area, and

each image pixel includes:

a thin film stack of an electroluminescent layer and a photo/diode layer, said electroluminescent layer and said photo/diode layer constituting an optical converter,

the monoscopic display comprises:

a plurality of addressing pixels including first addressing pixels and second addressing pixels for illuminating the thin film stack,

a controller for addressing the first addressed pixel and the second addressed pixel, for emitting light from the first addressed pixel and the second addressed pixel,

The first addressed pixel defines a first direction from the corresponding image pixel towards the viewer,

the second addressed pixel defining a second direction to be viewed from the corresponding image pixel, the first direction being different from the second direction,

light from the first addressed pixel has a higher intensity than light from the second addressed pixel.

Claims

the plurality of pixel circuits includes:

4. A display according to any of the preceding points, each sub-pixel group having a first number of sub-pixels, such as sub-pixel rows, oriented substantially horizontally and a second number of sub-pixels, such as sub-pixel columns, oriented substantially vertically.

5. A display as claimed in any one of the preceding points, the number of control circuits being equal to the sum of the first number of sub-pixels and the second number of sub-pixels.

6. A display according to any of the preceding points, the plurality of image pixels comprising a first image pixel comprising a first group of sub-pixels comprising a first sub-pixel.

7. A display according to any of the preceding points, the first sub-pixel group comprising a second sub-pixel.

8. The display of any of the foregoing points, the first subpixel defining a first direction or first angle relative to the viewer's point of view,

9. A display according to any of the preceding points, the plurality of image pixels comprising second image pixels comprising a second group of sub-pixels comprising a third sub-pixel.

10. A display according to any of the preceding points, the first and third sub-pixels being preferably addressed by a common or identical address control signal such that light emitted or propagating from the first and second sub-pixels is visible from the viewer point of view.

11. A display according to any of the preceding points, the third sub-pixel defining a third direction or second angle relative to the viewer's point of view.

12. A display according to any of the preceding points, the first angle or direction being substantially the same as the third angle or direction or differing from the third angle or direction by less than 10%, such as by 5%.

13. A display according to any of the preceding points, the display comprising a control system for controlling the light intensity and angle or direction of light emitted or propagated from the plurality of pixels such that light emitted or propagated from the plurality of pixels is visible from the viewer point of view.

14. A display according to any of the preceding points, the electrode wire comprising:

a plurality of data lines for transmitting the luminance values,

a plurality of address lines for transmitting the address signals,

15. A display as claimed in any one of the preceding points, the plurality of scan lines de-multiplexing the luminance values.