CN116507120A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN116507120A
CN116507120A CN202310538883.0A CN202310538883A CN116507120A CN 116507120 A CN116507120 A CN 116507120A CN 202310538883 A CN202310538883 A CN 202310538883A CN 116507120 A CN116507120 A CN 116507120A
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China
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layer
electrode
initial
dielectric layer
sacrificial layer
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肖凡
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310538883.0A priority Critical patent/CN116507120A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises the following steps: providing a substrate; forming a first laminated layer on the substrate, wherein the first laminated layer comprises a plurality of first electrode columns, a first sacrificial layer and a first supporting layer, each first electrode column extends along the thickness direction of the substrate, the first sacrificial layer fills gaps between adjacent first electrode columns, the first supporting layer covers the top surface of the first sacrificial layer, and the top surface of the first supporting layer is not higher than the top surface of the first electrode column; and forming a second lamination layer on the first lamination layer, wherein the second lamination layer comprises a plurality of second electrode columns, a second sacrificial layer and a second supporting layer, each second electrode column extends along the thickness direction of the substrate, the bottom surface of each second electrode column is contacted with the top surface of one first electrode column, the second sacrificial layer fills a gap between adjacent second electrode columns, and the second supporting layer covers the top surface of the second sacrificial layer, so that the stability of the semiconductor structure is at least improved.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
Embodiments of the present disclosure relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
The memory is a memory means for storing programs and various data information. Random Access Memory (Random Access Memory, RAM) used in a typical computer system can be divided into dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) and Static Random Access Memory (SRAM), which are semiconductor Memory devices commonly used in computers and are composed of a plurality of repeated Memory cells.
The memory cell generally includes a capacitor and a transistor, both of a source and a drain of the transistor are connected to a bit line structure, and the other two of the source and the drain are connected to the capacitor, the capacitor includes a capacitor contact structure and a capacitor, and a word line structure of the memory cell can control the opening or closing of a channel region of the transistor, thereby reading data information stored in the capacitor through the bit line structure, or writing the data information into the capacitor through the bit line structure for storage.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the stability of the semiconductor structure.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a semiconductor structure, including: providing a substrate; forming a first laminated layer on the substrate, wherein the first laminated layer comprises a plurality of first electrode columns, a first sacrificial layer and a first supporting layer, each first electrode column extends along the thickness direction of the substrate, the first sacrificial layer fills gaps between adjacent first electrode columns, the first supporting layer covers the top surface of the first sacrificial layer, and the top surface of the first supporting layer is not higher than the top surface of the first electrode column; and forming a second lamination layer on the first lamination layer, wherein the second lamination layer comprises a plurality of second electrode columns, a second sacrificial layer and a second supporting layer, each second electrode column extends along the thickness direction of the substrate, the bottom surface of each second electrode column is contacted with the top surface of one first electrode column, the second sacrificial layer fills a gap between every two adjacent second electrode columns, and the second supporting layer covers the top surface of the second sacrificial layer.
In some embodiments, forming a first stack on a substrate includes: forming an initial first electrode layer, wherein the initial first electrode layer covers the surface of the substrate; patterning the initial first electrode layer to form a plurality of first electrode columns arranged at intervals in an array; filling an initial first sacrificial layer in the gap between the first electrode columns, wherein the top surface of the initial first sacrificial layer is higher than the top surface of the first electrode columns; removing part of the initial first sacrificial layer to form a first sacrificial layer, and forming a spacing groove between the top surface of the first sacrificial layer and the side wall of the first electrode column; a first support layer is formed in the spacer grooves.
In some embodiments, forming a second stack over the first stack includes: forming an initial second sacrificial layer, wherein the initial second sacrificial layer covers the top surface of the first laminated layer; forming an initial second supporting layer, wherein the initial second supporting layer covers the surface of the initial second sacrificial layer; patterning an initial second sacrificial layer and an initial second supporting layer, forming a plurality of second electrode holes by taking the top surface of the first electrode column as an etching stop layer, taking the rest of the initial second sacrificial layer as a sacrificial layer and taking the rest of the initial second supporting layer as a supporting layer; the second electrode hole is filled to form a second electrode column.
In some embodiments, forming the second electrode hole includes: patterning the initial second sacrificial layer and the initial second supporting layer to obtain an initial second electrode hole, wherein the orthographic projection of the initial second electrode hole on the surface of the substrate coincides with the orthographic projection of the first electrode column on the surface of the substrate; and (3) horizontally etching the initial second sacrificial layer and the initial first supporting layer to obtain a second electrode hole, wherein the orthographic projection area of the second electrode hole on the surface of the substrate is larger than that of the first electrode column on the surface of the substrate.
In some embodiments, after forming the first electrode column, further comprising: forming a first dielectric layer, wherein the first dielectric layer covers the side wall of the first electrode column; after forming the second electrode hole, before forming the second electrode post, further comprising: and forming a second dielectric layer, wherein the second dielectric layer covers the inner side wall of the second electrode hole, the second dielectric layer is in contact with the first dielectric layer, and the thickness of the second dielectric layer is larger than that of the first dielectric layer.
In some embodiments, after forming the second stack, further comprising: removing part of the first supporting layer and part of the second supporting layer, and removing the first sacrificial layer and the second sacrificial layer by adopting a first etching environment, wherein the etching rate of the first sacrificial layer is larger than that of the first dielectric layer under the first etching environment, and the etching rate of the second sacrificial layer is larger than that of the second dielectric layer; and forming an upper electrode layer, wherein the upper electrode layer covers the side surface of the first dielectric layer, which is far away from the first electrode column, and the side surface of the second dielectric layer, which is far away from the second electrode column.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including: a substrate; the first electrode columns are positioned on the substrate, each first electrode column extends along the thickness direction of the substrate, the first support layer is positioned between the tops of the adjacent first electrode columns, and the top surface of the first support layer is not higher than the top surface of the first electrode column; the second electrode columns extend along the thickness direction of the substrate, the bottom surface of each second electrode column is contacted with the top surface of one first electrode column, and the second support layer is positioned between the tops of the adjacent second electrode columns.
In some embodiments, the material of the first electrode column is the same as the material of the second electrode column.
In some embodiments, the second electrode column has a dimension that is greater than the dimension of the first electrode column in a direction parallel to the substrate surface.
In some embodiments, the semiconductor structure further comprises: the first dielectric layer covers the side wall of the first electrode column; the second dielectric layer covers the side wall of the second electrode column and is in contact with the first dielectric layer, and the thickness of the second dielectric layer is larger than that of the first dielectric layer; and the upper electrode layer covers the side surface of the first dielectric layer, which is far away from the first electrode column, and the side surface of the second dielectric layer, which is far away from the second electrode column.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
according to the manufacturing method of the semiconductor structure, the first lamination and the second lamination are formed in the lamination mode, the first electrode column in the first lamination and the second electrode column in the second lamination can be used as the lower electrode layer of the capacitor structure together, so that the capacitor structure with a larger depth-to-width ratio can be formed by stacking, a capacitor hole with an excessively large depth-to-width ratio is not required to be formed in a one-step process, the problem of etching offset is avoided, the manufacturing accuracy of the capacitor structure is improved, and the stability of the semiconductor structure is further improved. In addition, a first supporting layer is arranged between the tops of the first electrode columns, a second supporting layer is arranged between the tops of the second electrode columns, and the first supporting layer and the second supporting layer can be used as supporting structures to avoid collapse of the first electrode columns and the second electrode columns in the process of subsequently removing the first sacrificial layer and the second sacrificial layer, so that the stability of the semiconductor structure is improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 to 22 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
When forming a capacitor structure in a related process, a capacitor hole with a larger depth-to-width ratio is usually formed in the sacrificial layer, and then the capacitor hole is filled to form a lower electrode layer of the capacitor structure; and removing the sacrificial layer, forming a capacitance dielectric layer and an upper electrode layer covering the surface of the capacitance dielectric layer on the surface of the lower electrode layer, wherein the lower electrode layer, the capacitance dielectric layer and the upper electrode layer jointly form a capacitance structure. With the increasing integration level of semiconductor devices, the capacitor structure needs to have a larger depth-to-width ratio to have a higher charge storage capability, and the capacitor hole with a high depth-to-width ratio is always a very large challenge for an etching process, so that a capacitor hole offset problem usually exists when the etched capacitor hole with a high depth-to-width ratio is formed, so that a lower electrode layer formed in the capacitor hole cannot be normally connected with a corresponding contact structure, a memory unit cannot be formed with a corresponding transistor structure, and after the sacrificial layer is removed, the lower electrode layer with a high depth-to-width ratio is easy to collapse.
According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which is at least beneficial to improving the stability of the semiconductor structure.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 1 to 22 are schematic structural views corresponding to respective steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, and the method for manufacturing a semiconductor structure according to the embodiment will be described in detail with reference to the accompanying drawings, specifically as follows:
referring to fig. 1 to 22, a method of manufacturing a semiconductor structure includes:
referring to fig. 1, a substrate 100 is provided.
In some embodiments, the substrate 100 may include: a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the base semiconductor includes silicon, germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or a group III-V semiconductor material, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and/or aluminum gallium arsenide, etc. In some embodiments, the substrate 100 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.
Referring to fig. 2, a first stack 110 is formed on a substrate 100, the first stack 110 includes a plurality of first electrode pillars 111, a first sacrificial layer 112, and a first supporting layer 113, each first electrode pillar 111 extends along a thickness direction of the substrate 100, the first sacrificial layer 112 fills a gap between adjacent first electrode pillars 111, the first supporting layer 113 covers a top surface of the first sacrificial layer 112, and a top surface of the first supporting layer 113 is not higher than a top surface of the first electrode pillar 111. In this way, the top surface of the first electrode column 111 can be used as a reference in the subsequent process, so as to improve the alignment accuracy of the second electrode column and the first electrode column 111 formed later.
In fig. 2, the top surface of the first support layer 113 is flush with the top surface of the first electrode column 111. In some embodiments, the top surface of the first support layer may also be lower than the top surface of the first electrode pillar.
In some embodiments, the material forming the first sacrificial layer 112 includes a material with a relatively large etching selectivity, such as silicon oxide, so as to be easily removed in a subsequent process.
In some embodiments, a transistor, a word line, and a bit line may be disposed within the substrate, a gate of the transistor is electrically connected to the word line, one of a source or a drain of the transistor is electrically connected to the bit line, and the other of the source or the drain of the transistor is electrically connected to a contact structure for electrical connection with the first electrode pillar. Thus, the transistor can be electrically connected with the corresponding capacitor structure of the first electrode column through the contact structure, the transistor and the corresponding capacitor structure form a memory cell, and the corresponding word line and bit line can realize the memory or the reading of the memory cell.
In some embodiments, forming the first stack 110 on the substrate 100 includes: referring to fig. 3, an initial first electrode layer (not shown) is formed to cover the surface of the substrate 100; the initial first electrode layer is patterned to form a plurality of first electrode columns 111 arranged in an array at intervals. Referring to fig. 4, an initial first sacrificial layer (not shown) is filled in the gaps between the first electrode posts 111, and a top surface of the initial first sacrificial layer is higher than a top surface of the first electrode posts 111; a portion of the initial first sacrificial layer is removed to form a first sacrificial layer 112, and a spacer 213 is formed between the top surface of the first sacrificial layer 112 and the sidewall of the first electrode column 111. Referring back to fig. 2, the first support layer 113 is formed in the spacing groove 213.
In some embodiments, forming the first stack 110 on the substrate 100 includes: referring to fig. 5, an initial first sacrificial layer (not shown) is formed to cover the surface of the substrate 100; forming an initial first support layer (not shown in the drawings) covering a surface of the initial first sacrificial layer; the initial first sacrificial layer and the initial first support layer are patterned to form a plurality of first electrode holes 211, the remaining initial first sacrificial layer being the first sacrificial layer 112, and the remaining initial first support layer being the first support layer 113. Referring back to fig. 2, the first electrode hole 211 is filled to form the first electrode column 111.
In some embodiments, forming the first stack 110 on the substrate 100 includes: referring to fig. 6, an initial first sacrificial layer 212 is formed, the initial first sacrificial layer 212 covering the surface of the substrate 100; patterning the initial first sacrificial layer 212 to form a plurality of first electrode holes 211; the first electrode hole 211 is filled to form the first electrode column 111. Referring back to fig. 4, a portion of the initial first sacrificial layer 212 is removed, and the remaining initial first sacrificial layer 212 serves as the first sacrificial layer 112, and a spacer 213 is formed between the top surface of the first sacrificial layer 112 and the sidewall of the first electrode column 111. Referring back to fig. 2, the spacer grooves 213 are filled to form the first support layer 113.
Referring to fig. 7, a second stack 120 is formed on the first stack 110, the second stack 120 includes a plurality of second electrode pillars 121, a second sacrificial layer 122, and a second supporting layer 123, each second electrode pillar 121 extends along a thickness direction of the substrate 100, a bottom surface of each second electrode pillar 121 contacts a top surface of a first electrode pillar 111, the second sacrificial layer 122 fills a gap between adjacent second electrode pillars 121, and the second supporting layer 123 covers the top surface of the second sacrificial layer 122.
The first electrode column 111 in the first stack layer 110 and the second electrode column 121 in the second stack layer 120 can be used together as a lower electrode layer of the capacitor structure, and the capacitor structure with a larger aspect ratio can be formed by stacking in a manner of forming the second stack layer 120 on the first stack layer 110 without forming a capacitor hole with an excessively large aspect ratio in a one-step process, so that the problem of etching offset is avoided, the manufacturing accuracy of the capacitor structure is improved, and the stability of the semiconductor structure is further improved. In addition, the first supporting layer 113 is disposed between the top portions of the first electrode columns 111, the second supporting layer 123 is disposed between the top portions of the second electrode columns 121, and in the subsequent process of removing the first sacrificial layer 112 and the second sacrificial layer 122, the first supporting layer 113 and the second supporting layer 123 can serve as supporting structures to avoid collapse of the first electrode columns 111 and the second electrode columns 121, so that stability of the semiconductor structure is improved.
In fig. 7, the top surface of the second support layer 123 is flush with the top surface of the second electrode pillar 121. In some embodiments, the top surface of the second support layer may also be lower than the top surface of the second electrode pillar. It will be appreciated that stacking may also continue on the surface of the second stack 120 to form a third stack, a fourth stack … …, etc. The top surface of the second supporting layer 123 is not higher than the top surface of the second electrode pillar 121, which is beneficial to taking the top surface of the second electrode pillar 121 as a reference in the subsequent process, and improving the alignment accuracy of the subsequently formed third electrode pillar and the second electrode pillar 121. Similarly, the effect described above can be applied to the subsequent stacked layers, where the support layer is not higher than the top surface of the electrode column.
In some embodiments, forming the second stack 120 on the first stack 110 includes: referring to fig. 8, an initial second sacrificial layer (not shown) is formed, which covers the top surface of the first stack 110; forming an initial second support layer (not shown in the drawings) covering the surface of the initial second sacrificial layer; the initial second sacrificial layer and the initial second support layer are patterned, and a plurality of second electrode holes 221 are formed with the top surface of the first electrode column 111 as an etching stop layer, the remaining initial second sacrificial layer is used as the second sacrificial layer 122, and the remaining initial second support layer is used as the second support layer 123. Referring back to fig. 7, the second electrode hole 221 is filled to form a second electrode pillar 121.
In some embodiments, forming the second stack 120 on the first stack 110 includes: referring to fig. 9, an initial second sacrificial layer 222 is formed, the initial second sacrificial layer 222 covering the surface of the first stack 110; patterning the initial second sacrificial layer 222 to form a plurality of second electrode holes 221; the second electrode hole 221 is filled to form a second electrode pillar 121. Referring to fig. 10, a portion of the initial second sacrificial layer 222 is removed, the remaining initial second sacrificial layer 222 serves as the second sacrificial layer 122, and isolation grooves 323 are formed between the top surface of the second sacrificial layer 122 and the sidewalls of the second electrode pillars 121. Referring back to fig. 7, the isolation trench 323 is filled to form the second support layer 123.
In some embodiments, the orthographic projection area of the second electrode hole 221 on the surface of the substrate 100 is larger than the orthographic projection area of the first electrode pillar 111 on the surface of the substrate 100. In this way, the second electrode hole 221 may have a larger etching window, which is more beneficial to the alignment of the second electrode hole 221 with the first electrode pillar 111, i.e. to the alignment of the second electrode pillar 121 with the first electrode pillar 111, so that the first electrode pillar 111 and the second electrode pillar 121 can be fully electrically contacted.
In some embodiments, the second electrode hole 221 may be directly formed on the surface of the substrate 100 with a larger orthographic projection area than the orthographic projection area of the first electrode post 111 on the surface of the substrate 100.
In some embodiments, forming the second electrode hole 221 may include: referring to fig. 11, after the initial second sacrificial layer 222 and the initial second support layer 223 are formed, the initial second sacrificial layer 222 and the initial second support layer 223 are patterned to obtain an initial second electrode hole 321, and an orthographic projection of the initial second electrode hole 321 on the surface of the substrate 100 coincides with an orthographic projection of the first electrode post 111 on the surface of the substrate 100. Referring back to fig. 8, the initial second sacrificial layer 222 and the initial second support layer 223 are laterally etched to obtain a second electrode hole 221, the orthographic projection area of the second electrode hole 221 on the surface of the substrate 100 is larger than the orthographic projection area of the first electrode post 111 on the surface of the substrate 100, the remaining initial second sacrificial layer 222 serves as the second sacrificial layer 122, and the remaining initial second support layer 223 serves as the second support layer 123.
That is, when forming the second electrode hole 221, the initial second electrode hole 321 is formed, and then the initial second electrode hole 321 is laterally etched to form the second electrode hole 221 with a larger size, where the size of the initial second electrode hole 321 corresponds to the size of the first electrode pillar 111, the mask used in forming the initial second electrode hole 321 may be the same as the mask used in forming the first electrode pillar 111, so that the number of masks may be reduced, and the manufacturing cost of the semiconductor structure may be reduced.
In some embodiments, after forming the first electrode column 111, further comprising: referring to fig. 12, a first dielectric layer 114 is formed, the first dielectric layer 114 covering sidewalls of the first electrode column 111. Referring to fig. 13, a first sacrificial layer 112 is formed, the first sacrificial layer 112 being located on a surface of the first dielectric layer 114 and filling gaps between the first electrode pillars 111; a first support layer 113 is formed on top of the first sacrificial layer 112. Referring to fig. 14, an initial second sacrificial layer (not shown) is formed, which covers the top surface of the first stack 110; forming an initial second support layer (not shown in the drawings) covering the surface of the initial second sacrificial layer; patterning the initial second sacrificial layer and the initial second supporting layer, and forming a plurality of second electrode holes 221 by using the top surface of the first electrode column 111 as an etching stop layer, wherein the orthographic projection area of the second electrode holes 221 on the surface of the substrate 100 is larger than the orthographic projection area of the first electrode column 111 and the first dielectric layer 144 on the side wall thereof on the surface of the substrate 100, the remaining initial second sacrificial layer is used as the second sacrificial layer 122, and the remaining initial second supporting layer is used as the second supporting layer 123. Referring to fig. 15, a second dielectric layer 214 is formed, the second dielectric layer 214 covers the inner sidewall of the second electrode hole 221, the second dielectric layer 214 contacts the first dielectric layer 114, and the thickness of the second dielectric layer 214 is greater than the thickness of the first dielectric layer 114 in a direction parallel to the surface of the substrate 100; the remaining second electrode holes 221 are filled to form second electrode pillars 121.
Accordingly, the first dielectric layer 114 and the second dielectric layer 214 cover the surfaces of the first electrode column 111 and the second electrode column 121, and the first electrode column 111 is connected with the second electrode column 121, and the first dielectric layer 114 is connected with the second dielectric layer 124, so that the first electrode column 111 and the second electrode column 121 can jointly form a lower electrode layer of the capacitor structure, the first dielectric layer 114 and the second dielectric layer 124 can jointly serve as a capacitor dielectric layer of the capacitor structure, the first sacrificial layer 112 and the second sacrificial layer 122 can be directly removed in the subsequent process, and then an upper electrode layer covering the first dielectric layer 114 and the second dielectric layer 124 can be formed.
In addition, the thickness of the second dielectric layer 214 is greater than that of the first dielectric layer 114, so that the contact stability between the second dielectric layer 214 and the first dielectric layer 114 can be improved, and the short circuit of the capacitor structure caused by poor contact between the first dielectric layer 114 and the second dielectric layer 214 is avoided.
In the direction parallel to the surface of the substrate 100, the size of the second electrode hole 221 is greater than or equal to the sum of the sizes of the first dielectric layer 114 on the first electrode pillar 111 and the sidewall thereof, so that the second dielectric layer 214 can be thicker and can be fully connected with the first dielectric layer 114, and meanwhile, the second electrode pillar 121 is kept to have a larger size so as to have higher charge storage capacity.
In some embodiments, the size of the second electrode pillar 121 may be smaller than or equal to the size of the first electrode pillar 111 in a direction parallel to the surface of the substrate 100. It will be appreciated that, in order to satisfy that the second dielectric layer 214 can be sufficiently connected to the first dielectric layer 114, the thickness of the second dielectric layer 214 needs to be greater than that of the first dielectric layer 114, and then the size of the remaining second electrode hole 221 is the size of the second electrode pillar 121, and the size of the remaining second electrode hole 221 may be less than or equal to that of the first electrode pillar 111, and the size of the corresponding second electrode pillar 121 may be less than or equal to that of the first electrode pillar 111.
In some embodiments, the second electrode post may have a dimension greater than the dimension of the first electrode post in a direction parallel to the substrate surface.
In some embodiments, the dielectric constant of the second dielectric layer 214 may be greater than or equal to the dielectric constant of the first dielectric layer 114. Thus, the capacitance corresponding to the second electrode pillar 121 can have higher charge storage capacity.
It can be appreciated that, if the size of the remaining second electrode hole 221 is smaller than or equal to the size of the first electrode pillar 111 after the second dielectric layer 214 is formed, the size of the corresponding second electrode pillar 121 is smaller than or equal to the size of the first electrode pillar 111, and the dielectric constant of the second dielectric layer 214 is larger than or equal to the dielectric constant of the first dielectric layer 114, which is beneficial for the corresponding capacitance of the second electrode pillar 121 to have sufficient charge storage capability.
In some embodiments, if the first electrode pillar is formed by forming the first electrode hole and refilling the first electrode hole, the first dielectric layer may be formed on the inner sidewall of the first electrode hole, and then the remaining first electrode hole may be filled to form the first electrode pillar.
In some embodiments, forming the second stack 120 on the first stack 110 includes: referring to fig. 16, an initial second electrode layer (not shown) is formed, the initial second electrode layer covering the surface of the first stack 110; the initial second electrode layer is patterned to form a plurality of second electrode columns 121 arranged in an array at intervals. Referring back to fig. 10, an initial second sacrificial layer (not shown in the drawings) is filled in the gaps between the second electrode posts 121, and the top surface of the initial second sacrificial layer is higher than the top surface of the second electrode posts 121; part of the initial second sacrificial layer is removed to form a second sacrificial layer 122, and an isolation groove 323 is formed between the top surface of the second sacrificial layer 122 and the side wall of the second electrode column. Referring back to fig. 7, the first support layer 123 is formed in the isolation groove 323.
In some embodiments, referring to fig. 7, the second electrode pillar 121 has a size larger than that of the first electrode pillar 111 in a direction parallel to the surface of the substrate 100. In this way, the alignment of the second electrode pillar 121 and the first electrode pillar 111 is more facilitated, so that the first electrode pillar 111 and the second electrode pillar 121 can be electrically contacted, so that the first electrode pillar 111 and the second electrode pillar 121 form a whole to be used as a lower electrode layer of the capacitor structure, and the larger size of the second electrode pillar 121 can be beneficial to improving the charge storage capacity of the capacitor structure.
Further, in some embodiments, referring to fig. 17, as before forming the second electrode pillar 121, the sidewall of the first electrode pillar 111 is covered with the first dielectric layer 114, and the difference between the size of the second electrode pillar 121 and the size of the first electrode pillar 111 may be smaller than the thickness of the first dielectric layer 114 on the surface parallel to the substrate 100. It will be appreciated that a larger size of the second electrode pillar 121 may be advantageous for improving the charge storage capacity of the capacitor, but the second electrode pillar 121 needs to expose the first dielectric layer 114 so that the second dielectric layer 124 formed later can be connected to the first dielectric layer 114 to form a complete capacitor dielectric layer.
In some embodiments, when the surface of the first electrode pillar 111 has the first dielectric layer 114 and the surface of the second electrode pillar 121 has the second dielectric layer 124, after forming the second stack 120, further includes: referring to fig. 18, a portion of the first support layer 113 and a portion of the second support layer 123 are removed, and the first sacrificial layer 112 and the second sacrificial layer 122 are removed using a first etching environment, wherein in the first etching environment, an etching rate of the first sacrificial layer 112 is greater than an etching rate of the first dielectric layer 114, and an etching rate of the second sacrificial layer 122 is greater than an etching rate of the second dielectric layer 124. Referring to fig. 19, an upper electrode layer 130 is formed, the upper electrode layer 130 covering a side surface of the first dielectric layer 114 remote from the first electrode post 111 and a side surface of the second dielectric layer 124 remote from the second electrode post 121.
It will be appreciated that in the process of removing the first sacrificial layer 112 and the second sacrificial layer 122, damage to the first dielectric layer 114 and the second dielectric layer 124 needs to be avoided, so as to avoid damage to the capacitor dielectric layer and further avoid affecting the performance of the capacitor structure, so that the etching selectivity of the first etching environment to the first sacrificial layer 112 is required to be greater than that to the first dielectric layer 114, and meanwhile, the etching selectivity to the second sacrificial layer 122 is required to be greater than that to the second dielectric layer 124.
It is understood that referring to fig. 19, the upper electrode layer 130 may also cover a portion of the surface of the substrate 100. Thus, the plurality of capacitor structures may share the same upper electrode layer 130.
In some embodiments, the first etching environment may employ nitric acid, ammonium fluoride, hydrofluoric acid, ethylenediamine, sodium carbonate, or the like as the etching liquid.
Further, in some embodiments, before forming the upper electrode layer 130, further includes: referring to fig. 20, a third dielectric layer 134 is formed, the third dielectric layer 134 covering the top surface of the second electrode pillar 121 and interfacing with the second dielectric layer 124. The first dielectric layer 114, the second dielectric layer 124 and the third dielectric layer 134 form a complete capacitor dielectric layer, the first electrode column 111 and the second electrode column 121 form a complete lower electrode layer, and the subsequently formed upper electrode layer 130 may directly form a complete capacitor structure with the capacitor dielectric layer and the lower electrode layer.
In some embodiments, after the second stack layer is formed, a third dielectric layer and a supplemental upper electrode layer may be formed on the top surface of the second electrode pillar to form a complete capacitor structure.
In some embodiments, if the first dielectric layer 114 is not formed on the sidewall of the first electrode pillar 111 and the second dielectric layer 124 is not formed on the sidewall of the second electrode pillar 121 in the process of forming the first stack 110 and the second stack 120, after forming the second stack 120, the method includes: referring to fig. 21, a portion of the first support layer 113 and a portion of the second support layer 123 are removed, and the first sacrificial layer 112 and the second sacrificial layer 122 are removed using a second etching environment, wherein the etching rate of the first sacrificial layer 112 is greater than the etching rate of the first electrode post 111 and the etching rate of the second sacrificial layer 122 is greater than the etching rate of the second electrode post 121 in the second etching environment. Referring to fig. 22, a capacitance dielectric layer 140 is formed, the capacitance dielectric layer 140 covering the surface of the first electrode column 111 and the surface of the second electrode column 121; an upper electrode layer 130 is formed, and the upper electrode layer 130 covers the surface of the capacitive dielectric layer 140.
It can be appreciated that in the process of removing the first sacrificial layer 112 and the second sacrificial layer 122, damage to the first electrode pillar 111 and the second electrode pillar 121 needs to be avoided, so as to avoid damage to the lower electrode layer of the capacitor structure, and further avoid influencing the performance of the capacitor structure, so that the etching selectivity of the second etching environment to the first sacrificial layer 112 needs to be greater than that to the first electrode pillar 111, and meanwhile, the etching selectivity to the second sacrificial layer 122 needs to be greater than that to the second electrode pillar 121.
Referring to fig. 18, the capacitor dielectric layer 140 may be formed to cover a portion of the surface of the substrate 100 and a portion of the surfaces of the first support layer 113 and the second support layer 123. Further, referring to fig. 19, the upper electrode layer 130 may also be formed to cover the surface of the capacitive dielectric layer 140 away from the substrate 100 and the surface of the capacitive dielectric layer 140 away from the first and second support layers 113 and 123. Thus, the capacitor structures can share the same capacitor dielectric layer 140 and the upper electrode layer 130.
In some embodiments, the second etching environment may employ nitric acid, ammonium fluoride, hydrofluoric acid, ethylenediamine, sodium carbonate, or the like as the etching liquid.
In some embodiments, the material forming the capacitive dielectric layer 140 includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or combinations thereof.
In some embodiments, the material forming the upper electrode layer 130 includes at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.
According to the manufacturing method of the semiconductor structure, the first lamination layer 110 and the second lamination layer 120 are formed in a lamination mode, the first electrode column 111 in the first lamination layer 110 and the second electrode column 121 in the second lamination layer 120 can be used as the lower electrode layer of the capacitor structure together, so that the capacitor structure with a larger depth-to-width ratio can be formed by stacking, a capacitor hole with an excessively large depth-to-width ratio is not required to be formed in one step of process, the problem of etching offset is avoided, the manufacturing accuracy of the capacitor structure is improved, and the stability of the semiconductor structure is further improved. In addition, the first supporting layer 113 is disposed between the top portions of the first electrode columns 111, the second supporting layer 123 is disposed between the top portions of the second electrode columns 121, and in the subsequent process of removing the first sacrificial layer 112 and the second sacrificial layer 122, the first supporting layer 113 and the second supporting layer 123 can serve as supporting structures to avoid collapse of the first electrode columns 111 and the second electrode columns 121, so that stability of the semiconductor structure is improved.
According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a semiconductor structure that may be formed using the method for manufacturing a semiconductor structure described above, so as to improve the performance of the semiconductor structure. It should be noted that, in the same or corresponding parts as those of the above embodiments, reference may be made to the corresponding descriptions of the above embodiments, and detailed descriptions thereof will be omitted.
The following will describe the semiconductor structure provided in this embodiment in detail with reference to the accompanying drawings, and specifically includes:
referring to fig. 21, a semiconductor structure comprising: a substrate 100; a plurality of first electrode pillars 111 on the substrate 100, and a first support layer 113, each first electrode pillar 111 extending along a thickness direction of the substrate 100, the first support layer 113 being located between tops of adjacent first electrode pillars 111, wherein a top surface of the first support layer 113 is not higher than a top surface of the first electrode pillar 111; the second electrode pillars 121 and the second supporting layer 123 extend along the thickness direction of the substrate 100, the bottom surface of each second electrode pillar 121 contacts with the top surface of one first electrode pillar 111, and the second supporting layer 123 is located between the tops of the adjacent second electrode pillars 121.
In some embodiments, the material of the first electrode column 111 and the material of the second electrode column 121 may each include at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.
In some embodiments, the material of the first electrode column 111 and the material of the second electrode column 121 may be the same. In this way, the performance of the lower electrode layer of the capacitor structure formed by the first electrode column 111 and the second electrode column 121 is uniform, which is beneficial to improving the stability of the capacitor structure.
In some embodiments, the material of the first electrode column 111 may be different from the material of the second electrode column 121.
In some embodiments, the material of the first support layer 113 and the material of the second support layer 123 may each include silicon nitride, silicon carbide, silicon oxynitride, or the like.
In some embodiments, the material of the first support layer 113 and the material of the second support layer 123 may be the same. In this way, the first support layer 113 and the second support layer 123 may have the same etching selectivity under the same etching environment, so as to maintain good morphology of both the first support layer 113 and the second support layer 123 under the etching environment to support the first electrode column 111 and the second electrode column 121.
In some embodiments, the material of the first support layer 113 and the material of the second support layer 123 may be different.
In some embodiments, the size of the second electrode post 121 is greater than the size of the first electrode post 111 in a direction parallel to the surface of the substrate 100. In this way, when the second electrode pillar 121 is formed, the second electrode pillar 121 is aligned with the first electrode pillar 111, so that the first electrode pillar 111 and the second electrode pillar 121 can be electrically contacted, so that the first electrode pillar 111 and the second electrode pillar 121 form a whole to be used as a lower electrode layer of the capacitor structure, and the larger size of the second electrode pillar 121 can be beneficial to improving the charge storage capacity of the capacitor structure.
In some embodiments, referring to fig. 19, the semiconductor structure further comprises: a first dielectric layer 114, the first dielectric layer 114 covering sidewalls of the first electrode column 111; the second dielectric layer 124, the second dielectric layer 124 covers the sidewall of the second electrode pillar 121 and contacts the first dielectric layer 114, the thickness of the second dielectric layer 124 is greater than the thickness of the first dielectric layer 114; and an upper electrode layer 130, the upper electrode layer 130 covering a side surface of the first dielectric layer 114 remote from the first electrode post 111 and a side surface of the second dielectric layer 124 remote from the second electrode post 121.
In some embodiments, referring to fig. 20, the semiconductor structure further comprises: and a third dielectric layer 134, wherein the third dielectric layer 134 covers the top surface of the second electrode pillar 121 and is connected to the second dielectric layer 124. The first dielectric layer 114, the second dielectric layer 124, and the third dielectric layer 134 form a complete capacitor dielectric layer, the first electrode column 111 and the second electrode column 121 form a complete lower electrode layer, and the upper electrode layer 130 may form a complete capacitor structure with the capacitor dielectric layer and the lower electrode layer.
In some embodiments, the material of the first dielectric layer 114 and the material of the second dielectric layer 124 each include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or combinations thereof.
In some embodiments, the material of the first dielectric layer 114 may be the same as the material of the second dielectric layer 124. Thus, the capacitance dielectric layers formed by the first dielectric layer 114 and the second dielectric layer 124 have uniform performance.
In some embodiments, the material of the first dielectric layer 114 may be different from the material of the second dielectric layer 124.
In the semiconductor structure provided in the embodiment of the present disclosure, the first electrode column 111 in the first stack layer 110 and the second electrode column 121 in the second stack layer 120 can be used together as the lower electrode layer of the capacitor structure, so that the capacitor structure with a larger aspect ratio is formed by stacking, and the capacitor hole with an excessively large aspect ratio is not required to be formed in a one-step process, thereby avoiding the problem of etching offset, improving the accuracy of manufacturing the capacitor structure, and further improving the stability of the semiconductor structure. In addition, the first support layer 113 is arranged between the tops of the first electrode columns 111, the second support layer 123 is arranged between the tops of the second electrode columns 121, and the first support layer 113 and the second support layer 123 can serve as support structures to prevent the first electrode columns 111 and the second electrode columns 121 from collapsing, so that the stability of the semiconductor structure is improved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first laminated layer on the substrate, wherein the first laminated layer comprises a plurality of first electrode columns, a first sacrificial layer and a first supporting layer, each first electrode column extends along the thickness direction of the substrate, the first sacrificial layer fills a gap between adjacent first electrode columns, the first supporting layer covers the top surface of the first sacrificial layer, and the top surface of the first supporting layer is not higher than the top surface of the first electrode column;
forming a second lamination layer on the first lamination layer, wherein the second lamination layer comprises a plurality of second electrode columns, a second sacrificial layer and a second supporting layer, each second electrode column extends along the thickness direction of the substrate, the bottom surface of each second electrode column is in contact with the top surface of one first electrode column, the second sacrificial layer fills a gap between every two adjacent second electrode columns, and the second supporting layer covers the top surface of the second sacrificial layer.
2. The method of manufacturing a semiconductor structure of claim 1, wherein forming a first stack on the substrate comprises:
forming an initial first electrode layer, wherein the initial first electrode layer covers the surface of the substrate;
patterning the initial first electrode layer to form a plurality of first electrode columns arranged at intervals in an array;
filling an initial first sacrificial layer in the gap between the first electrode columns, wherein the top surface of the initial first sacrificial layer is higher than the top surface of the first electrode columns;
removing part of the initial first sacrificial layer to form the first sacrificial layer, wherein a spacing groove is formed between the top surface of the first sacrificial layer and the side wall of the first electrode column;
the first support layer is formed in the spacer grooves.
3. The method of manufacturing a semiconductor structure of claim 2, wherein forming a second stack over the first stack comprises:
forming an initial second sacrificial layer, wherein the initial second sacrificial layer covers the top surface of the first laminated layer;
forming an initial second support layer, wherein the initial second support layer covers the surface of the initial second sacrificial layer;
patterning the initial second sacrificial layer and the initial second supporting layer, forming a plurality of second electrode holes by taking the top surface of the first electrode column as an etching stop layer, taking the rest of the initial second sacrificial layer as the sacrificial layer and taking the rest of the initial second supporting layer as the supporting layer;
and filling the second electrode hole to form the second electrode column.
4. The method of manufacturing a semiconductor structure according to claim 3, wherein forming the second electrode hole comprises:
patterning the initial second sacrificial layer and the initial second supporting layer to obtain an initial second electrode hole, wherein the orthographic projection of the initial second electrode hole on the surface of the substrate coincides with the orthographic projection of the first electrode column on the surface of the substrate;
and transversely etching part of the initial second sacrificial layer and the initial second supporting layer to obtain a second electrode hole, wherein the orthographic projection area of the second electrode hole on the surface of the substrate is larger than that of the first electrode column on the surface of the substrate.
5. The method of manufacturing a semiconductor structure according to claim 3, further comprising, after forming the first electrode pillar:
forming a first dielectric layer, wherein the first dielectric layer covers the side wall of the first electrode column;
after forming the second electrode hole, before forming the second electrode pillar, further comprising:
and forming a second dielectric layer, wherein the second dielectric layer covers the inner side wall of the second electrode hole, the second dielectric layer is in contact with the first dielectric layer, and the thickness of the second dielectric layer is larger than that of the first dielectric layer.
6. The method of manufacturing a semiconductor structure according to claim 5, further comprising, after forming the second stack:
removing part of the first supporting layer and part of the second supporting layer, and removing the first sacrificial layer and the second sacrificial layer by adopting a first etching environment, wherein the etching rate of the first sacrificial layer is greater than that of the first dielectric layer in the first etching environment, and the etching rate of the second sacrificial layer is greater than that of the second dielectric layer;
and forming an upper electrode layer, wherein the upper electrode layer covers the side surface of the first dielectric layer, which is far away from the first electrode column, and the side surface of the second dielectric layer, which is far away from the second electrode column.
7. A semiconductor structure, comprising:
a substrate;
a plurality of first electrode columns and a first supporting layer, wherein each first electrode column extends along the thickness direction of the substrate, the first supporting layer is positioned between the tops of the adjacent first electrode columns, and the top surface of the first supporting layer is not higher than the top surface of the first electrode column;
the substrate comprises a plurality of second electrode columns and a second supporting layer, wherein each second electrode column extends along the thickness direction of the substrate, the bottom surface of each second electrode column is contacted with the top surface of one first electrode column, and the second supporting layer is positioned between the tops of the adjacent second electrode columns.
8. The semiconductor structure of claim 7, wherein a material of the first electrode pillar is the same as a material of the second electrode pillar.
9. The semiconductor structure of claim 7, wherein a dimension of the second electrode pillar is greater than a dimension of the first electrode pillar in a direction parallel to the substrate surface.
10. The semiconductor structure of claim 7, wherein the semiconductor structure further comprises:
the first dielectric layer covers the side wall of the first electrode column;
the second dielectric layer covers the side wall of the second electrode column and is in contact with the first dielectric layer, and the thickness of the second dielectric layer is larger than that of the first dielectric layer;
and the upper electrode layer covers the side surface of the first dielectric layer, which is far away from the first electrode column, and the side surface of the second dielectric layer, which is far away from the second electrode column.
CN202310538883.0A 2023-05-11 2023-05-11 Semiconductor structure and manufacturing method thereof Pending CN116507120A (en)

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