CN116505940B - Low-noise PLL phase-locked loop circuit - Google Patents
Low-noise PLL phase-locked loop circuit Download PDFInfo
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- CN116505940B CN116505940B CN202310752363.XA CN202310752363A CN116505940B CN 116505940 B CN116505940 B CN 116505940B CN 202310752363 A CN202310752363 A CN 202310752363A CN 116505940 B CN116505940 B CN 116505940B
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 20
- 238000001514 detection method Methods 0.000 claims abstract description 11
- 230000005669 field effect Effects 0.000 claims description 69
- 238000005070 sampling Methods 0.000 claims description 58
- 239000003990 capacitor Substances 0.000 claims description 26
- 238000004458 analytical method Methods 0.000 claims description 10
- 238000007405 data analysis Methods 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention provides a low noise PLL phase-locked loop circuit, comprising: the phase frequency detection unit is used for comparing an input signal with a reference signal to generate an error signal; an adjustment signal generation unit configured to generate an adjustment signal based on the error signal; a correction signal generation unit configured to generate a correction signal based on the adjustment signal; and the loading unit is used for loading the adjustment signal and the correction signal to the input end of the generating device of the original signal corresponding to the input signal. The low-noise PLL phase-locked loop circuit of the invention effectively reduces the noise of the oscillation signal of the oscillation circuit and ensures the stability of the function of the oscillation signal in the circuit.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a low-noise PLL (phase locked loop) circuit.
Background
PLL phase locked loop circuits are used in many applications. For example: for clock retiming and recovery, can be used as a frequency synthesizer, a tunable oscillator, and the like. The shadow of the radio receiver and the test equipment can be found in many radio frequency devices. Depending on its implementation, it can serve near dc to GHz and higher frequencies, playing a number of critical roles in the circuit. Therefore, how to realize the low-noise operation of the PLL phase-locked loop circuit can ensure the low-noise characteristic of the oscillation signal of the oscillation circuit which is correspondingly adjusted, and can help ensure the stability of the function which is exerted in the circuit.
Disclosure of Invention
One of the purposes of the present invention is to provide a PLL phase-locked loop circuit with low noise, which effectively reduces the noise of the oscillating signal of the oscillating circuit, and ensures the stability of the function of the PLL phase-locked loop circuit in the circuit.
The embodiment of the invention provides a low-noise PLL phase-locked loop circuit, which comprises:
the phase frequency detection unit is used for comparing an input signal with a reference signal to generate an error signal;
an adjustment signal generation unit configured to generate an adjustment signal based on the error signal;
a correction signal generation unit configured to generate a correction signal based on the adjustment signal;
and the loading unit is used for loading the adjustment signal and the correction signal to the input end of the generating device of the original signal corresponding to the input signal.
Preferably, the phase frequency detection unit includes:
the signal input end of the first D-type trigger is connected with logic high voltage, and the clock control end of the first D-type trigger is connected with a reference signal;
the signal input end of the second D-type trigger is connected with logic high voltage, and the clock control end of the second D-type trigger is connected with an input signal;
the first input end of the logic AND gate circuit is connected with the output end of the first D-type trigger, the second input end of the logic AND gate circuit is connected with the output end of the D-type trigger, and the output ends of the logic AND gate circuit are respectively connected with the zero clearing ends of the first D-type trigger and the second D-type trigger;
wherein the output of the first D-type flip-flop and the output of the second D-type flip-flop together constitute an error signal.
Preferably, the input signal is taken from the output of the generating device via a frequency divider.
Preferably, the adjustment signal generating unit includes:
the control input end of the first switch circuit is connected with the output end of the first D-type trigger;
the control input end of the second switch circuit is connected with the output end of the second D-type trigger;
the source electrode of the first field effect tube is connected with the input end of the first switch circuit, and the drain electrode of the first field effect tube is connected with logic high voltage;
the drain electrode of the second field effect tube is connected with the input end of the second switch circuit, and the source electrode of the second field effect tube is grounded;
the drain electrode of the third field effect tube is connected with logic high voltage, and the grid electrode of the third field effect tube is connected with the grid electrode of the first field effect tube and the source electrode of the third field effect tube;
the source electrode of the fourth field effect tube is grounded, the drain electrode of the fourth field effect tube is connected with the source electrode of the third field effect tube, and the grid electrode of the fourth field effect tube is connected with the grid electrode of the second field effect tube;
the source electrode of the fifth field effect tube is grounded, and the grid electrode of the fifth field effect tube is connected with the grid electrode of the fourth field effect tube and is connected with the drain electrode of the fourth field effect tube;
the two ends of the current source are respectively connected with logic high voltage and the drain electrode of the fifth field effect transistor;
one end of the first capacitor is connected with logic high voltage;
one end of the inductor is connected with the first capacitor, and the other end of the inductor is respectively connected with the output ends of the first switch circuit and the second switch circuit;
one end of the second capacitor is connected with logic high voltage, and the other end of the second capacitor is connected with the output ends of the first switch circuit and the second switch circuit respectively;
the adjusting signal output end is connected with one end of the second capacitor, which is connected with the output ends of the first switch circuit and the second switch circuit.
Preferably, the first field effect transistor is a P-channel field effect transistor.
Preferably, the correction signal generation unit includes:
the adjusting signal sampling sub-units are used for respectively sampling the adjusting signals to obtain a plurality of sampling data;
a frequency detection subunit for detecting the frequency of the input signal;
a sampling control circuit for controlling the sampling frequency and the sampling timing of each adjustment signal sampling circuit based on the frequency of the input signal;
the data analysis subunit is used for analyzing the plurality of sampling data and generating a control signal;
and a correction signal generation subunit for generating a correction signal based on the control signal.
Preferably, the sampling control circuit controls the sampling frequency and the sampling timing of each adjustment signal sampling circuit based on the frequency of the input signal, and includes:
inquiring a preset sampling frequency comparison table based on the frequency of the input signal, and determining the sampling frequency;
acquiring a sampling time table associated with a sampling frequency;
based on the sample timing table, a sample timing is determined.
Preferably, the data analysis subunit analyzes the plurality of sampled data, generates a control signal, and performs the following operations:
constructing a control analysis parameter set based on the plurality of sampling data;
matching the control analysis parameter set with each standard parameter set in a preset control signal generation library, and extracting a control signal parameter set corresponding to the standard parameter set matched with the control analysis parameter set;
based on the set of control signal parameters, a control signal is generated.
Preferably, the loading unit includes:
a sixth field effect transistor, the grid electrode of which is connected with the output end of the correction signal generation subunit, and the drain electrode of which is connected with logic high voltage;
one end of the third capacitor is connected with the source electrode of the sixth field effect transistor, and the other end of the third capacitor is grounded; the generating device is connected in parallel with the third capacitor.
Preferably, the generating device includes: an oscillator.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of a low noise PLL circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a phase frequency detection unit according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an adjustment signal generating unit according to an embodiment of the invention;
fig. 4 is a schematic diagram of a loading unit according to an embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
An embodiment of the present invention provides a low noise PLL phase-locked loop circuit, as shown in fig. 1, including:
a phase frequency detection unit 1 for comparing an input signal with a reference signal to generate an error signal;
an adjustment signal generation unit 2 for generating an adjustment signal based on the error signal;
a correction signal generation unit 3 for generating a correction signal based on the adjustment signal;
and the loading unit 4 is used for loading the adjustment signal and the correction signal to the input end of the generating device of the original signal corresponding to the input signal.
According to the phase-locked loop circuit, sampling analysis is carried out on the adjusting signal generated by the adjusting signal generating unit of the phase-locked loop circuit, so that the adjusting signal is corrected, the adjusting speed of the output signal of the generating device is optimized, noise caused by adjustment is reduced, and the stability of the function of the generating device in the circuit is guaranteed.
To enable comparing an input signal with a reference signal, an error signal is generated, as shown in fig. 2, the phase frequency detection unit comprises:
a first D-type trigger D1, the signal input end of which is connected with the logic high voltage VDD, and the clock control end of which is connected with the reference signal f0;
a second D-type trigger D2, the signal input end of which is connected with the logic high voltage VDD, and the clock control end of which is connected with the input signal f1;
the logic AND circuit 10 has a first input end connected with the output end of the first D-type trigger D1, a second input end connected with the output end of the D-type trigger D2, and output ends respectively connected with the zero clearing ends of the first D-type trigger D1 and the second D-type trigger D2;
wherein the output of the first D-type flip-flop D1 and the output of the second D-type flip-flop D2 together constitute an error signal.
In order to achieve the acquisition of the input signal, the input signal is acquired from the output of the generating device by means of a frequency divider.
As shown in fig. 3, the adjustment signal generating unit includes:
a first switch circuit 11, the control input end of which is connected with the output end of a first D-type trigger D1; the first switch circuit 11 switches under the signal of the output end of the first D-type trigger D1 to realize whether the signal of the first switch circuit 11 is loaded to the adjustment signal output end;
a second switch circuit 12 having a control input connected to the output of the second D-type flip-flop D2; the second switch circuit 12 switches under the signal of the output end of the second D-type trigger D2 to realize whether the signal of the second switch circuit 12 is loaded to the adjustment signal output end;
the source electrode of the first field effect transistor M1 is connected with the input end of the first switch circuit 11, and the drain electrode of the first field effect transistor M1 is connected with the logic high voltage VDD; the first field effect transistor M1 and the like are all MOS transistors, wherein MOS is an abbreviation of MOSFET. MOSFET Metal-Oxide-semiconductor field effect transistor (MOSFET) is abbreviated as Metal-Oxide-Semiconductor Field-Effect Transistor.
The drain electrode of the second field effect transistor M2 is connected to the input end of the second switch circuit 12, and the source electrode of the second field effect transistor M2 is grounded;
the drain electrode of the third field effect tube M3 is connected with the logic high voltage VDD, and the grid electrode of the third field effect tube M3 is connected with the grid electrode of the first field effect tube M1 and the source electrode of the third field effect tube M1;
the source electrode of the fourth field effect tube M4 is grounded, the drain electrode of the fourth field effect tube M4 is connected with the source electrode of the third field effect tube M3, and the grid electrode of the fourth field effect tube M4 is connected with the grid electrode of the second field effect tube M2;
a source electrode of the fifth field effect tube M5 is grounded, and a grid electrode of the fifth field effect tube M5 is connected with a grid electrode of the fourth field effect tube M4 and is connected with a drain electrode of the fourth field effect tube M;
the two ends of the current source A1 are respectively connected with the logic high voltage VDD and the drain electrode of the fifth field effect transistor M5;
one end of the first capacitor C1 is connected with a logic high voltage VDD;
one end of the inductor L1 is connected with the first capacitor C1, and the other end of the inductor L is respectively connected with the output ends of the first switch circuit 11 and the second switch circuit 12; the first capacitor C1 and the first inductor L1 form an RC circuit;
one end of the second capacitor C2 is connected with the logic high voltage VDD, and the other end of the second capacitor C2 is respectively connected with the output ends of the first switch circuit 11 and the second switch circuit 12; the first capacitor C1, the second capacitor C2, and the inductor L1 form a filter circuit, and output currents of the first switch circuit 11 and the second switch circuit 12 are subjected to filter processing or the like to form an adjustment signal;
the adjustment signal output terminal is connected to one end of the second capacitor C2 connected to the output terminals of the first switch circuit 11 and the second switch circuit 12.
The first field effect transistor is a P-channel field effect transistor.
Wherein the correction signal generation unit includes:
the adjusting signal sampling sub-units are used for respectively sampling the adjusting signals to obtain a plurality of sampling data; the main function of the adjusting signal sampling subunit is to sample and analog-to-digital convert the adjusting signal;
a frequency detection subunit for detecting the frequency of the input signal;
a sampling control circuit for controlling the sampling frequency and the sampling timing of each adjustment signal sampling circuit based on the frequency of the input signal; according to the frequency of the input signal, the sampling frequency and the sampling time are adjusted, so that the sampling data can be used for correction and determination, and the correction is accurately carried out;
the data analysis subunit is used for analyzing the plurality of sampling data and generating a control signal; the step is digital-to-analog conversion, converting the digital signal into analog signal;
and a correction signal generation subunit for generating a correction signal based on the control signal. The control signal controls the action of the waveform generator so as to generate a correction signal;
the sampling control circuit controls the sampling frequency and the sampling time of each adjusting signal sampling circuit based on the frequency of the input signal, and comprises:
inquiring a preset sampling frequency comparison table based on the frequency of the input signal, and determining the sampling frequency;
acquiring a sampling time table associated with a sampling frequency;
based on the sample timing table, a sample timing is determined.
The data analysis subunit analyzes the plurality of sampled data, generates a control signal, and executes the following operations:
constructing a control analysis parameter set based on the plurality of sampling data;
matching the control analysis parameter set with each standard parameter set in a preset control signal generation library, and extracting a control signal parameter set corresponding to the standard parameter set matched with the control analysis parameter set;
based on the set of control signal parameters, a control signal is generated.
As shown in fig. 4, the loading unit 4 includes:
a sixth field effect transistor M6, the grid electrode of which is connected with the output end of the correction signal generation subunit, and the drain electrode of which is connected with the logic high voltage VDD;
one end of the third capacitor C3 is connected with the source electrode of the sixth field effect transistor M6, and the other end of the third capacitor C is grounded; the generating device 13 is connected in parallel with the third capacitance C3.
Wherein the generating device comprises: an oscillator.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (7)
1. A low noise PLL phase locked loop circuit comprising:
the phase frequency detection unit is used for comparing an input signal with a reference signal to generate an error signal;
an adjustment signal generation unit configured to generate an adjustment signal based on the error signal;
a correction signal generation unit configured to generate a correction signal based on the adjustment signal;
the loading unit is used for loading the adjustment signal and the correction signal to the input end of the generating device of the original signal corresponding to the input signal;
wherein the phase frequency detection unit includes:
the signal input end of the first D-type trigger is connected with logic high voltage, and the clock control end of the first D-type trigger is connected with the reference signal;
the signal input end of the second D-type trigger is connected with logic high voltage, and the clock control end of the second D-type trigger is connected with the input signal;
the first input end of the logic AND gate circuit is connected with the output end of the first D-type trigger, the second input end of the logic AND gate circuit is connected with the output end of the second D-type trigger, and the output ends of the logic AND gate circuit are respectively connected with the zero clearing ends of the first D-type trigger and the second D-type trigger;
wherein the output of the output end of the first D-type trigger and the output of the output end of the second D-type trigger jointly form the error signal;
the input signal is obtained from the output end of the generating device through a frequency divider;
wherein the adjustment signal generation unit includes:
the control input end of the first switch circuit is connected with the output end of the first D-type trigger;
the control input end of the second switch circuit is connected with the output end of the second D-type trigger;
the source electrode of the first field effect tube is connected with the input end of the first switch circuit, and the drain electrode of the first field effect tube is connected with logic high voltage;
the drain electrode of the second field effect tube is connected with the input end of the second switch circuit, and the source electrode of the second field effect tube is grounded;
the drain electrode of the third field effect tube is connected with logic high voltage, and the grid electrode of the third field effect tube is connected with the grid electrode of the first field effect tube and the source electrode of the third field effect tube;
the source electrode of the fourth field effect tube is grounded, the drain electrode of the fourth field effect tube is connected with the source electrode of the third field effect tube, and the grid electrode of the fourth field effect tube is connected with the grid electrode of the second field effect tube;
the source electrode of the fifth field effect tube is grounded, and the grid electrode of the fifth field effect tube is connected with the grid electrode of the fourth field effect tube and is connected with the drain electrode of the fourth field effect tube;
the two ends of the current source are respectively connected with logic high voltage and the drain electrode of the fifth field effect transistor;
one end of the first capacitor is connected with logic high voltage;
one end of the inductor is connected with the first capacitor, and the other end of the inductor is respectively connected with the output ends of the first switch circuit and the second switch circuit;
one end of the second capacitor is connected with logic high voltage, and the other end of the second capacitor is connected with the output ends of the first switch circuit and the second switch circuit respectively;
and the adjusting signal output end is connected with one end of the second capacitor, which is connected with the output ends of the first switch circuit and the second switch circuit.
2. The low noise PLL phase locked loop circuit of claim 1 wherein the first field effect transistor is a P-channel field effect transistor.
3. The low noise PLL phase locked loop circuit of claim 1 wherein the correction signal generating unit comprises:
the adjusting signal sampling sub-units are used for respectively sampling the adjusting signals to obtain a plurality of sampling data;
a frequency detection subunit for detecting the frequency of the input signal;
a sampling control circuit for controlling the sampling frequency and the sampling timing of each adjustment signal sampling circuit based on the frequency of the input signal;
the data analysis subunit is used for analyzing the plurality of sampling data and generating a control signal;
and a correction signal generation subunit for generating a correction signal based on the control signal.
4. The low noise PLL phase locked loop circuit of claim 3 wherein the sampling control circuit controls a sampling frequency and a sampling timing of each adjustment signal sampling circuit based on a frequency of the input signal, comprising:
inquiring a preset sampling frequency comparison table based on the frequency of the input signal, and determining the sampling frequency;
acquiring a sampling time table associated with the sampling frequency;
and determining sampling time based on the sampling time table.
5. The low noise PLL phase locked loop circuit of claim 3 wherein said data analysis subunit analyzes a plurality of said sampled data to generate a control signal performing the operations of:
constructing a control analysis parameter set based on a plurality of the sampling data;
matching the control analysis parameter set with each standard parameter set in a preset control signal generation library, and extracting a control signal parameter set corresponding to the standard parameter set matched with the control analysis parameter set;
the control signal is generated based on the control signal parameter set.
6. The low noise PLL phase locked loop circuit of claim 3 wherein the loading unit comprises:
a sixth field effect transistor, the grid electrode of which is connected with the output end of the correction signal generation subunit, and the drain electrode of which is connected with logic high voltage;
one end of the third capacitor is connected with the source electrode of the sixth field effect transistor, and the other end of the third capacitor is grounded; the generating device is connected in parallel with the third capacitor.
7. The low noise PLL phase locked loop circuit of claim 1 wherein the generating means comprises: an oscillator.
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| CN102522985A (en) * | 2011-12-31 | 2012-06-27 | 杭州士兰微电子股份有限公司 | Locking-phase ring and voltage-controlled oscillator thereof |
| US8461890B1 (en) * | 2011-07-20 | 2013-06-11 | United Microelectronics Corp. | Phase and/or frequency detector, phase-locked loop and operation method for the phase-locked loop |
| CN103828240A (en) * | 2011-07-28 | 2014-05-28 | 英特尔公司 | Circuitry and method for controlling characteristic of periodic signal |
| CN109787621A (en) * | 2017-11-13 | 2019-05-21 | 西安电子科技大学昆山创新研究院 | Sub-sampling digital phase-locked loop |
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| WO2007018105A1 (en) * | 2005-08-11 | 2007-02-15 | Semiconductor Energy Laboratory Co., Ltd. | Voltage controlled oscillator and phase-locked loop |
| KR102298158B1 (en) * | 2014-08-25 | 2021-09-03 | 삼성전자주식회사 | Semiconductor device and Phase Locked Loop comprising the same |
| US10923442B2 (en) * | 2017-03-10 | 2021-02-16 | Drexel University | Protecting analog circuits with parameter biasing obfuscation |
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|---|---|---|---|---|
| US8461890B1 (en) * | 2011-07-20 | 2013-06-11 | United Microelectronics Corp. | Phase and/or frequency detector, phase-locked loop and operation method for the phase-locked loop |
| CN103828240A (en) * | 2011-07-28 | 2014-05-28 | 英特尔公司 | Circuitry and method for controlling characteristic of periodic signal |
| CN102522985A (en) * | 2011-12-31 | 2012-06-27 | 杭州士兰微电子股份有限公司 | Locking-phase ring and voltage-controlled oscillator thereof |
| CN109787621A (en) * | 2017-11-13 | 2019-05-21 | 西安电子科技大学昆山创新研究院 | Sub-sampling digital phase-locked loop |
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