CN116504287A

CN116504287A - Improved timing circuit for memory

Info

Publication number: CN116504287A
Application number: CN202310481022.3A
Authority: CN
Inventors: S·戈什; 晶昌镐
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2016-07-08
Filing date: 2017-06-07
Publication date: 2023-07-28
Also published as: CN109416920A; EP3482396A1; EP3482396B1; WO2018009298A1; US9858988B1; EP4213151A1; US20180012649A1; CN109416920B

Abstract

A memory is presented. The memory includes a plurality of memory cells, a word line coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy word line. The dummy word line is configured to mimic at least a portion of a word line. An apparatus is presented. The apparatus includes a first memory having a first word line coupled to a first number of memory cells. The second memory has a second word line coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit for enabling memory operations. The timing circuit includes a delay stage corresponding to a load of a third number of memory cells. The third number is different from the first number.

Description

Improved timing circuit for memory

The present application is a divisional application of application number 201780041794.8, entitled "improved timing circuit for memory", having application date 2017, month 06, and 07.

Technical Field

The present disclosure relates to devices having memory, and in particular to electronic devices and Integrated Circuits (ICs) having memory incorporating improved tracking circuits.

Background

Memory is an important component of wireless communication devices. In recent years, wireless communication technologies and devices (e.g., cellular phones, tablet computers, notebook computers, etc.) have become increasingly popular and increasingly used. These electronic devices are increasingly complex and now often incorporate multiple processors (e.g., baseband processors and/or application processors) and other ICs that allow users to run complex and power-intensive software applications (e.g., music players, web browsers, video streaming applications, etc.). As performance requirements increase, ICs for wireless communication applications may incorporate multiple processors and memories. The memories may have memory arrays of different memory array sizes and different sizes or configurations.

One design challenge is to reduce the complexity of designing memories of different array sizes. For example, a memory array of memory may be generated by a memory compiler. However, it may not be easy to generate timing circuits that operate memories of different memory array sizes. One problem is that the timing circuit balances the performance and reliability of memories of different memory array sizes.

Disclosure of Invention

Aspects of a memory are disclosed. In one implementation, the memory includes a plurality of memory cells, a word line coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy word line. The dummy word line is configured to emulate at least a portion of the (emulate) word line.

Aspects of a method for operating a memory are disclosed. In one implementation, the method includes asserting a word line coupled to a plurality of memory cells and enabling a sense amplifier coupled to one of the plurality of memory cells. Enabling the sense amplifier is based on flowing a signal through the delay stage and the dummy word line. The dummy word line is configured to mimic at least a portion of a word line.

Aspects of an apparatus are disclosed. In one implementation, the apparatus includes a first memory having a first number of memory cells and a first word line coupled to the first number of memory cells. The second memory includes a second number of memory cells and a second word line coupled to the second number of memory cells. Each of the first memory and the second memory includes a timing circuit for enabling memory operations. The timing circuit includes a delay stage configured to correspond to a load of a third number of memory cells. The third number of memory cells is different from the first number of memory cells.

Aspects of a method for operating a first memory and a second memory are disclosed. In one implementation, the method includes: the method includes asserting a first word line in a first memory coupled to a first number of memory cells, enabling memory operations of the first memory via a first delay stage, asserting a second word line in a second memory coupled to a second number of memory cells, and enabling memory operations of the second memory via a second delay stage. The first delay stage and the second delay stage are configured to correspond to a load of a third number of memory cells. The third number of memory cells is different from the first number of memory cells.

It is understood that other aspects of the apparatus and methods will become readily apparent to those skilled in the art from the following detailed description, wherein various aspects of the apparatus and methods are shown and described by way of illustration. As will be recognized, these aspects may be embodied in other and different forms, and the details of these aspects may be modified in various other respects. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.

Drawings

FIG. 1 is a diagram of one exemplary embodiment of an IC incorporating memory of different memory array sizes.

FIG. 2 is a circuit diagram of one exemplary embodiment of a memory cell for an SRAM.

FIG. 3 is a functional block diagram of an exemplary embodiment of the memory of FIG. 2.

FIG. 4 is a waveform diagram of differential voltages on bit lines and sense amplifiers enabled based thereon.

FIG. 5 is a diagram of one exemplary embodiment of a timing circuit that operates to enable a sense amplifier.

Fig. 6 is a logic diagram of one exemplary embodiment of a row decoder including a pre-decoder.

FIG. 7 is a waveform diagram of a timing circuit that asserts the SAEN signal to enable the sense amplifier of FIG. 3.

FIG. 8 is a diagram of one exemplary embodiment of a timing circuit that operates to enable a sense amplifier.

FIG. 9 is a diagram of one exemplary embodiment of a delay stage in a timing circuit.

FIG. 10 is a diagram of one exemplary embodiment of a timing circuit that operates to enable a sense amplifier.

FIG. 11 is a flow chart of a method for operating the memory of FIG. 8.

Fig. 12 is a flow chart of a method for operating the memory of fig. 1 and 8.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other designs.

Several aspects of the present disclosure will now be presented with reference to various apparatuses and methods. These apparatus and methods will be described in the following detailed description and illustrated in the figures by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The various apparatuses and methods presented throughout this disclosure may be implemented in various forms of hardware. As an example, any apparatus or method, alone or in combination, may be implemented as an integrated circuit or as part of an integrated circuit. The integrated circuit may be an end product such as a microprocessor, digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), programmable logic, or any other suitable integrated circuit. Alternatively, the integrated circuit may be integrated with other chips, discrete circuit elements, and/or other components as part of an intermediate product (such as a motherboard) or end product.

The methods disclosed herein include one or more operations or acts for implementing the described methods. The method operations and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of operations or actions is specified, the order and/or use of specific operations and/or actions may be modified without departing from the scope of the claims.

The word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiment" of an apparatus or method does not require that all embodiments of the invention include the described component, structure, feature, function, process, advantage, benefit or mode of operation.

The terms "connected," "coupled," or any variant thereof, refer to any connection or coupling, either direct or indirect, between two or more elements, and may encompass the presence of one or more intervening elements between two elements that are "connected" or "coupled" together. The coupling or connection between the elements may be physical, logical, or a combination thereof. As used herein, two elements may be considered to be "connected" or "coupled" together through the use of one or more wires, cables, and/or printed electrical connections, as well as through the use of electromagnetic energy such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region, and the optical (both visible and non-visible) regions, as a few non-limiting and non-exhaustive examples.

Any reference herein to an element using designations such as "first," "second," etc. generally does not limit the number or order of the element. Rather, such designations are used herein as a convenient method of distinguishing between two or more elements or two or more instances of an element. Thus, references to first and second elements do not mean that only two elements may be used, or that the first element must precede the second element.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including" and/or "having," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As understood by one of ordinary skill in the art, the terms "approximately" and/or "approximately" are intended to indicate a degree sufficient to achieve the intended purpose.

Various aspects of an apparatus and method for a sensor of an improved timing circuit are provided in the context of a Static Random Access Memory (SRAM) incorporated within an IC for wireless communications. However, as those skilled in the art will readily appreciate, aspects and applications of the present disclosure may not be limited thereto. For example, the present disclosure may be readily applied to other types of memories and applications. Accordingly, all references to specific applications of the presented apparatus or method are intended to illustrate only exemplary aspects of the apparatus or method, and it should be understood that such aspects may have wide application variations.

FIG. 1 is a diagram of one exemplary embodiment of an IC incorporating memory of different memory array sizes. IC 102 may be on one or more discrete substrates and may include a processor or processors for wireless communication. For example, IC 102 may incorporate an integrated application and baseband processor for a cellular telephone. The IC 102 includes various circuit blocks or cores, such as a Graphics Processor Unit (GPU), a Digital Signal Processor (DSP), a modem for wireless data communications, a Central Processing Unit (CPU), and Wireless Local Area Network (WLAN) circuit blocks. The circuit block may be, for example, a collection of circuits.

IC 102 also incorporates various memories including memories 124-1 and 124-2. Memory in IC 102 may be used to store program instructions and data. Memories 124-1 and 124-2 may include a memory array of memory cells arranged in rows and columns of memory cells. Memories 124-1 and 124-2 may have different memory array sizes or configurations (e.g., rows and columns of memory cells). For example, memory 124-1 may have a memory array with C1 columns and R1 rows, and memory 124-2 may have a memory array with C2 columns and R2 rows. In one implementation, C2 is greater than C1, and R1 is greater than R2. As a result, the word lines in memory 124-1 (each coupled to a C1 column) may be shorter than the word lines in memory 124-2 (each coupled to a C2 column), and the columns in memory 124-1 (each coupled to an R1 row) may be longer than the columns in memory 124-2 (each coupled to an R2 row).

As described below, differences in the configuration of the memory arrays may result in different design requirements for memories 124-1 and 124-2. Each of memories 124-1 and 124-2 includes timing circuitry for operating memory operations (e.g., activating sense amplifiers) in the respective memories. The timing circuitry that operates memories 124-1 and 124-2 may be customized to operate each of the configurations of the memory array. However, such a design would be time consuming. Sharing a common scheme for the timing circuits may be advantageous by allowing greater automation for generating the timing circuits.

Memories 124-1 and 124-1 may be any suitable memory technology such as, for example, SRAM. However, as will be readily appreciated by those skilled in the art, the memory 124 need not be limited to SRAM. SRAM includes an array of storage elements called "cells", "memory cells", or "bit cells". Each memory cell may be configured to store one bit of data (e.g., a logic 1 or a logic 0). FIG. 2 is a circuit diagram of one exemplary embodiment of a memory cell for an SRAM. The memory cell 200 is implemented with a six transistor (6T) configuration. However, as will be readily appreciated by those skilled in the art, the cells may be implemented in a four transistor (4T) configuration or any other suitable transistor configuration.

The memory cell 200 is shown with two inverters 202, 204. The first inverter 202 includes a p-channel transistor 206 and an n-channel transistor 208. The second inverter 204 includes a p-channel transistor 210 and an n-channel transistor 212. In the depicted embodiment, inverters 202 and 204 are powered by VDD and have a return VSS (e.g., ground). The first inverter 202 and the second inverter 204 are interconnected to form a cross-coupled latch. A first n-channel access transistor 214 couples the output node 216 from the first inverter 202 to the bit line BL, and a second n-channel access transistor 218 couples the output node 220 from the second inverter 204 to the bit line BLB (whose value is the inverse or inverse of the bit line BL). The gates of access transistors 214, 218 are coupled to a word line WL.

The read operation may be initiated by precharging or charging the bit lines BL and BLB to a predetermined level that is determined not to disturb the data stored in the memory cell 200. In some examples, a precharge circuit (not shown for clarity) precharges or pulls up bit lines BL and BLB to a predetermined level that does not flip the stored data. The predetermined level may be a high level or VDD. In some examples, the predetermined level may be a fraction (e.g., half) of VDD. Word line WL is then asserted to connect cross-coupled inverters 202, 204 to bit lines BL and BLB via access transistors 214 and 218, respectively. As an example, memory cell 200 may store a logic 1 by storing a low level (e.g., ground) at output node 216 and a high level (e.g., VDD) at output node 220. The output node state is maintained by the cross-coupled inverters 202, 204. When word line WL is asserted, inverter 202 discharges bit line BL through access transistor 214 and output node 216. Bit line BLB is held high by inverter 204 through access transistor 218 and output node 220. Thus, the differential voltage on the bit line pair BL and BLB is established by the pull-down of the bit line BL.

The bit lines BL and BLB are fed to a Sense Amplifier (SA) (not shown) which senses the data carried thereon (e.g., differential voltages on the bit line pairs BL and BLB) and outputs a logic level (e.g., logic 1) as read data to peripheral circuits external to the memory. The SA will be discussed in detail below.

A write operation may be initiated by setting bit lines BL and BLB to the value to be written to memory cell 200 and asserting word line WL. That is, the write data is driven onto the bit lines BL and BLB. Word line WL may be asserted before or after a value to be written (e.g., write data) is provided to bit lines BL and BLB. As an example, a logic 1 may be written to the memory cell 200 by setting the bit line BL to a logic level 0 and setting the bit line BLB to a logic 1. The logic level 0 at the bit line BL is applied to the input of the second inverter 204 through the access transistor 214, which in turn forces the output node 220 of the second inverter 204 to VDD. The output node 220 of the second inverter 204 is applied to the input of the first inverter 202, which in turn forces the output node 216 of the first inverter 202 to VSS. Logic level 0 may be written to memory cell 200 by inverting the values of bit lines BL and BLB. The write driver is designed to be stronger than the pull-up transistors (206 and 210) in the memory cell 200 so that the write data can override the previous states of the cross-coupled inverters 202, 204.

After the read or write operation is completed, the word line is de-asserted, causing access transistors 214 and 218 to disconnect bit lines BL and BLB from both inverters 202, 204. The cross-coupling between the two inverters 202, 204 maintains the state of the inverter output as long as the memory cell 200 is powered.

FIG. 3 is a functional block diagram of an exemplary embodiment of the memory of FIG. 2. Memory 124 may be incorporated as memory 124-1 and/or memory 124-2 of fig. 1. The read operation is provided by way of example and the write operation and related circuitry are omitted for clarity. Memory 124 includes a memory array 302 with supporting circuitry to decode addresses and perform read and write operations. The memory array 302 includes memory cells 200 arranged to share connections in horizontal and vertical columns. Specifically, each horizontal row of memory cells 200 shares a word line WL, and each vertical column of memory cells 200 shares a pair of bit lines BL and BLB. The size (i.e., number of cells) of the memory array 302 may vary depending on various factors, including the particular application, speed requirements, layout and test requirements, and overall design constraints imposed on the system. The memory array 302 may contain thousands or millions of memory cells.

In the exemplary embodiment of the memory shown in FIG. 3, the memory array 302 is formed of a memory array arranged in a 2 pattern ⁿ Horizontal lines sum 2 ^m (x) (2) of vertical columns ⁿ x2 ^m (x) A) memory cell 200, 2 ^m Is the number of words per row and x is the number of bits output for a read access. Referring again to FIG. 1, in memory 124-1, the number of rows R1 corresponds to 2 ⁿ And column number C1 corresponds to 2 ^m (x) A. The invention relates to a method for producing a fibre-reinforced plastic composite Also, in memory 124-2, the number of rows R2 corresponds to 2 ⁿ And column number C2 corresponds to 2 ^m (x) A. The invention relates to a method for producing a fibre-reinforced plastic composite Referring again to fig. 3, a peripheral (not shown) may randomly access any word (i.e., x cells) in the memory array 302 using an (n+m) -bit wide address. In other words, the memory 124 outputs x bits of read data for a read operation and writes x bits of write data in the memory array 302 for a write operation.

In memory 124, n bits of an address are provided to an input of row decoder 304 and m bits of an address are provided to an input of column decoder 306. The row decoder 304 (e.g., a word line decoder) converts the n-bit address to 2 ⁿ The word line outputs. A different word line WL is asserted by the row decoder 304 for each different n-bit row address. As a result, 2 in the horizontal line with the word line WL asserted ^m (x) Each of the memory cells 200 is connected to 2 through its access transistor ^m (x) One pair of bit lines BL and BLB is as described above in connection with FIG. 2. Data stored in the memory cells is provided to the bl_rd and blb_rd bit line pairs through the selected bit line pairs BL and BLB and x multiplexers 308 along with the asserted word lines WL, as described in connection with fig. 2. The BL_RD and BLB_RD bit lines are provided to the SA 320 for amplification, and the resulting amplified data is output as read data.

In some examples, row decoder 304 may be enabled or disabled (e.g., clocked) by signal WLCLK. When the WLCLK signal is deasserted, the row decoder 304 does not assert any word lines. Thus, the WLCLK signal may control the period and timing at which the word line is asserted.

For column decoding, memory 124 provides m bits of an address to column decoder 306. Column decoder 306 provides 2 ^m Selection of output columns (CS (1) -CS (2) ^m ) With different ones of the outputs being asserted for each different combination of address inputs. The outputs are provided to x multiplexers 308. As an example, multiplexer 308 may include a transmission gate. Each multiplexer may be 2 ^m :1 multiplexer and selects 2 read from memory array 302 based on the output from column decoder 306 ^m One of the bit line pairs. With x multiplexers 308, x bits are selected and output for each read access. In some examples, multiplexer 308 may be considered to be 2 ^m :1 selector. The selected x bit line pairs are output to SA 320 as bit line pairs GBL and GBL B.

The timing circuit 310 is configured to time the enabling of the SA 320. Timing circuit 310 times the enabling to ensure that a sufficient voltage difference (corresponding to the voltage difference on bit line pair GBL and gbl_b read by SA 320) is formed on bit line pair BL and BLB. If SA 320 is enabled too early (e.g., before the voltage difference on bit line pairs BL and BLB reaches a readable threshold), SA 320 may misread the data and output an erroneous value. If SA 320 is enabled too late, read access time of memory 124 is prevented.

FIG. 4 is a differential voltage on a bit line (for the memory array shown in FIG. 3 employing memory cell 200 of FIG. 2) and sense amplification enabled based thereonWaveform diagram of the device. At T ₀ At this point, the word line WL is asserted (e.g., the row decoder 304 pulls the selected word line WL high). In response, the memory cell 200 coupled to the selected word line WL pulls down the bit line BL or BLB. For example, a logic 1 is stored in memory cell 200 (a low level is stored at node 216 and a high level is stored at node 220). The bit line BL is pulled down via node 216 and access transistor 214. Thus, a voltage difference is formed between the bit line pair BL and BLB. Voltage difference threshold dv_th (at T ₂ At) means that SA 320 can accurately read and amplify the voltage difference on bit line pair BL and BLB as the minimum voltage difference of the read data. In one example, at T ₂ T before ₁ The SAEN signal is asserted (e.g., the timing circuit 310 outputs a high SAEN signal). As shown in fig. 4, at T ₁ At this point, the voltage difference at the bit line pair BL and BLB is smaller than the threshold dv_th, and thus, the SA 320 may output erroneous read data. In another example, at T ₂ Thereafter T ₃ The SAEN signal is asserted. Thus, the read access time is unnecessarily delayed. In one aspect, timing circuit 310 may time activation of SA 320 (e.g., asserting the SAEN signal) closer to T for both memories 124-1 and 124-2 ₂ 。

FIG. 5 is a diagram of one exemplary embodiment of a timing circuit that operates to enable a sense amplifier. In the memory 124, the memory array 302 is formed within a physical area, i.e., the memory array 519. Memory 124 includes clock logic 522 configured to receive a system clock CLK and read/write commands Rd/Wr. The read/write command Rd/Wr may enable assertion of the WLCLK signal. Clock logic 522 may assert WLCLK to enable word line WL based on CLK timing.

In one implementation, as presented in fig. 3, the row decoder 304 receives an n-bit address (e.g., a row address) to assert a selected word line WL. The row decoder 304 includes a pre-decoder 524 and a WL decoder 526. The pre-decoder 524 provides a first level of decoding of the row address and outputs a pre-decoded address 525.WL decoder 526 performs a second stage of decoding and decodes pre-decode address 525 to assert the selected word line WL.

Fig. 6 is a logic diagram of one exemplary embodiment of a row decoder including a pre-decoder. A 4-bit row address is used as an example (e.g., n equals 4). The pre-decoders 524 may include a first set and a second set of pre-decoders 524. The first set of pre-decoders 524 decodes row addresses 0 and 1 (e.g., the lower two bits of the row address) and outputs a first set of pre-decoded addresses 525 (0-3). When the WLCLK signal is asserted, one of the first set of pre-decode addresses 525 (0-3) will be asserted, corresponding to one of the four states of row addresses 0 and 1. The second set of pre-decoders 524 decodes row addresses 2 and 3 (e.g., the upper two bits) and outputs a second set of pre-decoded addresses 525 (4-7). One of the second set of pre-decode addresses 525 (4-7) will be asserted, corresponding to one of the four states of row addresses 2 and 3.

WL decoder 526 may be configured to generate 16 word lines WL and assert a selected one based on the first set of pre-decode addresses 525 (0-3) and the second set of pre-decode addresses 525 (4-7). Each of the 16 word lines WL may be based on one of the first set of pre-decoded addresses 525 (0-3) and one of the second set of pre-decoded addresses 525 (4-7). In one implementation, pre-decode address 525 may physically extend approximately 3/4 of the distance of WL decoder 526. For example, pre-decode address 525 (3) is used to generate WL (3) and WL (15), and both word lines WL (3) and WL (15) are approximately 3/4 as far as all word lines. In other words, word lines WL (3) and WL (15) are separated by space of 12 word lines (3/4 of the total length of WL decoder 526, or of the total of 16 word lines). Thus, in one physical implementation, pre-decode address 525 (3) extends 3/4 of WL decoder 526.

Referring again to fig. 5, the memory array 302 (e.g., memory array region 519) is shown having dimensions of row length times column length. The row length corresponds to the length of the column number (e.g., C1 for memory 124-1 and C2 for memory 124-2). The column length corresponds to the length of the row number (e.g., R1 for memory 124-1 and R2 for memory 124-2). In one physical implementation, WL decoder 526 outputs a word line WL over the row length of memory array 302 (e.g., memory array region 519). Thus, the pre-decode address 525 at about 3/4 of the length of the WL decoder 526 may extend about 3/4 of the length of the column.

Fig. 5 also includes a timing circuit 310 configured to generate a SAEN signal to activate SA 320. In one implementation, the timing circuit 310 uses the dummy word line DWL 532 and the dummy bit line DBL 530 to timing assertion of the SAEN signal (to activate the SA 320). The dummy word line DWL 532 may emulate the word line WL and the dummy bit line DBL 530 may emulate the bit line BL or BLB. The term "impersonate" is not limited to impersonators being identical to the impersonated object. In some examples, the term "mimic" indicates that the simulator models certain aspects of the object being modeled, including, for example, physical parameters of resistance or capacitance.

The dummy word line DWL 532 may include a conductive layer (e.g., the same conductive layer as the word line WL) that is routed to half the distance of the word line WL (e.g., 1/2 of the row length). The dummy word line DWL 532 may be folded such that the total length of the dummy word line DWL 532 is the same or approximately the same as the word line WL. In this way, the dummy word line DWL 532 mimics the resistance and capacitance of the word line WL. The dummy bit line DBL 530 may include a conductive layer (e.g., the same conductive layer as the bit line BL or BLB) that is routed the same distance (e.g., column length) of the bit line BL or BLB. In this way, the dummy bit line DBL 530 mimics the resistance and capacitance of the bit line BL or BLB.

In one implementation, the dummy bit line DBL 530 may be routed within the memory array region 519 and, thus, may be implemented using the same process (e.g., the same type of metal layer, diffusion, etc.) as the memory cell 200. Further, dummy cells 505 may be added to couple to dummy bit line DBL 530. The dummy cell 505 may mimic (e.g., be the same as) the loading of the memory cell 200 to the bit line BL or BLB. FIG. 5 illustrates one example of the same number of dummy cells 505 coupled to the dummy bit line DBL 530 as the number of memory cells 200 coupled to bit line BL or BLB. In this way, the dummy bit line DBL 530 further mimics the bit line BL or BLB. In some examples, the memory compiler may generate dummy bit line DBL 530 and dummy cell 505 to automate the process.

In some examples, the dummy word line DWL 532 may not be routed in the memory array region 519 due to layout limitations of the memory array 302 or limitations of the memory compiler. Thus, the dummy word line DWL 532 that mimics the word line WL may be less accurate.

The timing circuit 310 includes a buffer 508, a first logic block 510, and a second logic block 512. The structure of the first logic block 510 and the second logic block 512 is not particularly limited, and thus, the first logic block 510 and the second logic block 512 are illustrated as blocks. In one implementation, buffer 508 receives the WLCLK signal and may assert a dummy word line DWL 532 via node 514 in response to assertion of the WLCLK signal. Signaling on the dummy word line DWL 532 that mimics the word line WL is output to the first logic block 510 via node 516. The first logic block 510 may assert (e.g., pull down) the dummy bit line DBL 530 via the node 518 in response to signaling from the dummy word line DWL 532. Thus, the signaling on node 518 mimics the pull down of bit line BL or BLB by memory cell 200 in a read operation. The second logic block 512 is coupled to a node 518 as an input. In response to the dummy bit line DBL 530 being pulled down to a threshold level (e.g., at node 518), the second logic block 512 may assert the SAEN signal (e.g., pulled high) to enable the SA 320. For example, the second logic block 512 may determine a threshold level of the dummy bit line DBL 530 to trigger assertion of the SAEN signal. Logic blocks 510 and 512 may also add delay for additional timing margin. In the manner described, the timing circuit 310 times the assertion of the SAEN signal via the dummy word line DWL 532 and the dummy bit line DBL 530 in response to the assertion of the WLCLK signal.

Applying the timing circuit 310 to various sizes of memories, such as memories 124-1 and 124-2, may result in varying results. To simplify the design process, the added delay in logic blocks 510 and 512 may be the same for both memory 124-1 and memory 124-2. As presented in fig. 1, in memory 124-1, the column length may be greater than the row length. Thus, the dummy bit line DBL 530 may dominate the timing of the timing circuit 310 when the timing circuit 310 is operated with memory 124-1. In the timing circuit 310, the dummy bit line DBL 530 that is routed in the memory array region 519 can closely emulate the bit line BL or BLB. Thus, the timing circuit 310 may not need to add a delay for the timing margin to operate in the memory 124-1 in a more reliable manner (e.g., the SA 320 is not prematurely activated).

In memory 124-2, the row length may be greater than the column length. Thus, when operating the timing circuit 310 in the case of memory 124-2, the timing of the dummy bit line DBL 530 may be less important in the operation of the timing circuit 310 than in the case of memory 124-1. In other words, the timing of the dummy word line DWL 532 plays a more important role in the memory 124-2. In the timing circuit 310, the dummy word line DWL 532 that is routed outside the memory array region 519 may not closely emulate the word line WL. Thus, the timing circuit 310 may need to add a delay for the timing margin to operate the memory 124-2. For example, referring to FIG. 4, the timing circuit 310 may be at T ₂ Is set for the optimal read time. When timing circuit 310 is applied to memory 124-1, timing circuit 310 may be at T due to the added delay ₃ The SAEN signal is asserted. In general, memory 124-1 (configured to have a column length greater than a row length) is slower, and the added delay exacerbates the problem by making memory 124-1 even slower.

FIG. 7 is a waveform diagram of a timing circuit that asserts the SAEN signal to enable the sense amplifier of FIG. 3. At T ₀ At this point, the WLCLK signal is asserted (e.g., pulled high) to signal the beginning of a memory access. In response, word line WL is asserted and bit line BL or BLB is pulled down, as described with respect to fig. 4. At T ₁ At this point, the dummy word line is asserted. For example, in timing circuit 310, buffer 508 pulls up dummy word line DWL 532 at node 514. At T ₂ At this point, the dummy bit line DBL is pulled down to mimic the pull down of bit line BL or BLB. For example, in timing circuit 310, buffer 508 pulls up dummy word line DWL 532 at node 514.

At T ₃ At this point, the dummy bit line DBL 530 is pulled down to a level that triggers the second logic block 512. For example, the trigger level at dummy bit line DBL 530 may correspond to the optimal voltage difference at bit line pair BL and BLB. The optimal voltage difference may be a voltage difference that does not cause erroneous reading at the SA 320 and is not too large to cause a delay in the reading time. At T ₄ Where in response to deficiencyThe set bit line DBL 530 is pulled to a trigger level, and the second logic block 512 asserts the SAEN signal to enable SA 320. In some examples, T ₄ Corresponding to the optimal timing for asserting the SAEN signal. Thus, at T ₄ Asserting the SAEN signal to turn on the SA 320 allows the SA 320 to read out the correct read data without undue delay. However, when timing circuit 310 is used in both memories 124-1 and 124-2, a delay may be added for memory 124-2 (e.g., to account for the master wordline delay, as described above). As a result, the timing circuit 310 in memory 124-1 may be at T ₅ The SAEN signal is asserted.

Exemplary embodiments of timing circuits for balancing read access times across differently configured memories (e.g., memories 124-1 and 124-2) are presented herein. One aspect of the exemplary embodiments presented below allows for reducing the additional delay for memory 124-1 (e.g., where the column length is greater than the row length) to reduce read access time. For example, embodiments reduce T of FIG. 7 ₄ And T ₅ And thereby improves the read access time of memory 124-1.

FIG. 8 is a diagram of one exemplary embodiment of a timing circuit that operates to enable a sense amplifier. The memory 124 includes a plurality of memory cells 200 arranged as a memory array 302 in a memory array area 519. The word line WL is coupled to a plurality of memory cells 200 (e.g., a C1 or C2 column of memory cells 200 is coupled to the word line WL). Each column of memory cells 200 may be coupled to a SA 320 via a bit line pair BL and BLB, as presented with respect to fig. 3. The bit line pairs BL and BLB are routed through (e.g., arranged in) the memory array region 519.

Memory 124 incorporates timing circuitry 810 configured to operate differently configured memories (e.g., memory 124-1 and memory 124-2). The timing circuit 810 includes a delay chain incorporating a delay stage 809, a dummy word line DWL 832, and a dummy bit line DBL 530 arranged in series. In one example, the dummy bit line DBL 530 (and dummy cells 505) may be routed in the memory array region 519 and coupled to the same number of dummy cells 505 as the memory 124 and timing circuit 310 of fig. 5.

In timing circuit 810, buffer 508 receives the WLCLK signal and outputs signaling to delay stage 809 via node 813. Delay stage 809 receives signaling via node 813 and outputs to dummy word line DWL 832 via node 814. The dummy word line DWL 832 is coupled to the first logic block 510 via node 516. In response to a change in the state of the dummy word line DWL 832, the first logic block 510 outputs to node 518, which node 518 is coupled to the dummy bit line DBL 530. In response to an operation of the dummy bit line DBL 530 (e.g., pulling down the dummy bit line DBL 530), the second logic block 512 outputs a SAEN signal to enable the SA 320.

In one implementation, buffer 508 receives the WLCLK signal and may assert a dummy word line DWL 832 via delay stage 809 in response to assertion of the WLCLK signal, dummy word line DWL 832 and delay stage 809 being arranged in series. The dummy word line DWL 832 may be configured to mimic the delay of at least a portion of the word line WL (e.g., less than the entire word line WL). For example, the portion of the word line WL may be half or about half of the word line WL. The dummy word line DWL 832 may be folded and include two branches each being 1/4 of the length of the word line WL.

In one aspect, the delay stage 809 may include a resistive-capacitive (RC) delay circuit. FIG. 9 is a diagram of one exemplary embodiment of a delay stage in a timing circuit. Delay stage 809 may include a distributed RC circuit with four equal RC stages. The first stage includes a resistor R1 and a capacitor C1. The second stage includes a resistor R2, a capacitor C2, and the like. The number of RC stages is not particularly limited. The total resistance of delay stage 809 is the sum of the resistances of all RC stages (e.g., resistors R1-R4). The total capacitance of the delay stage 809 is the sum of the capacitances of all RC stages (e.g., capacitors C1-C4).

In one aspect, the delay stage 809 mimics a portion of the word line WL and the loading of the plurality of memory cells 200 coupled to the portion of the word line WL. For example, delay stage 809 may include a load corresponding to at least one of memory cells 200. The total capacitance of delay stage 809 may approximate the load of a fixed number of memory cells 200 coupled to word line WL (e.g., the load of the gates of access transistors 214 and 218). For both memories 124-1 and 124-2, the fixed number may be, for example, 64. Delay stage 809 may also include a load corresponding to a second portion of word line WL. For example, delay stage 809 may also include a resistance and capacitance of word line WL coupled to the length of a fixed number of memory cells 200. For example, the total resistance of delay stage 809 may correspond to the resistance of word line WL coupled to the length of 64 memory cells 200. In addition to the loading of a fixed number of memory cells 200, the total capacitance of the delay stage 809 may also include the capacitance of the word line WL coupled to the length of 64 memory cells 200.

The timing circuit 810 may provide different tracking of word lines WL for different configurations of memory. For example, the length and load of word line WL in memory 124-1 is greater than the length and load of word line WL in memory 124-2. Thus, the loading of the 64 memory cells 200 of the delay stage 809 may account for a greater portion of the loading of the word line WL in memory 124-2 than the loading of memory 124-1. Thus, memory 124-2 requires less latency and T of FIG. 7 ₄ And T ₅ The difference between them decreases.

With continued reference to fig. 8, in another aspect, the dummy word line DWL 832 may be configured to mimic the delay of at least a portion of the word line WL (e.g., less than the entirety of the word line WL). For example, a portion of the word line WL may be or be about the entirety of the word line WL (e.g., its entire length). The dummy word line DWL 832 may be folded and include two branches each being 1/2 of the length of the word line WL.

The delay stage 809 may be configured to correspond to a delay of a portion of a word line decoder (e.g., row decoder 304) configured to drive the word line WL. For example, the word line decoders may include address decoders, such as pre-decoder 524. Delay stage 809 may be configured to correspond to the delay of an address decoder (e.g., pre-decoder 524). That is, the portion of the word line decoder may be an address decoder, such as the pre-decoder 524. In one implementation, the total resistance and capacitance of delay stage 809 may be configured to approximate the delay of pre-decoder 524 (and may include the delay of pre-decoded address 525).

In another implementation, referring to fig. 1 and 8, the first memory 124-1 includes a first word line (e.g., one of the word lines WL of fig. 8) coupled to a first number (e.g., C1) of memory cells 200. The second memory 124-2 includes a second word line (e.g., one of the word lines WL of fig. 8) coupled to a second number (e.g., C2) of memory cells 200. Each of the first memory 124-1 and the second memory 124-2 includes a timing circuit 810 to enable memory operations, such as activation of the SA 320 to output read data. The timing circuit 810 includes a delay stage 809 corresponding to the load of the third number of memory cells 200. The third number may be 64 different from C1 and/or C2. In some examples, the number of memory cells 200 coupled to word lines WL in memories 124-1 and 124-2 may range from 8 to 256, and the load in delay stage 809 corresponds to a fixed number of memory cells 200 independent of the number of memory cells 200 coupled to word lines WL in memories 124-1 and 124-2. In some examples, delay stage 809 may include an RC delay circuit (see, e.g., fig. 9) to perform the delay function.

The timing circuit 810 may also include a dummy word line DWL 832 configured to mimic the delay of at least a portion of the word lines WL in the first memory 124-1 and the second memory 124-2. In some examples, the dummy word line DWL 832 is configured to mimic the delay of half or about half of the word line WL.

In the embodiments presented above, the timing circuit 810 may more closely track the assertion of the word line WL. Thus, less delay is required for both memories 124-1 and 124-2, and T of FIG. 7 ₄ And T is ₅ The difference between them can thus be reduced.

FIG. 10 is a diagram of one exemplary embodiment of a timing circuit that operates to enable a sense amplifier. Memory 124 incorporates timing circuitry 1010 configured to operate differently configured memories (e.g., memories 124-1 and 124-2). The timing circuit 1010 may be configured as a delay chain incorporating the dummy word line DWL 1032, the dummy decoding address DDA 1019, and the dummy bit line DBL 530 arranged in series. In one example, the dummy bit line DBL 530 may be routed in the memory core region and coupled to the same number of dummy cells as the memory 124 and timing circuit 310 of fig. 5.

In timing circuit 1010, buffer 508 receives the WLCLK signal and outputs signaling to dummy word line DWL 1032 via node 813. The dummy word line DWL 1032 is coupled to the dummy decoder logic 1013 via node 1014. The dummy decoder logic 1013 asserts (e.g., drives high) the dummy decoding address DDA 1019 via node 814. In response to a change in the state of the dummy decoding address DDA 1019, the first logic block 510 outputs to a node 518, the node 518 being coupled to the dummy bit line DBL 530. In response to an operation of the dummy bit line DBL 530 (e.g., pulling down the dummy bit line DBL 530), the second logic block 512 outputs a SAEN signal to enable the SA 320.

In one implementation, the dummy word line DWL 1032 may be configured to mimic the delay of at least a portion of the word line WL (e.g., less than the entirety of the word line WL). For example, the portion of the word line WL may be or about the entirety of the word line WL. The dummy word line DWL 1032 may be folded and includes two branches each being 1/2 of the length of the word line WL.

The dummy decoding address DDA 1019 may be referred to as a delay stage because the dummy decoding address DDA 1019 provides a delay function. The word line decoder (e.g., row decoder 304) includes at least one decoded address (e.g., pre-decoded address 525). The dummy decoded address DDA 1019 may be configured to emulate the pre-decoded address 525. As presented above, pre-decode address 525 may extend a distance of approximately 3/4 of WL decoder 526. The dummy decoding address DDA 1019 may likewise include conductive lines (e.g., metal layers) routed for 3/4 of the WL decoder 526 to emulate the pre-decoding address 525.

In the embodiment presented above, the timing circuit 1010 may more closely track the assertion of the word line WL by tracking the pre-decode address 525. For example, referring to FIG. 1, the column length of memory 124-1 may be greater than the column length of memory 124-2 (e.g., because the number of rows R1 per column of memory 124-1 is greater than the number of rows R2 per column of memory 124-2). Because the assertion of word line WL is tracked more closely in both memories 124-1 and 124-2, less added delay is required for both memories 124-1 and 124-2. T of FIG. 7 ₄ And T is ₅ The difference between them can thus be reduced.

FIG. 11 is a flow chart 1100 of a method for operating the memory of FIG. 8. The method may be performed by, for example, the circuits of fig. 8 and 9. At 1112, word lines coupled to a plurality of memory cells are asserted. For example, a word line decoder (e.g., row decoder 304) decodes an address and asserts a word line WL. At 1114, the address is decoded to output at least one decoded address. For example, row decoder 304 includes a pre-decoder 524. The pre-decoder 524 decodes the row address and outputs a pre-decoded address 525.

At 1116, a sense amplifier coupled to one of the plurality of memory cells is enabled. For example, the timing circuit 810 is configured to enable the SAEN signal to activate the SA 320. The timing circuit 810 causes a signal to flow through the delay stage 809 and through the dummy word line DWL 532. Referring to fig. 8, delay stage 809 may be configured to correspond to a delay in asserting a portion of word line WL. At 1118, a dummy decoded address is output by the delay stage to simulate decoding an address. For example, the portion of the asserted word line WL may be a pre-decoder 524 that decodes for a pre-decode address 525. Referring to fig. 10, the delay stage 809 may output a dummy decoded address DDA 1019 configured to mimic the decoding of the pre-decoded address 525.

Referring to 1116, the dummy word line DWL 532 may be configured to mimic, for example, half of the word line WL in one case and the entirety of the word line WL in the second case. The delay stage 809 and the dummy word line DWL 532 may be arranged in series. Timing circuit 810 may also enable SA 320 based on operating dummy bit line DBL 530. The dummy bit line DBL 530 may be configured to emulate a bit line BL or BLB coupled to the SA 320.

Fig. 12 is a flow chart of a method of operating the memory of fig. 1 and 8. Method 1210 may be performed by memory 124-1 and memory 124-2 of fig. 1 that incorporate timing circuitry 810. At 1212, a first word line coupled to a first number of memory cells is asserted in a first memory. For example, memory 124-1 includes word lines WL, each of which is coupled to C1 memory cells 200. Referring to fig. 8, memory 124-1 may include a row decoder 304 configured to assert a selected word line WL. At 1214, memory operations of the first memory are enabled via the first delay stage. For example, the timing circuit 810 of the memory 124-1 includes a delay stage 809, and the SA 320 is enabled via the delay stage 809.

At 1216, a second word line coupled to a second number of memory cells is asserted in a second memory. For example, memory 124-2 (e.g., a second memory) includes word lines WL, each of which is coupled to C2 memory cells 200. Referring to fig. 8, memory 124-2 may include a row decoder 304 configured to assert a selected word line WL. At 1218, memory operations of the second memory are enabled via the second delay stage. For example, the timing circuit 810 of the memory 124-2 includes a delay stage 809 (e.g., a second delay stage) and enables the SA 320 via the delay stage 809.

In some examples, delay stages 809 of memory 124-1 and memory 124-2 may be configured to correspond to the load of a third or fixed number of memory cells 200. For example, the third or fixed number may be 64. The numbers C1 and C2 may range from 8 to 256, and the third or fixed number may be different from the number C1 and/or the number C2. In some examples, delay stages 809 of memory 124-1 and memory 124-2 may include RC delay circuits shown in FIG. 9.

It should be understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. It is understood that the particular order or hierarchy of steps in the process may be rearranged based on design preferences. In addition, some steps may be combined or omitted. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one only" unless specifically so stated, but rather "one or more". The term "some" means one or more unless specifically stated otherwise. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed in accordance with the definition of 35 u.s.c. ≡112 (f) unless the phrase "means for … …" is used to recite the element explicitly, or in the case of method claims, the phrase "step for … …" is used to recite the element.

Claims

1. A memory (124-1; 124-2) includes:

a plurality of memory cells (200) arranged as a memory array (302) in a memory array area (519) of a memory array size;

a word line (WL (1)) coupled to the plurality of memory cells (200);

a sense amplifier (320) coupled to one of the plurality of memory cells (200); and

timing circuit (810)

Is configured to enable (1116; SAEN) the sense amplifier (320), and

comprising a delay stage (809) and a dummy word line (832) arranged in series;

wherein the dummy word line (832) is configured to mimic at least a portion of the word line (WL (1)), and

wherein the delay stage (809) is configured to emulate

A part of the word line (WL (1)) and

a load of a plurality of memory cells (200) is coupled to the portion of the word line (WL (1)).

2. The memory (124-1; 124-2) of claim 1, wherein the timing circuit (810) is configured to provide different tracking of the word line (WL (1)) for differently configured memories.

3. The memory (124-1; 124-2) of claim 1, wherein the timing circuit is further coupled to a word line clock or clock logic (552) independent of a word line decoder (526).

4. The memory (124-1; 124-2) of claim 1, further comprising:

a bit line (BL (1)) configured to couple the sense amplifier (320) and the one of the plurality of memory cells (200), wherein the bit line (BL (1)) is disposed in the memory array region (519); and

a dummy bit line (530) routed in the memory array region (519) to emulate the bit line (BL (1)), wherein the timing circuit (810) is further configured to enable (1116; SAEN) the sense amplifier (320) based on operation of the dummy bit line (530).

5. The memory (124-1; 124-2) of claim 1, wherein the at least a portion of the word line (WL (1)) is less than the entirety of the word line (WL (1)).

6. The memory (124-1; 124-2) of claim 1, wherein the at least a portion of the word line (WL (1)) is about half the length of the word line (WL (1)).

7. The memory (124-1; 124-2) of claim 3, wherein the word line decoder (526) is further configured to drive the word line (WL (1)), wherein the delay stage (809) is configured to mimic a delay corresponding to a portion of the word line decoder (526), the portion including the address decoder (524).

8. The memory (124-1; 124-2) of claim 3, wherein the word line decoder (526) is further configured to drive the word line (WL (1)), wherein the word line decoder (526) is configured to output at least one decoded address, and the delay stage (809) is configured to emulate the word line decoder (526) by outputting a dummy decoded address.

9. A method of operating a memory (124-1; 124-2) includes:

asserting a word line coupled to a plurality of memory cells (200) arranged as a memory array (302) in a memory array area (519) of a memory array size;

enabling a sense amplifier (320) coupled to one of the plurality of memory cells (200), wherein enabling the sense amplifier is based on flowing a signal through a timing circuit (810) comprising a delay stage (809) and a dummy word line (832) arranged in series,

wherein the delay stage (809) is configured to emulate

A part of the word line (WL (1)) and

10. The method of claim 9, wherein the timing circuit (810) is configured to provide different tracking of the word line (WL (1)) for differently configured memories.

11. The method of claim 9, wherein the timing circuit is further coupled to a word line clock or clock logic (552) independent of a word line decoder (526).

12. The method of claim 9, wherein enabling the sense amplifier is further based on operating a dummy bit line,

wherein the dummy bit line is configured to emulate a bit line (BL (1)) coupling the sense amplifier (320) and the one of the plurality of memory cells (200), and

wherein the bit line (BL (1)) and the dummy bit line (530) are disposed in the memory array region (519).

13. The method of claim 9, wherein the at least a portion of the word line (WL (1)) is smaller than the entirety of the word line (WL (1)).

14. The method of claim 9, wherein the at least a portion of the word line (WL (1)) is about half the length of the word line (WL (1)).

15. The method of claim 11, wherein the word line decoder (526) is further configured to drive the word line (WL (1)), wherein the delay stage (809) is configured to mimic a delay corresponding to a portion of the word line decoder (526), the portion including the address decoder (524).

16. The method of claim 11, wherein the word line decoder (526) is further configured to drive the word line (WL (1)), wherein the word line decoder (526) is configured to output at least one decoded address, and the delay stage (809) is configured to emulate the word line decoder (526) by outputting a dummy decoded address.