CN116502595A

CN116502595A - Random walking-based capacitance extraction method and device, equipment and medium

Info

Publication number: CN116502595A
Application number: CN202310473096.2A
Authority: CN
Inventors: 喻文健
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2023-04-27
Filing date: 2023-04-27
Publication date: 2023-07-28

Abstract

The disclosure relates to a capacitance extraction method, a device, equipment and a medium based on random walk, wherein the method comprises the steps of randomly sampling on a Gaussian surface surrounding a first wire net to obtain first sampling points, and determining a corresponding first symmetry point set based on the first sampling points; for each sampling point in the first symmetrical point set, randomly walking based on the sampling points, stopping randomly walking until the sampling points are positioned on the surface of the first conductor, and determining a first capacitance value according to the position of the sampling points on the surface of the first conductor when randomly walking is stopped; determining a first capacitance sequence according to the first capacitance value; if the first capacitance sequence meets the preset condition, determining a target capacitance value according to the first capacitance sequence; and if the first capacitance sequence does not meet the preset condition, repeating the random sampling and random walking processes until the first capacitance sequence meets the preset condition. The capacitor extraction method, device, equipment and medium based on random walk provided by the embodiment of the disclosure can remarkably shorten the overall calculation time.

Description

Random walking-based capacitance extraction method and device, equipment and medium

Technical Field

The disclosure relates to the technical field of integrated circuits, and in particular relates to a capacitor extraction method, device, equipment and medium based on random walk.

Background

In the design flow of the integrated circuit, firstly, functional description is put forward, then, the layout describing the technological size and structure of the semiconductor is obtained through logic design and layout design, and finally, layout verification is carried out, namely, whether the design meets the requirements is verified through computer software simulation. If the requirements are met, the next production and manufacture are carried out. Otherwise, if the requirements are not met, returning to the logic design and carrying out necessary correction on the layout design. In layout verification, an important link is "interconnect parasitic parameter extraction".

With the development of integrated circuit manufacturing technology, the scale of circuits is continuously increasing and the feature size is continuously shrinking, and many chips today contain hundreds of millions of devices. However, the parasitic effects of interconnect lines in integrated circuits have caused interconnect lines to have an effect on circuit delay that exceeds the effect of devices on circuit delay. Therefore, accurate calculation of parameters such as capacitance and resistance of the interconnection line is required to ensure correct validity of circuit simulation and verification. In order to improve the calculation accuracy, the capacitance parameter extraction between the interconnection lines needs to use a three-dimensional extraction method, namely, a three-dimensional field solver is utilized for solving. The calculation of the field solver is time-consuming, and has great significance for optimization and acceleration research of the algorithm. Among the field solver methods of integrated circuit capacitance parameter extraction, the random walk capacitance extraction algorithm is a popular method. Unlike the conventional finite difference, finite element and boundary element methods, which do not require a solution to a linear system of equations, the main step in computation is to randomly take points in space, and the process of such a series of random points and ultimately stopping at a certain conductor surface is visually known as a random walk path.

At present, the related technology changes probability distribution required by random sampling on the surfaces of a Gaussian surface and a transfer cube through importance sampling and layering sampling technology, so that variance of a weight sequence used for calculating a capacitance value is reduced, the number of random walking times is reduced by a few times under the same accuracy requirement, and the purpose of improving the calculation speed is achieved. Although the existing work can accelerate the calculation speed of the random walk capacitance extraction algorithm, the calculation of the capacitance between a single separated conductor block (a single cuboid in three-dimensional space) and other conductors is mainly considered. In an actual integrated circuit interconnect structure, a plurality of conductors are connected to form a signal path (commonly referred to as a "net") and the capacitance between the entire net and other conductors or nets is calculated before the delay time for the signal to travel across the net can be analyzed.

In addition, the related art establishes a gaussian surface for each conductor block constituting the main conductor net, then randomly samples on their aggregate, and achieves the effect of directly sampling the gaussian surface established for the whole net by appropriately rejecting sampling. However, in an actual integrated circuit, the interconnection lines are very densely distributed and the number of conductor blocks is large, and one wire mesh often comprises tens or even thousands of conductor blocks, so that the gaussian surfaces of the conductor blocks are mutually overlapped, and when the sampling is refused, the probability of refusing is high, and a large amount of calculation is required to obtain an effective gaussian surface sampling point. In the original random walk method, one Gaussian surface sampling point corresponds to one random walk path, the calculation cost of Gaussian surface sampling occupies a large proportion in the total calculation amount of executing one random walk path, and whether the number of Gaussian surface sampling points can be reduced under the condition of reaching the same accuracy is an important problem faced by the random walk capacitance extraction method.

Disclosure of Invention

In view of this, the disclosure provides a method, a device and a medium for extracting capacitance based on random walk, which can reduce the number of sampling points of a gaussian surface while achieving the same accurate result, and remarkably shorten the overall calculation time.

According to an aspect of the present disclosure, there is provided a random walk-based capacitance extraction method, including:

randomly sampling on a Gaussian surface surrounding a first wire network to obtain first sampling points, and determining a corresponding first symmetrical point set based on the first sampling points, wherein the first wire network is formed by connecting a plurality of conductors in an integrated circuit, the first symmetrical point set comprises a plurality of sampling points, any sampling point in the first symmetrical point set is a sampling point symmetrical to the Gaussian surface, and the symmetrical sampling point is also positioned in the first symmetrical point set;

for each sampling point in the first symmetrical point set, randomly walking based on the sampling point until the sampling point is positioned on the surface of a first conductor, stopping the random walking, and determining a first capacitance value according to the position of the sampling point on the surface of the first conductor when the random walking is stopped, wherein the first conductor represents any one conductor in the integrated circuit, and the first capacitance value is used for indicating the capacitance between the first wire mesh and the first conductor;

Determining a first capacitance sequence according to the first capacitance value, wherein the first capacitance sequence comprises a plurality of capacitance values between a first wire net and a second wire net which are determined based on random walking, and the second wire net is formed by connecting a plurality of conductors in the integrated circuit and is mutually independent from the first wire net;

if the first capacitance sequence meets a preset condition, determining a target capacitance value according to the first capacitance sequence; and if the first capacitance sequence does not meet the preset condition, repeating the random sampling and random walking processes until the first capacitance sequence meets the preset condition, wherein the target capacitance value is used for indicating the capacitance between the first wire net and the second wire net.

In this way, a symmetrical point set is determined through one sampling point on the Gaussian surface of the first wire net, and random walking is continued from each sampling point in the symmetrical point set, which is equivalent to sending out a plurality of symmetrical random walking paths from one Gaussian surface sampling point until the symmetrical random walking paths walk to the surface of other conductors, and corresponding capacitance values are stopped and determined, so that the target capacitance value between the concerned first wire net and the concerned second wire net is determined through the capacitance sequence conforming to the preset condition, the number of Gaussian surface sampling points is reduced while the same accurate result is achieved, and the whole calculation time can be obviously shortened.

In one possible implementation, the method further includes: setting a first parameter, wherein the first parameter is used for indicating the number of symmetrical random walking paths sent out based on the first sampling point; the number of sampling points in the first symmetry point set is consistent with the number of symmetrical random walking paths indicated by the first parameter.

Therefore, by setting the first parameter, a quantity basis is provided for the follow-up determination of the symmetrical point set, so that each sampling point in the follow-up symmetrical point set is used for carrying out random walking, and the whole calculation time is shortened.

In a possible implementation manner, the determining a corresponding first symmetry point set based on the first sampling point includes: constructing a first cube, and randomly sampling on the surface of the first cube to obtain a second sampling point, wherein the first cube is used for indicating a cube which is constructed by taking the first sampling point as a center, does not overlap with the first conductor and has the largest volume; determining a third sampling point on the surface of the first cube from the second sampling point, the third sampling point being used to indicate one or more sampling points that are symmetrical to the second sampling point about the gaussian surface; and determining a first symmetry point set corresponding to the first sampling point based on the second sampling point and the third sampling point.

In this way, the first cube is constructed, the second sampling point and the third sampling point are determined based on the surface of the first cube, so that the first symmetry point set is obtained, the number of Gaussian surface sampling points is reduced, and the overall calculation efficiency is improved.

In a possible implementation manner, the second sampling point is located in a designated area of the surface of the first cube, and the size of the designated area is determined according to the first parameter; the third sampling point is located in an area of the surface of the first cube other than the designated area.

In this way, by determining the second sampling point on the designated area of the first cube and determining the third sampling point on the other area of the first cube based on the second sampling point, the range of random sampling is narrowed, which also contributes to shortening the overall calculation time.

In one possible implementation manner, the randomly walking based on the sampling point until the sampling point is located on the surface of the first conductor stops the random walking, and determining the first capacitance value according to the position of the sampling point on the surface of the first conductor when the random walking is stopped includes: judging whether the sampling point is positioned on the surface of the first conductor or not: if the sampling point is positioned on the surface of the first conductor, determining the first capacitance value according to the position of the sampling point on the surface of the first conductor when stopping the random walk; if the sampling point is not located on the surface of the first conductor, a second cube which is not overlapped with any conductor in the integrated circuit and has the largest volume is built by taking the sampling point as a center, a new sampling point is obtained by random sampling on the surface of the second cube, the random walking is stopped based on the new sampling point until the new sampling point is located on the surface of the first conductor, and the first capacitance value is determined according to the position of the new sampling point on the surface of the first conductor when the walking is stopped.

Therefore, by judging whether each sampling point in the first symmetrical point set is directly located on the surface of the conductor or located on the surface of the conductor after random walking, the obtained capacitance value is ensured to be determined when the sampling point is located on the surface of the conductor, and the accuracy of the capacitance value between the first wire net and other conductors is improved.

In a possible implementation manner, the determining the first capacitance value according to the position of the sampling point on the surface of the first conductor when stopping the random walk includes: in the case where the sampling point is located on the surface of the first conductor: if the first conductor belongs to the second wire net, determining the first capacitance value according to the position of the sampling point on the surface of the second wire net; if the first conductor does not belong to the second wire net, determining a corresponding first capacitance value according to the position of the sampling point on the surface of the first conductor, and taking zero as the capacitance value between the first wire net and the second wire net.

In this way, the effectiveness and accuracy of the subsequent judgment based on the first capacitance sequence are ensured by setting the capacitance value between the first wire mesh and the second wire mesh to zero under the condition that the sampling points randomly walk other conductors instead of the second wire mesh.

In one possible implementation, the method further includes: determining a first average and a first variance of all capacitance values in the first capacitance sequence; judging whether a first ratio of the first variance to the first average value meets a preset threshold value or not, and if the first ratio is smaller than or equal to the preset threshold value, determining that the first capacitance sequence meets the preset condition.

In this way, whether the first capacitance sequence meets the preset condition is determined by judging whether the ratio of the variance to the mean value of the first capacitance sequence is not larger than a preset threshold value, so that the whole running time can be flexibly adjusted according to the actually required data precision.

In a possible implementation manner, the determining a target capacitance value according to the first capacitance sequence includes: and taking the ratio of the sum of all capacitance values in the first capacitance sequence to a second parameter as the target capacitance value, wherein the second parameter is determined by the number of the first sampling points.

In this way, the target capacitance value concerned is determined through the first capacitance sequence meeting the preset condition and the second parameter determined by the first sampling point number, the whole running time can be flexibly adjusted according to the actually required data precision, and ideal capacitance data can be extracted.

According to another aspect of the present disclosure, there is provided a capacitance extraction device based on random walk, including:

the first determining module is configured to obtain first sampling points by random sampling on a Gaussian surface surrounding a first wire network, and determine a corresponding first symmetrical point set based on the first sampling points, wherein the first wire network is formed by connecting a plurality of conductors in an integrated circuit, the first symmetrical point set comprises a plurality of sampling points, any sampling point in the first symmetrical point set has sampling points symmetrical to the Gaussian surface, and the symmetrical sampling points are also positioned in the first symmetrical point set;

a second determination module configured to, for each sampling point in the first set of symmetry points, perform a random walk based on the sampling point, stop the random walk until the sampling point is located on a surface of a first conductor, and determine a first capacitance value according to a position of the sampling point on the surface of the first conductor when the random walk is stopped, the first conductor representing any one of conductors in the integrated circuit, the first capacitance value being used to indicate a capacitance magnitude between the first net and the first conductor;

A third determination module configured to determine a first capacitance sequence from the first capacitance values, the first capacitance sequence comprising capacitance values between a plurality of first nets determined based on random walk and a second net composed of a plurality of conductor connections in the integrated circuit and independent of the first nets;

a fourth determining module configured to determine a target capacitance value according to the first capacitance sequence if the first capacitance sequence meets a preset condition; and if the first capacitance sequence does not meet the preset condition, repeating the random sampling and random walking processes until the first capacitance sequence meets the preset condition, wherein the target capacitance value is used for indicating the capacitance between the first wire net and the second wire net.

In one possible implementation, the apparatus further includes: a parameter setting module configured to set a first parameter for indicating a number of symmetrical randomly walked paths issued based on the first sampling point; the number of sampling points in the first symmetry point set is consistent with the number of symmetrical random walking paths indicated by the first parameter.

In one possible implementation, the apparatus further includes: a fifth determination module configured to determine a first average and a first variance of all capacitance values in the first sequence of capacitances; the judging module is configured to judge whether a first ratio of the first variance to the first average value meets a preset threshold, and if the first ratio is smaller than or equal to the preset threshold, the first capacitor sequence is determined to meet the preset condition.

According to another aspect of the present disclosure, there is provided an electronic device including: a processor; a memory for storing processor-executable instructions; the processor is configured to implement the capacitance extraction method when executing the instructions stored in the memory.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the capacitance extraction method described above.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of a three-dimensional interconnect structure of an integrated circuit provided in accordance with an embodiment of the present disclosure.

Fig. 2 shows a flowchart of a capacitance extraction method provided according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a capacitance extraction method provided according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of a capacitance extraction method provided according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of a capacitance extraction method provided according to an embodiment of the present disclosure.

Fig. 6 shows a block diagram of a capacitance extraction device provided according to an embodiment of the present disclosure.

Fig. 7 shows a block diagram of an apparatus for performing a capacitance extraction method provided in accordance with an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

In order to facilitate understanding of the technical solutions provided by the embodiments of the present disclosure by those skilled in the art, a technical environment in which the technical solutions are implemented is described below.

In the design flow of the integrated circuit, firstly, functional description is put forward, then, the layout describing the technological dimension and structure of the semiconductor is obtained through logic design and layout design, and finally, layout verification is carried out, namely, whether the design meets the requirements is verified through computer software simulation. In layout verification, an important link is "extraction of interconnection parasitic parameters", namely, accurate calculation of capacitance parameters of interconnection lines is needed to ensure correct validity of circuit simulation and verification.

Currently, in a field solver method for extracting capacitance parameters of an integrated circuit, a random walk capacitance extraction algorithm is a popular method, and the main step of the method is to randomly take points in space. Although the existing work can accelerate the calculation speed of the random walk capacitance extraction algorithm, the calculation of the capacitance between the single separated conductor block and other conductors is mainly considered. However, in an actual integrated circuit interconnect structure, the capacitance between the entire net and other conductors or nets needs to be calculated before the delay time in the signal passing over the net can be analyzed.

In addition, the proposal in the related art firstly establishes the Gaussian surface for each conductor block composing the main conductor net, then carries out random sampling on the combination set of the conductor blocks, and achieves the effect of directly sampling the Gaussian surface established for the whole net through proper refusal sampling. However, in an actual integrated circuit, the interconnection lines are very densely distributed and the number of conductor blocks is large, and one wire mesh often comprises tens or even thousands of conductor blocks, so that the gaussian surfaces of the conductor blocks are mutually overlapped, and when the sampling is refused, the probability of refusing is high, and a large amount of calculation is required to obtain an effective gaussian surface sampling point. In the original random walk method, one Gaussian surface sampling point corresponds to one random walk path, the calculation cost of Gaussian surface sampling occupies a large proportion in the total calculation amount of executing one random walk path, and whether the number of Gaussian surface sampling points can be reduced under the condition of reaching the same accuracy is an important problem faced by the random walk capacitance extraction method.

The embodiment of the disclosure provides a capacitance extraction method based on random walk, which is characterized in that a symmetry point set is determined through one sampling point on a Gaussian surface of a first wire network, and random walk is continued from each sampling point in the symmetry point set, which is equivalent to that a plurality of symmetrical random walk paths are sent out from one Gaussian surface sampling point until the surfaces of other conductors are walked, and corresponding capacitance values are stopped and determined, so that a target capacitance value between a concerned first wire network and a concerned second wire network is determined through a capacitance sequence according with preset conditions, the number of the Gaussian surface sampling points is reduced while the same accurate result is achieved, and the whole calculation time can be remarkably shortened.

The capacitance extraction method based on random walk provided by the embodiment of the disclosure is executed aiming at layout data of an integrated circuit, and information such as a first wire net, a first conductor, a second wire net and the like in the capacitance extraction method can be obtained from the layout data of the integrated circuit. Layout data may be information describing an integrated circuit interconnection net, which may include, but is not limited to, spatial conductor geometry information, spatial medium geometry and attribute information.

Fig. 1 shows a schematic diagram of a three-dimensional interconnect structure of an integrated circuit provided in accordance with an embodiment of the present disclosure. As shown in fig. 1, the three-dimensional interconnect structure of an integrated circuit may include a single three-dimensional conductor (block) or may include a net of multiple conductor blocks connected. Thus, the spatial conductor geometry information may include geometry information for individual conductors and geometry information for nets.

Fig. 2 shows a flowchart of a capacitance extraction method provided according to an embodiment of the present disclosure. As shown in fig. 2, the capacitance extraction method may include:

step S201, randomly sampling on a Gaussian surface surrounding a first wire net to obtain first sampling points, and determining a corresponding first symmetry point set based on the first sampling points.

Step S202, for each sampling point in the first symmetrical point set, randomly walking is performed based on the sampling point, the random walking is stopped until the sampling point is positioned on the surface of the first conductor, and the first capacitance value is determined according to the position of the sampling point on the surface of the first conductor when the random walking is stopped.

Step S203, a first capacitance sequence is determined according to the first capacitance value.

Step S204, if the first capacitance sequence meets the preset condition, determining a target capacitance value according to the first capacitance sequence; and if the first capacitance sequence does not meet the preset condition, repeating the random sampling and random walking processes until the first capacitance sequence meets the preset condition.

The first net and the second net may each be comprised of a plurality of conductor connections in an integrated circuit, and the second net is independent of the first net. The first conductor may represent any one of the conductors in the integrated circuit, and the first conductor may be a conductor included in the first net or the second net, may be a conductor included in a net other than the first net or the second net, or may be a single conductor other than the first net or the second net.

By executing steps S201 to S204, a set of symmetry points can be determined from one sampling point on the gaussian surface of the first net, and random walking can be continued from each sampling point in the set of symmetry points, which is equivalent to sending out a plurality of symmetrical random walking paths from one sampling point of the gaussian surface until the current reaches the surface of other conductors, stopping and determining corresponding capacitance values, so that the capacitance between the first net and the second net of interest, that is, a target capacitance value, is determined through a capacitance sequence conforming to preset conditions, and thus the number of sampling points of the gaussian surface can be reduced while the same accurate result is achieved, and the overall calculation time can be remarkably shortened.

It should be noted that the number of objects of interest may be one or more, may be only the first net and the second net, and may further include the first net and other nets, which is not limited by the embodiments of the present disclosure.

In step S201, a virtual Gaussian surface sampling technique may be used to randomly sample on the Gaussian surface surrounding the first net to obtain first sampling points, and a corresponding first set of symmetry points may be determined based on the valid first sampling points.

The first net is formed by connecting a plurality of conductor blocks, and the Gaussian surface surrounding the first net can comprise the Gaussian surface corresponding to each conductor block. In one possible implementation, the Gaussian surface surrounding the first net may be established by:

step one, acquiring space data information required by establishing a Gaussian surface of a first wire network, wherein the space data information is a result of grid division of a three-dimensional simulation area based on which interconnection capacitance extraction is based and conductor block information contained in each grid.

And secondly, controlling each conductor block in the first wire net to expand outwards according to a first preset length to obtain a query cuboid corresponding to each conductor block. For example, the first preset length may be a minimum side length of the spatial grid, which is not limited by the embodiments of the present disclosure.

Step three, aiming at each query cuboid, obtaining conductor blocks contained in all space lattices intersected with the query cuboid to form a candidate conductor list; if the candidate list is empty, the minimum distance from the corresponding conductor block of the query cuboid to the outer boundary of all the space lattices intersected with the corresponding query cuboid is obtained, the corresponding conductor block of the query cuboid is controlled to be expanded outwards by one half of the minimum distance, a Gaussian surface corresponding to the corresponding conductor block of the query cuboid is obtained, otherwise, the minimum distance from the corresponding conductor block of the query cuboid to the conductor block in the candidate conductor list is obtained, and the corresponding conductor block of the query cuboid is controlled to be expanded outwards by one half of the minimum distance, so that the Gaussian surface corresponding to the corresponding conductor block of the query cuboid is obtained.

Thus, the method can realize high-efficiency processing of the large-scale integrated circuit layout containing a large number of conductor blocks, still follow the virtual Gaussian surface sampling technology, innovate in establishing the Gaussian surface surrounding the wire network, and can efficiently process the wire network containing thousands of conductors, which is hundreds of times faster than the original method.

In addition to the above steps, the gaussian surface of the first net may be established according to other schemes in the related art, which is not limited in the embodiments of the present disclosure.

In one possible implementation, the valid first sampling point may be obtained by:

step one, generating a uniformly distributed random number R between 0 and 1 ₁ According to random number R ₁ The accumulated area vector selects the Gaussian surface G of the first net _k . Wherein the first net comprises N _b Individual conductor block B _i The three-dimensional shape corresponding to the first wire net is N _b Individual conductor block B _i Each conductor block B of the first net _i Corresponding to a block Gaussian surface G _i Per block Gaussian surface G _i Not intersecting other conductor blocks than the first net, accumulating the ith component of the area vectorS _j Representing the area S of each block Gaussian surface Gi _i ，i＝1、2、…、N _b ，i≠k。

Step two, at G _k Randomly selecting a point m according to uniform distribution.

Step three, checking the points m and the block Gaussian surface G in sequence _i To discard the gaussian surface G that does not fall on the first net _k Sampling points on the sample, and obtaining n _c Is a value of (a). Wherein n is _c Indicating that if point m falls on the Gaussian surface G of the first net _k On, then point m is at n at the same time _c Block Gaussian surface G _i And (3) upper part.

Step four, generating a uniformly distributed random number R between 0 and 1 ₂ 。

Step five, judging R ₂ Whether or not it is greater than 1/n _c When R is ₂ Greater than 1/n _c Returning to the first execution step; when R is ₂ Not more than 1/n _c Generating a uniformly distributed random number R between 0 and 1 ₃ 。

Step six, judging R ₃ Whether or not it is greater than p (m)/U, when R ₃ When the ratio is greater than p (m)/U, returning to the execution step I; when R is ₃ When the value is not greater than p (m)/U, the determination point m is the Gaussian surface G of the first net _k The effective sampling point on the first net, wherein p (m) is the Gaussian surface G of the first net _k An up-sampling probability density function.

Therefore, the effective first sampling point which meets the sampling probability density distribution function corresponding to the Gaussian surface of the first net can be obtained through the steps, and the subsequent processing result obtained based on the effective first sampling point is more accurate.

In addition to the above steps, the effective first sampling point may be determined on the gaussian surface of the first net according to other schemes in the related art, which is not limited in the embodiments of the present disclosure.

After determining a valid first sampling point, a corresponding first set of symmetry points may be determined based on the first sampling point. The first set of symmetry points may include a plurality of sampling points, any one of the first set of symmetry points having a sampling point that is symmetrical about a gaussian surface, and the symmetrical sampling points also being located in the first set of symmetry points, it being understood that any one of the plurality of sampling points is not on the gaussian surface surrounding the first net.

In one possible implementation, determining the corresponding first set of symmetry points based on the first sampling points in step S201 may include: constructing a first cube, and randomly sampling on the surface of the first cube to obtain a second sampling point, wherein the first cube is used for indicating a cube which is constructed by taking the first sampling point as the center, does not overlap with a first conductor and has the largest volume, and the first conductor represents any one conductor in the integrated circuit; determining a third sampling point on the surface of the first cube from the second sampling point, the third sampling point being indicative of one or more sampling points that are symmetric with respect to the gaussian surface with the second sampling point; and determining a first symmetry point set corresponding to the first sampling point based on the second sampling point and the third sampling point. In this way, the first cube is constructed, the second sampling point and the third sampling point are determined based on the surface of the first cube, so that the first symmetry point set is obtained, the number of Gaussian surface sampling points is reduced, and the overall calculation efficiency is improved.

Fig. 3 shows a schematic diagram of a capacitance extraction method provided according to an embodiment of the present disclosure. In one placeIn the example, as shown in FIG. 3, for a Gaussian surface G located on a first wire mesh _i The effective first sampling point m1 is used for constructing a first cube T1 which is not overlapped with any conductor in the integrated circuit layout and has the largest volume by taking the first sampling point m1 as the center, randomly sampling the surface of the first cube T1 to obtain a point m2, constructing a cube T2 which is not overlapped with any conductor in the integrated circuit layout and has the largest volume by taking the point m2 as the center, randomly sampling the surface of the cube T2 to obtain a point m3, and ending the random walking if the obtained point m3 is positioned on the surface of a certain conductor. Such a series of random sampling points and finally stopping on a certain conductor surface is called a random walking path, and the path from the first sampling point m1 to m2 to m3 shown in fig. 3 is a random walking path based on the first sampling point.

In one possible implementation, the capacitance extraction method may further include setting a first parameter, where the first parameter is used to indicate a number of symmetrical randomly walking paths emitted based on the first sampling point; the number of sampling points in the first set of symmetry points is consistent with the number of symmetrical randomly walked paths indicated by the first parameter. Therefore, by setting the first parameter, a quantity basis is provided for the follow-up determination of the symmetrical point set, so that each sampling point in the follow-up symmetrical point set is used for carrying out random walking, and the whole calculation time is shortened.

In one possible implementation, the second sampling point may be located in a designated area of the surface of the first cube, and the size of the designated area may be determined according to the first parameter; the third sampling point may be located at an area of the surface of the first cube other than the designated area. Wherein the first parameter is used for indicating the number of symmetrical random walking paths sent out based on the first sampling points, and the number of the sampling points in the first symmetrical point set is consistent with the number of symmetrical random walking paths indicated by the first parameter. In this way, by determining the second sampling point on the designated area of the first cube and determining the third sampling point on the other area of the first cube based on the second sampling point, the range of random sampling is narrowed, which also contributes to shortening the overall calculation time.

The first parameter Ns may be any one of 2, 4, 8, 16. Fig. 4 shows a schematic diagram of a capacitance extraction method provided according to an embodiment of the present disclosure. As shown in fig. 4, the leftmost cube T is a cube constructed with the first sampling point r as the center, and n is the external normal vector of the gaussian surface where the first sampling point r is located at the point r. The designated area where the second sampling point is located may be obtained by processing the cube T according to the first parameter Ns. Taking Ns as 2 for example, the cube T is divided into two along the central axis where the first sampling point r is located to obtain the cube T shown in fig. 4 ₂ Cube T ₂ Is half the volume of the cube T so that the second sampling point can be located in the cube T ₂ Front, top, bottom, back, and right side of (a). The front surface, the top surface, the bottom surface, the back surface and the right side surface are all illustrated, and are not disclosed to be limited to this, and the designated area where the second sampling point can be located is actually determined according to the cube obtained by processing the first parameter Ns. When Ns takes 4, the cube T shown in FIG. 4 ₄ Is one quarter of the volume of the cube T. When Ns takes 8, the cube T shown in FIG. 4 ₈ One eighth of a cube T. When Ns takes 16, the cube T shown in FIG. 4 ₁₆ One sixteenth of a cube T.

The first parameter, also referred to as symmetric multi-emission parameter, may be used to indicate that the number of symmetric randomly walked paths emanating from the first sampling point is 2 or 4 or 8 or 16, that is, the number of sampling points in the first set of symmetry points determined based on the first sampling point is 2 or 4 or 8 or 16. The following describes the determination process of the first symmetry point set taking Ns as an example 2:

fig. 5 shows a schematic diagram of a capacitance extraction method provided according to an embodiment of the present disclosure. In one example, the first parameter Ns is set to 2. As shown in FIG. 5, to lie on a Gaussian surface G surrounding the first wire mesh ₁ Constructing a first cube T by taking a first sampling point r as a center ₁ According to the first cube T ₁ The medium distribution condition of the first cube T is obtained by searching a pre-calculated and stored jump probability table ₁ Randomly sampled probability distribution on the surface of the first cube T ₁ Is defined in a surface of a substrateI.e.Up-random sampling to obtain a second sampling point r ⁺ And according to the second sampling point r ⁺ The position of (2) is r ⁺ With respect to Gaussian surface G ₁ Symmetrical and located in a first cube T ₁ Areas s of the surface of (a) other than the specified area ₁ ^- Third sampling point r ^- Thereby determining a first symmetry point set R= { R corresponding to the first sampling point R ⁺ ,r ^- }。

Similarly, when Ns takes 2 and Ns takes 4 or 8 or 16, the first symmetry point set corresponding to the first sampling point includes Ns sampling points, one point a of Ns sampling points is located on the 1/Ns surface of the first cube corresponding to the first sampling point, positions of other Ns-1 points are obtained according to the position of the point a, other Ns-1 symmetry points of the point a symmetrical on the surface of the first cube are obtained, and Ns sampling points are symmetrical about the gaussian surface.

For the first set of symmetry points determined in step S201, a first capacitance value determined based on random walk can be obtained by performing step S202, which can be used to indicate the capacitance magnitude between the first net and the first conductor. Based on the first capacitance value determined in step S202, a first capacitance sequence may be obtained, where the first capacitance sequence may include a plurality of capacitance values between the first net and the second net determined based on random walk.

The step S202 of randomly walking based on the sampling point, stopping randomly walking until the sampling point is located on the surface of the first conductor, and determining the first capacitance value according to the position of the sampling point on the surface of the first conductor when randomly walking is stopped, may include: judging whether the sampling point is positioned on the surface of the first conductor; if the sampling point is positioned on the surface of the first conductor, determining a first capacitance value according to the position of the sampling point on the surface of the first conductor when the random walk is stopped; if the sampling point is not positioned on the surface of the first conductor, a second cube which is not overlapped with any conductor in the integrated circuit and has the largest volume is constructed by taking the sampling point as a center, a new sampling point is obtained by random sampling on the surface of the second cube, the judgment process is executed based on the new sampling point until the new sampling point is positioned on the surface of the first conductor, random walking is stopped, and a first capacitance value is determined according to the position of the new sampling point on the surface of the first conductor when the walking is stopped.

In one possible implementation, determining the first capacitance value according to the position of the sampling point on the surface of the first conductor when stopping the random walk in step S202 may include: in the case where the sampling point is located on the surface of the first conductor: if the first conductor belongs to the second wire net, determining a first capacitance value according to the position of the sampling point on the surface of the second wire net; if the first conductor does not belong to the second wire net, determining a corresponding first capacitance value according to the position of the sampling point on the surface of the first conductor, and taking zero as the capacitance value between the first wire net and the second wire net.

In one possible implementation, the determining the first capacitance value according to the position of the sampling point on the surface of the first conductor when stopping the random walk in step S202 may be determined by searching a pre-calculated and stored weight data table according to the medium distribution condition of the first cube.

In one example, the first parameter Ns is set to 2, and the second parameter N is initialized _walk Is 0. As shown in fig. 5, the number i=1 of the first net, the number j=2 of the second net, and the number j=3 of the conductor block are set. Let N _walk +1 (i.e. N at this time) _walk =1), a first symmetry point set is obtained according to the determined first sampling point R, wherein r= { R ⁺ ,r ^- }. For R in R ⁺ Firstly, judging that r is obtained by random walking based on a first sampling point r ⁺ Whether or not it is located on the surface of the first conductor, r as shown in FIG. 5 ⁺ Not on the surface of any conductor, then r ⁺ Building for the centre a second cube T which does not overlap any conductor in the integrated circuit and has the greatest volume ₅ In the second cube T ₅ Randomly sampling on the surface of the sample to obtain a new sampling point r1 ⁺ And judge r1 ⁺ Whether or not it is located on the surface of the first conductor, as shown in FIG. 5, r1 ⁺ At the surface of the second net, thereby stopping random walk and according to r1 ⁺ A first capacitance value is determined at a location of the surface of the second net, the first capacitance value representing a capacitance magnitude w1 between the first net and the second net, such that there is a first capacitance sequence C (1, 2) = { w1}, representing a capacitance between the first net and the second net, and there is a sequence C (1, 3) = {0}, representing a capacitance between the first net and the conductor block. Next, for R in R ^- Likewise, first determine r ^- Whether or not it is located on the surface of the first conductor, r as shown in FIG. 5 ^- Not on the surface of any conductor, then r ^- Building for the centre a second cube T which does not overlap any conductor in the integrated circuit and has the greatest volume ₃ In the second cube T ₃ Randomly sampling on the surface of the sample to obtain a new sampling point r1 ^- And judge r1 ^- Whether or not it is located on the surface of the first conductor, as shown in FIG. 5, r1 ⁺ Is located at the surface of the first net, stopping the random walk and yielding a first sequence of capacitances C (1, 2) = { w1,0}, while the sequence of capacitances C (1, 3) = {0,0}, representing the capacitance between the first net and the conductor block.

According to the first capacitance sequence determined in step S202, the first capacitance sequence meeting the preset condition may be processed in step S204 to obtain a final target capacitance value.

In one possible implementation manner, the capacitance extraction method may further include: determining a first average and a first variance of all capacitance values in the first capacitance sequence; judging whether a first ratio of the first variance to the first average value meets a preset threshold value or not, and if the first ratio is smaller than or equal to the preset threshold value, determining that the first capacitor sequence meets a preset condition. In this way, whether the first capacitance sequence meets the preset condition is determined by judging whether the ratio of the variance to the mean value of the first capacitance sequence is not larger than a preset threshold value, so that the whole running time can be flexibly adjusted according to the actually required data precision.

In one possible implementation, determining the target capacitance value according to the first capacitance sequence in step S204 may include: the ratio of the sum of all capacitance values in the first capacitance sequence to the second parameter is taken as a target capacitance value, and the second parameter is determined by the number of the first sampling points. In this way, the target capacitance value concerned is determined through the first capacitance sequence meeting the preset condition and the second parameter determined by the first sampling point number, the whole running time can be flexibly adjusted according to the actually required data precision, and ideal capacitance data can be extracted.

In an example, let the number i=1 of the first net and the number j=2 of the second net, the first capacitance sequence determined in step S202 be C (1, 2) = { w1, w2, w3, w4}, and the corresponding second parameter N _walk =2, calculating a first average of all capacitance values in the first capacitance sequence C (1, 2) asAnd a first difference s ² If s ² //>If the first capacitance sequence is smaller than or equal to the preset threshold value, determining that the first capacitance sequence meets the preset condition to (w1+w2+w3+w4)/N _walk As a target capacitance value, i.e., the capacitance value between the first net and the second net. If s ² //>Greater than a preset threshold, let N _walk +1, re-at the Gaussian surface G of the first net ₁ And determining a new first sampling point, so as to obtain a corresponding first symmetry point set, and further, randomly walking based on the sampling points in the first symmetry point set until the obtained first capacitance sequence meets the preset condition.

In addition to the preset conditions shown by way of example, the present disclosure is not limited to this, and it may also determine whether the first capacitor sequence reaches the desired target according to other schemes in the related art.

In one example, the extraction of interconnect capacitance parameters in VLSI circuits may be accomplished by:

step one, information describing an interconnection network of an integrated circuit is obtained, wherein the information comprises space conductor geometric information, space medium geometric information and attribute information, and the information is generally stored in a hard disk file in a certain format.

Step two, obtaining a jump probability table and a weight data table required by the random walking process. The jump probability table and the weight data table are both pre-calculated and stored as hard disk files.

Step three, the serial number of the main conductor net, namely the first net, is acquired and is set as i.

And step four, establishing a Gaussian surface Gi surrounding the first wire net. The gaussian surface Gi comprises the own gaussian surface established by each of the individual conductor blocks in the first net.

Step five, initializing a capacitance value array C _ij ＝0,I.e. the capacitance of the first net i to the other net is initialized to 0.

Step six, setting a first parameter, namely a symmetrical multi-emission parameter Ns, and initializing the number of random walking paths, namely a second parameter N _walk =0. Where Ns is 2 or 4 or 8 or 16.

Step seven, N _walk ＝N _walk +1。

Step eight, using a virtual Gaussian surface sampling technique to sample the Gaussian surface G _i And randomly sampling to obtain an effective sampling point r.

Step nine, constructing a first cube T which is the largest transfer cube with r as the center and does not overlap with the conductor.

Step ten, obtaining probability distribution for randomly sampling the surface of the first cube T by looking up a jump probability table according to the medium distribution condition of the first cube T, and then standing at the firstRandomly taking points on 1/Ns surface of square T to obtain points r ⁺ 。

Step eleven, according to point r ⁺ The position of (2) to obtain r ⁺ The other Ns-1 symmetry points, symmetrical on the surface of the first cube T, are symmetrical about the gaussian surface, making these points into a set R.

Step twelve, a sampling point R is taken out from the set R ⁽¹⁾ ：

a) If r ⁽¹⁾ Recording the conductor number j on the surface of the first conductor, searching a weight data table according to the medium distribution condition of the first cube T to obtain omega, and jumping to the step c) according to the corresponding weight; if r ⁽¹⁾ And b) is performed without being on the surface of the first conductor.

b) At point r ⁽¹⁾ Constructing a transfer cube T 'with the largest volume for the center and without overlapping any conductor, combining a jump probability table according to the medium distribution condition of the T' to obtain probability distribution for randomly sampling the surface of the transfer cube T ', and randomly taking a point r' on the surface of the T ', wherein r' is used as a new r ⁽¹⁾ For new r ⁽¹⁾ Executing a).

c)C _ij ＝C _ij +ω。

d) If the point in the set R is not taken, the step is skipped.

Step thirteen, judge C _ij If the calculated termination condition, i.e. the preset condition (see above for details) is met, if not, then jumping to step seven; if so, then the resulting array C of capacitance values representing the first net i to all other conductors j _ij The final result of the capacitance parameter to be extracted is the result.

In this way, by adopting the method that a plurality of symmetrical random walking paths are respectively sent out from each effective sampling point on the Gaussian surface surrounding the first wire net, the number of Gaussian surface sampling points is reduced while the same accurate result is achieved under the condition that the same random error of the result is met, and the whole calculation time can be shortened through fewer Gaussian surface sampling points. Through calculation experiments on structures in an actual integrated circuit, the times of the reduction of the calculation time obtained through verification can reach 2 to 8 times.

The embodiment of the disclosure also provides a capacitor extraction device based on random walk. Fig. 6 shows a block diagram of a capacitance extraction device provided according to an embodiment of the present disclosure. As shown in fig. 6, the capacitance extracting apparatus 600 may include:

a first determining module 601, where the first determining module 601 is configured to randomly sample on a gaussian surface surrounding a first net to obtain a first sampling point, and determine a corresponding first symmetry point set based on the first sampling point, where the first net is formed by connecting a plurality of conductors in an integrated circuit, the first symmetry point set includes a plurality of sampling points, any sampling point in the first symmetry point set has a sampling point symmetrical about the gaussian surface, and the symmetrical sampling point is also located in the first symmetry point set;

a second determining module 602, the second determining module 602 being configured to, for each sampling point in the first set of symmetry points, perform a random walk based on the sampling point, stop the random walk until the sampling point is located on a surface of a first conductor, and determine a first capacitance value according to a position of the sampling point on the surface of the first conductor when the random walk is stopped, the first conductor representing any one of the conductors in the integrated circuit, the first capacitance value being indicative of a capacitance magnitude between the first net and the first conductor;

A third determining module 603, the third determining module 603 being configured to determine a first capacitance sequence according to the first capacitance value, the first capacitance sequence comprising a plurality of capacitance values between a first net and a second net determined based on random walk, the second net being composed of a plurality of conductor connections in the integrated circuit and being independent of the first net;

a fourth determining module 604, where the fourth determining module 604 is configured to determine a target capacitance value according to the first capacitance sequence if the first capacitance sequence meets a preset condition; and if the first capacitance sequence does not meet the preset condition, repeating the random sampling and random walking processes until the first capacitance sequence meets the preset condition, wherein the target capacitance value is used for indicating the capacitance between the first wire net and the second wire net.

In some embodiments, the functions or modules included in the capacitance extraction device provided in the embodiments of the present disclosure may be used to perform the method described in the foregoing capacitance extraction method embodiment, and the specific implementation thereof may refer to the description of the foregoing capacitance extraction method embodiment, which is not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the capacitance extraction method described above. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.

In some embodiments, functions or modules included in the computer readable storage medium provided by the embodiments of the present disclosure may be used to perform the method described in the foregoing embodiments of the capacitance extraction method, and specific implementation thereof may refer to the description of the foregoing embodiments of the capacitance extraction method, which is not repeated herein for brevity.

The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; the processor is configured to implement the capacitance extraction method when executing the instructions stored in the memory.

In some embodiments, functions or modules included in the electronic device provided by the embodiments of the present disclosure may be used to perform the method described in the foregoing embodiments of the capacitance extraction method, and specific implementation thereof may refer to the description of the foregoing embodiments of the capacitance extraction method, which is not repeated herein for brevity.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

In some embodiments, a function or a module included in a computer program product provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing embodiments of the capacitance extraction method, and a specific implementation of the method may refer to the description of the foregoing embodiments of the capacitance extraction method, which is not repeated herein for brevity.

Fig. 7 is a block diagram of an apparatus for performing a capacitance extraction method provided in accordance with an embodiment of the present disclosure. For example, the apparatus 1900 may be provided as a server or terminal device. Referring to fig. 7, the apparatus 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.

The apparatus 1900 may further comprise a power component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input/output interface 1958 (I/O interface). The apparatus 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server ^TM ，Mac OS X ^TM ，Unix ^TM ,Linux ^TM ，FreeBSD ^TM Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of apparatus 1900 to perform the above-described methods.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. The capacitor extraction method based on random walk is characterized by comprising the following steps:

2. The method according to claim 1, wherein the method further comprises: setting a first parameter, wherein the first parameter is used for indicating the number of symmetrical random walking paths sent out based on the first sampling point;

the number of sampling points in the first symmetry point set is consistent with the number of symmetrical random walking paths indicated by the first parameter.

3. The method of claim 2, wherein the determining a respective first set of symmetry points based on the first sampling points comprises:

Constructing a first cube, and randomly sampling on the surface of the first cube to obtain a second sampling point, wherein the first cube is used for indicating a cube which is constructed by taking the first sampling point as a center, does not overlap with the first conductor and has the largest volume;

determining a third sampling point on the surface of the first cube from the second sampling point, the third sampling point being used to indicate one or more sampling points that are symmetrical to the second sampling point about the gaussian surface;

and determining a first symmetry point set corresponding to the first sampling point based on the second sampling point and the third sampling point.

4. A method according to claim 3, wherein the second sampling point is located in a designated area of the surface of the first cube, the size of the designated area being determined in accordance with the first parameter;

the third sampling point is located in an area of the surface of the first cube other than the designated area.

5. The method of claim 1, wherein the randomly walking based on the sampling point until the sampling point is on a surface of a first conductor, and determining a first capacitance value based on a position of the sampling point on the surface of the first conductor when the randomly walking is stopped, comprises:

Judging whether the sampling point is positioned on the surface of the first conductor or not:

if the sampling point is positioned on the surface of the first conductor, determining the first capacitance value according to the position of the sampling point on the surface of the first conductor when stopping the random walk;

if the sampling point is not located on the surface of the first conductor, a second cube which is not overlapped with any conductor in the integrated circuit and has the largest volume is built by taking the sampling point as a center, a new sampling point is obtained by random sampling on the surface of the second cube, the random walking is stopped based on the new sampling point until the new sampling point is located on the surface of the first conductor, and the first capacitance value is determined according to the position of the new sampling point on the surface of the first conductor when the walking is stopped.

6. The method of claim 1, wherein determining the first capacitance value based on the location of the sampling point on the surface of the first conductor while stopping the random walk comprises:

in the case where the sampling point is located on the surface of the first conductor:

if the first conductor belongs to the second wire net, determining the first capacitance value according to the position of the sampling point on the surface of the second wire net;

If the first conductor does not belong to the second wire net, determining a corresponding first capacitance value according to the position of the sampling point on the surface of the first conductor, and taking zero as the capacitance value between the first wire net and the second wire net.

7. The method according to claim 1, wherein the method further comprises:

determining a first average and a first variance of all capacitance values in the first capacitance sequence;

judging whether a first ratio of the first variance to the first average value meets a preset threshold value or not, and if the first ratio is smaller than or equal to the preset threshold value, determining that the first capacitance sequence meets the preset condition.

8. The method of claim 7, wherein said determining a target capacitance value from said first capacitance sequence comprises:

and taking the ratio of the sum of all capacitance values in the first capacitance sequence to a second parameter as the target capacitance value, wherein the second parameter is determined by the number of the first sampling points.

9. A capacitance extraction device based on random walk, characterized by comprising:

10. The apparatus of claim 9, wherein the apparatus further comprises: a parameter setting module configured to set a first parameter for indicating a number of symmetrical randomly walked paths issued based on the first sampling point;

11. The apparatus of claim 10, wherein the determining the respective first set of symmetry points based on the first sampling points comprises:

12. The apparatus of claim 11, wherein the second sampling point is located at a designated area of the surface of the first cube, the designated area being sized according to the first parameter;

13. The apparatus of claim 9, wherein the randomly walking based on the sampling point until the sampling point is located on a surface of a first conductor, and wherein determining a first capacitance value based on a position of the sampling point on the surface of the first conductor when the randomly walking is stopped, comprises:

14. The apparatus of claim 9, wherein the determining a first capacitance value based on the location of the sampling point on the surface of the first conductor while stopping the random walk comprises:

15. The apparatus of claim 9, wherein the apparatus further comprises:

a fifth determination module configured to determine a first average and a first variance of all capacitance values in the first sequence of capacitances;

the judging module is configured to judge whether a first ratio of the first variance to the first average value meets a preset threshold, and if the first ratio is smaller than or equal to the preset threshold, the first capacitor sequence is determined to meet the preset condition.

16. The apparatus of claim 15, wherein said determining a target capacitance value from said first capacitance sequence comprises:

17. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the capacitance extraction method of any one of claims 1 to 8 when executing the instructions stored by the memory.

18. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the capacitance extraction method of any one of claims 1 to 8.