CN116501507A - Method for interrupt processing, interrupt control module, processor, and storage medium - Google Patents
Method for interrupt processing, interrupt control module, processor, and storage medium Download PDFInfo
- Publication number
- CN116501507A CN116501507A CN202310772043.0A CN202310772043A CN116501507A CN 116501507 A CN116501507 A CN 116501507A CN 202310772043 A CN202310772043 A CN 202310772043A CN 116501507 A CN116501507 A CN 116501507A
- Authority
- CN
- China
- Prior art keywords
- core
- interrupt
- resource channel
- target
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000012545 processing Methods 0.000 title claims abstract description 31
- 108091006146 Channels Proteins 0.000 claims description 227
- 230000004044 response Effects 0.000 claims description 4
- 239000000284 extract Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 9
- 238000004891 communication Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- 230000001174 ascending effect Effects 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000013468 resource allocation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to the technical field of integrated circuits and discloses a method for interrupt processing, which is applied to a processor comprising a first core and a second core, wherein a plurality of resource channels share and use an interrupt source, the interrupt source is mapped to the first core and the second core, the plurality of resource channels comprise a first resource channel corresponding to the first core, and a second resource channel corresponding to the second core; the method comprises the following steps: in a plurality of resource channels, when the resource channel is interrupted, an interrupt trigger instruction is generated; responding to an interrupt trigger instruction, and selecting a target resource channel by the current core; the current core is a first core or a second core; the current core determines a target core corresponding to the target resource channel; and executing the interrupt operation of the resource channel by the current core according to the matching condition of the current core and the target core. The utility model can promote the utilization ratio of resource channel. The application also discloses an interrupt control module, a processor and a storage medium.
Description
Technical Field
The present application relates to the field of integrated circuit technology, for example, to a method for interrupt processing, and an interrupt control module, a processor, and a storage medium.
Background
Currently, chip peripherals are increasingly powerful, and many IPs (Intellectual Property Core, reusable design modules with proprietary intellectual property in semiconductor integrated circuit designs) have multiple sources of interruption. The number of interrupt sources can be reduced to a certain extent by adopting a mode that adjacent or similar resources share one interrupt source, so that the utilization rate of the interrupt sources is improved.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
however, different vendors all require a scheme of respectively allocating adjacent resource channels or similar resource channels to different cores to avoid sharing the interrupt source. With the increase of chip cost and the increasing of resource demand, the resource channel is necessarily in shortage under the application scene of the multi-core chip with shortage of resources. Thus, reasonable allocation cannot be realized by the resource channels, and the utilization rate of the resource channels is low.
It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
The embodiment of the disclosure provides a method for interrupt processing, an interrupt control module, a processor and a storage medium, so as to improve the utilization rate of a resource channel.
In some embodiments, the method is applied to a processor comprising a first core and a second core, a plurality of resource channels share use of one interrupt source, the interrupt source mapped to the first core and the second core, the plurality of resource channels comprising a first resource channel corresponding to the first core, and a second resource channel corresponding to the second core; the method comprises the following steps: in a plurality of resource channels, when the resource channel is interrupted, an interrupt trigger instruction is generated; responding to an interrupt trigger instruction, and selecting a target resource channel by the current core; the current core is a first core or a second core, and the target resource channel is a first resource channel or a second resource channel; the current core determines a target core corresponding to the target resource channel; and executing the interrupt operation of the resource channel by the current core according to the matching condition of the current core and the target core.
In some embodiments, the current core performs an interrupt operation of the resource channel according to a matching condition of the current core and the target core, including: under the condition that the current core is matched with the target core, acquiring an interrupt identifier of the target resource channel; and executing the interrupt operation of the target resource channel under the condition that the interrupt identifier indicates that the target resource channel is in an interrupt trigger state.
In some embodiments, the identity of the first core and the second core are different, and the current core is determined to match the target core in the following manner: the identity of the current core is the same as the identity of the target core.
In some embodiments, the current core performs an interrupt operation of the resource channel according to a matching condition between the current core and the target core, and further includes: under the condition that the current core is not matched with the target core, the current core selects a non-selected target resource channel as a new target resource channel; determining a new target core corresponding to the new target resource channel; and executing the interrupt operation of the new target resource channel by the current core according to the matching condition of the current core and the new target core.
In some embodiments, the interrupt trigger instruction includes a channel number of each of the first resource channel and the second resource channel, and the selecting, by the current core, the target resource channel in response to the interrupt trigger instruction includes: the current core extracts respective channel serial numbers of the first resource channel and the second resource channel from the interrupt trigger instruction; the current core randomly selects a resource channel corresponding to a channel sequence number as a target resource channel.
In some embodiments, the first resource channel is disposed adjacent to the second resource channel.
In some embodiments, the interrupt control module comprises a processing unit and a first storage unit storing program instructions, the processing unit being configured to perform the method for interrupt processing as described above when running the program instructions.
In some embodiments, the processor comprises: the first core and the second core are configured with the interrupt control module; the second storage unit is used for storing configuration information, wherein the configuration information comprises a corresponding relation between the first core and the first resource channel and a corresponding relation between the second core and the second resource channel.
In some embodiments, the processor further comprises: a first interrupt status register configured to store an interrupt identification to indicate an interrupt trigger status of the first resource channel; a second interrupt status register is adapted to store an interrupt identification indicating an interrupt trigger status of the second resource channel.
In some embodiments, the storage medium stores program instructions that, when executed, perform a method for interrupt processing as described above.
The method for interrupt processing, the interrupt control module, the processor and the storage medium provided by the embodiment of the disclosure can realize the following technical effects:
and generating an interrupt trigger instruction when the resource channel interrupt occurs. The current core responds to the interrupt trigger instruction, a target resource channel is selected from the resource channels with interrupt, and then the target core corresponding to the target resource channel is determined. And finally, executing the interrupt operation of the resource channel according to the matching condition of the resource channel and the target core. Thus, the current core can know whether the corresponding resource channel is interrupted or not. On the basis of sharing the resource channel, accurate judgment of interrupt processing is realized, and the utilization rate of the resource channel is improved.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a hardware schematic of a processor provided by an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a method for interrupt handling provided by an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another method for interrupt handling provided by an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another method for interrupt handling provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of another method for interrupt handling provided by an embodiment of the present disclosure;
FIG. 6 is a schematic illustration of one application of an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of an interrupt control module provided by an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise indicated.
In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.
The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.
In the embodiment of the disclosure, the processor is a multi-core processor, and a plurality of resource channels share one interrupt source. The interrupt sources are mapped to the first core and the second core. The plurality of resource channels includes a first resource channel corresponding to the first core and a second resource channel corresponding to the second core.
In this way, when the first core and the second core share and use one interrupt source and the interrupt source is mapped to the first core and the second core, and any one of the resource channels is interrupted, the interrupted resource channel correspondingly generates an interrupt trigger instruction and sends the interrupt trigger instruction to the first core and the second core through the interrupt source.
As an example, as shown in connection with fig. 1, the plurality of resource channels includes a first resource channel CH 2n Second resource channel CH 2n+1 . First resource channel CH 2n And a second resource channel CH 2n+1 Sharing an interrupt source. Mapping interrupt sources to a first Core using an interrupt control module 0 And a second Core 1 。
Based on the above processor, referring to fig. 2, an embodiment of the disclosure provides a method for interrupt processing, applied to a processor including a first core and a second core, the method including:
and S01, in the plurality of resource channels, when the resource channel is interrupted, an interrupt trigger instruction is generated.
S02, responding to an interrupt trigger instruction, and selecting a target resource channel by the current core. The current core is a first core or a second core, and the target resource channel is a first resource channel or a second resource channel.
S03, the current core determines a target core corresponding to the target resource channel.
S04, executing the interrupt operation of the resource channel by the current core according to the matching condition of the current core and the target core.
By adopting the method for interrupt processing provided by the embodiment of the disclosure, an interrupt trigger instruction is generated when the resource channel is interrupted. The current core responds to the interrupt trigger instruction, a target resource channel is selected from the resource channels with interrupt, and then the target core corresponding to the target resource channel is determined. And finally, executing the interrupt operation of the resource channel according to the matching condition of the resource channel and the target core. Thus, the current core can know whether the corresponding resource channel is interrupted or not. On the basis of sharing the resource channel, accurate judgment of interrupt processing is realized, and the utilization rate of the resource channel is improved. Meanwhile, the resource allocation from any resource channel to any core is realized, and the number of the resource channels is increased.
The execution body of the method for interrupt processing is a first core or a second core. Because the first core and the second core share and use a plurality of resource channels, when any one of the resource channels is interrupted, the interrupted resource channel simultaneously sends an interrupt trigger instruction to the first core and the second core. After receiving the interrupt trigger instruction, the first core and the second core may execute steps S02 to S04 simultaneously, or may sequentially execute steps S02 to S04. Regarding the execution sequence of the first core and the second core, embodiments of the present disclosure may not be specifically limited. It can be understood that, when the first core and the second core execute steps S02 to S04 simultaneously, the response speed of the interrupt can be improved.
In addition, in practical applications, steps S02 to S04 may be executed by the interrupt handling function of the first core or the interrupt handling function of the second core.
Optionally, as shown in connection with fig. 2, the current core performs an interrupt operation of the resource channel according to a matching condition between the current core and the target core, including:
s11, under the condition that the current core is matched with the target core, the current core acquires the interrupt identification of the target resource channel.
S12, under the condition that the interrupt identifier indicates that the target resource channel is in an interrupt trigger state, the current core executes the interrupt operation of the target resource channel.
Therefore, under the condition that the current core is matched with the target core, the current core also judges the interrupt triggering state of the target resource channel again so as to accurately judge whether the target resource channel is triggered to be interrupted or not. Therefore, in the embodiment of the present disclosure, after the current core is matched with the target core, the interrupt identifier of the target resource channel is obtained, and when the interrupt identifier indicates that the target resource channel is in the interrupt trigger state, the interrupt operation of the target resource channel is executed. Therefore, on the basis of sharing the resource channels, the method is favorable for accurately judging interrupt processing, improving the utilization rate of the resource channels, realizing resource allocation from any resource channel to any core, and being favorable for increasing the number of the resource channels.
It should be noted that, when the current core is matched with the target core, after the current core obtains the interrupt identifier of the target resource channel, the method further includes: in the event that the interrupt identification indicates that the target resource channel is not in the interrupt triggered state, the current core does not perform any operations.
Optionally, the identity of the first core is different from the identity of the second core. The current core determines that the current core matches the target core in the following manner:
the identity of the current core is the same as the identity of the target core.
Thus, the identity of the first core is different from the identity of the second core. When the embodiment of the disclosure judges that the identifier of the current core is the same as the identifier of the target core, it can be determined that the current core is matched with the target core. The method is beneficial to realizing accurate judgment of interrupt processing.
It will be appreciated that when the identity of the current core is different from the identity of the target core, the current core determines that the current core does not match the target core.
Optionally, as shown in connection with fig. 4, the current core performs an interrupt operation of the resource channel according to a matching situation between the current core and the target core, and further includes:
s21, under the condition that the current core is not matched with the target core, the current core selects the unselected target resource channel as a new target resource channel.
S22, the current core determines a new target core corresponding to the new target resource channel.
S23, the current core executes interrupt operation of the new target resource channel according to the matching condition of the current core and the new target core.
Thus, when the current core is not matched with the target core, the current core selects the unselected target resource channel as a new target resource channel, and determines a new target core corresponding to the new target resource channel. And executing the interrupt operation of the new target resource channel according to the matching condition of the new target resource channel and the new target core. Thus, the current core can sequentially execute interrupt judgment of different resource channels, and the utilization rate of the resource channels is improved.
It can be understood that, in the case that the current core is the first core or the second core, the first core performs steps S02 to S04 at most twice, and the second core performs steps S02 to S04 at most twice, so that a resource channel in which an interrupt operation needs to be performed can be determined, and a corresponding interrupt operation is performed. Thus, on the basis of sharing the resource channel, false triggering of the interrupt operation of the resource channel is avoided.
In addition, the method for interrupt processing provided by the embodiment of the present disclosure may be extended to a processor including more than three cores.
Optionally, the interrupt trigger instruction includes a channel sequence number of each of the first resource channel and the second resource channel.
Referring to fig. 5, in response to an interrupt trigger instruction, the current core selects a target resource channel, including:
s31, the current core extracts the channel serial numbers of the first resource channel and the second resource channel from the interrupt trigger instruction.
S32, the current core randomly selects a resource channel corresponding to a channel sequence number as a target resource channel.
Thus, the current core can traverse all the resource channels, interrupt judgment is carried out on the selected target resource channel, and the reliability of the interrupt judgment of the resource channel is improved.
Optionally, the current core randomly selects a resource channel corresponding to a channel sequence number as the target resource channel, including: the current core sorts the different channel numbers. The current core selects a resource channel corresponding to the smallest channel sequence number from the ordered channel sequence numbers as a target resource channel, or the current core selects a resource channel corresponding to the largest channel sequence number from the ordered channel sequence numbers as the target resource channel.
As an example, the channel number of the first resource channel is 2n, and the channel number of the second resource channel is 2n+1. Wherein n is a positive integer. The current core randomly selects a resource channel corresponding to a channel sequence number as a target resource channel, and the method comprises the following steps: the current core performs an ascending sort (2n, 2n+1) of the different channel numbers. The current core selects a resource channel corresponding to the smallest channel number 2n from the channel numbers in ascending order as a target resource channel.
Optionally, the first resource channel is disposed adjacent to the second resource channel.
Thus, the current core can traverse all the resource channels, and the interrupt judgment reliability of the resource channels is improved.
Optionally, the processor determines that the first resource channel is disposed adjacent to the second channel in the following manner: the absolute value of the difference between the channel identification of the first resource channel and the channel identification of the second resource channel is equal to 1. As an example, the channel number of the first resource channel is 2m and the channel number of the second resource channel is 2m+1. Wherein m is a positive integer.
In practical application, as shown in fig. 6, the first resource channel is CH 2 The second resource channel is CH 3 . The processor includes a first Core 0 And a second Core 1 . First Core 0 With the first resource channel CH 2 Has a corresponding relationship. Second Core 1 And a second resource channel CH 3 Has a corresponding relationship.
The method for interrupt handling specifically performs the steps of:
s101, when the second resource channel CH occurs 3 At the time of interruptionSecond resource channel CH 3 And generating an interrupt trigger instruction and sending the interrupt trigger instruction to the first core and the second core.
S102, responding to an interrupt trigger instruction, and selecting a target resource channel as a first resource channel CH by the current core 2 . Wherein the current Core is a first Core 0 Or a second Core 1 . Step S103 and step S110 are performed.
S103, first Core 0 Determining a target resource channel CH 3 The corresponding target Core is the second Core 1 。
S104, the first Core is confirmed 0 With the target Core 1 Step S105 is performed if there is no match. S105, first Core 0 Selecting a first resource channel CH 2 As a new target resource channel.
S106, first Core 0 Determining a first resource channel CH 2 The corresponding new target Core is the first Core 0 。
S107, confirmed, the first Core 0 Matching with the new target core, step S108 is performed.
S108, first Core 0 Acquiring a first resource channel CH 2 Is provided.
S109, after confirmation, the interrupt identifier indicates that the target resource channel is not in the interrupt trigger state, the first Core 0 No operation is performed.
S110, second Core 1 Determining a target resource channel CH 3 The corresponding target Core is the second Core1.
S111, confirmed, second Core 1 With the target Core 1 Matching, step S110 is performed.
S112, second Core 1 Acquiring a second resource channel CH 3 Is provided.
S113, through confirmation, the interrupt identifier represents the second resource channel CH 3 In an interrupt triggered state, the second Core 1 Executing the second resource channel CH 3 Is of (2)And (3) operating.
As shown in connection with fig. 7, an embodiment of the present disclosure provides an interrupt control module including a processing unit (processor) 400 and a first memory unit (memory) 401. Optionally, the apparatus may further comprise a communication interface (Communication Interface) 402 and a bus 403. The processing unit 400, the communication interface 402, and the first storage unit 401 may perform communication with each other through the bus 403. The communication interface 402 may be used for information transfer. The processing unit 400 may call logic instructions in the first storage unit 401 to perform the method for interrupt handling of the above-described embodiment.
Further, the logic instructions in the first storage unit 401 described above may be implemented in the form of a software functional unit and may be stored in a computer readable storage medium when sold or used as a separate product.
The first storage unit 401 serves as a computer readable storage medium, and may be used to store a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processing unit 400 executes the functional application and the data processing by executing the program instructions/modules stored in the first storage unit 401, that is, implements the method for interrupt processing in the above-described embodiment.
The first storage unit 401 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functions; the storage data area may store data created according to the use of the terminal device, etc. Further, the first storage unit 401 may include a high-speed random access memory, and may also include a nonvolatile memory.
The disclosed embodiments provide a processor, comprising: a first core, a second core, and a second memory unit. The first core and the second core are configured with means for interrupt handling as described above. And a second storage unit storing configuration information. The configuration information comprises a corresponding relation between the first core and the first resource channel and a corresponding relation between the second core and the second resource channel.
Optionally, the processor further includes a first interrupt status register and a second interrupt status register. A first interrupt status register configured to store an interrupt identification to indicate an interrupt trigger status of the first resource channel. A second interrupt status register is adapted to store an interrupt identification indicating an interrupt trigger status of the second resource channel. In this way, the interrupt control module is further configured to read the interrupt identifier stored in the first interrupt status register to obtain the interrupt trigger status of the first resource channel, or to read the interrupt identifier stored in the second interrupt status register to obtain the interrupt trigger status of the second resource channel.
Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for interrupt processing.
The computer readable storage medium may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.
Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium including: a plurality of media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or a transitory storage medium.
The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.
Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A method for interrupt processing, applied to a processor comprising a first core and a second core, characterized in that a plurality of resource channels share one interrupt source, the interrupt source being mapped to the first core and the second core, the plurality of resource channels comprising a first resource channel corresponding to the first core and a second resource channel corresponding to the second core; the method comprises the following steps:
in a plurality of resource channels, when the resource channel is interrupted, an interrupt trigger instruction is generated;
responding to an interrupt trigger instruction, and selecting a target resource channel by the current core; the current core is a first core or a second core, and the target resource channel is a first resource channel or a second resource channel;
the current core determines a target core corresponding to the target resource channel;
and executing the interrupt operation of the resource channel by the current core according to the matching condition of the current core and the target core.
2. The method according to claim 1, wherein the current core performs an interrupt operation of the resource channel according to a matching condition between the current core and the target core, including:
under the condition that the current core is matched with the target core, acquiring an interrupt identifier of the target resource channel;
and executing the interrupt operation of the target resource channel under the condition that the interrupt identifier indicates that the target resource channel is in an interrupt trigger state.
3. The method of claim 2, wherein the identity of the first core and the second core are different, and wherein the current core and the target core are determined to match in the following manner:
the identity of the current core is the same as the identity of the target core.
4. The method according to claim 2, wherein the current core performs an interrupt operation of the resource channel according to a matching condition between the current core and the target core, further comprising:
under the condition that the current core is not matched with the target core, the current core selects a non-selected target resource channel as a new target resource channel;
determining a new target core corresponding to the new target resource channel;
and the current core executes the interrupt operation of the new target resource channel according to the matching condition of the current core and the new target core.
5. The method according to any one of claims 1 to 4, wherein the interrupt trigger instruction includes a channel number of each of the first resource channel and the second resource channel, and the selecting, by the current core, the target resource channel in response to the interrupt trigger instruction includes:
the current core extracts respective channel serial numbers of the first resource channel and the second resource channel from the interrupt trigger instruction;
the current core randomly selects a resource channel corresponding to a channel sequence number as a target resource channel.
6. The method of any of claims 1 to 4, wherein the first resource channel is disposed adjacent to the second resource channel.
7. An interrupt control module comprising a processing unit and a first storage unit storing program instructions, wherein the processing unit is configured to perform the method for interrupt processing according to any of claims 1 to 6 when executing the program instructions.
8. A processor, comprising:
a first core and a second core configured with the interrupt control module of claim 7;
the second storage unit is used for storing configuration information, wherein the configuration information comprises a corresponding relation between the first core and the first resource channel and a corresponding relation between the second core and the second resource channel.
9. The processor of claim 8, further comprising:
a first interrupt status register configured to store an interrupt identification to indicate an interrupt trigger status of the first resource channel;
a second interrupt status register is adapted to store an interrupt identification indicating an interrupt trigger status of the second resource channel.
10. A storage medium storing program instructions which, when executed, perform a method for interrupt processing according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310772043.0A CN116501507B (en) | 2023-06-28 | 2023-06-28 | Method for interrupt processing, interrupt control module, processor, and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310772043.0A CN116501507B (en) | 2023-06-28 | 2023-06-28 | Method for interrupt processing, interrupt control module, processor, and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116501507A true CN116501507A (en) | 2023-07-28 |
| CN116501507B CN116501507B (en) | 2023-10-24 |
Family
ID=87327050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310772043.0A Active CN116501507B (en) | 2023-06-28 | 2023-06-28 | Method for interrupt processing, interrupt control module, processor, and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116501507B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180373633A1 (en) * | 2017-06-27 | 2018-12-27 | Intel Corporation | System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms |
| CN111831412A (en) * | 2020-07-01 | 2020-10-27 | Oppo广东移动通信有限公司 | Interrupt processing method and device, storage medium and electronic equipment |
| CN114595186A (en) * | 2022-05-09 | 2022-06-07 | 深圳比特微电子科技有限公司 | Inter-core communication method and communication device of multi-core processor |
| WO2022116755A1 (en) * | 2020-12-03 | 2022-06-09 | 哲库科技(北京)有限公司 | Crash machine information storage method for multi-core system, medium and electronic device |
| CN115827269A (en) * | 2022-11-18 | 2023-03-21 | 北醒（北京）光子科技有限公司 | Inter-core communication channel construction method and device, storage medium and laser radar |
| CN115840621A (en) * | 2021-09-18 | 2023-03-24 | 炬芯科技股份有限公司 | Interaction method and related device of multi-core system |
| CN116257364A (en) * | 2023-05-12 | 2023-06-13 | 苏州浪潮智能科技有限公司 | Method and device for occupying resources among systems, storage medium and electronic device |
-
2023
- 2023-06-28 CN CN202310772043.0A patent/CN116501507B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180373633A1 (en) * | 2017-06-27 | 2018-12-27 | Intel Corporation | System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms |
| CN111831412A (en) * | 2020-07-01 | 2020-10-27 | Oppo广东移动通信有限公司 | Interrupt processing method and device, storage medium and electronic equipment |
| WO2022116755A1 (en) * | 2020-12-03 | 2022-06-09 | 哲库科技(北京)有限公司 | Crash machine information storage method for multi-core system, medium and electronic device |
| CN115840621A (en) * | 2021-09-18 | 2023-03-24 | 炬芯科技股份有限公司 | Interaction method and related device of multi-core system |
| CN114595186A (en) * | 2022-05-09 | 2022-06-07 | 深圳比特微电子科技有限公司 | Inter-core communication method and communication device of multi-core processor |
| CN115827269A (en) * | 2022-11-18 | 2023-03-21 | 北醒（北京）光子科技有限公司 | Inter-core communication channel construction method and device, storage medium and laser radar |
| CN116257364A (en) * | 2023-05-12 | 2023-06-13 | 苏州浪潮智能科技有限公司 | Method and device for occupying resources among systems, storage medium and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116501507B (en) | 2023-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109784930B (en) | Block chain transaction data processing method and device, electronic equipment and medium | |
| CN102542192B (en) | Method and device for carrying out selective starting on USB (Universal Serial Bus) device, and computer terminal | |
| US20180129574A1 (en) | Central Processing Unit CPU Hot-Remove Method and Apparatus, and Central Processing Unit CPU Hot-Add Method and Apparatus | |
| CN106844055B (en) | Task execution method and device | |
| CN105808342B (en) | method, judgment device and system for distributing client request | |
| CN111597040A (en) | Resource allocation method, device, storage medium and electronic equipment | |
| CN112000019B (en) | Method, device and equipment for sharing equipment instruction control | |
| CN116501507B (en) | Method for interrupt processing, interrupt control module, processor, and storage medium | |
| CN103164492A (en) | File copying method between electronic devices and electronic devices | |
| CN104123188A (en) | Resource allocating method and related devices | |
| CN107566543B (en) | Node identifier setting method and device | |
| CN101493808B (en) | Serial using method and multi-core processor | |
| CN103701587A (en) | Multi-interface cryptographic module parallel scheduling method | |
| CN105892995A (en) | Minus searching method and device as well as processor | |
| CN112783971B (en) | Transaction recording method, transaction query method, electronic device and storage medium | |
| CN102638403B (en) | Method and device for processing messages | |
| CN105138406A (en) | Task processing method, task processing device and task processing system | |
| CN115345131A (en) | Method and device for constructing hierarchical relationship tree and electronic equipment | |
| CN114418147A (en) | Method and device for processing abnormity of main charging module, terminal and storage medium | |
| CN115687223A (en) | Method and device for serial port communication of embedded equipment, embedded equipment and storage medium | |
| CN113157603A (en) | Data reading device, method, chip, computer equipment and storage medium | |
| CN111355642B (en) | Distributed equipment condition judgment method and system | |
| CN117762841A (en) | Method and device for DMA (direct memory access) arbitration and DMA arbiter | |
| CN117270766A (en) | Data storage architecture, method for data storage, electronic device and storage medium | |
| CN111597039B (en) | Method, device and equipment for optimizing memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |