CN116501237A - Solid-state storage AI coprocessor and solid-state storage system - Google Patents

Solid-state storage AI coprocessor and solid-state storage system Download PDF

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Publication number
CN116501237A
CN116501237A CN202210062548.3A CN202210062548A CN116501237A CN 116501237 A CN116501237 A CN 116501237A CN 202210062548 A CN202210062548 A CN 202210062548A CN 116501237 A CN116501237 A CN 116501237A
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coprocessor
memory
solid
firmware
flash memory
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潘玉茜
陈毅成
肖军
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Futurepath Technology Co ltd
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Futurepath Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0622—Securing storage systems in relation to access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Human Computer Interaction (AREA)
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  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
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Abstract

The invention discloses a solid-state storage AI coprocessor and a solid-state storage system, and relates to the technical field of solid-state storage. The solid-state storage AI coprocessor comprises a central processing unit, a memory, an encryption coprocessor, an AI coprocessor, a firmware protection coprocessor and a communication interface which are connected through a data bus, wherein the central processing unit is used for executing various instructions related to a solid-state storage function; the memory is used for storing data; the encryption coprocessor is used for encrypting and decrypting the data in the memory and verifying the identity of the visitor; the AI coprocessor is used for carrying out durability detection and life prediction on the externally connected flash memory chip and providing a hardware acceleration function; the firmware protection coprocessor is used for protecting the firmware from being tampered with maliciously and repairing the firmware. The solid-state memory AI coprocessor can greatly improve the flash memory management function of the solid-state memory, thereby effectively improving the read-write performance of the solid-state memory.

Description

Solid-state storage AI coprocessor and solid-state storage system
Technical Field
The invention relates to the technical field of solid-state storage, in particular to a solid-state storage AI coprocessor and a solid-state storage system.
Background
Solid state memories, abbreviated as SSDs, can be classified into flash-based SSDs and DRAM-based SSDs, depending on the storage medium. The SSD based on the FLASH memory is quite common, the SSD solid-state memory adopts a FLASH chip as a storage medium, the appearance forms are quite various, such as a notebook hard disk, a micro hard disk, a USB FLASH disk and the like, the SSD solid-state memory has the greatest advantages of being movable, the data protection is not controlled by a power supply, and the SSD solid-state memory is suitable for various environments and is quite suitable for personal users.
Because the FLASH chip is used as a storage medium and has no mechanical structure, the data searching time, the delay time and the seek time are omitted, the response speed is high, but at the same time, the number of writing operations of the FLASH memory is limited, if 10 ten thousand writing operations are performed on some units, the writing reliability of the subsequent units cannot be ensured, and some units can be invalid, so that the data reading and writing speeds and performances of the solid-state memory are severely limited, and the service life of the SSD disk can be even influenced.
At present, flash memory management of a solid-state memory, such as wear-leveling, bad block management, encryption authentication and the like, is performed by a controller in the solid-state memory, however, as the data storage amount in a flash memory chip is larger and larger, the data storage scene is more and more complex, the difficulty of flash memory management is multiplied, and the flash memory management and the bad block management and the encryption authentication all have heavy burdens on the controller in the solid-state memory, so that the read-write performance of the solid-state memory is finally reduced.
Disclosure of Invention
In view of this, the present invention provides a solid-state memory AI coprocessor and a solid-state memory system, which mainly aims to solve the technical problem that flash memory management may cause the decrease of the read-write performance of the solid-state memory.
To achieve the above object, the present invention provides a solid-state memory AI coprocessor comprising a central processing unit, a memory, an encryption coprocessor, an AI coprocessor, a firmware protection coprocessor and a communication interface, wherein,
the central processing unit, the memory, the encryption coprocessor, the AI coprocessor, the firmware protection coprocessor and the communication interface are connected through a data bus;
the central processing unit is used for executing various instructions related to the solid-state storage function; the memory is used for storing data; the encryption coprocessor is used for encrypting and decrypting the data in the memory and verifying the identity of the visitor; the AI coprocessor is used for carrying out durability detection and life prediction on the externally connected flash memory chip and providing a hardware acceleration function; the firmware protection coprocessor is used for protecting the firmware from being tampered with maliciously and repairing the firmware.
In one embodiment, optionally, the central processor is integrated with a plurality of computing engines and has a memory protection unit built therein, wherein each computing engine is configured to independently complete a different processing task, and the memory protection unit is configured to detect whether a memory address corresponding to a memory access signal generated by the central memory is in a defined domain.
In one embodiment, optionally, the central processor is configured to: when the external flash memory chip is detected to be erased, the erasing times of the flash memory chip are stored in a memory; when detecting that an external flash memory chip is subjected to reading operation, storing the erasing times, the operation time and the original error rate of the flash memory chip in a memory; reading out data in a flash memory unit with the original error rate higher than the preset error rate in an external flash memory chip, and storing the data in the flash memory unit with the original error rate lower than the preset error rate; and storing the bad block position of the external flash memory chip in a memory.
In one embodiment, the memory optionally includes a read-only memory for storing the boot loader, the chip initiator, and the firmware program, a non-volatile memory for storing the temporary code and the operational data, and a static random access memory for storing the base code and the user data.
In one embodiment, the encryption coprocessor optionally incorporates a true random number generator and supports asymmetric encryption algorithms, hash encryption algorithms, and symmetric encryption algorithms.
In one embodiment, optionally, the AI coprocessor is to: reading the erasing times, the operation time and the original error rate of the external flash memory chip from the memory; performing durability detection on the flash memory chip according to the erasing times of the flash memory chip; and predicting the service life of the flash memory chip according to the erasing times, the operation time and the original error rate of the flash memory chip.
In one embodiment, optionally, the AI coprocessor is further configured to: storing each value in the initialized machine learning weight matrix in each operation unit of the AI coprocessor; and multiplying the machine learning weight matrix by the data stored in each operation unit in turn to obtain an output matrix of the machine learning weight matrix.
In one embodiment, optionally, the firmware protects the coprocessor for: based on a state machine algorithm, when illegal intrusion of the memory is detected, the firmware program stored in the memory is covered with the firmware program of the current version, so that the firmware is protected from being tampered maliciously and repaired.
In one embodiment, the communication interface optionally includes a high-speed serial interface, a non-volatile memory interface, a switch interface, a universal serial interface, and a single-wire debug interface.
In addition, to achieve the above objective, the present invention further proposes a solid-state storage system, which includes a solid-state storage controller, a flash memory chip, a communication interface, and a solid-state storage AI coprocessor according to any one of the above embodiments, wherein the solid-state storage AI coprocessor is connected to the solid-state storage controller through a communication bus.
The invention provides a solid-state storage AI coprocessor and a solid-state storage system, wherein the solid-state storage AI coprocessor comprises a central processing unit, a memory, an encryption coprocessor, an AI coprocessor, a firmware protection coprocessor and a communication interface which are connected through a data bus, wherein the central processing unit can be used for executing various instructions related to a solid-state storage function, the memory can be used for storing data, the encryption coprocessor can be used for encrypting and decrypting the data in the memory and verifying the identity of a visitor, the AI coprocessor can be used for carrying out durability detection and service life prediction on an external flash memory chip, and providing a hardware acceleration function, and the firmware protection coprocessor can be used for protecting the firmware from being tampered maliciously and repairing the firmware. The solid-state memory AI coprocessor can provide various functions such as firmware protection, durability management, life prediction, bad block management, secure encryption and the like for the solid-state memory, greatly improves the flash memory management function of the solid-state memory, and effectively improves the read-write speed and the storage performance of the solid-state memory.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 shows a schematic diagram of a solid-state memory AI coprocessor according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a solid state storage system according to an embodiment of the present invention;
wherein: 11-central processing unit, 12-memory, 13-encryption coprocessor, 14-AI coprocessor, 15-firmware protection coprocessor, 21-solid state memory controller, 22-flash memory chip, 23-communication interface, 24-solid state memory AI coprocessor.
Detailed Description
The invention will be described in detail hereinafter with reference to the drawings in conjunction with embodiments. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
In order to further describe the technical means and effects adopted for achieving the preset aim of the invention, the following detailed description refers to the specific implementation, structure, characteristics and effects according to the application of the invention with reference to the accompanying drawings and preferred embodiments. In the following description, different "an embodiment" or "an embodiment" do not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.
Solid state storage AI coprocessors and solid state storage systems according to some embodiments of the invention are described below in conjunction with fig. 1 and 2.
In one embodiment, a solid state memory AI coprocessor is provided. As shown in fig. 1, the solid-state memory AI coprocessor includes a central processor 11, a memory 12, an encryption coprocessor 13, an AI coprocessor 14, a firmware protection coprocessor 15, and a communication interface. The central processing unit 11, the memory 12, the encryption coprocessor 13, the AI coprocessor 14, the firmware protection coprocessor 15 and the communication interface are all connected through a data bus. In this embodiment, the devices may communicate with each other through a bus Arbiter (bus Arbiter), that is, a master device that needs to use a bus may issue a bus use request to the bus Arbiter, and the bus Arbiter may grant the bus Arbiter to a designated master device after determining.
In this embodiment, the central processor 11 may be used to execute instructions related to the solid state storage function, and the central processor 11 may support a widely used ARM or RISC-V instruction set, and support multiple access modes (e.g., user access mode and privileged access mode, etc.); the memory 12 may comprise different types of memory, such as read only memory ROM, non-volatile memory FLASH, static random access memory RAM, etc., wherein the different types of memory may be used to store different types of data; the encryption coprocessor 13 may be used to encrypt and decrypt data in the memory and verify the identity of the visitor through an internally integrated true random number generator (true random number generator, TRNG) and various encryption algorithms (e.g., SM2/SM3/SHA/AES/SM4, etc.); the AI coprocessor 14 can be used for performing durability detection and life prediction on an external flash memory chip through various algorithms stored internally, and providing a hardware acceleration function for the solid-state memory AI coprocessor through a plurality of internally integrated operation units; the firmware protection coprocessor 15 can be used for detecting illegal invasion through a state machine algorithm, protecting the firmware from being tampered maliciously and repairing the firmware through a firmware coverage method; the communication interfaces include a high-speed serial interface (e.g., a high-speed SPI interface), a non-volatile memory interface (e.g., an ONFI3.0 interface), a switch interface (e.g., a toggle2.0 interface), a universal serial interface (e.g., a UART interface), and a single-wire debug interface (e.g., a SWD interface), among others.
The solid-state storage AI coprocessor provided by the embodiment comprises a central processing unit, a memory, an encryption coprocessor, an AI coprocessor, a firmware protection coprocessor and a communication interface which are connected through a data bus, wherein the central processing unit can be used for executing various instructions related to a solid-state storage function, the memory can be used for storing data, the encryption coprocessor can be used for encrypting and decrypting the data in the memory and verifying the identity of a visitor, the AI coprocessor can be used for carrying out durability detection and life prediction on an external flash memory chip, and providing a hardware acceleration function, and the firmware protection coprocessor can be used for protecting firmware from malicious tampering and repairing the firmware. The solid-state memory AI coprocessor can provide various functions such as firmware protection, durability management, life prediction, bad block management, secure encryption and the like for the solid-state memory, greatly improves the flash memory management function of the solid-state memory, and effectively improves the read-write speed and the storage performance of the solid-state memory.
In one embodiment, the central processor is a high-performance and software programmable multi-core CPU. Specifically, the central processing unit supports ARM or RISC-V instruction sets based on widely used Arm or RISC-V architecture, and can provide a high-performance and flexible use mode, wherein a clock source can be configured into an internal clock by software, and the main frequency is 200MHz. And a plurality of complete computing engines are integrated in the central processing unit, and each computing engine can independently complete different processing tasks, so that each processor does not need to wait for the completion of other tasks when different tasks are required to be completed, the performance is improved, and the task realization process is more flexible. In addition, the central processor supports a three-stage pipeline operation mode, namely, the central processor can divide an instruction into three stages to be respectively executed, so that a plurality of operations are synchronously performed, and by dividing tasks among a plurality of execution cores, the central processor can execute more tasks in a specific clock cycle. Furthermore, the central processing unit is also internally provided with a memory protection unit (MemoryProtectionUnit, MPU), and the memory protection unit can be used for detecting whether a memory address corresponding to a memory access signal generated by the central memory is in a defined domain or not, so that the memory is protected.
In one embodiment, the central processor may perform endurance detection and life prediction with the assistance of an AI coprocessor. Specifically, the central processing unit can store the erasing times of the flash memory chip in the memory when the external flash memory chip is detected to perform erasing operation, so as to realize the durability record of the flash memory chip, and can store the erasing times, the operation time and the original error rate of the flash memory chip in the memory when the external flash memory chip is detected to perform reading operation, so as to provide relevant parameters of life prediction for the AI coprocessor. In addition, the CPU can also perform wear balance and bad block management. Specifically, the central processing unit can read out the data in the flash memory unit with the original error rate higher than the preset error rate in the external flash memory chip and store the data in the flash memory unit with the original error rate lower than the preset error rate, and can also store the bad block position of the external flash memory chip in the memory. In this way, the solid-state memory AI coprocessor can effectively improve the service life of the flash memory chip in the solid-state memory.
In one embodiment, the memory includes a read-only memory ROM that can be used to store a bootloader, a chip start-up program, a firmware program, and the like, a nonvolatile memory FLASH that can be used to store temporary codes and operation data, whose storage area can be flexibly used as a code area and a data area, and that supports a chip erase operation, and a static random access memory RAM that can be used to store basic codes and user data. In this embodiment, bootloader is a first code segment executed by the embedded system after power-up, after it completes initialization of the cpu and related hardware, loads an operating system image or a cured embedded application into the memory, and jumps to a space where the operating system is located, and starts the operating system to run.
In one embodiment, the encryption coprocessor has a True Random Number Generator (TRNG) built in and can generate a true random number when performing encryption operations, thereby improving the reliability of the encryption operations. In addition, the encryption coprocessor can also support various encryption algorithms such as an asymmetric encryption algorithm (such as an SM2 encryption algorithm and the like), a hash encryption algorithm (such as an SM3/SHA encryption algorithm and the like), a symmetric encryption algorithm (such as an SM4/AES encryption algorithm and the like) and the like, so that the encryption coprocessor has strong universality.
In one embodiment, the AI coprocessor may perform endurance detection and life prediction on the external flash memory chip through an internally stored algorithm. Specifically, the AI coprocessor may read the number of times of erasure, the operation time and the original error rate of the external flash memory chip from the memory, perform endurance detection on the flash memory chip according to the number of times of erasure of the flash memory chip, predict the service life of the flash memory chip according to the number of times of erasure, the operation time and the original error rate of the flash memory chip, and finally, send the results of endurance detection and life prediction to the central processing unit, so that the central processing unit executes instructions related to functions such as wear balance and bad block management.
In one embodiment, the AI coprocessor may also provide hardware acceleration functionality for the solid state storage AI coprocessor. Specifically, the AI coprocessor may store each value in the initialized machine learning weight matrix in each operation unit of the AI coprocessor, and then multiply the machine learning weight matrix with data stored in each operation unit in sequence to obtain an output matrix of the machine learning weight matrix. By the aid of the mode, the AI coprocessor can effectively improve data processing speed of machine learning, data encryption, life prediction, firmware protection and other functions.
In one embodiment, the firmware protection coprocessor may perform firmware protection and firmware repair. Specifically, the firmware protection coprocessor can cover the firmware program stored in the memory with the firmware program of the current version based on a state machine algorithm when illegal intrusion of the memory is detected, so that the firmware is protected from being tampered maliciously and repaired. In this embodiment, when the firmware protection coprocessor detects that the memory has a security hole, the response time of the firmware protection coprocessor can reach nanosecond level, so that unauthorized intrusion can be effectively prevented, and malicious tampering of the firmware in the memory by illegal intrusion is avoided.
In one embodiment, the communication interfaces include a high-speed serial interface (high-speed SPI interface), a non-volatile memory interface (ONFI 3.0 interface), a switcher interface (toggle 2.0 interface), a universal serial interface (UART interface), and a single-wire debug interface (SWD interface). In this embodiment, the solid-state storage AI coprocessor may interact with the solid-state storage controller of the solid-state storage system at speeds above 100MB/s through a high-speed SPI interface and an ONFI3.0/toggle2.0 interface. In addition, the high-speed SPI interface can support the Quad SPI protocol, and according to the protocol, the read-write speed of the solid-state storage system can reach 4-6 times of that of the common serial flash memory; the ONFI3.0/Toggle2.0 interface can support the ONFI3.0/Toggle2.0 protocol, and the data throughput of the interface can reach more than 100MB/s according to the protocol.
In one embodiment, there is also provided a solid-state storage system, as shown in fig. 2, which includes a solid-state storage controller 21 (also called SSD controller or SSD host chip), a flash memory chip 22, a communication interface 23, and a solid-state storage AI coprocessor 24 (also called storage processing Unit SPU, storageProcessing Unit) according to any one of the above embodiments, wherein the solid-state storage AI coprocessor 24 may be connected to the solid-state storage controller 21 through a communication bus.
In this embodiment, the solid state memory controller may be divided into four parts and may be implemented in hardware or firmware, respectively. The first part is a host interface that can implement the industry standard protocols required (e.g., protocols such as MMC, SD, CF) to ensure logical and electrical interoperability between the flash memory chip and the host, the block being a hybrid of hardware (drivers, etc.) and firmware (command decoding executed by the embedded processor) that can be used to decode command sequences called by the host and process data streams into and out of the flash memory chip. The second part is a Flash File System (FFS), which can support file systems using flash chips, SSDs, and USB (e.g., disk). The third part is an Error Correction Code (ECC), which can be used to correct errors in the flash memory chip. The fourth part is a flash interface, which may be used to implement a protocol for transferring data with a flash chip.
Further, the solid state memory AI coprocessor (SPU) includes a central processing unit, a memory, an encryption coprocessor, an AI coprocessor, a firmware protection coprocessor, and a communication interface. The CPU, the memory, the encryption coprocessor, the AI coprocessor, the firmware protection coprocessor and the communication interface are all connected through a data bus. In a solid state memory AI coprocessor, a central processor may be used to execute instructions related to solid state memory functions and support a widely used ARM or RISC-V instruction set, as well as support multiple access modes (e.g., user access mode and privileged access mode, etc.); the memory may comprise different types of memory, such as read only memory ROM, non-volatile memory FLASH, static random access memory RAM, etc., wherein the different types of memory may be used to store different types of data; the encryption coprocessor 13 may be used to encrypt and decrypt data in the memory and verify the identity of the visitor through an internally integrated True Random Number Generator (TRNG) and various encryption algorithms (e.g., SM2/SM3/SHA/AES/SM4, etc.); the AI coprocessor can be used for carrying out durability detection and life prediction on an external flash memory chip through various algorithms stored in the AI coprocessor, and providing a hardware acceleration function through a plurality of internally integrated operation units so as to improve the read-write performance of the solid-state memory; the firmware protection coprocessor can be used for detecting illegal invasion through a state machine algorithm, protecting the firmware from being tampered maliciously and repairing the firmware through a firmware coverage method. The communication interfaces include a high-speed serial interface (e.g., a high-speed SPI interface), a non-volatile memory interface (e.g., an ONFI3.0 interface), a switch interface (e.g., a toggle2.0 interface), a universal serial interface (e.g., a UART interface), and a single-wire debug interface (e.g., a SWD interface), among others.
Further, a solid state memory AI coprocessor (SPU) may be connected to the SSD host chip through a high speed SPI (NOR flash) interface, ONFI, or Toggle interface. Among them, the functionality of the solid state memory AI coprocessor comes from 3 key factors:
(1) Industry standard, high performance, software programmable multi-core CPU, integrating multiple complete compute engines in CPU, can provide high performance and flexible usage based on widely used Arm or RISC-V architecture. Each computing engine independently completes different tasks, so that each processor does not need to wait for other tasks to complete when different tasks are required to be completed, and the task realization process is more flexible while the performance is improved. By dividing tasks among multiple execution cores, a multi-core processor may perform more tasks within a particular clock cycle.
(2) The high-performance communication interface, the high-speed SPI interface and the ONFI3.0/Toggle2.0 interface can perform data interaction with the SSD main control chip at a speed of more than 100 MB/s. The high-speed SPI interface supports the Quad SPI protocol, and the read-write speed of the Quad SPI according to the protocol is 4-6 times of that of a common serial flash memory; the ONFI3.0/Toggle2.0 interface supports the ONFI3.0/Toggle2.0 protocol, and the data throughput of the interface can reach more than 100MB/s according to the protocol.
(3) The rich flexible programmable acceleration engine can provide hardware acceleration functions for AI and machine learning, safety, life prediction algorithm, firmware protection and the like, improve SSD data reliability and safety, and reduce main control load.
In this embodiment, the most core tasks of the solid state memory AI coprocessor (SPU) are Flash management, including endurance record and life calculation, bad block management, refresh and weather-scaling policy calculation, and tasks of encryption security and authentication classes, master firmware protection and firmware restoration, etc. From the aspect of storage service, the SPU can be considered to greatly enhance related Flash management functions in the SSD main control chip, and the hardware is adopted to accelerate, so that the read-write speed and the storage performance of the solid-state memory are effectively improved.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A solid state memory AI coprocessor comprising a central processing unit, a memory, an encryption coprocessor, an AI coprocessor, a firmware protection coprocessor and a communication interface, wherein,
the central processing unit, the memory, the encryption coprocessor, the AI coprocessor, the firmware protection coprocessor and the communication interface are connected through a data bus;
wherein the central processing unit is used for executing various instructions related to the solid state storage function; the memory is used for storing data; the encryption coprocessor is used for encrypting and decrypting data in the memory and verifying the identity of a visitor; the AI coprocessor is used for carrying out durability detection and life prediction on an external flash memory chip and providing a hardware acceleration function; the firmware protection coprocessor is used for protecting the firmware from being tampered maliciously and repairing the firmware.
2. The solid state memory AI coprocessor of claim 1, wherein the central processor is integrated with a plurality of compute engines and built-in memory protection units, wherein each compute engine is configured to independently complete a different processing task, and the memory protection units are configured to detect whether a memory address corresponding to a memory access signal generated by the central memory is in a defined domain.
3. The solid state memory AI coprocessor of claim 1 or 2, wherein the central processor is configured to:
when the external flash memory chip is detected to be erased, the erasing times of the flash memory chip are stored in the memory;
when detecting that an external flash memory chip is subjected to reading operation, storing the erasing times, the operation time and the original error rate of the flash memory chip in the memory;
reading out data in a flash memory unit with an original error rate higher than a preset error rate in an external flash memory chip, and storing the data in the flash memory unit with the original error rate lower than the preset error rate;
and storing the bad block position of the external flash memory chip in the memory.
4. The solid state memory AI coprocessor of claim 1, wherein the memory includes read-only memory for storing boot loader programs, chip boot programs, and firmware programs, non-volatile memory for storing temporary code and operational data, and static random access memory for storing base code and user data.
5. The solid state memory AI coprocessor of claim 1, wherein the encryption coprocessor incorporates a true random number generator and supports asymmetric encryption algorithms, hash encryption algorithms, and symmetric encryption algorithms.
6. The solid state memory AI coprocessor of claim 1, wherein the AI coprocessor is configured to:
reading the erasing times, the operation time and the original error rate of an external flash memory chip from the memory;
performing durability detection on the flash memory chip according to the erasing times of the flash memory chip;
and predicting the service life of the flash memory chip according to the erasing times, the operation time and the original error rate of the flash memory chip.
7. The solid state memory AI coprocessor of claim 1 or 6, further configured to:
storing each value in the initialized machine learning weight matrix in each operation unit of the AI coprocessor;
and multiplying the machine learning weight matrix with the data stored in each operation unit in turn to obtain an output matrix of the machine learning weight matrix.
8. The solid state memory AI coprocessor of claim 1, wherein the firmware protection coprocessor is to:
based on a state machine algorithm, when illegal intrusion of the memory is detected, the firmware program stored in the memory is covered with the firmware program of the current version, so that the firmware is protected from being tampered maliciously and repaired.
9. The solid state memory AI coprocessor of claim 1, wherein the communication interface includes a high-speed serial interface, a non-volatile memory interface, a switcher interface, a universal serial interface, and a single wire debug interface.
10. A solid state storage system comprising a solid state storage controller, a flash memory chip, a communication interface, and a solid state storage AI coprocessor as claimed in any one of claims 1 to 9, wherein the solid state storage AI coprocessor is connected to the solid state storage controller by a communication bus.
CN202210062548.3A 2022-01-19 2022-01-19 Solid-state storage AI coprocessor and solid-state storage system Pending CN116501237A (en)

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