CN1165000C - Microprocessor high speed buffer storage method of dynamic index - Google Patents

Microprocessor high speed buffer storage method of dynamic index Download PDF

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CN1165000C
CN1165000C CNB011447087A CN01144708A CN1165000C CN 1165000 C CN1165000 C CN 1165000C CN B011447087 A CNB011447087 A CN B011447087A CN 01144708 A CN01144708 A CN 01144708A CN 1165000 C CN1165000 C CN 1165000C
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index
cache
speed
access
buffer storage
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CN1427341A (en
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胡伟武
张福新
唐志敏
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Loongson Technology Corp Ltd
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Institute of Computing Technology of CAS
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Abstract

The present invention relates to a dynamic index method for the high-speed buffer storage of a microprocessor, which comprises the steps: 1. the position of an index field dynamically changes with the change of the behavior of program access storage; 2. in the association of multiple channel groups, the indexes of different groups are mutually independent and can be different; 3. a control register is assigned by an operating system to control a mode for forming an Index and a Tag which access a high-speed buffer storage from an internal storage address. The present invention can fit the accessing behavior of different programs in a computer system by dynamically regulating the organization of the high-speed buffer storage of a microprocessor to enhance the integral hit rate of the high-speed buffer storage so as to fully enhance the speed of system operation.

Description

The microprocessor cache method of dynamic index
Technical field
The present invention relates to micro-processor architecture, particularly a kind of microprocessor cache method of dynamic index.
Background technology
As everyone knows, fast one more than the order of magnitude always of the speed of processor than the access speed of internal memory, and the gap on this performance of processor and storer increases with the speed in every year about 50%, makes memory access speed more and more become the bottleneck that improves processor performance.Utilize principle of locality, the high-speed cache that uses one or more level is one of effective means that addresses this problem.High-speed cache is one, and capacity is little but special memory that access speed is fast is deposited processor most recently used instruction and data.During the processor working procedure, if instruction and data in high-speed cache, then can be, otherwise will send memory access request with very high speed visit, wait for the long period.Design the average internal storage access time that outstanding high-speed cache can reduce processor significantly.
Whenever, high-speed cache has been deposited the sub-fraction content of internal memory.In essence, be that many selection of this mapping relations has determined a given memory block can leave which position of high-speed cache in to few mapping relations between internal memory and the high-speed cache, also influence determines that this memory block is whether in the speed of high-speed cache.The conventional microprocessor high-speed cache is in order to guarantee cache access speed, generally uses very simple mapping relations, usually is directly to do the piece index of high-speed cache with some of memory address.And what of the cacheline that can be mapped to according to a memory block, high-speed cache can be divided into direct mapping, multichannel set associative, complete association three classes.Directly in Ying She the high-speed cache, each memory block is mapped to a fixing cacheline; In the high-speed cache of complete association, each memory block can be mapped to any one cacheline; The multichannel set associative then is compromise between the two: cacheline can be divided into several groups (each group has several and just is called several roads set associative), and each memory block can be mapped to any piece in certain group.Directly Ying She cache hardware is the simplest, helps reducing cost and improves high-speed cache speed, but occur easily that a plurality of memory blocks are competed same cacheline and the situation that can not utilize other free block.And complete association is just in time opposite.
Fig. 1 (a) has provided the conventional microprocessor high-speed cache theory structure of one two road set associative.In the drawings, the address of access cache is divided into three fixing part: Tag, Index, and Offset.Wherein Index is used for the indexes cached piece, and Tag is used for judging relatively with the Tag of high-speed cache whether cache access hits, and Offset is used for selecting the content that needs in the piece of choosing.The aforementioned cache structure is based on the hypothesis to the memory access locality, supposes that promptly the low portion of memory access address in a period of time changes the most frequent.Meet the program that this section's locality is supposed for memory access, the aforementioned cache structure can reach bigger hit rate.But the memory access feature of many programs does not satisfy this locality.
Fig. 2 has provided three c program segments, and they each have different memory access features.In the program segment of Fig. 2 (a), two-dimensional array a and b press row access.In the C language, the data of array are to deposit in internal memory by row.Therefore, the program segment memory access locality of Fig. 2 (a) is better, can reach higher hit rate with the traditional cache of Fig. 1 (a) structure.But in the program of Fig. 2 (b), two-dimensional array a and b press column access, and in the program of Fig. 2 (c), two-dimensional array a presses row access and b presses column access, and the memory access locality is bad, are difficult to the hit rate that reaches higher with the traditional cache of Fig. 1 (a) structure.Because for a certain row of a or b, all elements of these row all is mapped in same group (piece) of high-speed cache probably, can cause the frequent substitution of this group (piece) and other group (piece) free time need not by column access.And in real system, these three kinds of memory access memory access are all very common, and for example: the array of C language is deposited by row, and the array of formula translation is deposited by row, and during matrix multiple, general algorithm be to one of them matrix by row access, another is pressed column access.
Causing the not high reason of program cache hit rate among Fig. 2 (b) and 2 (c) is that the tissue of high-speed cache and the memory access feature of program do not match.In the program of Fig. 2 (b), the low level of memory access address changes unhappy, what address change was the most frequent is some middle position, if therefore some is the Index of high-speed cache with the centre, these addresses relatively are evenly distributed in the whole high-speed cache, thereby obtain cache hit rate preferably.And to the program among Fig. 2 (c), the different piece that then will use reference address when visit array a and array b just can obtain cache hit rate preferably as Index.
People also once attempted to address the above problem from all angles.(referring to A.Seznec.A Case for two_way skewed Associative Cache, the 20 for A.Seznec ThAnnual, 1993) think that the mode that only indexes with fixing position is effective inadequately, he proposes to use a suitable map addresses function that memory address is mapped to the high-speed cache address to each road of set associative cache, thereby improves the hit rate of high-speed cache.A.Seznec and some other researchist have also discussed the due character of this map addresses function, and obtain effect preferably with some object lessons.But the shortcoming of this method is that reasonable in theory mapping function often can not be practical because hardware realization difficulty or cost are too big, and it also is difficult to the different memory access features of dynamically adapting distinct program in addition.Other method is also seldom practical, and present processor high speed buffer memory majority still adopts traditional multichannel set associative mode.
Summary of the invention
The purpose of this invention is to provide a kind of cache method based on dynamic index, it can dynamically be adjusted the index field in the address (Index) according to the memory access feature of program, thereby improves the hit rate of high-speed cache.
For achieving the above object, the microprocessor cache method of dynamic index comprises step:
1, the position of index field dynamic change with the variation of procedure stores access characteristic.
2, the index of different groups is independent mutually in the multichannel set associative, can be different.
3, operating system forms the Index of access cache and the mode of Tag with control from memory address to the control register assignment.
By the tissue of dynamic adjustment microprocessor cache, the present invention can adapt to the memory access feature that various programs are different in the computer system, improves whole cache hit rate, and then improves system running speed all sidedly.
Description of drawings
Fig. 1 is based on the cache design of dynamic index;
Fig. 2 is the example of memory access feature.
Embodiment
Different programs has different memory access features, and the indexed mode of high-speed cache should be not unalterable, and should dynamically adjust according to the memory access feature of program.The memory access locality of program not necessarily only is presented as the low level frequent variations of memory access address, also may be presented as other frequent variations of memory access address.
Based on the high-speed cache of two road set associatives of dynamic index shown in Fig. 1 (b).The main thought of this design is before access cache memory address to be carried out proper transformation, forms the Index and the Tag that relatively are fit to the procedure stores access characteristic and visits high-speed cache.In multichannel set associative structure, different groups can have different Index and Tag.As an example, the cache content of the program segment that Fig. 1 (b) has provided Fig. 2 (c) when carrying out indexes with low level when wherein visiting array a, and during visit array b with middle some index.
In the high-speed cache based on dynamic index, the selection of each group Index and Tag is controlled by a control register IndexSelect.How operating system can be by being formed the Index and the Tag of access cache by memory address to the decision of the assignment of this register.And the foundation of operating system formation IndexSelect content is one group of statistic registers.The memory address of these statistic registers snoop accesses high-speed caches and add up each of memory address or the variation frequency of field (field can comprise multidigit) (in realizing MIPS CPU of the present invention, because idle control register number is not a lot, when monitoring memory address, do not monitor the variation frequency of each address, but, monitor the variation frequency of each section) the address segmentation.Can select one of following two kinds of methods the opportunity that operating system reads statistic registers and revises the IndexSelect control register.The one, utilize clock to interrupt regularly reading the content of statistic registers, if find that current Index generation type and memory access feature are not inconsistent then definite new Index generation type and revise IndexSelect control register content.The 2nd, when not being the Index position, hardware discovery cache miss rate position too high or that variation is the fastest do not produce exception, and in exception handler, read statistic registers and revise the IndexSelect register by operating system.It is worthy of note, before the each IndexSelect of modification register, all need refreshing high-speed cache to guarantee that the old content in the high-speed cache can not misapplied.
Owing to above-mentionedly forms Index and Tag is on the critical path of access cache, so to try one's best simply by the mode that memory address forms Index and Tag by memory address.The process that is formed Index and Tag by memory address is multiselect one circuit basically, select memory address by IndexSelect which form Tag and Index.Because the content of IndexSelect remains unchanged for a long time, therefore as long as guarantee access instruction is not appearred in next bat after the IndexSelect assignment, make hardware have time enough that the content of IndexSelect is deciphered the formation gating signal, the above-mentioned delay that dynamically forms Index and Tag by memory address be one-level with or the delay of door.In realizing MIPS CPU of the present invention, get back to the process of carrying out end from MTC0 instruction (being used for revising the instruction of control register) and stop the finger of getting of subsequent instructions, thereby avoid mistake occurring in the Index change procedure.

Claims (4)

1, a kind of microprocessor cache method based on dynamic index comprises step:
(1), the position of index field dynamic change with the variation of procedure stores access characteristic;
(2), in the multichannel set associative different group with index field independently;
(3), operating system is to the control register assignment, so that determine the Index and the Tag of memory address formation access cache.
2, by the described cache method of claim 1, it is characterized in that: the selection of each group Index and Tag is controlled by a control register.
3, by the described cache method of claim 1, it is characterized in that: processor uses the memory address of one group of statistic registers snoop accesses high-speed cache and adds up each of memory address or the variation frequency of field.
4, by the described cache method of claim 1, it is characterized in that: operating system is utilized statistic registers to make a policy and is changed the tissue of high-speed cache by write control register, to adapt to the procedure stores access characteristic.
CNB011447087A 2001-12-20 2001-12-20 Microprocessor high speed buffer storage method of dynamic index Expired - Lifetime CN1165000C (en)

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CN104346404A (en) * 2013-08-08 2015-02-11 华为技术有限公司 Method, equipment and system for accessing data

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US6973540B2 (en) * 2003-07-25 2005-12-06 Freescale Semiconductor, Inc. Method and apparatus for selecting cache ways available for replacement
WO2005013135A1 (en) * 2003-07-29 2005-02-10 Intel Corporation System and method for transferring blanks
CN101187901B (en) * 2007-12-20 2012-07-18 康佳集团股份有限公司 High speed cache system and method for implementing file access
CN102662868B (en) * 2012-05-02 2015-08-19 中国科学院计算技术研究所 For the treatment of dynamic group associative cache device and the access method thereof of device
CN104731519B (en) * 2013-12-20 2018-03-09 晨星半导体股份有限公司 The dynamic image system and method for memory cache managing device and application the memory cache managing device
CN112799977B (en) * 2021-02-26 2022-07-19 中国人民解放军国防科技大学 Real-time protection method and device for cache partition and cache access of computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104346404A (en) * 2013-08-08 2015-02-11 华为技术有限公司 Method, equipment and system for accessing data
CN104346404B (en) * 2013-08-08 2018-05-18 华为技术有限公司 A kind of method, equipment and system for accessing data

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