CN116491072A

CN116491072A - Encoding method, decoding method, and communication device

Info

Publication number: CN116491072A
Application number: CN202280007642.7A
Authority: CN
Inventors: 格里岑弗拉基米尔•维塔利耶维奇; 李云龙; 弗拉迪斯拉夫·奥博连采夫
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-01-29
Filing date: 2022-01-28
Publication date: 2023-07-25
Also published as: WO2022161449A1

Abstract

The application provides an encoding method, a decoding method and a communication device. The encoding method may include: acquiring a bit sequence to be encoded; performing space coupling coding on a bit sequence to be coded to obtain a coded codeword; the coded code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is an unbalanced coupling relation. By the method, the coupling relation between the current code block bit and the historical code block bit is unbalanced coupling, namely, 2 or more than 2 crossing points can exist between the current code block and the historical code block, so that the time required by the unbalanced space coupling code to collect all bits of the code word is shorter than that of the balanced coupling code. Thus, the same number of real codewords are transmitted, and the unbalanced coupling has a shorter delay.

Description

Encoding method, decoding method, and communication device

The priority of the patent application filed by russian federal intellectual property agency, application number RU2021101961, application name "encoding method, decoding method, and communication device" at day 29, 1, 2021, is claimed in this application, the entire contents of which are incorporated herein by reference.

Technical Field

The present application relates to the field of communication technology, and more particularly, to an encoding method, a decoding method, and a communication apparatus.

Background

A coding scheme based on spatial coupling (spatially coupled, SC) is currently known. Spatial coupling is a way of designing a semi-infinite sequence of codeword symbols such that any symbol in the sequence of codeword symbols is contained in at least one finite subsequence, the finite subsequences constituting a codeword. In the code words coded based on the space coupling mode, the component codes are formed by interleaving and combining the characteristics based on the current information block and the information block generated in history, and the information sequences can continuously form new code words through the space coupling mode.

With the development of communication technology, the demand for coding and decoding is more and more urgent, and how to increase the rate of spatially coupled coding and decoding is a problem that needs to be solved in the industry.

Disclosure of Invention

The application provides an encoding method, a decoding method and a communication device, so as to reduce the delay of encoding and decoding and accelerate the convergence rate of decoding.

In a first aspect, a method of encoding is provided. The method may be performed by the encoding end device, or may be performed by a chip or a system-on-chip or a circuit configured in the encoding end device, which is not limited in this application.

The method may include: acquiring a bit sequence to be encoded; performing space coupling coding on a bit sequence to be coded to obtain a coded codeword; the code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling.

A code block represents a part of a codeword matrix C of w rows and n columns of w×n, or represents a part of a symbol matrix C of w rows and n columns of w×n. The codeword matrix C may be in units of codeword symbols, and thus the codeword matrix C may also be understood as a symbol sequence, which constitutes a symbol matrix.

The historical code block and the current code block may be considered as being of a relative meaning, which will be understood by those skilled in the art. For example, for a current coded code block, it may be considered a current code block; for a code block that has completed encoding before the current code block, it can be considered a history code block. As another example, for a currently decoded code block, it may be considered a current code block; for a code block that has completed decoding before the current code block, it can be considered a history code block.

Unbalanced spatial coupling may mean that there are 2 or more intersections of the current component code and the historical component code, or that there are 2 or more intersections of the current code block and the historical code block.

The representation of the coupling relationship may be a submatrix, or may be a symbol (bit), for example.

Based on the scheme, the coupling relation between the current code block bit and the historical code block bit is designed to be unbalanced coupling, so that the current component code comprises one or more symbols of the historical component code, such as the current component code comprises 2 or more symbols of the historical component code. Thus, the unbalanced spatially coupled code takes less time to align all bits of the codeword than the balanced coupled code. Thus, the same number of real codewords are transmitted, and the unbalanced coupling has a shorter delay. Since the delay of transmitting the same number of real code words is reduced, the occupied data buffer is correspondingly reduced. In addition, since the data buffer transmitting the same number of real codewords becomes smaller, the power consumption caused by the data buffer is also reduced accordingly.

It is understood that with respect to real codewords, those skilled in the art will understand their meaning. The real codeword portion, i.e., the portion of the current component code that is uncoupled. The current component code comprises a coupled part and an uncoupled part, the coupled part typically being non-transmitted, the uncoupled part being transmitted, the uncoupled part comprising information bits and check bits, that is to say the check bits of the information and component code. Wherein the check bits are typically generated from the coupled portion of the component code and the information bits.

In a second aspect, a decoding method is provided. The method may be performed by the decoding end device, or may be performed by a chip or a system-on-chip or a circuit configured in the decoding end device, which is not limited in this application.

The method may include: receiving a codeword to be decoded; decoding the code word; the code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling.

Alternatively, the codeword may be a codeword encoded via unbalanced spatial coupling.

Based on the scheme, in the decoding process of the space coupling code, the component codes with the coupling relation can mutually assist in decoding through iterative decoding, for example, the decoding of the history code word which is successfully decoded can assist in decoding the current code word through the coupling relation; for another example, the decoding result of the current code block may also assist in decoding the historical code block, so that the decoding may be iterated multiple times. Due to unbalanced spatial coupling, there are 2 or more intersections of the current component code with the historical component code. The same successfully decoded historical component code, which has a coupled relationship with the current codeword, helps more decoding of the current codeword than if there was only one intersection. Therefore, the convergence rate of decoding can be increased in iterative decoding.

With reference to the first aspect or the second aspect, in some implementations, the codeword is a codeword matrix C with a number of columns n and a number of rows semi-infinite; the codeword matrix C comprises a virtual codeword matrix and a real codeword matrix, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling, and comprises the following steps: the coupling relationship between the sub-matrix of the virtual codeword matrix and the sub-matrix of the real codeword matrix is an unbalanced coupling relationship.

For example, the codeword matrix C may be in units of codeword symbols.

Illustratively, each row of codeword matrix C may be defined as a component code.

Illustratively, codeword matrix C is divided into A, B parts by columns, A represents a virtual codeword matrix, B represents a real codeword matrix, and (A, B) may be denoted as a zipper pair. Wherein,Z×[n]representing said codeword matrix C with a number of columns n. (A, B) may include the following features:

(1) A and B divide codeword matrix C into 2 parts, namely asub=zx [ n ]]And is also provided withAlternatively, it can be appreciated that the component codes in codeword matrix C are divided into 2 parts, one part at A and one part at B.

(2) For all i ε Z; j, j ' e [ n ], if (i, j) e A and j ' < j, (i, j ') e A.

With reference to the first aspect or the second aspect, in some implementations, the sub-matrix of the virtual codeword matrix is coupled by a sub-matrix of the historical real codeword matrix.

With reference to the first aspect or the second aspect, in some implementations, a row of the codeword matrix C is denoted as wq+i, a column of the codeword matrix C is denoted as ws+j, and a submatrix T of the codeword matrix C _q,s The following formula is satisfied:

T _q,s ＝{c _qw+i,ws+j ∈C}；

wherein T is _q,s Representing the first codeword matrix CW×w submatrices of q rows and s-th columns; s epsilon [2L ]]；i,j∈[w]The method comprises the steps of carrying out a first treatment on the surface of the L, w is a positive integer.

With reference to the first or second aspect, in some implementations, for s ε [ L ]]Sub-matrix T of the virtual codeword matrix in codeword matrix C _q,s The following formula is satisfied:

wherein ψ (q, s) represents the unbalanced coupling function; the superscript T denotes the transpose.

Illustratively, the coupling function may be a function that is periodic with μ, where μ >0:ψ (q+μ, s) =ψ (q, s). In this case, such a coupling function may be called a periodic coupling function.

With reference to the first aspect or the second aspect, in some implementations, at least two s correspond to the same ψ (q, s).

With reference to the first aspect or the second aspect, in some implementations, the q value is fixed, and at least two s correspond to the same ψ (q, s).

Thus, the corresponding ψ (q, s) is the same for at least two s corresponding to a fixed q value, or at least two s corresponding to the same q.

With reference to the first aspect or the second aspect, in certain implementations,

ψ(q,s)＝ψ(s)。

Based on the above scheme, the coupling function may be independent of the number of rows.

With reference to the first aspect or the second aspect, in some implementations, the characteristics of the codeword matrix C include:

the unit of the codeword matrix C is codeword symbol, Z x [ n ] represents the codeword matrix C with the number of columns of n, wherein m=wL, n=2wL, L and w are positive integers, and m represents the column width of each row of the virtual codeword matrix;

the rows of codeword matrix C are denoted wq+i, the columns are denoted ws+j, q ε Z, s ε [2L ], and i, j ε [ w ];

definition of w×w matrix T _q,s Is a submatrix of codeword matrix C, T _q,s ＝{c _qw+i,ws+j ∈C:i,j∈[w]}；

Dividing codeword matrix C into units according to w×w submatrices, and T _q,s W×w submatrices representing the qth row and the sth column;

for s E [ L ]]Sub-matrices defining a virtual codeword matrixThe submatrices of the virtual codeword matrix are obtained by coupling the submatrices of the historical real codeword matrix;

wherein ψ (q, s) is a positive integer; psi and s are not bijective for at least one q e Z.

With reference to the first aspect or the second aspect, in some implementations, the codeword includes a plurality of component codes, each component code consisting of one or more columns of the history code block and a row coupling of the current code block.

Thus, one or more columns of the history code block, and the rows of the current code block, may be coupled to form a component code.

With reference to the first aspect or the second aspect, in some implementations, the codeword includes a plurality of code blocks, the plurality of component codes includes a first component code, and at least two symbols in the first component code are from different codeword sub-matrices of a same code block.

With reference to the first aspect or the second aspect, in some implementations, the symbols in the first component code include one or more first symbols and a plurality of second symbols, the first symbols belonging to the code block B _i The second symbol belonging to one or more code blocks B _j Where i and j are positive integers and j is less than i.

With reference to the first aspect or the second aspect, in some implementations, the symbols in the first component code form a plurality of blocks, and the symbols of the first component code include:

(i-f ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j),

wherein f ₁ ，f ₂ ，f ₃ Is a function of an output positive integer having (i, j, k) as a variable; (i, j, k) represents code block B _i The j-th column in the kth w×w block; (i, j) represents code block B _i R line of (2); f (f) ₁ (i,j,1)≥f ₁ (i,j,2)≥…≥f ₁ (i,j,s)>0，1≤f ₂ (i,j,k)≤w，1≤f ₃ And (i, j, k) is less than or equal to s, k, w, s are positive integers.

With reference to the first aspect or the second aspect, in certain implementations, j is less than or equal to w and k is less than or equal to s;

f ₁ (i,j,s+1)＝1；

f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；

f ₂ (i,j,k)＝j；

f ₃ (i,j,k)＝k。

f ₁ (i,j,s+1)＝1；

f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；

f ₂ (i,j,k)＝j；

f ₃ (i,j,k)＝s-k+1。

With reference to the first aspect or the second aspect, in certain implementations, the codeword includes the following features:

code block offset constituting the first component code: f (f) ₁ (i,j,k)＝f ₁ (k) λ -2 x floor ((k-1)/2), wherein floor represents a rounding down, λ is a constant;

symbols in the first component code form a plurality of blocks, column numbers within a block: f (f) ₂ (i,j,k)＝f ₂ (j)；

Block numbers within code blocks constituting the first component code: f (f) ₃ (i,j,k)＝f ₃ (k)＝s-k+1。

With reference to the first aspect or the second aspect, in certain implementations, the codeword includes a plurality of component codes, the component codes being any of: reed-solomon codes RS codes, BCH codes, low density parity check codes LDPC codes.

The component codes may be, for example, non-binary BCH codes.

In a third aspect, a method of encoding is provided. The method may be performed by the encoding end device, or may be performed by a chip or a system-on-chip or a circuit configured in the encoding end device, which is not limited in this application.

The method may include: acquiring a bit sequence to be encoded; performing space coupling coding on a bit sequence to be coded to obtain a coded codeword; wherein, the code word is a code word matrix C with the number of columns of n and the number of rows of semi-infinite; the codeword matrix C is divided into A, B parts according to columns, wherein A is a virtual codeword matrix, B is a real codeword matrix, and the coupling relation between the codeword sub-matrices of A and B is unbalanced; the codeword matrix C is characterized by:

In a fourth aspect, a decoding method is provided. The method may be performed by the decoding end device, or may be performed by a chip or a system-on-chip or a circuit configured in the decoding end device, which is not limited in this application.

The method may include: receiving a codeword to be decoded; decoding the code word; wherein, the code word is a code word matrix C with the number of columns of n and the number of rows of semi-infinite; the codeword matrix C is divided into A, B parts according to columns, wherein A is a virtual codeword matrix, B is a real codeword matrix, and the coupling relation between the codeword sub-matrices of A and B is unbalanced; the codeword matrix C is characterized by:

In a fifth aspect, a method of encoding is provided. The method may be performed by the encoding end device, or may be performed by a chip or a system-on-chip or a circuit configured in the encoding end device, which is not limited in this application.

The method may include: acquiring a bit sequence to be encoded; performing space coupling coding on a bit sequence to be coded to obtain a coded codeword; the codeword structure is described as follows:

Mapping the data stream to a semi-infinite code block sequence; the semi-infinite long code block sequence can be decomposed into a plurality of w×m code blocks, w and m being positive integers; the symbols in the component code belonging to code block B _i Two or more symbols belonging to one or more code blocks B _j The method comprises the steps of carrying out a first treatment on the surface of the Wherein i and j are positive integers, j being smaller than i; the component code consists of data symbols and check symbols; the component code check symbols are composed of one or more code blocks B _i And two or more code blocks B belonging to two or more _j Generating; code block B _i Or B is a _j Can be expressed as a matrix of w x m; the code length of the component code is 2*m; each code block B _i Matrix, which can be expressed as wx (sxw), each B _i Can be divided into s blocks w×w, s being a positive integer, m=s×w; b (B) _i The j-th column in the kth w×w block is denoted as (i, j, k), code block B _i Where i is a positive integer, j is a positive integer less than or equal to w, and k is a positive integer less than or equal to s; the component codes are expressed as: (i-f) ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j); wherein f ₁ ，f ₂ ，f ₃ Is an output positive integer taking (i, j, k) as a variableA function; f (f) ₁ (i,j,1)≥f ₁ (i,j,2)≥…≥f ₁ (i,j,s)>0，1≤f ₂ (i,j,k)≤w，1≤f ₃ (i,j,k)≤s。

In a sixth aspect, a decoding method is provided. The method may be performed by the decoding end device, or may be performed by a chip or a system-on-chip or a circuit configured in the decoding end device, which is not limited in this application.

The method may include: receiving a codeword to be decoded; decoding the code word; the codeword structure is described as follows: mapping the data stream to a semi-infinite code block sequence; the semi-infinite long code block sequence can be decomposed into a plurality of w×m code blocks, w and m being positive integers; the symbols in the component code belonging to code block B _i Two or more symbols belonging to one or more code blocks B _j The method comprises the steps of carrying out a first treatment on the surface of the Wherein i and j are positive integers, j being smaller than i; the component code consists of data symbols and check symbols; the component code check symbols are composed of one or more code blocks B _i And two or more code blocks B belonging to two or more _j Generating; code block B _i Or B is a _j Can be expressed as a matrix of w x m; the code length of the component code is 2*m; each code block B _i Matrix, which can be expressed as wx (sxw), each B _i Can be divided into s blocks w×w, s being a positive integer, m=s×w; b (B) _i The j-th column in the kth w×w block is denoted as (i, j, k), code block B _i Where i is a positive integer, j is a positive integer less than or equal to w, and k is a positive integer less than or equal to s; the component codes are expressed as: (i-f) ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j); wherein f ₁ ，f ₂ ，f ₃ Is a function of an output positive integer having (i, j, k) as a variable; f (f) ₁ (i,j,1)≥f ₁ (i,j,2)≥…≥f ₁ (i,j,s)>0，1≤f ₂ (i,j,k)≤w，1≤f ₃ (i,j,k)≤s。

With reference to the fifth aspect or the sixth aspect, in some implementations, the component codes are expressed as follows: (i-f) ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j).

Wherein f ₁ ，f ₂ ，f ₃ Is a function of the output positive integer; f (f) ₁ (i,j,s+1)＝1，f ₁ (i, j, k) is equal to f ₁ (i, j, k+1) or f ₁ (i,j,k+1)+2；f ₂ (i,j,k)＝j；f ₃ (i, j, k) =k; wherein j is less than or equal to w and k is less than or equal to s.

Wherein f ₁ ，f ₂ ，f ₃ Is a function of the output positive integer; f (f) ₁ (i,j,s+1)＝1，f ₁ (i, j, k) is equal to f ₁ (i, j, k+1) or f ₁ (i,j,k+1)+2；f ₂ (i,j,k)＝j；f ₃ (i, j, k) =s-k+1; wherein j is less than or equal to w and k is less than or equal to s.

In a seventh aspect, there is provided a communication device comprising means or units for performing the method in any of the possible implementations of the first, third or fifth aspects.

In an eighth aspect, there is provided a wireless communication device comprising means or units for performing the method of any one of the possible implementations of the second, fourth or sixth aspects.

In a ninth aspect, there is provided a communication device comprising a processor coupled to a memory, operable to perform the method of any one of the possible implementations of the first, third or fifth aspects. Optionally, the communication device further comprises a memory. Optionally, the communication device further comprises a communication interface, and the processor is coupled to the communication interface. Optionally, the communication device further comprises a communication interface, and the processor is coupled to the communication interface.

In one implementation, the communication device is a network device. When the communication device is a network device, the communication interface may be a transceiver, or an input/output interface.

In another implementation, the communication device is a chip or a system-on-chip. When the communication device is a chip or a chip system, the communication interface may be an input/output interface, an interface circuit, an output circuit, an input circuit, a pin, or related circuits on the chip or the chip system. The processor may also be embodied as processing circuitry or logic circuitry.

In a tenth aspect, a communication device is provided that includes a processor. The processor is coupled to the memory and operable to execute instructions in the memory to implement the method of any one of the possible implementations of the second, fourth or sixth aspects described above. Optionally, the communication device further comprises a memory. Optionally, the communication device further comprises a communication interface, and the processor is coupled to the communication interface. Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input/output interface may be an input/output circuit.

In one implementation, the communication device is a terminal device. When the communication device is a terminal device, the communication interface may be a transceiver, or an input/output interface. Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input/output interface may be an input/output circuit.

In an eleventh aspect, there is provided a processor comprising: input circuit, output circuit and processing circuit. The processing circuit is configured to receive a signal via the input circuit and transmit a signal via the output circuit, such that the method of any one of the first to sixth aspects, and any one of the possible implementations of the first to sixth aspects, is implemented.

In a specific implementation process, the processor may be a chip, the input circuit may be an input pin, the output circuit may be an output pin, and the processing circuit may be a transistor, a gate circuit, a trigger, various logic circuits, and the like. The input signal received by the input circuit may be received and input by, for example and without limitation, a receiver, the output signal may be output by, for example and without limitation, a transmitter and transmitted by a transmitter, and the input circuit and the output circuit may be the same circuit, which functions as the input circuit and the output circuit, respectively, at different times. The embodiments of the present application do not limit the specific implementation manner of the processor and the various circuits.

In a twelfth aspect, a processing device is provided that includes a processor and a memory. The processor is configured to read instructions stored in the memory and is configured to receive a signal via the receiver and to transmit a signal via the transmitter to perform the method of the first to sixth aspects and any one of the possible implementations of the first to sixth aspects.

Optionally, the processor is one or more, and the memory is one or more.

Alternatively, the memory may be integrated with the processor or the memory may be separate from the processor.

In a specific implementation process, the memory may be a non-transient (non-transitory) memory, for example, a Read Only Memory (ROM), which may be integrated on the same chip as the processor, or may be separately disposed on different chips.

It should be appreciated that the related data interaction process, for example, transmitting the indication information, may be a process of outputting the indication information from the processor, and the receiving the capability information may be a process of receiving the input capability information by the processor. Specifically, the data output by the processing may be output to the transmitter, and the input data received by the processor may be from the receiver. Wherein the transmitter and receiver may be collectively referred to as a transceiver.

The processor in the twelfth aspect may be a chip, and the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like; when implemented in software, the processor may be a general-purpose processor, implemented by reading software code stored in a memory, which may be integrated in the processor, or may reside outside the processor, and exist separately.

In a thirteenth aspect, there is provided a computer program product comprising: a computer program (which may also be referred to as code, or instructions) which, when executed, causes a computer to perform the method of the first to sixth aspects and any one of the possible implementations of the first to sixth aspects.

In a fourteenth aspect, there is provided a computer readable medium storing a computer program (which may also be referred to as code, or instructions) which, when run on a computer, causes the computer to perform the method of the first to sixth aspects and any one of the possible implementations of the first to sixth aspects.

Drawings

Fig. 1 is a schematic diagram of a wireless communication system 100 suitable for use in embodiments of the present application.

Fig. 2 is a basic flow diagram for communicating using wireless technology suitable for use in embodiments of the present application.

Fig. 3 is a schematic block diagram of an encoding method provided according to an embodiment of the present application.

Fig. 4 shows a schematic diagram of an unbalanced spatially coupled codeword structure suitable for use in an embodiment of the present application.

Fig. 5 shows a schematic diagram of a balanced spatially coupled codeword structure.

Fig. 6 is a schematic block diagram of a decoding method provided according to an embodiment of the present application.

Fig. 7 shows a schematic diagram of an unbalanced spatially coupled codeword structure suitable for use in a further embodiment of the present application.

Fig. 8 shows a comparison of decoding performance of unbalanced space-coupled codes provided in accordance with the present application and balanced space-coupled codes of the prior art.

Fig. 9 is a schematic diagram of an example of the communication device of the present application.

Fig. 10 is a schematic diagram of an example of the communication device of the present application.

Fig. 11 is a schematic diagram of an example of the encoding-side optical communication apparatus of the present application.

Fig. 12 is a schematic diagram of an example of the decoding-side optical communication device of the present application.

Detailed Description

The technical solutions in the present application will be described below with reference to the accompanying drawings.

The technical solution of the embodiments of the present application may be applied to various wireless communication systems, for example, the wireless communication systems may include, but are not limited to: a wireless local area network (wireless local access network, WLAN) system, a narrowband internet of things (NB-IoT) system, a fifth generation (5th generation,5G) system or a New Radio (NR), a long term evolution (long term evolution, LTE) system or a 5G later communication system, etc. The technical solutions of the embodiments of the present application may also be applied to device-to-device (D2D) communication, machine-to-machine (machine to machine, M2M) communication, machine type communication (machine type communication, MTC), satellite communication, and communication in a car networking system. For example, the technical solution of the embodiment of the present application may be applied to an application scenario of a 5G mobile communication system, such as enhancing mobile bandwidth (enhance mobile broadband, eMBB), high reliability low latency communication (ultra reliable low latency communication, URLLC), enhancing mass machine connection communication (massive machine type communication, eMTC), and the like.

Fig. 1 is a schematic diagram of a wireless communication system 100 suitable for use in embodiments of the present application. As shown in fig. 1, the wireless communication system 100 may include at least one network device, such as the network device 111 shown in fig. 1, and the wireless communication system 100 may further include at least one terminal device, such as the terminal device 121 shown in fig. 1, and the terminal device 123. A network device (such as network device 111 shown in fig. 1) may communicate wirelessly with one or more terminal devices (such as terminal device 121 and terminal device 123 shown in fig. 1).

The network device and the terminal device in fig. 1 communicate using wireless technology. When the network device transmits a signal, it is a transmitting end, and when the network device receives a signal, it is a receiving end. The same applies to the terminal device, which is a transmitting end when the terminal device transmits a signal, and a receiving end when the terminal device receives a signal.

Fig. 2 is a basic flow diagram for communicating using wireless technology. The source of the transmitting end is sent out on the channel after source coding, channel coding, rate matching, modulation and the like in sequence. The receiving end receives the signal and then obtains the information sink after demodulation, de-rate matching, channel decoding and information source decoding.

It should be understood that fig. 2 is merely an exemplary illustration for easy understanding, and other processing steps or other modification processing may be included in the actual communication, which is not limited thereto.

Channel coding and decoding are one of the core technologies in the wireless communication field, and the improvement of the performance of the channel coding and decoding directly improves the network coverage and the user transmission rate.

It should be understood that, for example, in the communication system shown in fig. 1 or the flow shown in fig. 2, the original information is encoded by an encoding end (encoder), then transmitted through a channel, received by a decoding end (decoder), and then decoded by the decoding end, and then the original information is restored.

The encoding end may also be referred to as a transmitting end (or transmitting device), and the decoding end may also be referred to as a receiving end (or receiving device) of information or data.

In the embodiment of the application, the transmitting end and the receiving end can perform wired communication, for example, optical communication, and the coding scheme of the application can be applied to the coding process of the wired communication. Alternatively, in the embodiment of the present application, the transmitting end and the receiving end may perform wireless communication, for example, may be applied to an encoding process in a wireless communication system.

The scheme provided by the application can be used for the coding process of the sending equipment and the decoding process of the receiving equipment.

The sending device may be a network device, and the receiving device may be a terminal device. Alternatively, the transmitting device may be a terminal device and the receiving device may be a network device. Alternatively, the transmitting device may be a terminal device and the receiving device may be a terminal device. Alternatively, the transmitting device may be a network device and the receiving device may be a network device. The specific form of the network device and the terminal device is not strictly limited.

With the rapid development of technologies such as big data, artificial intelligence (artificial intelligence, AI), cloud computing and the like, the application of data centers is also becoming wider and wider. The demand for transmission capacity by systems has grown in bursts. As the bandwidth of the system increases, the noise of the system increases, and the bandwidth limit of the system is more serious than before. Interconnection of data centers is to improve performance by various means of technology. One important approach includes forward error correction (forward error correction, FEC) (alternatively referred to as forward error correction code).

The forward error correction is an error control method, which refers to a technology that a signal is coded in advance according to a certain algorithm before being sent into a transmission channel, redundancy codes with the characteristics of the signal are added, and the received signal is decoded at a receiving end according to a corresponding algorithm, so that error codes generated in the transmission process are found and corrected.

A forward error correction code KP4 is defined in IEEE 802.3. However, as channel conditions deteriorate, KP4 has been difficult to meet performance requirements. The KP4 cascade optical layer forward error correction code can be considered as an effective forward error correction code scheme with good compatibility by considering the factors of power consumption, time delay and the like.

For a brief introduction to concatenated coding, reference is made to the description in detail herein.

In applying channel coding techniques in practice, many practical factors, such as efficiency, performance, and latency, often need to be considered. As known from the channel coding theory, the decoding error probability becomes exponentially zero as the code length increases. Therefore, to increase the effectiveness of the error correction code, a long code may be used. One possible coding scheme may employ a generic concatenated code (generalized concatenated code, GCC) technique for coding. The GCC includes an outer code and an inner code. Wherein the input of the outer code coding is the information bit sequence to be coded, and the output of the outer code is used as the input of the inner code. The output of the inner code coding is the code word after the cascade coding is completed. It should be appreciated that outer and inner codes are a relative concept. Taking a system comprising three encodings as an example, the first encoding is an outer encoding relative to the second encoding, and the second encoding is an inner encoding relative to the first encoding. After the first encoding is completed, the second encoding is an outer code encoding with respect to the third encoding, and the third encoding is an inner code encoding with respect to the second encoding. Taking a system comprising two codes as an example, the outer code coding is performed first, and the inner code coding is performed later. The output of the outer code serves as the input of the inner code.

Illustratively, the code words provided according to the embodiments of the present application may be used as inner codes in concatenated codes, and may be used for interconnection between data centers.

The forward error correction code of the optical layer cascaded by the KP4 needs to meet certain conditions, such as high performance, low complexity, certain burst resistance capability and the like of the forward error correction code of the optical layer. Illustratively, spatially coupled error correction codes, i.e., KP4 concatenated spatially coupled error correction codes, may be used. By way of example and not limitation, spatially coupled error correction codes that satisfy the above conditions may include, but are not limited to: step codes (staircase codes), continuous interleaved BCH codes (CI-BCH codes), woven block codes (braided block code), open forward error correction codes (open forward error correction, ofcs), and the like. The characteristic of the presently known code words is that each component code of the spatially coupled error correction code consists of a current code block bit and part of the bits of one or more history code blocks. When composed of bits of a plurality of history code blocks. The number of bits belonging to each history code block is equal.

The scheme provided by the application can reduce the delay of encoding and decoding as much as possible and accelerate the convergence rate of decoding.

Various embodiments provided herein will be described in detail below with reference to the accompanying drawings.

Fig. 3 is a schematic diagram of an encoding method 300 according to an embodiment of the present application. The method 300 may include the following steps.

310, obtaining a bit sequence to be encoded;

320, coding the bit sequence to be coded to obtain a coded codeword;

the code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling.

A code block represents a part of a codeword matrix C of w rows and n columns of w×n, or represents a part of a symbol matrix C of w rows and n columns of w×n. The codeword matrix C may be in units of codeword symbols, and thus the codeword matrix C may also be understood as a semi-infinite symbol sequence, which constitutes a symbol matrix.

The historical code block and the current code block may be considered as being of a relative meaning, which will be understood by those skilled in the art. For example, for a current coded code block, it may be considered a current code block; for a code block that has completed encoding before the current code block, it can be considered a history code block. As another example, for a currently decoded code block, it may be considered a current code block; for a code block that has completed decoding before the current code block, it can be considered a history code block. For example, taking component codes C (w (q-1) +i) and C (w (q-4) +j) in FIG. 4 as examples, component code C (w (q-1) +i) may be considered the current component code and component code C (w (q-4) +j) may be considered the historical component code. The code word comprises a plurality of component codes, the component codes are formed by interleaving and combining characteristic based on the current information block and the historically generated information block, and the component codes with coupling relation can mutually assist decoding through iterative decoding. Therefore, based on the decoding result of the historical code block, the decoding of the current code block can be assisted, or the decoding result of the current code block can also assist the decoding of the historical code block, so that the iterative decoding can be repeated, and the decoding accuracy is improved.

Unbalanced spatial coupling means that there are 2 or more intersections of the current code block and the historical code block, or that there are 2 or more intersections of the current component code and the historical component code. It should be appreciated that the unbalanced spatial coupling, which means that there may be 2 or more intersections of the current code block with the historical code block, or the current component code with the historical component code, is not limited to having only 2 or more intersections. For example, in some cases, there may be a case where there is one intersection.

Unbalanced spatial coupling is understood to be relative to balanced spatial coupling. For example, refer to fig. 4 and 5.

In the unbalanced spatial coupling shown in fig. 4, there are 2 intersections of the current component code with the historical component code. In the unbalanced spatially coupled code shown in fig. 4, the component code C (w (q-1) +i) is coupled to a historical codeword matrix having a number of rows of 4. Taking the component code C (w (q-4) +j) of a certain line as an example, in the unbalanced space coupling code shown in fig. 4, the number of intersections of the component code C (w (q-1) +i) and the component code C (w (q-4) +j) is 2.

In the balanced spatial coupling shown in fig. 5, there are 1 intersection points of the current component code with the component code of the historical codeword matrix. In the balanced spatial coupling code shown in fig. 5, the component code C (w (q-1) +i) is coupled to a history codeword matrix having a number of rows of 7. Taking the component code C (w (q-4) +j) of a certain line as an example, in the balanced space coupling code shown in fig. 5, the number of intersections between the component code C (w (q-1) +i) and the component code C (w (q-4) +j) is 1.

The specific meaning of the codeword matrix and the component codes is described in detail below.

By the embodiment of the application, compared with balanced space coupling, unbalanced space coupling is adopted, and the component codes with the same length are coupled with the historical codeword matrixes with fewer rows. For example, referring to fig. 4 and 5, the unbalanced space coupling code takes a shorter time to align all bits of the component code than the balanced coupling code. Thus, the same number of real codewords are transmitted, and the unbalanced coupling has a shorter delay. Since the delay of transmitting the same number of real code words is reduced, the occupied data buffer is correspondingly reduced. In addition, since the data buffer transmitting the same number of real codewords becomes smaller, the power consumption caused by the data buffer is also reduced accordingly.

Fig. 6 is a schematic diagram of a decoding method 600 according to an embodiment of the present application. The method 600 may include the following steps.

610, receiving a codeword to be decoded;

620, decoding the codeword;

According to the embodiment of the application, when the code word is decoded, the results of at least two current code blocks can be obtained based on the decoding results of the historical code blocks, the decoding convergence speed is high, and the decoding delay is short.

In the decoding process of the space coupling code, the component codes with coupling relation can mutually assist in decoding through iterative decoding, for example, the history code words which are successfully decoded can assist in decoding the current code words through the coupling relation; for another example, the decoding result of the current code block may also assist in decoding the historical code block, so that the decoding may be iterated multiple times. Due to unbalanced spatial coupling, there are 2 or more intersections of the current component code with the historical component code. The same successfully decoded historical component code, which has a coupled relationship with the current codeword, helps more decoding of the current codeword than if there was only one intersection. Therefore, the convergence rate of decoding can be increased in iterative decoding.

In the following, for ease of understanding and description, two expressions of codeword structures provided herein are presented.

Mode 1 the codeword structure provided herein is based on the description of tiled zipper code.

The code words provided by the embodiment of the application are unbalanced space coupling codes with semi-infinite length.

The code word generated based on the space coupling coding mode is an unbalanced space coupling code with a semi-infinite length. Assuming that the codeword matrix is denoted as C, the codeword matrix C is a semi-infinite codeword sequence, the codeword sequence forms a codeword matrix, the number of rows of the codeword matrix is infinitely long, the number of columns of the codeword matrix is n, and n is a positive integer. Where semi-infinite, it is understood that the number of rows of the codeword matrix is not limited.

The unit of the codeword matrix may be a codeword symbol. The codeword matrix C is thus also understood to be a semi-infinite symbol sequence, which constitutes a symbol matrix with an infinitely long number of rows and n columns. A symbol may be understood as a carrier of information or data. For example, in binary symbols, one symbol is one bit; for another example, one symbol is one character in the 16-ary symbol. It should be understood that the relation between symbols and bits is not limited, and for example, one symbol may be one bit or a plurality of bits.

The position of the codeword symbol in the codeword matrix can be denoted by (i, j). (i, j) means that the codeword symbol is located in the ith row and jth column of the codeword matrix. Where (i, j) e z× [ n ], [ n ] = {0,1,., n-1}, z× [ n ] represents codeword matrix C with column number n.

Codeword symbols are finite field elements. A finite field means a field containing a finite number of elements. The number of bits of a finite field element is related to the finite field to which it belongs. For example, the finite field GF (256) of order 256 has a finite field element of 8 bits.

Codeword matrix C may include a virtual codeword matrix a and a real codeword matrix B.

(A, B) can be denoted as zipper pairs. Wherein,(A, B) includes the following features:

(2) For all i ε Z; j, j ' e [ n ], if (i, j) e A and j ' < j, (i, j ') e A.

Each row of codeword matrix C may be defined as a component code. For example, the component code is RS (224,218), where 218 is the information bit length and 224 is the encoded codeword length. The RS code is Reed-solomon (RS) code.

Defining a mapping pi of codeword symbols and row numbers in a codeword matrix ₁ :Z×[n]→Z，π ₁ (i, j) =i, for i ε Z, A _i ＝{a∈A：π ₁ (a)＝i}，B _i ＝{b∈B：π ₁ (b) =i }. Let m _i ＝|A _i |，m _i Representing the column width of the ith row of the matrix of dummy codewords. Illustratively, m _i =n/2. For example, m _i ＝112，n＝224。

A mapping phi between A and B is defined A.fwdarw.B.

If and only map phi is present ^-1 B- & gt A, for any a E A, B E B, there arePhi is bijective, phi ^-1 Called inverse mapping of phi.

If φ (i+v, j) =φ (i, j) + (v, 0), then φ is periodic and v is periodic.

If pi ₁ (φ(i,j))<i, then the map phi is causal. Hereinafter, for the description, phi is used ₁ Represents pi ₁ (φ(i,j))。

Furthermore, the coupling depth may be defined, e.g. denoted as λ. The coupling depth lambda represents the difference between the maximum line number of the current and the historical component codes. If the coupling depth lambda can satisfy the following formula: λ=max { i- Φ ₁ (i,j)}，j∈[m _i ]。

Some basic concepts are presented above and specific codeword structures are presented below in connection with fig. 4.

In mode 1, the codeword structure provided in the embodiments of the present application is similar to that of tiled zipper code.

Let m=wl, n=2wl assuming a fixed positive integer L, w. The rows and columns of codeword matrix C may be denoted as wq+i and ws+j in codeword symbols. Where q.epsilon.Z, s.epsilon.2L, and i, j.epsilon.w.

Definition of w×w matrix T _q,s Is a sub-matrix of codeword matrix C. It should be understood that the submatrix is only a name given to the description, and is not intended to limit the scope of the embodiments of the present application. For example, a w×w matrix T may be defined as described in the zip code _q,s Is a block (tile). For uniformity, the description is in terms of a sub-matrix. Dividing codeword matrix C into units of w×w submatrices, T _q,s Representing a w x w sub-matrix of row q and column s. T (T) _q,s ＝{c _qw+i,ws+j ∈C:i,j∈[w]}，T _q,s The relation with codeword matrix C may satisfy the following equation.

Codewords of different rowsSub-matrix T of matrix C _q,s The mapping relationship of (2) may be: for s E [ L ]]， That is, for s ε [ L ]]Sub-matrices of the virtual codeword matrix may be definedThe sub-matrices of the virtual codeword matrix may be coupled from the sub-matrices of the historical real codeword matrix.

Where ψ (q, s) may be called an inter-block coupling function (or may also be called an inter-frame coupling function), and the value of ψ (q, s) may be a positive integer. Optionally, the q value is fixed, and the ψ(s) corresponding to at least two s are the same. That is, for a q value, at least two s correspond to the same ψ(s).

Illustratively, the inter-code block coupling function provided by the embodiments of the present application may be independent of the number of rows, i.e., ψ (q, s) =ψ(s). In this example of the present invention, in this case,

if the code inter-block coupling function is a function that is periodic with μ, where μ >0:ψ (q+μ, s) =ψ (q, s), such a code inter-block coupling function may be called a periodic code inter-block coupling function (or may also be called a periodic inter-frame coupling function). Illustratively, the period may be a fixed value μ, such as the period may be fixed at 1.

If the relation between psi and s is bijective to any q epsilon Z, the coupling relation between code blocks can be called as balanced; otherwise the coupling relationship is unbalanced. In the embodiments of the present application, the coupling relationship is unbalanced.

For example, the embodiments of the present application provide a periodic 1, unbalanced spatial coupling function of the inter-block coupling function, and the inter-block coupling function is independent of the number of lines. By way of example, tables 1 and 2 show two possible coupling functions ψ(s). As can be seen from tables 1 and 2, at least two s correspond to the same ψ(s).

TABLE 1

s	0	1	2	3	4	5	6
ψ(s)	7	7	5	5	3	3	1

TABLE 2

s	0	1	2	3	4	5	6
ψ(s)	1	3	3	5	5	7	7

Taking the unbalanced coupling relation shown in table 1 as an example, an unbalanced spatial coupling code provided according to an embodiment of the present application is shown in fig. 4. Assuming that the component code is RS (224,218,7) over a finite field GF (256), the corresponding component code n=224, m=112, and the corresponding code block size is 16x112, i.e., l= 7,w =16, in symbols over one GF (256), and 8 bits.

As shown in FIG. 4, codeword matrix C has a column number n, and the rows and columns of codeword matrix C can be represented as wq+i and ws+j, where q ε Z, s ε [2L ], and i, j ε [ w ]. The codeword matrix C comprises a plurality of component codes, and each row of the codeword matrix C may be defined as a component code, i.e. a component code codeword length n. For example, the component codes C (w (q-1) +i) and C (w (q-4) +j) shown in FIG. 4.

As shown in fig. 4, the code is codedThe word matrix C is divided into cells by w×w submatrices. Each component code corresponds to a plurality of blocks, each block having a size w×w, i.e., each block represents a matrix of w×w. The wxw matrix is a sub-matrix of codeword matrix C, wxw matrix T _q,s Representing a w x w sub-matrix of row q and column s. T (T) _q,s ＝{c _qw+i,ws+j ∈C:i,j∈[w]}。

As shown in FIG. 4, each component code includes two parts, one part is at A and one part is at B, and each part occupies L T's respectively _q,s . As shown in fig. 4, the component code C (w (q-1) +i) is one row of the codeword matrix C. For distinction, the part of the component code C (w (q-1) +i) belonging to the virtual codeword matrix A is indicated by a dotted line, and the part of the component code C (w (q-1) +i) belonging to the real codeword matrix B is indicated by a thick solid line. The part of the component code C (w (q-1) +i) belonging to the virtual codeword matrix is distributed in the submatrix T of the virtual codeword matrix A _q-1,s Is a kind of medium. The part of the component code C (w (q-1) +i) belonging to the real codeword matrix is distributed in the submatrix T of the real codeword matrix B _q-1,L+s In which s is E [ L ]]。

As shown in FIG. 4, by unbalanced coupling relationshipIt is known that the number of the components,the sub-matrix of the virtual codeword matrix a is mapped by the sub-matrix of the real codeword matrix B.

Unbalanced spatially coupled codes, i.e., representing that there may be 2 or more intersections of the historical component code with the current component code. As shown in fig. 4, taking the history component code as C (w (q-4) +j), the current component code as C (w (q-1) +i) as an example, there are 2 intersections of the component code C (w (q-1) +i) and C (w (q-4) +j), which are C (w (q-4) +j,8×w+i) and C (w (q-4) +j,9×w+i), respectively. After successful decoding of the history component code C (w (q-4) +j), 2 crossing results can be obtained when the current component code C (w (q-1) +i) is decoded. Compared with the condition that the historical component code and the current component code have only one intersection point, the decoding speed is faster, and the decoding delay is shorter.

The component code is assumed to be an RS (224,218) over a finite field GF (256). In elements over a finite field GF (256). The check matrix H thereof may be as follows.

Column number 0 0 … 111 112 … 127 128 129 … 239

The original RS code length is reduced by 1, namely 2, of the finite field length ^m -1. The primitive RS code polynomials can be expressed as:

a ₀ +a ₁ X+a ₂ X ² +…+a ₂₅₄ X ²⁵⁴ 。

In the embodiment of the present application, the RS codeword described by the check matrix is a truncated RS code. Truncated partial code polynomial a ₁₁₂ X ¹¹² +…+a ₁₂₇ X ¹²⁷ And a ₂₄₀ X ²⁴⁰ +…+a ₂₅₄ X ²⁵⁴ Part(s).

The above description mainly uses the component code as the RS code as an example, and this is not limitative. As yet another example, taking the component code as a non-binary BCH as an example, i.e., in the present application, the unbalanced spatially coupled codeword may be encoded with the non-binary BCH code. BCH codes are taken from the abbreviations of Bose, ray-Chaudhuri and Hocquenghem and are one of the more studied coding methods in coding theory, especially error correction codes. BCH codes can be used to correct multiple levels of random error patterns, cyclic, error correction, variable length digital codes. BCH codes can also be used for prime-level or multi-level phase shift keying of prime power level.

The component codes of the unbalanced spatially coupled code are assumed to be non-binary BCHs [252,245,5] over the finite field GF (16). The code block is 42×126 symbols. The parameters expressed in the zip expression are l= 3,w =42, m=42×3=126. Let the period of the inter-code block coupling function ψ (q, s) be 2. Table 3 shows possible coupling functions ψ (q, s).

TABLE 3 Table 3

It should be understood that the coupling functions shown in table 3 are merely exemplary and are not strictly limited thereto.

It should also be understood that the above description is given by taking component codes as RS codes and non-binary BCH as examples, which are not limited thereto, and any form of component codes may be used in the embodiments of the present application. For example, the component codes may also be other types of codewords, such as BCH codes, low density parity check codes (low density parity check code, LDPC), etc.

It should also be appreciated that FIG. 4 described above is merely exemplary and is not limiting. For example, the blocks in fig. 4 may have other shapes.

In the above manner 1, the codeword structure provided in the embodiment of the present application is mainly described based on the description manner of tiled zipper code. It should be understood that the foregoing is merely illustrative and is not strictly limiting.

Mode 2, symbol representation of component code.

In the embodiment of the present application, the encoding end may encode finite field data symbols (hereinafter referred to as data streams) in an unbalanced spatial coupling manner. The codeword structure may be described as follows.

1. The data stream is mapped to a sequence of semi-infinite code blocks.

A code block may represent a portion of a symbol matrix C of w rows and n columns of w×n, e.g., the code block may be represented as a matrix of w×m, that is, a sequence of semi-infinitely long code blocks may be decomposed into a plurality of w×m code blocks, where n, w, m are positive integers and m is less than n. By way of example, and not limitation, m=n/2.

Each code block may be composed of a plurality of symbols, and the plurality of symbols in each code block may include data symbols or may further include check symbols.

As mentioned above, a symbol may be understood as a carrier of information or data, e.g. one symbol is a bit in a binary symbol; for another example, one symbol is one character in the 16-ary symbol. It should be understood that the relation between symbols and bits is not limited, and for example, one symbol may be one bit or a plurality of bits.

2. The symbols in the component code belonging to code block B _i Two or more symbols belonging to one or more code blocks B _j . Where i and j are integers and j is less than i.

The component codes may be structurally different codewords. The component codes belong to different code blocks B _j The number of symbols of (a) may be different.

3. The component code is formed of data symbols and check symbols, or the symbols in the component code include data symbols and check symbols.

4. The check symbols in the component code may be represented by one or more symbols belonging to code block B _i And two or more code blocks B belonging to two or more _j Is generated by a symbol of (c). The generated check symbols belong to code block B _i 。

5. The code block B _i Or B is a _j May be represented as a matrix of w x m.

6. The code length of the component code is 2*m.

7. Each code block B _i May be represented as a matrix of wx (sxw). Each B is _i Can be divided into s w×w blocks. s is a positive integer, m=s×w.

8. Definition code block B _i The j-th column in the kth w×w block is denoted (i, j, k). Definition code block B _i Is (i, j). Where i is a positive integer. j is a positive integer less than or equal to w, and k is a positive integer less than or equal to s.

9. The symbols of the component codes come from columns of different code blocks.

One example is: (i-f) ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j). Wherein f ₁ ，f ₂ ，f ₃ Is a function of the output positive integer taking (i, j, k) as a variable. f (f) ₁ (i,j,1)≥f ₁ (i,j,2)≥…≥f ₁ (i,j,s)>0，1≤f ₂ (i,j,k)≤w，1≤f ₃ (i, j, k) is less than or equal to s. Wherein i, j, k, w, s are positive integers.

Wherein, (i-f ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j) define an unbalanced coupling relationship of row (i, j) to the historical codeword portion.

10. The symbols of the component codes come from columns of different code blocks.

One possible way is: (i-f) ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j). Wherein f ₁ ，f ₂ ，f ₃ Is a function of the output positive integer. Wherein f ₁ (i,j,s+1)＝1，f ₁ (i, j, k) is equal to f ₁ (i, j, k+1) or f ₁ (i,j,k+1)+2；f ₂ (i,j,k)＝j；f ₃ (i, j, k) =k. Wherein i, j, k, w, s are positive integers. j is less than or equal to w, and k is less than or equal to s.

Yet another possible way is: (i-f) ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j). Wherein f ₁ ，f ₂ ，f ₃ Is a function of the output positive integer. Wherein f ₁ (i,j,s+1)＝1，f ₁ (i, j, k) is equal to f ₁ (i, j, k+1) or f ₁ (i,j,k+1)+2；f ₂ (i,j,k)＝j；f ₃ (i, j, k) =s-k+1. Wherein i, j, k, w, s are positive integers. j is less than or equal to w, and k is less than or equal to s.

It should be understood that the two possible ways described above are only examples, and any modifications belonging to the above-described ways are applicable to the embodiments of the present application.

11. The component codes may be, but are not limited to: BCH codes (e.g., non-binary BCH codes), RS codes, LDPC codes.

For ease of understanding, the exemplary description is provided in connection with fig. 7.

Take the RS (224,218) over GF (256) as an example. The component code consists of columns of the history code block and rows of the current code block coupled. As shown in fig. 7, a code block offset may be defined: f (f) ₁ (i,j,k)＝f ₁ (k) =λ -2 x floor ((k-1)/2). As previously described, λ represents the coupling depth and may be constant, e.g., λ=7. Column numbers within a block can be defined: f (f) ₂ (i,j,k)＝f ₂ (j) A. The invention relates to a method for producing a fibre-reinforced plastic composite The block numbers within a code block may be defined: f (f) ₃ (i,j,k)＝f ₃ (k) =s-k+1. Wherein, (i-f ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)， f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s)，f ₃ (i, j, s)) and row (i, j) define an unbalanced coupling relationship of row (i, j) to the historical codeword portion.

Taking fig. 7 as an example, a component code can be expressed as: b (20-f) ₁ (1)，f ₂ (j)，f ₃ (1))，B(20-f ₁ (2)，f ₂ (j)，f ₃ (2))，B(20-f ₁ (3)，f ₂ (j)，f ₃ (3))，B(20-f ₁ (4)，f ₂ (j)，f ₃ (4))，B(20-f ₁ (5)，f ₂ (j)，f ₃ (5))，B(20-f ₁ (6)，f ₂ (j)，f ₃ (6))，B(20-f ₁ (7)，f ₂ (j)，f ₃ (7) And B (20, j). The code length is 2*N, where n=s×w, the unit is a symbol, which may be binary or non-binary.

The codeword structure was described above from different angles in connection with modes 1 and 2, respectively.

Fig. 8 shows a comparison of decoding performance of unbalanced space-coupled codes provided in accordance with the present application and balanced space-coupled codes of the prior art. Specifically, fig. 8 shows simulated comparisons of unbalanced spatially coupled codes and balanced spatially coupled codes at different decoding window lengths. The simulation result of fig. 8 is represented by the abscissa indicating the Bit Error Rate (BER) input to the FEC decoder, and the ordinate indicating the Bit Error Rate (BER) after decoding by the FEC decoder. In the example shown in fig. 8, the decoding window lengths of the curve L1 and the curve L2 are 10, as denoted by W10; the decoding window lengths of the curve L3 and the curve L4 are both 20, for example, denoted as W20; the decoding window length for both curve L5 and curve L6 is 40, as noted by W40. As shown in fig. 8, by comparing the simulation of different decoding window lengths, in the case that the decoding window is smaller than 20, the unbalanced space coupling code has a lower error rate after correction under the condition of the same error rate before correction. Thus, to achieve the same performance, unbalanced spatially coupled codes require smaller decoding window lengths. Therefore, the code words based on unbalanced spatial coupling have faster decoding convergence speed and shorter decoding delay.

Furthermore, codewords based on unbalanced spatial coupling may achieve shorter buffering delay. Compared with balanced space coupling, unbalanced space coupling is adopted, and the component codes with the same length are coupled with the historical codeword matrixes with fewer rows. Thus, the same number of real codewords are transmitted and received, and the unbalanced coupling has a shorter delay. Further, since the delay of transmitting and receiving the same number of real code words is reduced, the occupied data buffer is correspondingly reduced, so that the coding and decoding device based on the code words of unbalanced space coupling can occupy smaller buffer, and the power consumption caused by the data buffer is correspondingly reduced.

It should be understood that the foregoing embodiments are mainly described by taking "code blocks" as examples, and it should be understood that "code blocks" may be replaced by "frames". For example, the inter-block coupling function may be replaced by an inter-frame coupling function.

It will be appreciated that in the foregoing embodiments of the methods and operations implemented by the encoding end device, the methods and operations implemented by the decoding end device may also be implemented by a component (e.g., a chip or a circuit) that may be used in the encoding end device, or the methods and operations implemented by the decoding end device may also be implemented by a component (e.g., a chip or a circuit) that may be used in the decoding end device.

The method provided in the embodiment of the present application is described in detail above with reference to fig. 3 to 8. The following describes in detail the communication device provided in the embodiment of the present application with reference to fig. 9 to 12. It should be understood that the descriptions of the apparatus embodiments and the descriptions of the method embodiments correspond to each other, and thus, descriptions of details not described may be referred to the above method embodiments, which are not repeated herein for brevity.

Fig. 9 is a schematic block diagram of a communication device provided in an embodiment of the present application. The apparatus 900 comprises a transceiver unit 910 and a processing unit 920. The transceiving unit 910 may receive information or data from the outside, and the transceiving unit 910 may transmit information or data to the outside, and the processing unit 920 may perform data processing, for example, channel coding.

Optionally, the apparatus 900 may further include a storage unit, where the storage unit may be used to store instructions and/or data, and the processing unit 920 may read the instructions and/or data in the storage unit.

The apparatus 900 may be configured to perform the actions performed by the encoding end in the above method embodiment, where the apparatus 900 may be an encoder or a component configurable in the encoder, and the processing unit 920 is configured to perform the operations related to the processing on the encoding side in the above method embodiment.

Alternatively, the apparatus 900 may be configured to perform the actions performed by the decoding side in the above method embodiment, where the apparatus 900 may be a decoder or a component configurable in the decoder, and the processing unit 920 is configured to perform the operations related to the processing on the decoding side in the above method embodiment.

As a design, the communication apparatus 900 is configured to perform the actions performed by the encoding end device in the above method embodiment, and the transceiver unit 910 is configured to: acquiring a bit sequence to be encoded; the processing unit 920 is configured to: performing space coupling coding on a bit sequence to be coded to obtain a coded codeword; the code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling.

The communication apparatus 900 may implement steps or processes performed corresponding to the encoding end device in the method 300 according to the embodiment of the present application, and the communication apparatus 900 may include units for performing the method performed by the encoding end device in the method 300 in fig. 3. And, each unit in the communication device 900 and the other operations and/or functions described above are respectively for implementing the corresponding flow of the method 300 in fig. 3.

As another design, the communication apparatus 900 is configured to perform the actions performed by the decoding end device in the above method embodiment, and the transceiver unit 910 is configured to: receiving a codeword to be decoded; the processing unit 920 is configured to: decoding the code word; the code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling.

The communication apparatus 900 may implement steps or processes performed corresponding to a decoding end device in the method 600 according to an embodiment of the present application, and the communication apparatus 900 may include a unit for performing the method performed by the decoding end device in the method 600 in fig. 6. And, each unit in the communication device 900 and the other operations and/or functions described above are respectively for implementing the corresponding flow of the method 600 in fig. 6.

As an example, the codeword is a codeword matrix C with n columns and semi-infinite rows, and the codeword matrix C includes a virtual codeword matrix and a real codeword matrix; the coupling relation between the current code block bit and the history code block bit is unbalanced coupling, comprising: the coupling relationship between the sub-matrix of the virtual codeword matrix and the sub-matrix of the real codeword matrix is an unbalanced coupling relationship.

As yet another example, the sub-matrix of the virtual codeword matrix is coupled by a sub-matrix of the historical real codeword matrix.

As yet another example, the rows of codeword matrix C are denoted wq+i, the columns of codeword matrix C are denoted ws+j,

sub-matrix T of codeword matrix C _q,s The following formula is satisfied:

T _q,s ＝{c _qw+i,ws+j ∈C}；

wherein T is _q,s W×w submatrices representing the qth row and the sth column in the codeword matrix C; l, w is a positive integer; s epsilon [2L ]]；i,j∈[w]。

As yet another example, for s ε [ L ]]Sub-matrix T of the virtual codeword matrix in codeword matrix C _q,s The following formula is satisfied:

As yet another example, the q value is fixed and the ψ (q, s) corresponding to at least two s are the same.

As yet another example, ψ (q, s) =ψ(s).

As yet another example, the characteristics of codeword matrix C include:

The codeword matrix C is defined as w multiplied by w submatrices Cell division, T _q,s W×w submatrices representing the qth row and the sth column;

As yet another example, the codeword includes a plurality of component codes, each component code consisting of one or more columns of the historical code block and a row coupling of the current code block.

As yet another example, the codeword comprises a plurality of code blocks, the plurality of component codes comprising a first component code, at least two symbols in the first component code being from different codeword sub-matrices of the same code block.

As yet another example, the symbols in the first component code include one or more first symbols belonging to code block B, and a plurality of second symbols _i The second symbol belonging to one or more code blocks B _j Where i and j are positive integers and j is less than i.

As yet another example, symbols in a first component code form a plurality of blocks, the first component code being represented as:

As yet another example, j is less than or equal to w and k is less than or equal to s; f (f) ₁ (i,j,s+1)＝1；f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；f ₂ (i,j,k)＝j；f ₃ (i,j,k)＝k。

As yet another example, j is less than or equal to w and k is less than or equal to s; f (f) ₁ (i,j,s+1)＝1；f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；f ₂ (i,j,k)＝j；f ₃ (i,j,k)＝s-k+1。

As yet another example, the codeword includes the following characteristics:

As yet another example, the codeword includes a plurality of component codes, the component codes being any of: reed-solomon codes RS codes, BCH codes, low density parity check codes LDPC codes.

The processing unit 920 in the above embodiments may be implemented by at least one processor or processor-related circuits. The transceiver unit 910 may be implemented by a transceiver or transceiver related circuits. The transceiver unit 910 may also be referred to as a communication interface or a communication unit or an input-output unit. The memory unit may be implemented by at least one memory.

The apparatus 900 in the above embodiment may be a communication device or a chip (e.g., an encoding chip or a decoding chip) configured in the communication device.

As shown in fig. 10, the embodiment of the present application further provides a communication device 1000. The communication device 1000 comprises a processor 1010, the processor 1010 being coupled to a memory 1020, the memory 1020 being for storing computer programs or instructions or and/or data, the processor 1010 being for executing the computer programs or instructions and/or data stored by the memory 1020, such that the method in the above method embodiments is performed.

Optionally, the communications device 1000 includes one or more processors 1010.

Optionally, as shown in fig. 10, the communication device 1000 may further include a memory 1020.

Optionally, the communications device 1000 may include one or more memories 1020.

Alternatively, the memory 1020 may be integrated with the processor 1010 or provided separately.

Optionally, as shown in fig. 10, the wireless communication device 1000 may further include a transceiver 1030, where the transceiver 1030 is configured to receive and/or transmit signals. For example, the processor 1010 is configured to control the transceiver 1030 to receive and/or transmit signals.

As an aspect, the communication apparatus 1000 is configured to implement the operations performed by the encoding end device in the above method embodiment.

For example, the processor 1010 is configured to implement the operations related to the processing performed by the encoding end device in the above method embodiment, and the transceiver 1030 is configured to implement the operations related to the transceiving performed by the encoding end device in the above method embodiment.

Alternatively, the communication apparatus 1000 is configured to implement the operations performed by the decoding end device in the above method embodiment.

For example, the processor 1010 is configured to implement operations related to processing performed by the decoding end device in the above method embodiment, and the transceiver 1030 is configured to implement operations related to transceiving performed by the decoding end device in the above method embodiment.

The encoding end device of the embodiment of the application may also be an optical communication device. Fig. 11 is a schematic diagram showing an example of the encoding-side optical communication device of the present application, and as shown in fig. 11, the encoding-side optical communication device may include an input interface, an FEC encoder, a memory, a modulator, and an optical interface.

The input interface is used for acquiring a bit sequence to be encoded, the FEC encoder is used for executing the determination process of the codeword matrix, and the memory can be used for storing related information of the codeword matrix.

The decoding end device in the embodiment of the application may also be an optical communication device. Fig. 12 is a schematic diagram showing an example of the decoding-side optical communication device of the present application, and as shown in fig. 12, the encoding-side optical communication device may include an optical interface, a demodulator, an FEC decoder, and an output interface.

The optical interface is used for acquiring a code word sequence to be decoded, and the FEC decoder is used for executing the determining process of the code word matrix.

The present application also provides a computer readable storage medium, on which computer instructions for implementing the method performed by the encoding end device or the decoding end device in the above method embodiments are stored.

For example, the computer program when executed by a computer may enable the computer to implement the method performed by the encoding end device or the decoding end device in the above-described method embodiments.

The embodiments of the present application also provide a computer program product containing instructions that, when executed by a computer, cause the computer to implement the method performed by the encoding end device or the decoding end device in the method embodiments described above.

The embodiment of the application also provides a communication system, which comprises the encoding end device and the decoding end device in the embodiment.

Any explanation and beneficial effects of the related content in any of the communication devices provided above may refer to the corresponding method embodiments provided above, and are not described herein.

It will be clearly understood by those skilled in the art that, for convenience and brevity, explanation and beneficial effects of the relevant content in any of the above-mentioned communication devices may refer to the corresponding method embodiments provided above, and are not repeated here.

In the embodiment of the application, the encoding end device or the decoding end device may include a hardware layer, an operating system layer running above the hardware layer, and an application layer running above the operating system layer. The hardware layer may include a central processing unit (central processing unit, CPU), a memory management unit (memory management unit, MMU), and a memory (also referred to as a main memory). The operating system of the operating system layer may be any one or more computer operating systems that implement business processing through processes (processes), for example, a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or windows operating system, etc. The application layer may include applications such as a browser, address book, word processor, instant messaging software, and the like.

The present embodiment does not particularly limit the specific structure of the execution body of the method provided in the present embodiment, as long as communication can be performed in the method provided in the present embodiment by running a program in which the code of the method provided in the present embodiment is recorded. For example, the execution body of the method provided in the embodiment of the present application may be an encoding end device or a decoding end device, or may be a functional module in the encoding end device or the decoding end device that can call a program and execute the program.

Various aspects or features of the present application can be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein may encompass a computer program accessible from any computer-readable device, carrier, or media.

Among other things, computer readable storage media can be any available media that can be accessed by a computer or data storage devices such as servers, data centers, etc. that contain one or more integration of the available media. Usable (or computer readable) media may include, for example, but are not limited to: magnetic media or magnetic storage devices (e.g., floppy disks, hard disks (e.g., removable disks), magnetic tape), optical media (e.g., compact Discs (CDs), digital versatile discs (digital versatile disc, DVDs), etc.), smart cards and flash memory devices (e.g., erasable programmable read-only memories (EPROMs), cards, sticks, or key drives, etc.), or semiconductor media (e.g., solid State Disks (SSDs), etc., U-discs, read-only memories (ROMs), random access memories (random access memory, RAMs), etc., various media that may store program code.

Various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to: wireless channels, and various other media capable of storing, containing, and/or carrying instruction(s) and/or data.

It should be appreciated that the processors referred to in the embodiments of the present application may be central processing units (central processing unit, CPU), but may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate arrays (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It should also be understood that the memory referred to in the embodiments of the present application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM). For example, RAM may be used as an external cache. By way of example, and not limitation, RAM may include the following forms: static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM).

It should be noted that when the processor is a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, the memory (storage module) may be integrated into the processor.

It should also be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the above-described division of units is merely a logical function division, and there may be another division manner in actual implementation, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Furthermore, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to implement the solution provided in the present application.

In addition, each functional unit in each embodiment of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.

When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. For example, the computer may be a personal computer, a server, or a network device, etc. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.) means from one website, computer, server, or data center. With respect to computer readable storage media, reference may be made to the description above.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims and the specification.

Claims

A method of encoding, comprising:

acquiring a bit sequence to be encoded;

performing space coupling coding on the bit sequence to be coded to obtain coded code words;

the code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling.
The method of claim 1, wherein the codeword is a codeword matrix C having a number of columns n and a number of rows semi-infinite, the codeword matrix C comprising a virtual codeword matrix and a real codeword matrix;

the coupling relation between the current code block bit and the history code block bit is unbalanced coupling, and the method comprises the following steps:

the coupling relation between the sub-matrix of the virtual codeword matrix and the sub-matrix of the real codeword matrix is an unbalanced coupling relation.
The method of claim 2, wherein the sub-matrix of the virtual codeword matrix is coupled by a sub-matrix of a historical real codeword matrix.
A method according to claim 2 or 3, characterized in that the rows of the codeword matrix C are denoted wq+i, the columns of the codeword matrix C are denoted ws+j,

a submatrix T of the codeword matrix C _q,s The following formula is satisfied:

T _q,s ＝{c _qw+i,ws+j ∈C}；

wherein T is _q,s W×w submatrices representing the qth row and the sth column in the codeword matrix C; l, w is a positive integer; s epsilon [2L ]]；i,j∈[w]。
The method of claim 4, wherein for s ε [ L ]]Sub-matrix T of the virtual codeword matrix in the codeword matrix C _q,s The following formula is satisfied:

wherein ψ (q, s) represents the unbalanced coupling function; the superscript T denotes the transpose.
The method of claim 5, wherein q values are fixed and at least two s correspond to the same ψ (q, s).
The method according to claim 5 or 6, wherein,

ψ(q,s)＝ψ(s)。
the method according to any of the claims 2 to 7, characterized in that the codeword matrix C is characterized by:

the unit of the codeword matrix C is a codeword symbol, zx [ n ] represents the codeword matrix C with the column number of n, wherein m=wL, n=2wL, L and w are positive integers, and m represents the column width of each row of the virtual codeword matrix;

The rows of the codeword matrix C are denoted wq+i, the columns are denoted ws+j, q ε Z, s ε [2L ], and i, j ε [ w ];

definition of w×w matrix T _q,s T being a submatrix of the codeword matrix C _q,s ＝{c _qw+i,ws+j ∈C:i,j∈[w]}；

Dividing the codeword matrix C into units according to w×w submatrices, and T _q,s W×w submatrices representing the qth row and the sth column;

for s E [ L ]]Sub-matrices defining a virtual codeword matrixThe submatrices of the virtual codeword matrix are obtained by coupling submatrices of the historical real codeword matrix;

wherein ψ (q, s) is a positive integer; psi and s are not bijective for at least one q e Z.
The method of claim 1, wherein the codeword comprises a plurality of component codes, each component code consisting of one or more columns of a history code block and a row coupling of a current code block.
The method of claim 9, wherein the codeword comprises a plurality of code blocks, the plurality of component codes comprising a first component code, at least two symbols in the first component code from different codeword sub-matrices of the same code block.
The method of claim 10, wherein the step of determining the position of the first electrode is performed,

the symbols in the first component code comprise one or more first symbols and a plurality of second symbols, the first symbols belong to a code block B _i The second symbol belongs to one or more code blocks B _j Where i and j are positive integers and j is less than i.
The method of claim 11, wherein symbols in the first component code form a plurality of blocks, the first component code being represented as:

(i-f ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j),

wherein f ₁ ，f ₂ ，f ₃ Is a function of an output positive integer having (i, j, k) as a variable; (i, j, k) represents code block B _i The j-th column in the kth w×w block; (i, j) represents code block B _i R line of (2); f (f) ₁ (i,j,1)≥f ₁ (i,j,2)≥…≥f ₁ (i,j,s)>0，1≤f ₂ (i,j,k)≤w，1≤f ₃ And (i, j, k) is less than or equal to s, k, w, s are positive integers.
The method of claim 12, wherein j is less than or equal to w and k is less than or equal to s;

f ₁ (i,j,s+1)＝1；

f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；

f ₂ (i,j,k)＝j；

f ₃ (i,j,k)＝k。
The method of claim 12, wherein j is less than or equal to w and k is less than or equal to s;

f ₁ (i,j,s+1)＝1；

f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；

f ₂ (i,j,k)＝j；

f ₃ (i,j,k)＝s-k+1。
The method according to any of the claims 12 to 14, characterized in that the codeword comprises the following characteristics:

code block offset of the first component code: f (f) ₁ (i,j,k)＝f ₁ (k) λ -2 x floor ((k-1)/2), wherein floor represents a rounding down, λ is a constant;

symbols in the first component code form a plurality of blocks, column numbers within the blocks: f (f) ₂ (i,j,k)＝f ₂ (j)；

Block numbers within code blocks constituting the first component code: f (f) ₃ (i,j,k)＝f ₃ (k)＝s-k+1。
The method according to any one of claims 1 to 15, wherein,

the codeword comprises a plurality of component codes, the component codes being any of: reed-solomon codes RS codes, BCH codes, low density parity check codes LDPC codes.
A method of decoding, comprising:

receiving a codeword to be decoded;

decoding the code word;

the code word comprises current code block bits and historical code block bits, and the coupling relation between the current code block bits and the historical code block bits is unbalanced coupling.
The method of claim 17, wherein the codeword is a semi-infinite codeword matrix C having a number of columns n and a number of rows, the codeword matrix C comprising a virtual codeword matrix and a real codeword matrix;

the coupling relation between the current code block bit and the history code block bit is unbalanced coupling, and the method comprises the following steps:

the coupling relation between the sub-matrix of the virtual codeword matrix and the sub-matrix of the real codeword matrix is an unbalanced coupling relation.
The method of claim 18, wherein the sub-matrix of the virtual codeword matrix is coupled by a sub-matrix of a historical real codeword matrix.
The method according to claim 18 or 19, characterized in that the rows of the codeword matrix C are denoted wq+i, the columns of the codeword matrix C are denoted ws+j,

A submatrix T of the codeword matrix C _q,s The following formula is satisfied:

T _q,s ＝{c _qw+i,ws+j ∈C}；

wherein T is _q,s W×w submatrices representing the qth row and the sth column in the codeword matrix C; l, w is a positive integer; s epsilon [2L ]]；i,j∈[w]。
The method of claim 20, wherein for s e [ L ]]Sub-matrix T of the virtual codeword matrix in the codeword matrix C _q,s The following formula is satisfied:

wherein ψ (q, s) represents the unbalanced coupling function; the superscript T denotes the transpose.
The method of claim 21, wherein q values are fixed and at least two s correspond to the same ψ (q, s).
The method according to claim 21 or 22, wherein,

ψ(q,s)＝ψ(s)。
the method according to any of the claims 18 to 23, characterized in that the codeword matrix C comprises:

the unit of the codeword matrix C is a codeword symbol, zx [ n ] represents the codeword matrix C with the column number of n, wherein m=wL, n=2wL, L and w are positive integers, and m represents the column width of each row of the virtual codeword matrix;

the rows of the codeword matrix C are denoted wq+i, the columns are denoted ws+j, q ε Z, s ε [2L ], and i, j ε [ w ];

definition of w×w matrix T _q,s T being a submatrix of the codeword matrix C _q,s ＝{c _qw+i,ws+j ∈C:i,j∈[w]}；

Dividing the codeword matrix C into units according to w×w submatrices, and T _q,s W×w submatrices representing the qth row and the sth column;

for s E [ L ]]Sub-matrices defining a virtual codeword matrixThe submatrices of the virtual codeword matrix are obtained by coupling submatrices of the historical real codeword matrix;

wherein ψ (q, s) is a positive integer; psi and s are not bijective for at least one q e Z.
The method of claim 17, wherein the codeword comprises a plurality of component codes, each component code consisting of one or more columns of a history code block and a row coupling of a current code block.
The method of claim 25, wherein the codeword comprises a plurality of code blocks, the plurality of component codes comprising a first component code, at least two symbols in the first component code being from different codeword sub-matrices of the same code block.
The method of claim 26, wherein the step of determining the position of the probe is performed,

the symbols in the first component code comprise one or more first symbols and a plurality of second symbols, the first symbols belong to a code block B _i The second symbol belongs to one or more code blocks B _j Where i and j are positive integers and j is less than i.
The method of claim 27, wherein symbols in the first component code form a plurality of blocks, the first component code being represented as:

(i-f ₁ (i,j,1)，f ₂ (i,j,1)，f ₃ (i,j,1))，(i-f ₁ (i,j,2)，f ₂ (i,j,2)，f ₃ (i,j,2))，…，(i-f ₁ (i,j,s)，f ₂ (i,j,s),f ₃ (i, j, s)) and row (i, j),

wherein f ₁ ，f ₂ ，f ₃ Is a function of an output positive integer having (i, j, k) as a variable; (i, j, k) represents code block B _i The j-th column in the kth w×w block; (i, j) represents code block B _i R line of (2); f (f) ₁ (i,j,1)≥f ₁ (i,j,2)≥…≥f ₁ (i,j,s)>0，1≤f ₂ (i,j,k)≤w，1≤f ₃ And (i, j, k) is less than or equal to s, k, w, s are positive integers.
The method of claim 28, wherein j is less than or equal to w and k is less than or equal to s;

f ₁ (i,j,s+1)＝1；

f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；

f ₂ (i,j,k)＝j；

f ₃ (i,j,k)＝k。
The method of claim 28, wherein j is less than or equal to w and k is less than or equal to s;

f ₁ (i,j,s+1)＝1；

f ₁ (i,j,k)＝f ₁ (i, j, k+1), or, f ₁ (i,j,k)＝f ₁ (i,j,k+1)+2；

f ₂ (i,j,k)＝j；

f ₃ (i,j,k)＝s-k+1。
The method according to any of the claims 18 to 30, characterized in that the codeword comprises the following characteristics:

code block offset of the first component code: f (f) ₁ (i,j,k)＝f ₁ (k) λ -2 x floor ((k-1)/2), wherein floor represents a rounding down, λ is a constant;

symbols in the first component code form a plurality of blocks, column numbers within the blocks: f (f) ₂ (i,j,k)＝f ₂ (j)；

Block numbers within code blocks constituting the first component code: f (f) ₃ (i,j,k)＝f ₃ (k)＝s-k+1。
The method according to any one of claims 17 to 31, wherein,

the codeword comprises a plurality of component codes, the component codes being any of: reed-solomon codes RS codes, BCH codes, low density parity check codes LDPC codes.
A chip comprising logic circuitry and a communication interface, the communication interface to receive and transmit data and/or information to be processed to the logic circuitry, the logic circuitry to perform the encoding of any of claims 1-16, and the communication interface to output the encoded codeword.
A chip comprising logic circuitry and a communication interface, the communication interface to receive and transmit data and/or information to be processed to the logic circuitry, the logic circuitry to perform the decoding process of any of claims 17-32, and the communication interface to output a decoding result.
An encoding apparatus comprising at least one processor coupled to at least one memory, the at least one processor configured to execute a computer program or instructions stored in the at least one memory to cause the communications apparatus to perform the encoding method of any one of claims 1-16.
The encoding device of claim 35, wherein the at least one processor is integrated with the at least one memory.
A decoding apparatus comprising at least one processor coupled to at least one memory, the at least one processor configured to execute a computer program or instructions stored in the at least one memory to cause the communication apparatus to perform the decoding method of any of claims 17-32.
The coding device of claim 37, wherein the at least one processor is integrated with the at least one memory.
A computer readable storage medium having stored therein computer instructions which, when run on a computer, implement the encoding method of any of claims 1-16.
A computer readable storage medium having stored therein computer instructions which, when run on a computer, implement the decoding method of any of claims 17-32.