CN116489113A - Port expanding method and system of switch chip and switch - Google Patents

Port expanding method and system of switch chip and switch Download PDF

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Publication number
CN116489113A
CN116489113A CN202310441813.3A CN202310441813A CN116489113A CN 116489113 A CN116489113 A CN 116489113A CN 202310441813 A CN202310441813 A CN 202310441813A CN 116489113 A CN116489113 A CN 116489113A
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China
Prior art keywords
port
ethernet
ethernet message
switch
switch chip
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CN202310441813.3A
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CN116489113B (en
Inventor
阮召崧
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Nanjing Jinzhen Microelectronics Technology Co ltd
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Nanjing Jinzhen Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/111—Switch interfaces, e.g. port details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The application provides a port expanding method and system of a switch chip and the switch, wherein the method comprises the following steps: acquiring a first Ethernet message, and replacing a preamble in the first Ethernet message as a data packet control header to generate a second Ethernet message; searching a forwarding result of the second Ethernet message based on a two-layer forwarding logic, and assigning the forwarding result to the data packet control header to generate a third Ethernet message; and checking a data packet control header of the third Ethernet message, and acquiring a target port based on a checking result so as to forward the third Ethernet message through the target port. The method and the device realize port expansion of the Ethernet chip based on the redefined data packet control header, and meanwhile, the extra cost of the Ethernet is not increased; the physical cascade between the low-speed switch chip and the high-speed switch chip is realized through the data packet control header, the number of switches is reduced, the management cost is reduced, and the competitiveness is improved.

Description

Port expanding method and system of switch chip and switch
Technical Field
The application belongs to the technical field of switches, and particularly relates to a port expanding method and system of a switch chip and a switch.
Background
The switch chip is one of the core components of the switch and is mainly responsible for high-performance and low-delay switching in the subnetwork. The connection capability of a switch-specific chip is objectively limited due to its limited number of physical ports, e.g., typically 16, 24, 48, etc.
To meet various flexible demands of networking, a common solution is to increase the number of switch chips in a switch system, and to increase the number of other devices connected to the switch chips by increasing the number of physical ports, so that a plurality of small switches are combined into one larger switch. Because of the high price of some switch-specific chips, the overall cost of the switch system is high if multi-node and large-scale switch deployment is to be implemented.
Disclosure of Invention
The purpose of the application is to provide a port expanding method and system of a switch chip and a switch, which are used for solving the technical problem of high management cost of the existing switch port expanding technology.
In a first aspect, the present application provides a port expansion method of a switch chip, including:
acquiring a first Ethernet message, and replacing a preamble in the first Ethernet message as a data packet control header to generate a second Ethernet message;
searching a forwarding result of the second Ethernet message based on a two-layer forwarding logic, and assigning the forwarding result to the data packet control header to generate a third Ethernet message;
and checking a data packet control header of the third Ethernet message, and acquiring a target port based on a checking result so as to forward the third Ethernet message through the target port.
In one implementation manner of the first aspect, the packet control header includes:
a start field, wherein the start field is a byte and is used for representing the start of the second Ethernet message and/or the third Ethernet message;
an expansion port field, wherein the expansion port field is one byte and is used for representing the port number of expansion;
the expansion content field is five bytes and is used for filling expansion information;
and the check field is one byte and is used for carrying out error check on the second Ethernet message and/or the third Ethernet message.
In an implementation manner of the first aspect, searching for a forwarding result of the second ethernet packet based on the two-layer forwarding logic, assigning the forwarding result to the packet control header, so as to generate a third ethernet packet includes:
searching a source address and a target address of the second Ethernet message based on the two-layer forwarding logic;
and assigning the source address and the target address to an expansion port field of a data packet control header to generate a third Ethernet message.
In an implementation manner of the first aspect, looking up a packet control header of the third ethernet packet, and acquiring a destination port based on a result of looking up, so as to forward the third ethernet packet through the destination port includes:
checking a data packet control header of the third Ethernet message to obtain a source address and a target address in an expansion port field;
searching a port table according to the target address in the expansion port field to acquire a target port;
and forwarding the third Ethernet message through the target port.
In a second aspect, the present application provides a switch, including a first switch chip, a second switch chip, and a third switch chip;
the first switch chip is used for acquiring a first Ethernet message and replacing a preamble in the first Ethernet message as a data packet control header so as to generate a second Ethernet message;
the second switch chip is cascaded with the first switch chip and is used for searching a forwarding result of the second Ethernet message based on a two-layer forwarding logic, and assigning the forwarding result to the data packet control header so as to generate a third Ethernet message;
the third switch chip is cascaded with the second switch chip, and is configured to view a packet control header of the third ethernet packet, and obtain a target port based on a viewing result, so as to forward the third ethernet packet through the target port.
In one implementation of the second aspect, the rate of the second switch chip is greater than the rates of the first switch chip and the third switch chip.
In one implementation manner of the second aspect, the first switch chip includes a first ethernet port and a first cascade port;
the first Ethernet port is used for inputting the first Ethernet message;
the first cascade port is used for outputting the second Ethernet message.
In one implementation manner of the second aspect, the second switch chip includes a second cascade port and a third cascade port;
the second cascade port is connected with the first cascade port and is used for inputting a second Ethernet message;
the third cascade port is used for outputting a third Ethernet message.
In one implementation manner of the second aspect, the third switch chip includes a fourth cascade port and a second ethernet port;
the fourth cascade port is connected with the third cascade port and is used for inputting a third Ethernet message;
the second ethernet port is a destination port for forwarding a third ethernet packet.
In a third aspect, the present application provides a system for expanding a port of a chip of a switch, including any one of the switches, a first terminal, and a second terminal;
the first terminal is connected with the switch through a first Ethernet port and is used for sending a first Ethernet message;
the second terminal is connected with the switch through a second Ethernet port and is used for receiving a third Ethernet message.
As described above, the port expanding method and system of the switch chip and the switch have the following beneficial effects:
(1) Redefining a start zone bit of the first Ethernet message, replacing a preamble in the first Ethernet message by using a data packet control header, and expanding a port of an Ethernet chip based on the redefined data packet control header without increasing the additional cost of the Ethernet;
(2) The physical cascade between the low-speed switch chip and the high-speed switch chip is realized through the data packet control header, so that a large-scale switch network is formed by a plurality of switch chips, the number of switches is reduced, the management cost is reduced, and the competitiveness is improved.
Drawings
Fig. 1 is a flowchart of a port expansion method of a switch chip according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a packet control header of a port expansion method of a switch chip according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a switch structure according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a cascade structure between a low-speed switch chip and a high-speed switch chip according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a port expansion system of a switch chip according to an embodiment of the present application.
Description of element reference numerals
1. Switch board
11. First switch chip
12. Second exchanger chip
13. Third switch chip
2. First terminal
3. Second terminal
S101-S104 steps
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that, the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In addition, descriptions such as those related to "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated in this application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.
The following embodiments of the present application provide a port expansion method and system for a switch chip, and a switch, which solve the technical problem of high management cost of the existing switch port expansion technology. The following describes the technical solutions in the embodiments of the present application in detail with reference to the drawings in the embodiments of the present application.
As shown in fig. 1, this embodiment provides a port expanding method of a switch chip, including:
step S101, a first Ethernet message is obtained, and a preamble in the first Ethernet message is replaced to be a data packet control header so as to generate a second Ethernet message.
As shown in table 1, the IEEE802.3 standard specifies the format of an ethernet message (abbreviated 802.3 Frame), and the 802.3 Frame includes a preamble (preamble), a Start-of-Frame Delimiter (SFD), a destination address (Destination Address, DA), a source address (SourceAddress, SA), an ethernet type (Ethertype), a VLAN TAG (TAG), and the remainder of the ethernet message (Rest ofEthernet Frame).
Table 1, ethernet message format specified by IEEE802.3 standard
In the ethernet protocol, the preamble field of the ethernet packet includes 7 bytes of "0x55" for synchronizing clocks of the sender and the receiver, and determining the start of a data frame. The SFD includes one byte of "0xD5" for indicating the end of the preamble and informing the receiver that the next field is the address of the destination host. The DA is six bytes of data for representing the MAC address of the destination node, i.e., the receiver of the data frame. The SA is six bytes of data used to represent the MAC address of the source node, i.e., the sender of the data frame. Ethertype is two bytes of data, which is a message to be transmitted by a stack port that can be defined by software, and in one embodiment, it can be defined as "0x9988", i.e., a stack type message, which is equivalent to a stack identifier. The TAG is five bytes of data, including information such as VLAN ID, priority, CFI, etc., and through the TAG, the switch can classify and forward the data frame according to different VLANs. Rest ofEthernet Frame is the remainder of the ethernet message.
The packet control header (Packet Control Header, PCH) is a network protocol header that is typically used with other protocol headers (e.g., IP headers, TCP/UDP headers, etc.) to achieve efficient data transmission and processing and to improve the performance, reliability, and security of the network. The PCH contains a number of fields for transmission of various control information such as queue number, flow control, error detection, etc. Specifically, as shown in table 2 and fig. 2, in one embodiment, the packet control header includes:
a. and the start field is one byte and is used for indicating the start of the second Ethernet message and/or the third Ethernet message.
Specifically, the field of the Start OfPacket (SOP) is Byte0, which functions equivalently to the SFD in the 802.3 frame.
It should be noted that, in the embodiments of the present application, a specific value may be specified to indicate the start of the ethernet packet. For example, the specific value may be "0xfb", or may be another value, which is not particularly limited herein.
b. And the expansion port field is one byte and is used for representing the port number of expansion.
Specifically, the field segment of the expansion port field is Byte1, and Byte1 includes 8 bits of pktTy [1:0], subPort ID [3:0] and ExtTy [1:0 ].
Wherein pktTy [1:0] comprises two bits of bit6 and bit7, and the following four ethernet messages can be represented by combination:
(1) 2' b0: representing a common Ethernet message;
(2) 2' b1: an Ethernet message for controlling is represented;
(3) 2' b10: -representing precision time protocol (Precision Time Protocol, PTP) messages;
(4) 2' b11: a message representing the enabling control of the quality of service (Quality ofService, qoS) function.
The subpart Id [3:0] includes four bits bit2 through bit5, which can represent up to 16 ports, 0-15.
ExtTy [1:0] includes two bits, bit0 and bit1, which, by combination, can represent the following meanings:
(1) 2' b0: indicating that PCH in the transmission direction and reception direction will be ignored when the value is 0;
(2) 2' b1: indicating that PCH in the transmission direction and reception direction will be ignored when the value is 0;
(3) 2' b10: representing the type of frame priority, including low priority and high priority;
(4) 2' b11: indicating that PCH in the transmit direction and the receive direction will be ignored when the value is 0.
c. And the expansion content field is five bytes and is used for filling expansion information.
Specifically, the field of the extended content field is five bytes in total from Byte2 to Byte 6. The filled expansion information is used to represent the specific meaning represented by each expansion port.
d. And the check field is one byte and is used for carrying out error check on the second Ethernet message and/or the third Ethernet message.
Specifically, the field segment of the check field is Byte7, and the check mode is cyclic redundancy check (Cyclic Redundancy Check, CRC). CRC is a method of detecting whether an error occurs in a data transmission process by generating a check value. In this implementation, by using CRC check, it is possible to detect whether the PCH is corrupted during transmission. When detecting that the PCH is damaged, retransmission is needed or other necessary error correction measures are adopted, so that transmission errors are effectively reduced, and the integrity and the correctness of the PCH are ensured.
Table 2, field of packet control header and related description
It should be noted that the above a-d fields of PCH are optional and may be configured according to actual requirements.
In this implementation manner, the preamble in the first ethernet packet is replaced with the packet control header, which is equivalent to redefining the start flag bit of the first ethernet packet, and the port expansion of the ethernet chip can be implemented based on the redefined packet control header without increasing the overhead of the ethernet.
Step S102, based on the two-layer forwarding logic, searching the forwarding result of the second Ethernet message, and assigning the forwarding result to the data packet control header to generate a third Ethernet message.
In an embodiment, searching for a forwarding result of the second ethernet packet based on the two-layer forwarding logic, and assigning the forwarding result to the packet control header to generate a third ethernet packet includes:
searching a source address and a target address of the second Ethernet message based on the two-layer forwarding logic;
and assigning the source address and the target address to an expansion port field of a data packet control header to generate a third Ethernet message.
Step S103, checking the data packet control header of the third Ethernet message, and acquiring a target port based on the checking result so as to forward the third Ethernet message through the target port.
In an embodiment, looking up the packet control header of the third ethernet packet, and acquiring the destination port based on the looking up result, so as to forward the third ethernet packet through the destination port includes:
checking a data packet control header of the third Ethernet message to obtain a source address and a target address in an expansion port field;
searching a port table according to the target address in the expansion port field to acquire a target port;
and forwarding the third Ethernet message through the target port.
In an embodiment, the method further includes step S104 of checking a packet control header of the third ethernet packet, and managing and controlling the network traffic based on the checking result.
In the embodiment of the present application, the management and control of network traffic are related to QoS functions, and when 2' b11 in pktTy [1:0] is in an active (enabled) state, that is, the quality of service (Quality ofService, qoS) is enabled, this step S104 may be executed.
Specifically, managing and controlling network traffic based on the viewing results includes: and classifying and setting the traffic of different priorities according to the 2' b10 of the ExtTy [1:0] field in the PCH, namely the type of the frame priority, so as to realize the guarantee of different service qualities. In the implementation mode, the performance and reliability of the network service can be optimized, and different requirements of different applications on bandwidth, delay, packet loss rate and the like are met.
The protection scope of the port expanding method of the switch chip in the embodiment of the application is not limited to the execution sequence of the steps listed in the embodiment, and all the schemes implemented by increasing or decreasing the steps and replacing the steps according to the principles of the application in the prior art are included in the protection scope of the application.
As shown in fig. 3, the present embodiment provides a switch 1 including a first switch chip 11, a second switch chip 12, and a third switch chip 13.
The first switch chip 11 is configured to obtain a first ethernet packet, and replace a preamble in the first ethernet packet with a packet control header to generate a second ethernet packet.
The second switch chip 12 is cascaded with the first switch chip 11, and is configured to find a forwarding result of the second ethernet packet based on a two-layer forwarding logic, and assign the forwarding result to the packet control header, so as to generate a third ethernet packet.
The third switch chip 13 is cascaded with the second switch chip 12, and is configured to view a packet control header of the third ethernet packet, and obtain a destination port based on a viewing result, so as to forward the third ethernet packet through the destination port.
It should be noted that, the structures and principles of the first switch chip 11, the second switch chip 12 and the third switch chip 13 in this embodiment correspond to the steps and embodiments in the port expansion method of the switch chip one by one, so that the description thereof is omitted here.
In one embodiment, the rate of the second switch chip 12 is greater than the rate of the first switch chip 11 and the third switch chip 13.
In one embodiment, the first switch chip 11 includes a first ethernet port and a first cascade port.
The first ethernet port is configured to input the first ethernet packet.
The first cascade port is used for outputting the second Ethernet message.
In one embodiment, the second switch chip 12 includes a second cascade port and a third cascade port.
The second cascade port is connected with the first cascade port and is used for inputting a second Ethernet message.
The third cascade port is used for outputting a third Ethernet message.
In one embodiment, the third switch chip 13 includes a fourth cascade port and a second ethernet port.
The fourth cascade port is connected with the third cascade port and is used for inputting a third Ethernet message.
The second ethernet port is a destination port for forwarding a third ethernet packet.
In this embodiment of the present application, the first switch chip 11 and the third switch chip 13 are low-speed switch chips, the second switch chip 12 is a high-speed switch chip, the rates of the first ethernet port and the second ethernet port are typically 1Gbps or 2.5Gbps, and the rates of the first cascade port, the second cascade port, the third cascade port and the fourth cascade port are typically 10Gbps.
It should be noted that the high-speed switch chip of the present application may support a plurality of low-speed switch chips, and in particular, the number of low-speed switch chips that may be cascaded is related to the number of ports on the high-speed switch chip. As shown in fig. 4, when there are (n+1) ports on the high-speed switch chip, then (n+1) low-speed switch chips can be cascaded.
In the implementation mode, the physical cascade connection between the low-speed switch chip and the high-speed switch chip is realized through the data packet control header, so that a large-scale switch network is formed by a plurality of switch chips, the number of switches is reduced, the management cost is reduced, and the competitiveness is improved.
In this embodiment, the first ethernet port and the second ethernet port include 10BASE-T, 100BASE-T, 1000BASE-T, and a fiber interface, and the specific types of the first ethernet port and the second ethernet port are not limited in this embodiment. The first and second, third and fourth cascaded ports form two sets of switch connection interfaces (Switch Link Interface, SLI). The SLI is an Ultra-short-distance gigabit media independent interface (Ultra-Short Reach Gigabit Media Independent Interface, USGMII), and the Ethernet message enters the high-speed switching chip from the low-speed switching chip through the USGMII and is finally forwarded to an external terminal through another low-speed switch. The USGMII standard is an efficient, flexible, extensible network interface technology that can support the design of high density switches and routers.
In the implementation manner, the USGMII port is adopted, so that the performance and reliability of the network equipment can be improved, and the cost and the power consumption are reduced. Compared with the existing 1000BASE-T interface, the USGMII interface has lower power consumption, higher speed and better expansibility, and can support more port density and higher bandwidth requirements. In addition, the USGMII interface also supports high-level functions such as configurable data packet size, flow control, multiple queues and the like so as to meet different application scene requirements.
The switch described in the embodiment of the present application may implement the port expansion method of the switch chip described in the present application, but the implementation device of the port expansion method of the switch chip described in the present application includes, but is not limited to, the structure of the switch listed in the present embodiment, and all structural modifications and substitutions made according to the principles of the present application in the prior art are included in the protection scope of the present application.
As shown in fig. 5, a system for expanding a chip port of a switch is characterized by comprising the switch, a first terminal and a second terminal.
The first terminal is connected with the switch through a first Ethernet port and is used for sending a first Ethernet message.
The second terminal is connected with the switch through a second Ethernet port and is used for receiving a third Ethernet message.
It should be noted that, the first terminal and the second terminal described in the present application may include a personal computer (Personal Computer, PC), a server, a router, a network storage device, a network camera, a monitoring device, a printer, an industrial control device, an intelligent terminal device, etc., and the specific types of the first terminal and the second terminal are not limited in this embodiment of the present application, and other external terminal devices with ethernet interfaces are also suitable for the present application.
In the several embodiments provided in this application, it should be understood that the disclosed system or method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules/units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.
The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the purposes of the embodiments of the present application. For example, functional modules/units in various embodiments of the present application may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.
In summary, the method and system for expanding the port of the switch chip and the switch redefine the start flag bit of the first ethernet message, and replace the preamble in the first ethernet message with the packet control header, so that the port expansion of the ethernet chip is realized, and meanwhile, the additional overhead of the ethernet is not increased; the physical cascade between the low-speed switch chip and the high-speed switch chip is realized through the data packet control header, so that a large-scale switch network is formed by a plurality of switch chips, the number of switches is reduced, the management cost is reduced, and the competitiveness is improved.
The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims (10)

1. The port expanding method of the switch chip is characterized by comprising the following steps of:
acquiring a first Ethernet message, and replacing a preamble in the first Ethernet message as a data packet control header to generate a second Ethernet message;
searching a forwarding result of the second Ethernet message based on a two-layer forwarding logic, and assigning the forwarding result to the data packet control header to generate a third Ethernet message;
and checking a data packet control header of the third Ethernet message, and acquiring a target port based on a checking result so as to forward the third Ethernet message through the target port.
2. The port expansion method of the switch chip according to claim 1, wherein the packet control header comprises:
a start field, wherein the start field is a byte and is used for representing the start of the second Ethernet message and/or the third Ethernet message;
an expansion port field, wherein the expansion port field is one byte and is used for representing the port number of expansion;
the expansion content field is five bytes and is used for filling expansion information;
and the check field is one byte and is used for carrying out error check on the second Ethernet message and/or the third Ethernet message.
3. The method of port expansion of a switch chip of claim 1, wherein looking up a forwarding result of the second ethernet packet based on a two-layer forwarding logic, assigning the forwarding result to the packet control header to generate a third ethernet packet comprises:
searching a source address and a target address of the second Ethernet message based on the two-layer forwarding logic;
and assigning the source address and the target address to an expansion port field of a data packet control header to generate a third Ethernet message.
4. The method for expanding ports of a switch chip according to claim 1, wherein looking up a packet control header of the third ethernet packet and acquiring a destination port based on a result of looking up, so as to forward the third ethernet packet through the destination port, comprises:
checking a data packet control header of the third Ethernet message to obtain a source address and a target address in an expansion port field;
searching a port table according to the target address in the expansion port field to acquire a target port;
and forwarding the third Ethernet message through the target port.
5. A switch, comprising a first switch chip, a second switch chip, and a third switch chip;
the first switch chip is used for acquiring a first Ethernet message and replacing a preamble in the first Ethernet message as a data packet control header so as to generate a second Ethernet message;
the second switch chip is cascaded with the first switch chip and is used for searching a forwarding result of the second Ethernet message based on a two-layer forwarding logic, and assigning the forwarding result to the data packet control header so as to generate a third Ethernet message;
the third switch chip is cascaded with the second switch chip, and is configured to view a packet control header of the third ethernet packet, and obtain a target port based on a viewing result, so as to forward the third ethernet packet through the target port.
6. The switch of claim 5, wherein the rate of the second switch chip is greater than the rate of the first switch chip and the third switch chip.
7. The switch of claim 5, wherein the first switch chip comprises a first ethernet port and a first cascade port;
the first Ethernet port is used for inputting the first Ethernet message;
the first cascade port is used for outputting the second Ethernet message.
8. The switch of claim 5, wherein the second switch chip comprises a second cascade port and a third cascade port;
the second cascade port is connected with the first cascade port and is used for inputting a second Ethernet message;
the third cascade port is used for outputting a third Ethernet message.
9. The switch of claim 5, wherein the third switch chip comprises a fourth cascaded port and a second ethernet port;
the fourth cascade port is connected with the third cascade port and is used for inputting a third Ethernet message;
the second ethernet port is a destination port for forwarding a third ethernet packet.
10. A switch chip port expansion system, comprising a switch according to any of claims 5 to 9, a first terminal and a second terminal;
the first terminal is connected with the switch through a first Ethernet port and is used for sending a first Ethernet message;
the second terminal is connected with the switch through a second Ethernet port and is used for receiving a third Ethernet message.
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