CN116488963A - Signal peak position detection device and method and input signal extraction equipment - Google Patents
Signal peak position detection device and method and input signal extraction equipment Download PDFInfo
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Abstract
The invention provides a signal peak position detection device, a signal peak position detection method and input signal extraction equipment, wherein a lookup table memory comprises: a look-up table comprising: the corresponding relation between the bit value of the sign bit of the input signal and the product result of the input signal and the local signal; the symbol extractor is used for: extracting a target bit value of a sign bit of an input signal corresponding to each sampling; the multiplexer is used for: for each sampling, searching a target product result matched with the target bit value from a lookup table in a lookup table memory according to the target bit value; the computing unit is used for: calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal in the time period of multiple sampling according to the sampling corresponding to the maximum module value in all the module values. The invention can omit a multiplier and an adder which are needed by the circuit for realizing the product operation, and greatly reduces the area and the whole power consumption of the circuit.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a signal peak position detection apparatus, a signal peak position detection method, an input signal extraction device, an electronic device, and a computer readable storage medium.
Background
The receiving apparatus needs to detect the boundary position of the target signal when receiving the signal, to extract the target signal from the received signal according to the boundary position.
At present, a cross-correlation synchronous detection circuit can be adopted to detect the boundary position of a target signal, specifically, a multiplier and an adder are adopted to perform complex signal multiplication calculation on an input signal sampled each time and a fixed local signal, and the signal position corresponding to the sample with the maximum modulus value is determined as the boundary position of the target signal through accumulation calculation of a multiplication result and modulo calculation of the accumulation result.
However, in the current cross-correlation synchronous detection circuit, complex signal product calculation based on the multiplier and the adder needs to be performed multiple times, which results in a large number of multipliers and adders in the circuit, and thus the area and the overall power consumption of the circuit are excessive.
Disclosure of Invention
The embodiment of the invention provides a signal peak value position detection device, a signal peak value position detection method, input signal extraction equipment, electronic equipment and a computer readable storage medium, so as to reduce the area of a cross-correlation synchronous detection circuit and the overall power consumption of the cross-correlation synchronous detection circuit.
In a first aspect, an embodiment of the present invention provides a signal peak position detection apparatus, including:
a symbol extractor, a multiplexer, a look-up table memory and a calculation unit; the method comprises the steps of carrying out a first treatment on the surface of the
The look-up table memory includes: a lookup table, the lookup table comprising: the corresponding relation between the bit value of the sign bit of the input signal and the product result of the input signal and the local signal;
the symbol extractor is configured to: extracting a target bit value of a sign bit of an input signal corresponding to each sampling;
the multiplexer is used for: for each sampling, according to the target bit value, searching a target product result matched with the target bit value from a lookup table in the lookup table memory;
the computing unit is used for: calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal in the time period of multiple sampling according to the sampling corresponding to the maximum module value in all the module values.
In a second aspect, an embodiment of the present invention provides a signal peak position detection method, where the method includes:
acquiring an input signal corresponding to each sampling, and extracting a target bit value of a sign bit of the input signal;
for each sampling, according to the target bit value, searching a target product result matched with the target bit value from the corresponding relation between the bit value of the sign bit of the input signal and the product result of the input signal and the local signal;
calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal according to the samples corresponding to the maximum module value in all the module values.
In a third aspect, an embodiment of the present invention provides an input signal extraction apparatus, including:
the signal peak position detection device is used for determining the peak position of an input signal in a time period corresponding to multiple sampling; the method comprises the steps of carrying out a first treatment on the surface of the The input signal comprises a target signal, and an identification signal sequence is spliced at the initial position of the target signal; the identification signal sequence is used for representing the peak position of the target signal; the target signal has a corresponding number of sequences;
the signal extraction device is used for determining an identification signal sequence of the input signal according to the peak position, and extracting the target signal from the input signal according to the identification signal sequence and the sequence number of the target signal.
In a fourth aspect, an embodiment of the present invention further provides an electronic device, including a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the method.
In a fifth aspect, embodiments of the present invention also provide a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the method.
In each sampling, the target bit value of the sign bit of the input signal corresponding to each sampling is extracted by a sign extractor; and searching a target product result matched with the target bit value from a lookup table in a lookup table memory according to the target bit value for each sampling through a multiplexer; then calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal according to the sampling corresponding to the maximum modulus. Based on the product result of the input signal and the local signal and the characteristic that the product result and the sign bit of the input signal are in one-to-one correspondence, the embodiment of the invention constructs the correspondence as a lookup table to be stored in the circuit, and when specific sampling is carried out, the product result corresponding to each sampling can be obtained through the lookup table, thereby omitting the multiplication operation of each sampling on the input signal and the local signal, omitting a multiplier and an adder required by the circuit for realizing the product operation, and greatly reducing the area and the overall power consumption of the circuit.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Fig. 1 is a block diagram of a signal peak position detecting device according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of an attenuation processing module according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating steps of a method for detecting a signal peak position according to an embodiment of the present invention;
fig. 4 is a block diagram of an input signal extraction apparatus provided by an embodiment of the present invention;
FIG. 5 is a logic block diagram of an electronic device provided by an embodiment of the present invention; the method comprises the steps of carrying out a first treatment on the surface of the
Fig. 6 is a logic block diagram of another electronic device according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
In the communication field, a transmitting end is often affected by the environment in the process of transmitting a target signal to a receiving end, so that the signal received by the receiving end is doped with an interference signal, and therefore, before the transmitting end transmits the target signal, the transmitting end can splice an identification signal sequence at the beginning of the target signal, and the identification signal sequence is used for representing the peak position of the target signal, namely, the identification signal sequence plays a role in boundary indication in the target signal. In order to accurately extract the target signal from the received signal, the receiving end needs to accurately identify the boundary position of the target signal in the received signal, namely, identify the peak position of the received signal, and after identifying the peak position of the received signal, the receiving end can intercept the signal from the peak position to extract the target signal.
The signal peak position detection device of the embodiment of the invention aims at determining the peak position of an input signal in a time period by using cross-correlation operation, wherein the cross-correlation operation is essentially a convolution operation, and the meaning of cross-correlation of two functions is as follows: the two functions are integrated by infinity by complex conjugate and inverse translation, respectively, and by multiplication, and the result of the cross-correlation operation reflects, physically, a measure of the similarity between the two signals.
Referring to fig. 1, a schematic diagram of a cross-correlation operation is shown, assuming that an input signal (which is a complex signal and has a real part and an imaginary part) has 5 samples (which reflect that the input signal has 5 signal positions) arranged in sequence in a time period, and a local signal (which is also a complex signal) has 3 sequences, the cross-correlation operation may be performed on the 5 samples respectively for 5 samples (the samples are in one-to-one correspondence), and for each sample, the samples corresponding to the samples may be multiplied by 3 sequences of the local signal respectively, and 3 multiplication results are accumulated and the accumulated value is modulo, so as to obtain a modulus corresponding to the samples, for example, a first sample is obtained, the samples 1 are multiplied by the sequences 1, 2, and 3 sequences 3 respectively, and the modulus corresponding to the first sample is obtained by accumulating the three multiplication results, and after the samples 1 are sampled, the samples are moved into a second sample for the samples 2, the samples are multiplied by the sequences 1, 2 are multiplied by the sequences 3 respectively, and the three multiplication results are not modulo-increased, and the second sampling result is obtained. And finally, determining the signal position corresponding to the sample with the maximum modulus as the peak position of the input signal, namely the boundary position (starting position) of the target signal in the input signal.
In the related art, the multiplication operation of two complex signals is involved in each sampling, and the multiplication operation of the complex signals is also involved in the addition operation, so that a relatively large number of multipliers and adders are required to be arranged in the cross-correlation operation circuit, and the area and the overall power consumption of the circuit are excessive.
In order to solve the above problems, the present invention finds that, based on a characteristic study of multiplication operation of an input signal (in the form of a complex signal) and a local signal (in the form of a complex signal), a combination of real and imaginary parts of a product result of the input signal and the local signal is in one-to-one correspondence with sign bits of the input signal, and the present invention can make statistics of the sign bits of the input signal and all the combination of the real and imaginary parts of the product result of the corresponding input signal and the local signal, construct a lookup table, which can store bit values of the sign bits of the input signal, the correspondence with the product result of the input signal and the local signal, store the lookup table in a lookup table memory in a circuit, and introduce a sign extractor and a multiplexer, and remove multipliers and adders in the circuit for implementing the product operation of the input signal and the local signal.
In each sampling, the embodiment of the invention extracts the target bit value of the sign bit of the input signal corresponding to each sampling through the sign extractor; and searching a target product result matched with the target bit value from a lookup table in a lookup table memory according to the target bit value for each sampling through a multiplexer; then calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal according to the sampling corresponding to the maximum modulus. Based on the product result of the input signal and the local signal and the characteristic that the product result and the sign bit of the input signal are in one-to-one correspondence, the embodiment of the invention constructs the correspondence as a lookup table to be stored in the circuit, and when specific sampling is carried out, the product result corresponding to each sampling can be obtained through the lookup table, thereby omitting the multiplication operation of each sampling on the input signal and the local signal, omitting a multiplier and an adder required by the circuit for realizing the product operation, and greatly reducing the area and the overall power consumption of the circuit.
Fig. 2 is a block diagram of a signal peak position detection apparatus according to an embodiment of the present invention, where, as shown in fig. 2, the apparatus may include: a symbol extractor, a multiplexer, a look-up table memory and a calculation unit; the look-up table memory includes: a look-up table comprising: the corresponding relation between the bit value of the sign bit of the input signal and the product result of the input signal and the local signal; the symbol extractor is used for: extracting a target bit value of a sign bit of an input signal corresponding to each sampling; the multiplexer is used for: for each sample, a lookup from a lookup table memory based on the target bit valueSearching a target product result matched with the target bit value in the table; the computing unit is used for: calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal in the time period of multiple sampling according to the sampling corresponding to the maximum module value in all the module values 。
In the embodiment of the invention, the characteristics of multiplication operation of the input signal and the local signal are analyzed firstly, and the input signal and the local signal are complex signals: i+jq form, the implementation of the cross-correlation operation is: let the input signal be rxZC (n), the local signal be LocalZC (n), slide the rxZC (n) m sample points and multiply with the conjugate of LocalZC (n) and sum, get the value of input signal at m moment, so rxZC (n) and cross-correlation function of LocalZC (n) are:
specifically, rxZC (n) =a+jb, localZC (n) =c+jd.
rxZC (n) ×localzc (n) = (a+jb) (c+jd) = (AC-BD) +j (ad+bc);
that is, the real part of the product result is: cmultouti=real (rxZC (n) LocalZC (n))=ac-BD.
The imaginary part of the product result is: cmultoutq=imag (rxZC (n) LocalZC (n))=ad+bc.
Extracting sign bits of the input signal rxZC (n), sign (rxZC (n))=sign (a+jb) = { sign (a), sign (B) }, setting sign bit 0 to represent positive number, and 1 to represent negative number, the { sign (a), sign (B) } has four combination modes:
{sign(A)，sign(B)}＝{0,0}or{0,1}or{1,0}or{1,1}。
from this, four combinations of the real part of the product result are possible: AC-bd= { C-D } or { c+d } or { -C-D } or { -c+d };
there are four combinations of the imaginary parts of the product result: AD+BC= { C+D } or { -C+D } or { C-D } or { -C-D;
that is, there are four combinations of the real part and the imaginary part of the product result: { C-D } or { C+D } or { -C-D } or { -C+D }.
In summary, there is a one-to-one correspondence between the real part and the imaginary part of the product result and the sign bit of the input signal participating in the product operation, and the embodiment of the invention can record the bit value of the sign bit of the input signal and the correspondence between the sign bit of the input signal and the product result of the local signal in advance, construct a lookup table, and then for each sampling, extract the sign bit { sign (a), sign (B) } of the sampled input signal as a bit enabling selection signal of the lookup table, and find the matched target product result from the lookup table as the product result of the sampled input signal and the local signal, thereby omitting the actual multiplication operation of the sampled input signal and the local signal each time, converting the actual multiplication operation into the lookup table to obtain the product result, and omitting a multiplier and an adder required for realizing the product operation in the circuit, thereby greatly reducing the area and the overall power consumption of the circuit.
For example, when the bit value of the sign bit ({ sign (a), sign (B) }) of the input signal is (0, 0) (representing a+b), the real part i=c-D, and the imaginary part q=c+d of the corresponding product result;
when the bit value of the sign bit ({ sign (a), sign (B) } of the input signal is (0, 1) (representing a-B), the real part i=c+d, and the imaginary part q= -c+d of the corresponding product result;
when the bit value of the sign bit ({ sign (a), sign (B) } of the input signal is (1, 0) (representing-a+b), the real part i= -C-D, and the imaginary part Q = C-D of the corresponding product result;
when the bit value of the sign bit ({ sign (a), sign (B) } of the input signal is (1, 1) (characterizing-a-B), the real part i= -c+d, and the imaginary part q= -C-D of the corresponding product result.
The correspondence may be recorded in a lookup table, and in a certain actual sampling, assuming that a sign bit of the input signal extracted by the sampling corresponding to the sampling point is a-B, a bit value corresponding to the sign bit is (0, 1), and a real part of a target product result of the input signal and the local signal may be found and determined from the lookup table to be c+d, and an imaginary part is-c+d.
For example, referring to fig. 1, as the correspondence between the sign bits of the input signal at different points and the product results of each sequence of the input signal and the local signal is stored in the lookup table, for the first sampling of the sample point 1, the target product result of the input signal of the sample point 1 and the sequence 2, and the target product result of the input signal of the sample point 3 and the sequence 1 can be obtained by looking up the table, so as to obtain three target product results, and finally, the calculation unit can accumulate the 3 target product results obtained by the first sampling by using the built-in adder to obtain an accumulated value, and then calculate the modulus corresponding to the first sampling according to the accumulated value by using the built-in modulus calculator; the method comprises the steps of carrying out a first treatment on the surface of the And after the calculation of all the sampled modulus values is completed, selecting a maximum modulus value through a built-in maximum value calculator, and determining the peak position of the input signal according to the sampling corresponding to the maximum modulus value.
In the cross-correlation operation process, the lookup table circuit replaces a multiplier and an adder for realizing product operation, so that the area and the power consumption of the circuit are effectively reduced, and the larger the length N of a local signal is, the more obvious the area and the power consumption of the circuit are reduced, and the more the benefit is obtained.
For example, the local signal LocalZC (N) length n=128 and bit width=5 bits, so that the scheme of the embodiment of the invention can realize N-point complex multiplication operation only through a lookup table with 24 bits of table width and 128 bits of table depth, and the number of multipliers and adders can be saved=128×3 (multipliers) +128×3 (adders), so that the optimization effect on the area and power consumption of the circuit is obvious.
Optionally, the input signal and the local signal are complex signals; the bit values of the sign bits of the input signal include: a bit value corresponding to a combination of sign bits of a real part and sign bits of an imaginary part of an input signal; bit values corresponding to different combinations are different; the product of the input signal and the local signal includes a real part and an imaginary part.
In the embodiment of the invention, the input signal and the local signal are in the form of complex signals: i+jq, where I is the real part and Q is the imaginary part, i.e. the complex signal is synthesized from a real signal and a virtual signal, the complex signal is expressed by complex numbers such that the complex signal is a vector signal having both amplitude and phase, and the product of the input signal in the form of a complex signal and the local signal in the form of a complex signal also includes the real part and the imaginary part.
Further, the sign bit of the input signal, that is, the sign bit Q including the sign bit I and the sign bit Q of the imaginary part, may be a bit value corresponding to a combination of the sign bit I and the sign bit Q of the imaginary part, and the combination of the sign bits mentioned in the embodiment of the present invention may specifically refer to a combination of the positive/negative sign of the sign bit I and the positive/negative sign of the sign bit Q of the imaginary part, for example, when the input signal is: in the case of i+jq, the combination of sign bits of the input signal is (-I, +q), if it is assumed that sign bit 0 represents a positive number and 1 represents a negative number, the bit value of the sign bit of the input signal is (1, 0); the input signals are: in the case of I-jQ, the combination of sign bits of the input signal is (-I, -Q), and the bit value of the sign bit of the input signal is (1, 1). It can be seen that the bit values corresponding to the different combinations are different.
Optionally, in a preferred implementation, the lookup table includes: a bit value of a sign bit of the input signal, and a result of adding a real part and an imaginary part of the product result; the multiplexer is particularly for: and according to the target bit value, searching a target addition result matched with the target bit value from a lookup table in a lookup table memory as a target product result.
In an embodiment of the present invention, referring to fig. 2, when an input signal sampled for one sample is input, a sign extractor may first extract a sign bit of the input signal, determine a target bit value (a bit value corresponding to a positive/negative sign combination relationship of a real part and an imaginary part) of the sign bit, then multiplex the target bit value, and find a target addition result matched with the target bit value from a lookup table in a lookup table memory as a target product result. And since the product result of the input signal and the local signal is also in the form of complex signals, the product result is represented as a sum result of real and imaginary parts.
For example, referring to one of the above examples, when the sign bit ({ sign (a), sign (B) }) of the input signal has a target bit value of (0, 1) (characterizing a-B), the real part i=c+d and the imaginary part q=c+d of the corresponding product result are obtained by looking up the table. The product result is represented by the result of the addition of the real part I and the imaginary part jQ.
Therefore, the corresponding relation between the sign bit of the input signal at different points and the product result of each sequence of the input signal and the local signal is stored in the lookup table, and the multiplier for realizing the product operation is replaced by the lookup table circuit.
Optionally, in the above preferred implementation, the addition result is a binary calculation result.
Preferably, the product result of the input signal and the local signal is formed by a real part and an imaginary part addition result, and if no improvement is adopted, the final obtaining of the product result also needs an adder to perform the addition operation of the real part and the imaginary part. The embodiment of the invention can calculate the addition result in advance, and the binary calculation result of the addition result is directly stored in the lookup table, so that an adder required for realizing product operation is further saved. Note that the addition result may be in the form of 10-ary, 16-ary, or the like, which is not particularly limited.
For example, the results derived for the example inference above, i.e., the real and imaginary parts of the product of the input signal and the local signal, combine in four ways: p0{ C-D } orP1{ C+D } orP2{ -C-D } orP3{ -C+D }.
Let P0, P1, P2, P3 have 6 bits of bit width.
P0 may be represented in binary form: [23:18];
p1 may be represented in binary form: [17:12];
p2 may be represented in binary form: [11:6];
p3 can be expressed in binary form: [5:0].
When the bit value of the sign bit ({ sign (a), sign (B) } of the input signal is (0, 0) (representing a+b), the real part i= [17 ] of the corresponding product result: 12], imaginary part q= [23:18];
when the bit value of the sign bit ({ sign (a), sign (B) } of the input signal is (0, 1) (representing a-B), the real part i= [23 ] of the corresponding product result: 18], imaginary part q= [11:6];
when the bit value of the sign bit ({ sign (a), sign (B) } of the input signal is (1, 0) (representing-a+b), the real part i= [ 5) of the corresponding product result: 0], imaginary part q= [17:12];
when the bit value of the sign bit ({ sign (a), sign (B) } of the input signal is (1, 1) (characterizing-a-B), the real part i= [ 11) of the corresponding product result: 6], imaginary part q= [5:0].
Alternatively, in another sub-optimal implementation, the multiplexer is specifically configured to: according to the target bit value, searching a real part and an imaginary part of a target product result matched with the target bit value from a lookup table in the lookup table memory; the computing unit is further configured to: and carrying out addition operation on the real part and the imaginary part of the target product result through a first adder to obtain the target product result.
Since the product of the input signal and the local signal is also in the form of a complex signal, the product is in the form of a summation of real and imaginary parts, and the look-up table may include: the bit value of the sign bit of the input signal is combined with the real and imaginary parts of the product result. The multiplexer can search the real part and the imaginary part of the target product result matched with the target bit value from the lookup table according to the target bit value; the calculation unit is then also for: and carrying out addition operation on the real part and the imaginary part of the target product result through a first adder to obtain the target product result.
Optionally, referring to fig. 2, the calculating unit includes: an adder, a modulus calculator, and a maximum calculator; the computing unit is used for: accumulating the target product result obtained by each sampling through the adder to obtain an accumulated value; calculating a corresponding module value of each sampling according to the accumulated value by the module value calculator; and selecting the maximum module value in all the module values through the maximum value calculator, and determining the peak position of the input signal according to the sampling corresponding to the maximum module value.
The adder is used for accumulating the product result of the input signal and each local signal sequence when sampling each time, the modulus value calculator obtains a modulus value according to the accumulated value, and the modulus value can be obtained by squaring the sum result of the square of the real part of the accumulated value and the square of the imaginary part of the accumulated value.
In each sampling, the target bit value of the sign bit of the input signal corresponding to each sampling is extracted by a sign extractor; and searching a target product result matched with the target bit value from a lookup table in a lookup table memory according to the target bit value for each sampling through a multiplexer; then calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal according to the sampling corresponding to the maximum modulus. Based on the product result of the input signal and the local signal and the characteristic that the product result and the sign bit of the input signal are in one-to-one correspondence, the embodiment of the invention constructs the correspondence as a lookup table to be stored in the circuit, and when specific sampling is carried out, the product result corresponding to each sampling can be obtained through the lookup table, thereby omitting the multiplication operation of each sampling on the input signal and the local signal, omitting a multiplier and an adder required by the circuit for realizing the product operation, and greatly reducing the area and the overall power consumption of the circuit.
Fig. 3 is a flowchart of steps of a signal peak position detection method according to an embodiment of the present invention, which is applied to the signal peak position detection apparatus, and the method includes:
step 201, an input signal corresponding to each sampling is obtained, and a target bit value of a sign bit of the input signal is extracted.
Step 202, for each sampling, searching a target product result matched with the target bit value from the corresponding relation between the bit value of the sign bit of the input signal and the product result of the input signal and the local signal according to the target bit value.
Step 203, calculating a corresponding modulus value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal according to the samples corresponding to the maximum module value in all the module values 。
The steps 201 to 203 of the embodiment of the present invention may be specifically described with reference to the foregoing corresponding description of the embodiment of fig. 2, which is not repeated herein.
Referring to fig. 4, an embodiment of the present invention further provides an input signal extraction apparatus, including: signal peak position detecting means and signal extracting means.
The signal peak position detection device is used for determining the peak position of an input signal in a time period corresponding to multiple sampling; the input signal comprises a target signal, and an identification signal sequence is spliced at the initial position of the target signal; the identification signal sequence is used for representing the peak position of the target signal; the target signal has a corresponding number of sequences; the signal extraction device is used for determining an identification signal sequence of the input signal according to the peak value position and extracting a target signal from the input signal according to the identification signal sequence and the sequence number of the target signal.
In the communication field, a transmitting end is often affected by the environment in the process of transmitting a target signal to a receiving end, so that the signal received by the receiving end is doped with an interference signal, and therefore, before the transmitting end transmits the target signal, the transmitting end can splice an identification signal sequence at the beginning of the target signal, and the identification signal sequence is used for representing the peak position of the target signal, namely, the identification signal sequence plays a role in boundary indication in the target signal. In order to accurately extract the target signal from the received signal, the receiving end needs to accurately identify the boundary position of the target signal in the received signal through the signal peak position detection device, namely, identify the peak position of the received signal, and after identifying the peak position of the received signal, the receiving end can determine the peak position as an identification signal sequence of the input signal through the signal extraction device, and extract the target signal from the input signal according to the identification signal sequence and the sequence number of the target signal.
In summary, in the embodiment of the present invention, in each sampling, a symbol extractor extracts a target bit value of a symbol bit of an input signal corresponding to each sampling; and searching a target product result matched with the target bit value from a lookup table in a lookup table memory according to the target bit value for each sampling through a multiplexer; then calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal according to the sampling corresponding to the maximum modulus. Based on the product result of the input signal and the local signal and the characteristic that the product result and the sign bit of the input signal are in one-to-one correspondence, the embodiment of the invention constructs the correspondence as a lookup table to be stored in the circuit, and when specific sampling is carried out, the product result corresponding to each sampling can be obtained through the lookup table, thereby omitting the multiplication operation of each sampling on the input signal and the local signal, omitting a multiplier and an adder required by the circuit for realizing the product operation, and greatly reducing the area and the overall power consumption of the circuit.
Fig. 5 is a block diagram of an electronic device 600, according to an example embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.
Referring to fig. 5, the electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input/output (I/O) interface 612, a sensor component 614, and a communication component 616.
The processing component 602 generally controls overall operation of the electronic device 600, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 602 can include one or more modules that facilitate interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate interaction between the multimedia component 608 and the processing component 602.
The memory 604 is used to store various types of data to support operations at the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phonebook data, messages, pictures, multimedia, and so forth. The memory 604 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.
The power supply component 606 provides power to the various components of the electronic device 600. The power supply components 606 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.
The multimedia component 608 includes a screen between the electronic device 600 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense demarcations of touch or sliding actions, but also detect durations and pressures associated with the touch or sliding operations. In some embodiments, the multimedia component 608 includes a front camera and/or a rear camera. When the electronic device 600 is in an operational mode, such as a shooting mode or a multimedia mode, the front-facing camera and/or the rear-facing camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
The audio component 610 is for outputting and/or inputting audio signals. For example, the audio component 610 includes a Microphone (MIC) for receiving external audio signals when the electronic device 600 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, audio component 610 further includes a speaker for outputting audio signals.
The I/O interface 612 provides an interface between the processing component 602 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.
The sensor assembly 614 includes one or more sensors for providing status assessment of various aspects of the electronic device 600. For example, the sensor assembly 614 may detect an on/off state of the electronic device 600, a relative positioning of the components, such as a display and keypad of the electronic device 600, the sensor assembly 614 may also detect a change in position of the electronic device 600 or a component of the electronic device 600, the presence or absence of a user's contact with the electronic device 600, an orientation or acceleration/deceleration of the electronic device 600, and a change in temperature of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 616 is utilized to facilitate communication between the electronic device 600 and other devices, either in a wired or wireless manner. The electronic device 600 may access a wireless network based on a communication standard, such as WiFi, an operator network (e.g., 2G, 3G, 4G, or 5G), or a combination thereof. In one exemplary embodiment, the communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 600 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for implementing a signal peak position detection method provided by an embodiment of the invention.
In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 604, including instructions executable by processor 620 of electronic device 600 to perform the above-described method. For example, the non-transitory storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
Fig. 6 is a block diagram of an electronic device 700, according to an example embodiment. For example, the electronic device 700 may be provided as a server. Referring to fig. 6, electronic device 700 includes a processing component 722 that further includes one or more processors and memory resources represented by memory 732 for storing instructions, such as application programs, executable by processing component 722. The application programs stored in memory 732 may include one or more modules that each correspond to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform a signal peak position detection method provided by the embodiment of the present invention.
The electronic device 700 may also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input output (I/O) interface 758. The electronic device 700 may operate based on an operating system stored in memory 732, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.
The embodiment of the invention also provides a computer readable storage medium, which enables the electronic device to execute the signal peak position detection method when the instructions in the computer readable storage medium are executed by a processor of the electronic device.
The embodiment of the invention also provides a computer program product, which comprises a computer program, wherein the computer program realizes the signal peak value position detection method when being executed by a processor.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A signal peak position detection apparatus, the apparatus comprising:
a symbol extractor, a multiplexer, a look-up table memory and a calculation unit;
the look-up table memory includes: a lookup table, the lookup table comprising: the corresponding relation between the bit value of the sign bit of the input signal and the product result of the input signal and the local signal;
the symbol extractor is configured to: extracting a target bit value of a sign bit of an input signal corresponding to each sampling;
the multiplexer is used for: for each sampling, according to the target bit value, searching a target product result matched with the target bit value from a lookup table in the lookup table memory;
the computing unit is used for: calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal in the time period of multiple sampling according to the sampling corresponding to the maximum module value in all the module values.
2. The signal peak position detection apparatus according to claim 1, wherein the input signal and the local signal are complex signals;
the bit values of the sign bits of the input signal include: a bit value corresponding to a combination of sign bits of a real part and sign bits of an imaginary part of the input signal; bit values corresponding to different combinations are different; the product of the input signal and the local signal includes a real part and an imaginary part.
3. The signal peak position detection apparatus according to claim 2, wherein the look-up table includes: a bit value of a sign bit of the input signal, and a summation result of a real part and an imaginary part of the product result;
the multiplexer is particularly for: and according to the target bit value, searching a target addition result matched with the target bit value from a lookup table in the lookup table memory as the target product result.
4. A signal peak position detection unit according to claim 3, wherein the addition result is a binary calculation result.
5. The signal peak position detection apparatus according to claim 2, wherein the multiplexer is specifically configured to: according to the target bit value, searching a real part and an imaginary part of a target product result matched with the target bit value from a lookup table in the lookup table memory;
the computing unit is further configured to: and carrying out addition operation on the real part and the imaginary part of the target product result through a first adder to obtain the target product result.
6. The signal peak position detection apparatus according to claim 1, wherein the calculation unit includes:
an adder, a modulus calculator, and a maximum calculator;
the computing unit is used for: accumulating the target product result obtained by each sampling through the adder to obtain an accumulated value; calculating a corresponding module value of each sampling according to the accumulated value by the module value calculator; and selecting the maximum module value in all the module values through the maximum value calculator, and determining the peak position of the input signal according to the sampling corresponding to the maximum module value.
7. A signal peak position detection method applied to a signal peak position detection apparatus according to any one of claims 1 to 6, comprising:
acquiring an input signal corresponding to each sampling, and extracting a target bit value of a sign bit of the input signal;
for each sampling, according to the target bit value, searching a target product result matched with the target bit value from the corresponding relation between the bit value of the sign bit of the input signal and the product result of the input signal and the local signal;
calculating a corresponding module value of each sampling according to a target product result obtained by each sampling; and determining the peak position of the input signal according to the samples corresponding to the maximum module value in all the module values.
8. An input signal extraction apparatus, comprising:
signal peak position detection means and signal extraction means according to any one of claims 1 to 6, the signal peak position detection means being arranged to determine the peak position of an input signal over a time period corresponding to a plurality of samples; the input signal comprises a target signal, and an identification signal sequence is spliced at the initial position of the target signal; the identification signal sequence is used for representing the peak position of the target signal; the target signal has a corresponding number of sequences;
the signal extraction device is used for determining an identification signal sequence of the input signal according to the peak position, and extracting the target signal from the input signal according to the identification signal sequence and the sequence number of the target signal.
9. An electronic device, comprising: a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the method of claim 7.
10. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of claim 7.
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