CN116488637A - Circuit for configuring phase number and distributing pwm pulse between phases for multiphase cot architecture - Google Patents
Circuit for configuring phase number and distributing pwm pulse between phases for multiphase cot architecture Download PDFInfo
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- CN116488637A CN116488637A CN202310618790.9A CN202310618790A CN116488637A CN 116488637 A CN116488637 A CN 116488637A CN 202310618790 A CN202310618790 A CN 202310618790A CN 116488637 A CN116488637 A CN 116488637A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
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- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a circuit for configuring phase numbers for a multiphase cot framework and distributing pwm pulses among phases, which comprises a configuration phase number circuit and a pwm pulse distribution circuit, wherein the pwm pulse distribution circuit comprises a NOT gate INV1, a NOT gate INV2, a NOT gate INV3, a chip EDT1, a chip EDT2, a chip EDT3, a chip EDT4, a chip EDT5, a chip EDT6, a NAND gate ND3, a NAND gate ND4, a chip phasesel1, a chip phasesel 2, a chip phase1ton, a chip phase2ton and a chip phase3ton; the invention designs a state machine circuit for configuring the phase number and a pwm pulse distribution circuit, and details the corresponding logic circuit and phase setting relation, thereby providing a foundation for the control of the large current of the cot architecture applied to the multiphase.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a circuit for configuring phase numbers for a multiphase cot framework and distributing pwm pulses among phases.
Background
The multi-phase structure on the market at present is mostly based on the constant frequency structure of EA, and the cot (constant on time) structure has the advantages of no need of external compensation, and fast load transient response, and is particularly important for multi-phase high-current application. The present patent therefore proposes a state machine in which the number of phases can be configured and on the basis of which the pwm pulses are distributed between the phases, so as to apply the cot architecture to the control of the high currents of the phases.
Disclosure of Invention
It is therefore an object of the present invention to provide a circuit for configuring the number of phases and distributing pwm pulses between the phases for a multi-phase cot architecture, which solves the above-mentioned problems.
In order to solve the technical problems, the invention provides the following technical scheme: the circuit for configuring the phase number and distributing the pwm pulses at intervals of the multiphase cot architecture comprises a configuration phase number circuit and a pwm pulse distribution circuit, wherein the configuration phase number circuit comprises AN AND gate AN1, AN AND gate AN2, a NAND gate ND1, a NAND gate ND2, a NOR gate NR1, a NOR gate NR3, a chip DFCN1 and a chip DFCN2, a pin d of the chip DFCN1 is connected with the output end of the AND gate AN1, a pin en 2 of the AND gate AN1, a pin b is connected with the pin q of the chip DFCN1, a pin qn is connected with the NOR gate NR2 and a pin a of the NAND gate ND2, a pin q of the chip DFCN2 is connected with the NOR gate NR1, the NOR gate NR2 and a pin b of the NAND gate ND2, AN1 is connected with the output end of the NOR gate NR2, a pin b of the NOR gate NR3 is connected with the output end of the NAND gate NR3, AN output end of the NOR gate NR3, AN output end of the NAND gate NR3 and AN output end of the NAND gate ND2, and AN output end of the NAND gate ND 2.
Preferably, the pins cp of the chips DFCN1 and DFCN2 are connected to the cp input, and the pin cdn is connected to the clrb input.
Preferably, the phase setting relationship of the configuration phase number circuit is as follows:
preferably, the pwm pulse distribution circuit includes an NOT gate INV1, an NOT gate INV2, an NOT gate INV3, a chip EDT1, a chip EDT2, a chip EDT3, a chip EDT4, a chip EDT5, a chip EDT6, a NAND gate ND3, a NAND gate ND4, a chip phase sel1, a chip phase sel2, a chip phase1ton, a chip phase2ton, and a chip phase3ton, and a pin a of the NAND gate ND3 is connected to a falling edge of the chip EDT1, a pin b is connected to a falling edge of the chip EDT2, a pin c is connected to a falling edge of the chip EDT3, input ends of the chip EDT1, the chip EDT2, and the chip EDT3 are respectively connected to pwm1, pwm2, and pwm3, an output end of the NAND gate ND3 is connected to a pin cp of the chip se1, a pin ph1 of the chip phase sel1 is connected to a pin of the chip phase1, a pin ph2 is connected to a pin of the chip phase2ton, the pin ph3 is connected with the pin pulssel of the chip phase3ton, the pin pwm of the phase1ton is connected with the pin a of the NOT gate INV1, the pin pwm of the phase2ton is connected with the pin a of the NOT gate INV2, the pin pwm of the phase3ton is connected with the pin a of the NOT gate INV3, the pin q of the NOT gate INV1 is connected with the input end of the chip EDT4, the pin q of the NOT gate INV3 is connected with the input end of the chip EDT6, the falling edge of the EDT4 is connected with the pin a of the NOT gate ND4, the falling edge of the EDT5 is connected with the pin b of the NOT gate ND4, the output of the NOT gate ND4 is connected with the pin of the chip phase sel2, the pin ph1 of the chip phase1ton is connected with the pin vc of the chip set 2, and the pin ph3 of the chip is connected with the pin vc of the chip phase 2.
Preferably, the pins clrb of the chips phase sel1 and phase sel2 are connected with clrb input, the pin en ph2 is connected with en ph2 input, and the pin en ph3 is connected with en ph3 input.
Compared with the prior art, the invention has the following beneficial effects: the invention designs a state machine circuit for configuring the phase number and a pwm pulse distribution circuit, and details the corresponding logic circuit and phase setting relation, thereby providing a foundation for the control of the large current of the cot architecture applied to the multiphase.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a phase number circuit of the present invention;
fig. 2 is a schematic diagram of the pwm pulse distribution circuit of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by one of ordinary skill in the art without inventive faculty, are intended to be within the scope of the present invention, based on the embodiments of the present invention.
Referring to fig. 1-2, an embodiment of the present invention is provided: for the multiphase cot architecture, a phase number circuit and a pwm pulse distribution circuit are configured, wherein the circuit comprises a configuration phase number circuit and a pwm pulse distribution circuit, the configuration phase number circuit comprises AN AND gate AN1, AN AND gate AN2, a NAND gate ND1, a NAND gate ND2, a NOR gate NR1, a NOR gate NR3, a chip DFCN1 and a chip DFCN2, a pin d of the chip DFCN1 is connected with AN output end of the AND gate AN1, a pin en 2, a pin b is connected with ph1, a pin q of the chip DFCN1 is connected with a pin a of the NOR gate NR1, a pin qn is connected with a pin NR2 and a pin a of the NAND gate ND2, a pin q of the chip DFCN2 is connected with the NOR gate NR1, a pin NR2 and the NAND gate ND2, AN output end of the NOR gate NR1 is connected with ph2, AN output end of the NOR gate NR2 is connected with ph2, AN output end of the NOR gate NR3 is connected with the output end of the NAND gate NR2, a pin b of the NOR gate NR3 is connected with the output end of the NAND gate ND2, and AN output end of the NAND gate ND2 is connected with the output end of the NAND gate NR 2; the pwm pulse distribution circuit includes an NOT gate INV1, an NOT gate INV2, an NOT gate INV3, a chip EDT1, a chip EDT2, a chip EDT3, a chip EDT4, a chip EDT5, a chip EDT6, a NAND gate ND3, a NAND gate ND4, a chip phase sel1, a chip phase sel2, a chip phase1ton, a chip phase2ton, and a chip phase3ton, and a pin a of the NAND gate ND3 is connected to a falling edge of the chip EDT1, a pin b is connected to a falling edge of the chip EDT2, a pin c is connected to a falling edge of the chip EDT3, input ends of the chip EDT1, the chip EDT2, and the chip EDT3 are respectively connected to pwm1, pwm2, and pwm3, an output end of the NAND gate ND3 is connected to a pin cp of the chip phase1, a pin ph1 of the chip phase sel1 is connected to a pin puse of the chip phase1ton, a pin ph2 is connected to a pin of the chip phase2ton, the pin ph3 is connected with the pin pulssel of the chip phase3ton, the pin pwm of the phase1ton is connected with the pin a of the NOT gate INV1, the pin pwm of the phase2ton is connected with the pin a of the NOT gate INV2, the pin q of the NOT gate INV1 is connected with the input end of the chip EDT4, the pin q of the NOT gate INV2 is connected with the input end of the chip EDT5, the pin q of the NOT gate INV3 is connected with the input end of the chip EDT6, the falling edge of the EDT4 is connected with the pin a of the NOT gate ND4, the falling edge of the EDT5 is connected with the pin b of the NOT gate ND4, the output of the NOT gate ND4 is connected with the pin cp of the chip phase sel2, the pin ph1 of the chip phase1ton is connected with the pin vc of the chip phase2, and the pin ph3 of the chip phase2 is connected with the pin vc of the chip v_c of the chip phase 3; the pins clrb of the chip phase sel1 and the chip phase sel2 are connected with clrb input, the pin en ph2 is connected with en ph2 input, and the pin en ph3 is connected with en ph3 input; the pins cp of the chip DFCN1 and the chip DFCN2 are connected with a cp input, and the pin cdn is connected with a clrb input; the phase setting relationship of the configuration phase number circuit is as follows:
working principle: in the configuration phase number circuit of the present invention, cp and clrb signals are input into a chip DFCN1 and a chip DFCN2, a q end of the chip DFCN1 outputs a signal to a nor gate NR1, a qn end outputs a signal to a nor gate NR2 and a nand gate ND2, a q end of the chip DFCN2 outputs a signal to a nor gate NR1, a nor gate NR2 and a nand gate ND2, a nor gate NR1 outputs a signal ph 1to AN and gate AN1, a nor gate ND2 outputs a signal ph 2to AN and AN gate AN2, AN en ph2 signal is input into AN and a nand gate ND1, respectively, AN en ph3 signal is input into AN and a ND1, AN1 outputs a signal to a d end of the chip DFCN1, AN2 outputs a signal to a d end of the chip DFCN2, AN ND1 outputs a signal to a nor gate NR3, and a nor gate NR3 outputs a signal ph3; in the pwm pulse distribution circuit of the present invention, en ph2/3 and clrb are input to the chip phase sel1 and the chip phase sel2, three signals pwm1/2/3 are input to the chip EDT1, the chip EDT2 and the chip EDT3, respectively, simultaneously, three signals are input to the chip EDT4, the chip EDT5 and the chip EDT6 after being inverted through the non-gate INV1, the non-gate INV2 and the non-gate INV3, the chip EDT1, the chip EDT2 and the chip EDT3 output signals to the nand gate ND3, the nand gate ND3 outputs the anypwm to the cp end of the chip phase sel1, the chip phase sel1/2/3 is output to the phase1ton, the chip phase2ton and the phase3 terminal, the chip EDT4, the chip EDT5 and the chip EDT6 output signals to the nand gate ND4, the nand gate ND4 outputs the anypcm to the chip phase2, the chip phase2 and the phase3 is output to the phase 1/2 ton end of the chip phase1, the chip phase 1/2 ton and the chip phase 3.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A circuit for configuring the number of phases and distributing pwm pulses between phases for a multiphase cot architecture, comprising a configuration phase number circuit and a pwm pulse distribution circuit, characterized in that: the configuration phase number circuit comprises AN AND gate AN1, AN AND gate AN2, a NAND gate ND1, a NAND gate ND2, a NOR gate NR1, a NOR gate NR2, a NOR gate NR3, a chip DFCN1 and a chip DFCN2, wherein a pin d of the chip DFCN1 is connected with AN output end of the AND gate AN1, a pin a of the AND gate AN1 is connected with en ph2, a pin b is connected with ph1, a pin q of the chip DFCN1 is connected with the NOR gate NR2 and a pin a of the NAND gate ND2, a pin q of the chip DFCN2 is connected with the NOR gate NR1, the NOR gate NR2 and a pin b of the NAND gate ND2, AN output end of the NOR gate NR1 is connected with ph1, AN output end of the NOR gate NR3 is connected with the pin a of the NAND gate ND1, AN output end of the NOR gate ND2 is connected with ph2, and AN output end of the NAND gate ND2 is connected with the output end of the NAND gate ND2, and AN output end of the NAND gate ND2 is connected with the output end of the NAND gate 2.
2. The circuit for configuring the number of phases and distributing pwm pulses between phases for a multi-phase cot architecture according to claim 1, wherein: the pins cp of the chips DFCN1 and DFCN2 are connected to the cp input, and the pin cdn is connected to the clrb input.
3. The circuit for configuring the number of phases and distributing pwm pulses between phases for a multi-phase cot architecture according to claim 1, wherein: the phase setting relationship of the configuration phase number circuit is as follows:
4. the circuit for configuring the number of phases and distributing pwm pulses between phases for a multi-phase cot architecture according to claim 1, wherein: the pwm pulse distribution circuit comprises an NOT gate INV1, an NOT gate INV2, an NOT gate INV3, a chip EDT1, a chip EDT2, a chip EDT3, a chip EDT4, a chip EDT5, a chip EDT6, a NAND gate ND3, a NAND gate ND4, a chip phasel 1, a chip phasel 2, a chip phasel 1ton, a chip phasel 2ton and a chip phasel 3ton, a pin a of the NAND gate ND3 is connected with the falling edge of the chip EDT1, a pin b is connected with the falling edge of the chip EDT2, a pin c is connected with the falling edge of the chip EDT3, input ends of the chip EDT1, the chip EDT2 and the chip EDT3 are respectively connected with pwm1, pwm2 and pwm3, an output end of the NAND gate ND3 is connected with a pin cp of the chip phasel 1, a pin ph1 of the chip phasel 1ton is connected with a pin pulsel of the chip phasel 2ton, a pin ph2 is connected with a pin of the chip phasel 2, the pin ph3 is connected with the pin pulssel of the chip phase3ton, the pin pwm of the phase1ton is connected with the pin a of the NOT gate INV1, the pin pwm of the phase2ton is connected with the pin a of the NOT gate INV2, the pin pwm of the phase3ton is connected with the pin a of the NOT gate INV3, the pin q of the NOT gate INV1 is connected with the input end of the chip EDT4, the pin q of the NOT gate INV3 is connected with the input end of the chip EDT6, the falling edge of the EDT4 is connected with the pin a of the NOT gate ND4, the falling edge of the EDT5 is connected with the pin b of the NOT gate ND4, the output of the NOT gate ND4 is connected with the pin of the chip phase sel2, the pin ph1 of the chip phase1ton is connected with the pin vc of the chip set 2, and the pin ph3 of the chip is connected with the pin vc of the chip phase 2.
5. The circuit for configuring the number of phases and distributing pwm pulses between phases for a multi-phase cot architecture according to claim 4, wherein: the pins clrb of the chip phase sel1 and the chip phase sel2 are connected with clrb input, the pin en ph2 is connected with en ph2 input, and the pin en ph3 is connected with en ph3 input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310618790.9A CN116488637B (en) | 2023-05-29 | 2023-05-29 | Circuit for distributing pwm pulse between phase number and phase position of multiphase cot architecture configuration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310618790.9A CN116488637B (en) | 2023-05-29 | 2023-05-29 | Circuit for distributing pwm pulse between phase number and phase position of multiphase cot architecture configuration |
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| Publication Number | Publication Date |
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| CN116488637A true CN116488637A (en) | 2023-07-25 |
| CN116488637B CN116488637B (en) | 2024-02-02 |
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| CN202310618790.9A Active CN116488637B (en) | 2023-05-29 | 2023-05-29 | Circuit for distributing pwm pulse between phase number and phase position of multiphase cot architecture configuration |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207530698U (en) * | 2017-11-30 | 2018-06-22 | 杭州凯尔达电焊机有限公司 | A kind of multi-channel PWM controller parallel connection synchronization control circuit |
| CN113556039A (en) * | 2021-07-22 | 2021-10-26 | 无锡职业技术学院 | Control system and method of multiphase DC-DC converter |
| CN115514225A (en) * | 2022-09-30 | 2022-12-23 | 骏盈半导体(上海)有限公司 | Maximum conduction time trigger circuit of multiphase control system |
-
2023
- 2023-05-29 CN CN202310618790.9A patent/CN116488637B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207530698U (en) * | 2017-11-30 | 2018-06-22 | 杭州凯尔达电焊机有限公司 | A kind of multi-channel PWM controller parallel connection synchronization control circuit |
| CN113556039A (en) * | 2021-07-22 | 2021-10-26 | 无锡职业技术学院 | Control system and method of multiphase DC-DC converter |
| CN115514225A (en) * | 2022-09-30 | 2022-12-23 | 骏盈半导体(上海)有限公司 | Maximum conduction time trigger circuit of multiphase control system |
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| CN116488637B (en) | 2024-02-02 |
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