CN116488620A

CN116488620A - Duty cycle correction circuit and chip

Info

Publication number: CN116488620A
Application number: CN202210058526.XA
Authority: CN
Inventors: 方海彬; 唐东升
Original assignee: Hefei Geyi Integrated Circuit Co Ltd
Current assignee: Hefei Geyi Integrated Circuit Co Ltd
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2023-07-25

Abstract

The invention provides a duty ratio correction circuit and a chip, which are provided with a pre-charging module, wherein a capacitor can be pre-charged to a preset voltage after each comparison of a comparator is finished, so that the charging time of a charge pump module to two charge and discharge nodes can be shortened, the analog voltage output by the two charge and discharge nodes can quickly reach the input voltage value which can be compared by the comparator when the analog voltage is compared next time, the starting time required by each comparison of the comparator is shortened, the response time and the stabilizing time of a loop of the duty ratio correction circuit per se are shortened, the clock duty ratio correction efficiency is improved finally, and the improvement of the signal transmission rate is facilitated.

Description

Duty cycle correction circuit and chip

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a duty cycle correction circuit and a chip.

Background

Generally, a clock signal is used as a reference signal for synchronizing operation timing between an internal circuit of some chips (e.g., a dynamic random access memory, etc.) and an external circuit, and generally, when the clock signal of the external circuit is applied to the internal circuit, clock skew (including delay or clock skew) caused by a signal path within the internal circuit may be caused. Thus, a phase-locked loop circuit and a duty cycle correction circuit are commonly used to work in concert to solve this problem. The phase-locked loop circuit may be a DLL (delay-locked loop, delay Locked Loop) circuit or a PLL (phase-locked loop, phase Locked Loop) circuit, which is used to synchronize a clock signal of an internal circuit and a clock signal of an external circuit, so as to solve the problem of clock skew, so that a clock delay between the internal circuit and the external circuit of the chip has a sufficient margin, thereby improving a timing function of the system; the duty cycle correction circuit is used to adjust the clock duty cycle (typically 50%) so that both the rising and falling edges of the clock signal can sample data (also known as high-speed data input and output operations), thereby increasing the transmission rate of the signal.

However, the existing duty cycle correction circuit has the disadvantage of long start-up time, which results in a long clock duty cycle calibration time, which is disadvantageous for improving the transmission rate of signals.

Disclosure of Invention

The invention aims to provide a duty ratio correction circuit and a chip, which can shorten starting time. The clock duty ratio calibration efficiency is improved, and the improvement of the signal transmission rate is facilitated.

In order to achieve the above object, the present invention provides a duty cycle correction circuit, which comprises a charge pump module, a comparator, a control module, a duty cycle correction module, a frequency division module, and a pre-charge module, wherein,

the input end of the frequency division module is coupled with the output end of the duty ratio correction module, and the frequency division module is used for generating a second clock signal and a third clock signal based on the first clock signal output by the duty ratio correction module, wherein the second clock signal and the first clock signal have the same duty ratio, and the third clock signal is an inverted signal of the second clock signal;

the charge pump module is provided with a first charge-discharge node and a second charge-discharge node, the first charge-discharge node is coupled with the non-inverting input end of the comparator, the second charge-discharge node is coupled with the inverting input end of the comparator, and the charge pump module is used for charging or discharging the first charge-discharge node and the second charge-discharge node under the control of the second clock signal and the third clock signal so as to output corresponding two paths of analog voltages;

The output end of the comparator is coupled with the input end of the control module, and the comparator is used for comparing two paths of analog voltages output by the charge pump module under the control of a comparison enabling signal;

the output end of the control module is coupled with one input end of the duty cycle correction module, and the control module is used for generating corresponding adjustment control signals according to the comparison result of the comparator and providing the adjustment control signals for the duty cycle correction module;

the duty ratio correction module is used for adjusting the duty ratio of the first clock signal according to the adjustment control signal output by the control module;

the pre-charging module is coupled to the first charging and discharging node and the second charging and discharging node, and is used for pre-charging the voltages of the first charging and discharging node and the second charging and discharging node to a preset voltage after the comparison of the comparator is finished under the control of a pre-charging control signal.

Optionally, the pre-charging module includes a first MOS transistor, a second MOS transistor, a first channel switch, a second channel switch, a first inverter, and a voltage dividing circuit; the gate end of the first MOS tube, the input end of the first inverter, the control end of the first channel switch and the control end of the second channel switch are all coupled with the pre-charge control signal; the source and drain ends of the first MOS tube are respectively connected with a power supply voltage and one end of the voltage dividing circuit, the output end of the first inverter is connected with the gate end of the second MOS tube, the source and drain ends of the second MOS tube are respectively connected with the other end of the voltage dividing circuit and the ground, the input end of the first channel switch and the input end of the second channel switch are connected with the output end of the voltage dividing circuit, the output end of the first channel switch is coupled with the first charge and discharge node, and the output end of the second channel switch is coupled with the second charge and discharge node.

Optionally, the charge pump module includes first to fourth current sources, third to sixth MOS transistors, and first and second capacitors; the first current source, the third MOS tube, the fourth MOS tube and the second current source are connected in series to form a first charge-discharge branch, gate ends of the third MOS tube and the fourth MOS tube are both coupled with the second clock signal, the third MOS tube is arranged between the first current source and a first charge-discharge node, the fourth MOS tube is arranged between the first charge-discharge node and the second current source, one end of the first capacitor is connected with the first charge-discharge node, and the other end of the first capacitor is grounded; the third current source, the fifth MOS tube, the sixth MOS tube and the fourth current source are connected in series to form a second charge-discharge branch, gate ends of the fifth MOS tube and the sixth MOS tube are both coupled with the third clock signal, the fifth MOS tube is arranged between the third current source and the second charge-discharge node, the sixth MOS tube is arranged between the second charge-discharge node and the fourth current source, one end of the second capacitor is connected with the second charge-discharge node, and the other end of the second capacitor is grounded.

Optionally, the duty cycle correction module includes a second inverter and a plurality of duty cycle correction units, an input end of the second inverter and an input end of the plurality of duty cycle correction units are connected to each other to form an input end of the duty cycle correction module for accessing an initial clock signal, and an output end of the second inverter and output ends of all the duty cycle correction units are connected to each other to form an output end of the duty cycle correction module.

Optionally, the duty cycle correction circuit further includes a negative feedback module, where the negative feedback module includes a third inverter, a third channel switch, and a fourth channel switch, the input end of the third inverter and the input end of the third channel switch are both connected to the output end of the comparator, the output end of the third inverter is connected to the input end of the fourth channel switch, the output end of the third channel switch and the output end of the fourth channel switch are connected to the same input end of the control module, and the control end of the third channel switch and the control end of the fourth channel switch are connected to clock signals that are opposite to each other.

Optionally, the duty cycle correction circuit further includes fifth to eighth channel switches, the fifth channel switch and the sixth channel switch are respectively coupled between the frequency division module and the charge pump module, the seventh channel switch is coupled between the first charge-discharge node and the non-inverting input terminal of the comparator, the eighth channel switch is coupled between the second charge-discharge node and the inverting input terminal of the comparator, the second clock signal is transmitted from the frequency division module to the charge pump module when the fifth channel switch is turned on, the third clock signal is transmitted from the frequency division module to the charge pump module when the sixth channel switch is turned on, the voltage of the first charge-discharge node is transmitted to the non-inverting input terminal of the comparator when the seventh channel switch is turned on, and the voltage of the second charge-discharge node is transmitted to the inverting input terminal of the comparator when the eighth channel switch is turned on.

Optionally, the duty cycle correction circuit further includes ninth to tenth channel switches; the input end of the ninth channel switch is connected with the second charge-discharge node, the output end of the ninth channel switch is connected with the in-phase input end of the comparator, the input end of the tenth channel switch is connected with the first charge-discharge node, and the output end of the tenth channel switch is connected with the inverting input end of the comparator; or, the input end of the ninth channel switch is connected with the input end of the fifth channel switch, the output end of the ninth channel switch is connected with the output end of the sixth channel switch, the input end of the tenth channel switch is connected with the input end of the sixth channel switch, and the output end of the tenth channel switch is connected with the output end of the fifth channel switch.

Based on the same inventive concept, the invention also provides a chip, which comprises the duty cycle correction circuit.

Optionally, the chip further includes a phase-locked loop circuit coupled to the duty cycle correction circuit, where the phase-locked loop circuit is disposed at a front end of the duty cycle correction circuit or disposed at a back end of the duty cycle correction circuit.

Optionally, the chip is a memory chip, and/or the phase-locked loop circuit is a PLL circuit or a DLL circuit.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. the pre-charging module is added, and the voltage of two input ends (namely a first charging and discharging node and a second charging and discharging node) of the comparator can be pre-charged to a preset voltage after each comparison of the comparator is finished, so that the charging time of the charge pump module to the two charging and discharging nodes can be shortened, the analog voltage output by the two charging and discharging nodes can quickly reach the input voltage value which can be compared by the comparator when the analog voltage is compared next time, the starting time required by each comparison of the comparator is shortened, the response time and the stabilizing time of a loop of the duty ratio correction circuit per se are shortened, the clock duty ratio calibration efficiency is improved finally, and the improvement of the signal transmission rate is facilitated.

2. The ninth channel switch and the tenth channel switch for eliminating input offset are added in front of the input end of the comparator or behind the output end of the frequency dividing module, and the voltage of the two input ends of the comparator or the clock signals output by the frequency dividing module can be overturned in each comparison period of the comparator, so that the influence of the input offset of the two input ends of the comparator on the high and low levels of the clock is the same, the inherent error of duty ratio adjustment is eliminated, and finally the clock signals with more balanced duty ratio are obtained.

3. The negative feedback module is additionally arranged between the output end of the comparator and the control module, so that the feedback of a loop of the duty cycle correction circuit can be regulated to be negative feedback all the time, the stability of the duty cycle correction circuit is enhanced, the nonlinear distortion of the duty cycle correction circuit is improved, and the noise and interference in the duty cycle correction circuit are suppressed.

Drawings

Fig. 1 is a schematic diagram of a circuit architecture design of a conventional duty cycle correction circuit.

Fig. 2 is a timing diagram of the operation of the duty cycle correction circuit shown in fig. 1.

Fig. 3 is a schematic circuit architecture design diagram of a duty cycle correction circuit according to a first embodiment of the present invention.

Fig. 4 is a schematic diagram showing a specific circuit connection example of the duty cycle correction circuit of the first embodiment of the present invention.

Fig. 5 is a schematic diagram showing a specific circuit connection example of the duty correction module in the duty correction circuit of the first embodiment of the present invention.

Fig. 6 is a schematic diagram of the operation timing of the duty cycle correction circuit according to the first embodiment of the present invention.

Fig. 7 is a schematic diagram showing a specific circuit connection example of the duty cycle correction circuit of the second embodiment of the present invention.

Fig. 8 is a schematic diagram showing a specific circuit connection example of the duty cycle correction circuit according to the third embodiment of the present invention.

Fig. 9 and 10 are schematic diagrams of two exemplary architectures of a chip according to a fourth embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. Although the terms first, second, third, etc. may be used herein to describe various elements, components and/or sections, these elements, components and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Thus, a first element, component, or section discussed below could be termed a second element, component, or section without departing from the teachings of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 shows a prior art duty cycle correction circuit for adjusting a clock duty cycle, which includes a charge pump module, a comparator COMP, a control module, and a duty cycle correction module, where the charge pump module is configured to convert the duty cycle of clock signals CKA and CKB output by the duty cycle correction module into two analog voltages, the comparator COMP is configured to compare the analog voltages output by the charge pump module, the control module is configured to generate a control signal of the duty cycle correction module according to a comparison result of the comparator COMP, and the duty cycle correction module receives a corresponding clock signal CLK and generates clock signals CKA and CKB (i.e., clock signals whose duty cycle is adjusted) that have a change with respect to the duty cycle of the clock signal CLK according to the control signal output by the control module.

The duty cycle correction circuit operates with the timing logic shown in fig. 2. The signal CMPE is an enable signal of the comparator COMP, and when CMPE is at a low level, the comparator COMP is not operated, and the clock signal CLK is an initial clock signal. The duty ratio correction circuit mainly comprises a charge-discharge stage, a comparison stage and a duty ratio adjustment stage, wherein in the charge-discharge stage, two clock signals CKA and CKB are transmitted to a charge pump module, and the high-level width edges of the CKA and the CKB respectively represent the low-level width and the high-level width of CLK. The high levels of CKA and CKB control the charge time of the node for outputting the corresponding analog voltage in the charge pump module, respectively, and the low levels of CKA and CKB control the discharge time of the node, respectively. In the comparison phase and the duty cycle adjustment phase, the two clock signals CKA and CKB are not supplied to the charge pump module, and in the duty cycle adjustment phase, the charge pump and the comparator are disconnected, and the corresponding capacitance in the charge pump is discharged to 0. The two analog voltages output by the final charge pump module can represent the low level width and the high level width of CLK, respectively. After a plurality of charge-discharge cycles, the comparator COMP is enabled, compares the magnitudes of the two analog voltages output by the charge pump module, and outputs the comparison result to the control module to generate a control signal of the duty cycle correction module, and the duty cycle correction module adjusts the duty cycle of the clock.

The above-described duty cycle correction circuit has the disadvantages: 1. the longer start-up time, the longer the charge time to the analog voltage output node in the charge pump module, the more common mode input voltage required by the comparator COMP can be reached, which results in a longer response time for the loop and an increase in the loop settling time. 2. The input offset voltage of the comparator COMP may cause a fixed adjustment error of the duty cycle correction circuit.

When the duty cycle correction circuit is applied to the DDR memory chip, the clock signal finally output by the duty cycle correction circuit is an external clock signal of the DDR memory chip, when the DDR memory chip is subjected to read-write operation, data are transmitted on the rising edge and the falling edge of the clock signal, if the duty cycle of the clock signal is lost, namely, the duty cycle of the clock signal finally output by the duty cycle correction circuit is not 50%, the width of the data transmitted on the rising edge and the falling edge of the clock signal is large, the width of the data is small, an eye pattern with a large eye size is seen at the data transmitting end, and even the problem of incomplete data transmission occurs.

Based on this, the invention provides a duty ratio correcting circuit and a chip, compared with the prior art, at least a pre-charging module is added, and the voltage of two input ends (namely a first charging and discharging node and a second charging and discharging node) of the comparator can be pre-charged to a preset voltage after each comparison of the comparator is finished, so that the charging time of the charge pump module to the two charging and discharging nodes can be shortened, the analog voltage output by the two charging and discharging nodes can quickly reach the input voltage value which can be compared by the comparator when the analog voltage is compared next time, the starting time required by each comparison of the comparator is shortened, the response time and the stabilizing time of a loop of the duty ratio correcting circuit per se are shortened, the clock duty ratio correcting efficiency is improved finally, and the improvement of the signal transmission rate is facilitated.

Further, a ninth channel switch and a tenth channel switch for eliminating input offset are added before the input end of the comparator or after the output end of the frequency dividing module, and the voltage of the two input ends of the comparator or the clock signal output by the frequency dividing module can be turned over in each comparison period of the comparator, so that the influence of the input offset of the two input ends of the comparator on the high and low levels of the clock is the same, the inherent error of duty ratio adjustment is eliminated, and finally the clock signal with more balanced duty ratio is obtained.

The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

First embodiment

Referring to fig. 3, the present embodiment provides a duty cycle correction circuit, which includes a charge pump module 10, a comparator 11, a control module 12, a duty cycle correction module 13, a frequency division module 14, and a pre-charging module 15.

The input end of the frequency dividing module 14 is coupled to the output end of the duty correcting module 13, and the frequency dividing module 14 is configured to generate a second clock signal CKA and a third clock signal CKB based on the first clock signal CLKi (where i=0 to m, m is an integer greater than or equal to 0) output by the duty correcting module 13, where the second clock signal CKA and the corresponding first clock signal CLKi have the same duty cycle, the third clock signal CKB is an inverse signal of the second clock signal CKA, and the sum of the duty cycle of the second clock signal CKA and the duty cycle of the third clock signal CKB is 1.

The charge pump module 10 has a first charge-discharge node a and a second charge-discharge node b, the first charge-discharge node a is coupled to the non-inverting input terminal "+" of the comparator 11, the second charge-discharge node b is coupled to the inverting input terminal "-" of the comparator 11, and the charge pump module 10 is configured to charge or discharge the first charge-discharge node a and the second charge-discharge node b under the control of the second clock signal CKA and the third clock signal CKB, so as to output the corresponding two analog voltages VA and VB.

The output end of the comparator 11 is coupled to the input end of the control module 12, and the comparator 11 is used for comparing the two analog voltages VA and VB output by the charge pump module 10 under the control of the comparison enabling signal CMPE. The output end of the control module 12 is coupled to one input end of the duty cycle correction module 13, and the control module 12 is configured to generate a corresponding adjustment control signal control according to the comparison result of the comparator 11, and provide the adjustment control signal control to the duty cycle correction module 13. The duty cycle correction module 13 is configured to adjust the duty cycle of the first clock signal CLKi output by the control module 12 according to the adjustment control signal control output by the control module. The pre-charge module 15 is coupled to the first charge-discharge node and the second charge-discharge node, and the pre-charge module 15 is configured to pre-charge the voltages VA and VB of the first charge-discharge node a and the second charge-discharge node b to a predetermined voltage, for example, half of the power supply voltage VDD (i.e., VDD/2) to which the charge pump module 10 is connected after the comparison of the comparator 11 is completed under the control of the pre-charge control signal CKP.

As an example, referring to fig. 4, in the present embodiment, the pre-charging module 15 includes a first MOS transistor P1, a second MOS transistor N1, a first channel switch Q1, a second channel switch Q2, a first inverter U1, and a voltage dividing circuit. The first MOS transistor P1 is a PMOS transistor, the second MOS transistor N1 is an NMOS transistor, the first channel switch Q1 and the second channel switch Q2 may be transistors or MOS transistors, and the voltage dividing circuit is composed of resistors R1 and R2 connected in series. The gate end of the first MOS tube PA, the input end of the first inverter U1, the control end of the first channel switch Q1 and the control end of the second channel switch Q2 are all coupled with a pre-charge control signal CKP, the source end of the first MOS tube P1 is respectively connected with a power supply voltage VDD, the drain end of the first MOS tube P1 is connected with one end of a resistor R1 (namely one end of a voltage dividing circuit), the output end of the first inverter U1 is connected with the gate end of a second MOS tube N1, the drain end of the second MOS tube N1 is connected with one end of a resistor R2 (namely the other end of the voltage dividing circuit), the source end of the second MOS tube N1 is grounded, the serial connection node of the resistor R1 and the resistor R2 is the output end of the voltage dividing circuit, the input end of the first channel switch Q1 and the input end of the second channel switch Q2 are connected with the serial connection node of the resistor R1 and the resistor R2, the output end of the first channel switch Q1 is coupled with a first charge and discharge node a, and the output end of the second channel switch Q2 is coupled with a second charge and discharge node b.

As an example, please continue to refer to fig. 4, the charge pump module 10 includes first to fourth current sources I1 to I4, a third MOS transistor P2, a fourth MOS transistor N2, a fifth MOS transistor P3, a sixth MOS transistor N3, a first capacitor C1, and a second capacitor C2. The first current source I1, the third MOS transistor P2, the fourth MOS transistor N2 and the second current source I2 are connected in series to form a first charge-discharge branch, gate ends of the third MOS transistor P2 and the fourth MOS transistor N2 are both coupled to the second clock signal CKA, the third MOS transistor P2 is disposed between the first current source I1 and the first charge-discharge node a, the fourth MOS transistor N2 is disposed between the first charge-discharge node a and the second current source I2, one end of the first capacitor C1 is connected to the first charge-discharge node a and the non-inverting input end of the comparator 11, and the other end of the first capacitor C1 is grounded; the third current source I3, the fifth MOS tube P3, the sixth MOS tube N3 and the fourth current source I4 are connected in series to form a second charge-discharge branch, gate ends of the fifth MOS tube P3 and the sixth MOS tube N3 are both coupled with the third clock signal CKB, the fifth MOS tube P3 is arranged between the third current source I3 and the second charge-discharge node b, the sixth MOS tube N3 is arranged between the second charge-discharge node b and the fourth current source I4, one end of the second capacitor C2 is connected with the second charge-discharge node b and the inverting input end of the comparator 11, and the other end of the second capacitor C2 is grounded.

Optionally, the third MOS transistor P2 and the fifth MOS transistor P3 are PMOS transistors, and the fourth MOS transistor N2 and the sixth MOS transistor N3 are NMOS transistors. In other embodiments of the present invention, the third MOS transistor P2 and the fifth MOS transistor P3 may be replaced by an NMOS transistor or a triode, and the fourth MOS transistor N2 and the sixth MOS transistor N3 may be replaced by a PMOS transistor or a triode, and at this time, the respective termination methods of the third MOS transistor P2, the fourth MOS transistor N2, the fifth MOS transistor P3 and the sixth MOS transistor N3 are adaptively adjusted.

As an example, referring to fig. 5, the duty cycle correction module 13 of the present embodiment includes a second inverter U2 and (n+1) duty cycle correction units 130 to 13n, where n is greater than or equal to 1 and is an integer. The input end of the second inverter U2 and the input ends of the respective duty correction units 130 to 13n are connected to each other to form an input end of the duty correction module 13 for accessing the initial clock signal CLK, and the output end of the second inverter U2 and the output ends of all the duty correction units 130 to 13n are connected to each other to form an output end of the duty correction module 13. Each duty ratio correction unit comprises two PMOS tubes and two NMOS tubes, wherein the source end of the first PMOS tube is connected with the power supply voltage VDD, the drain end of the first PMOS tube is connected with the source end of the second PMOS tube, the gate end of the first PMOS tube is connected with the adjusting control signal EA, the drain end of the second PMOS tube is connected with the drain end of the first NMOS tube, the gate end of the second PMOS tube is connected with the gate end of the first NMOS tube and is connected with the initial clock signal CLK, the source end of the first NMOS tube is connected with the drain end of the second NMOS tube, the source end of the second NMOS tube is grounded, and the gate end of the second NMOS tube is connected with the adjusting control signal EB. Specifically, for example, the duty ratio correction unit 130 includes PMOS transistors PM01 to PM02 and NMOS transistors NM01 to NM02, the source of the PMOS transistor PM01 is connected to the power supply voltage VDD, the drain is connected to the source of the PMOS transistor PM02, the gate of the PMOS transistor PM01 is connected to the adjustment control signal EA <0>, the drain of the PMOS transistor PM02 is connected to the drain of the NMOS transistor NM01, the gate of the PMOS transistor PM02 is connected to the gate of the NMOS transistor NM01 and is connected to the initial clock signal CLK, the source of the NMOS transistor NM01 is connected to the drain of the NMOS transistor NM02, the source of the NMOS transistor NM02 is connected to the ground, and the gate of the NMOS transistor NM02 is connected to the adjustment control signal EB <0>; by analogy, the duty ratio correction unit 13n includes PMOS transistors PMn1 to PMn2 and NMOS transistors NMn1 to NMn, the source of the PMOS transistor PMn1 is connected to the power supply voltage VDD, the drain is connected to the source of the PMOS transistor PMn2, the gate of the PMOS transistor PMn1 is connected to the adjustment control signal EA < n >, the drain of the PMOS transistor PMn2 is connected to the drain of the NMOS transistor NMn1, the gate of the PMOS transistor PMn2 is connected to the gate of the NMOS transistor NMn1 and is connected to the initial clock signal CLK, the source of the NMOS transistor NMn is connected to the drain of the NMOS transistor NMn2, the source of the NMOS transistor NMn is connected to the ground, and the gate of the NMOS transistor NMn is connected to the adjustment control signal EB < n >. Wherein EA <0> -EA < n > and EB <0> -EB < n > are adjustment control signals generated by the control module 12 according to the comparison result of the comparator 11.

Optionally, the duty cycle correction circuit of this embodiment further includes fifth to eighth channel switches Q5 to Q8, the fifth channel switch Q5 and the sixth channel switch Q6 are respectively coupled between the frequency dividing module 14 and the charge pump module 10, the seventh channel switch Q7 is coupled between the first charge-discharge node a and the non-inverting input terminal of the comparator 11, the eighth channel switch Q8 is coupled between the second charge-discharge node b and the inverting input terminal of the comparator 11, the control terminal of the fifth channel switch Q5 and the control terminal of the sixth channel switch Q6 are both connected to the control signal CKC, the control terminal of the seventh channel switch Q7 and the control terminal of the eighth channel switch Q8 are both connected to the control signal CKS, when the fifth channel switch Q5 is turned on, the second clock signal CKA is transmitted from the frequency dividing module 14 to the charge pump module 10, when the sixth channel switch Q6 is turned on, the third clock signal CKB is transmitted from the frequency dividing module 14 to the charge pump module 10, when the voltage of the seventh channel switch Q7 is transmitted to the non-inverting input terminal VA 11 of the comparator 11, and when the voltage of the seventh channel switch Q7 is turned on is transmitted to the non-inverting input terminal VA of the comparator 11.

It should be understood that the comparison enable signal CMPE, the precharge control signal CKP, the control signal CKC, and the control signal CKS are timings for controlling the entire circuit of the duty cycle correction circuit of the present embodiment, and a combination thereof can be used to set the initial voltage for the first charge-discharge node a and the second charge-discharge node b of the duty cycle correction circuit of the present embodiment, and to set the operation timings for the duty cycle correction circuit of the present embodiment as a whole, including a charge-discharge phase, a comparison phase, a precharge phase, and a duty cycle adjustment phase, as shown in fig. 6. The comparison enable signal CMPE, the precharge control signal CKP, the control signal CKC and the control signal CKS may be provided by the control module 12, or the control logic of the comparison enable signal CMPE, the precharge control signal CKP, the control signal CKC and the control signal CKS may be integrated into the frequency dividing module 14 (i.e. the comparison enable signal CMPE, the precharge control signal CKP, the control signal CKC and the control signal CKS are provided by the frequency dividing module 14), or the comparison enable signal CMPE, the precharge control signal CKP, the control signal CKC and the control signal CKS may be provided by circuits external to the duty cycle correction circuit of the present embodiment, or a part of the comparison enable signal CMPE, the precharge control signal CKP, the control signal CKC and the control signal CKS may be provided by one of the control module 12, the frequency dividing module 14 and the external circuit, and another part of the signals may be provided by the other of the control module 12, the frequency dividing module 14 and the external circuit.

Referring to fig. 4 and fig. 6, in the duty cycle correction circuit of the present embodiment, in the charge-discharge stage, the control signal CKC controls the fifth channel switch Q5 and the sixth channel switch Q6 to be turned on; in the comparison phase, the duty cycle adjustment phase and the precharge phase, the control signal CKC controls the fifth channel switch Q5 and the sixth channel switch Q6 to be turned off so that the second clock signal CKA and the third clock signal CKB are not transferred into the charge pump module 10; in the duty cycle adjustment stage, the control signal CKS controls the seventh channel switch Q7 and the eighth channel switch Q8 to be turned off; in the precharge phase, the precharge control signal CKP controls the first channel switch Q1 and the second channel switch Q2 to be turned on, and at this time, the voltage generated by dividing the resistors R1 and R2 becomes VDD/2 regardless of the magnitudes of VA and VB of the first capacitor C1 and the second capacitor C2 (when the resistors R1 and R2 are the same).

The duty cycle correction module 13 adjusts the duty cycle of the clock according to the following principle:

in the first period, the initial clock signal CLK (which can be regarded as CLK 0) is sent to the frequency dividing module 14, the generated second clock signal CKA and third clock signal CKB are denoted as CKA0 and CKB0, the comparator 11 compares VA and VB to determine whether the duty ratio of the initial clock signal CLK is greater than the target value (e.g., 50%) or less than the target value, and if the duty ratio of the initial clock signal CLK is greater than the target value, the duty ratio correcting module 13 adjusts the duty ratio of the initial clock signal CLK to be smaller, otherwise adjusts the duty ratio of the initial clock signal CLK to be larger, thereby obtaining the duty ratio-adjusted clock signal CLK1;

In the second period, the frequency dividing module 14 marks the second clock signals CKA and CKB generated based on the clock signal CLK1 as CKA1 and CKB1, the comparator 11 compares VA and VB and then determines whether the duty ratio of the clock signal CLK1 is greater than the target value or less than the target value, and if the duty ratio of the clock signal CLK1 is greater than the target value, the duty ratio correcting module 13 decreases the duty ratio of the clock signal CLK1, otherwise increases the duty ratio of the clock signal CLK1, thereby obtaining the duty ratio-adjusted clock signal CLK2;

and so on, until the comparator 11 compares VA and VB and then determines that the duty ratio of the clock signal CLKi at that time (where i=0 to m, m is an integer greater than or equal to 0) is equal to the target value, at this time, the duty-cycle-adjusted clock signal CLKi output by the duty-cycle correction module 13 may be locked as the clock signal that is finally output to the external circuit.

Compared with the prior art, the duty ratio correction circuit of the embodiment is added with the pre-charging module, and can pre-charge the voltages of two input ends (namely the first charging and discharging node and the second charging and discharging node) of the comparator to the preset voltage after each comparison of the comparator is finished, so that the charging time of the charge pump module to the two charging and discharging nodes can be shortened, the analog voltage output by the two charging and discharging nodes can quickly reach the input voltage value which can be compared by the comparator when the analog voltage is compared next time, the starting time required by each comparison of the comparator is shortened, the response time and the stabilizing time of a loop of the duty ratio correction circuit per se are shortened, the clock duty ratio calibration efficiency is improved finally, and the improvement of the signal transmission rate is facilitated.

Second embodiment

Referring to fig. 7, the present embodiment provides a duty cycle correction circuit, which is different from the first embodiment in that the duty cycle correction circuit of the present embodiment includes a negative feedback module 16 and ninth to tenth channel switches Q9 to Q10 in addition to a charge pump module 10, a comparator 11, a control module 12, a duty cycle correction module 13, a frequency division module 14, a precharge module 15, and fifth to eighth channel switches Q5 to Q8.

The negative feedback module 16 includes a third inverter U3, a third channel switch Q3, and a fourth channel switch Q4, wherein an input end of the third inverter U3 and an input end of the third channel switch Q3 are both connected to an output end of the comparator 11, an output end of the third inverter U3 is connected to an input end of the fourth channel switch Q4, an output end of the third channel switch Q3 and an output end of the fourth channel switch Q4 are connected to the same input end of the control module 12, a control end of the third channel switch Q3 is connected to the control signal CKS, a control end of the fourth channel switch Q4 is connected to the control signal cks_b, and the control signal CKS is an inverse signal of the control signal cks_b.

The input end of the ninth channel switch Q9 is connected with the second charge-discharge node b, the output end of the ninth channel switch Q9 is connected with the non-inverting input end of the comparator 11, the input end of the tenth channel switch Q10 is connected with the first charge-discharge node a, and the output end of the tenth channel switch Q10 is connected with the inverting input end of the comparator 11. The control terminal of the ninth channel switch Q9 and the control terminal of the tenth channel switch Q10 are both connected to the control signal cks_b.

In this embodiment, the negative feedback module 16 and the ninth to tenth channel switches Q9 to Q10 cooperate under the control of the control signal CKS and the control signal cks_b, control the two analog voltages VA and VB to be connected to the in-phase input end or the anti-phase input end of the comparator 11 in each comparison period in a flip manner, so that the input offset voltage of the comparator 11 is evenly distributed to the high level stage and the low level stage of the second clock signal CKA and the third clock signal CKB, and the loop feedback of the duty cycle correction circuit is adjusted to be negative feedback all the time, thereby eliminating the influence of the input offset voltage of the comparator 11 on the adjustment of the clock duty cycle, eliminating the inherent error of the adjustment of the duty cycle, enhancing the stability of the duty cycle correction circuit, improving the nonlinear distortion of the duty cycle correction circuit, inhibiting the noise and interference inside the duty cycle correction circuit, finally obtaining the clock signal with more balanced duty cycle, and improving the adjustment precision of the duty cycle correction circuit on the clock duty cycle.

Third embodiment

Referring to fig. 8, the present embodiment provides a duty cycle correction circuit, which is different from the first embodiment in that the duty cycle correction circuit of the present embodiment includes a negative feedback module 16 and ninth to tenth channel switches Q9 to Q10 in addition to a charge pump module 10, a comparator 11, a control module 12, a duty cycle correction module 13, a frequency division module 14, a precharge module 15, and fifth to eighth channel switches Q5 to Q8.

The input end of the ninth channel switch Q9 is connected with the input end of the fifth channel switch Q5, the output end of the ninth channel switch Q9 is connected with the output end of the sixth channel switch Q6, the input end of the tenth channel switch Q10 is connected with the input end of the sixth channel switch Q65, and the output end of the tenth channel switch Q10 is connected with the output end of the fifth channel switch Q5. The control terminal of the ninth channel switch Q9 and the control terminal of the tenth channel switch Q10 are both connected to the control signal ckc_b, and the control signal ckc_b is an inverse signal of the control signal CKC.

In this embodiment, the fifth to sixth channel switches Q5 to Q6 and the ninth to tenth channel switches Q9 to Q10 are mutually matched under the control of the control signal CKC and the control signal ckc_b, and the second clock signal CKA and the third clock signal CKB are controlled to be connected to the charge pump module 10 in a turnover manner in each comparison period, so that the two analog voltages VA and VB output by the charge pump module 10 are connected to the non-inverting input terminal or the inverting input terminal of the comparator 11 in a turnover manner in each comparison period, and further the input offset voltage of the comparator 11 is evenly distributed to the high level stage and the low level stage of the second clock signal CKA and the third clock signal CKB, and the negative feedback module 16 adjusts the loop feedback of the duty cycle correction circuit to be negative feedback all the time under the control of the control signal CKS and the control signal cks_b, thereby eliminating the influence of the input offset voltage of the comparator 11 on the clock duty cycle adjustment, eliminating the inherent error of the duty cycle adjustment, enhancing the stability of the duty cycle correction circuit, improving the non-linearity of the duty cycle correction circuit, and suppressing the noise of the duty cycle correction circuit and finally obtaining the duty cycle correction circuit.

Fourth embodiment

Referring to fig. 9 and 10, the present embodiment further provides a chip, which includes the duty cycle correction circuit 1 according to any one of the above embodiments of the present invention and a phase-locked loop circuit 2 coupled to the duty cycle correction circuit 1, where the phase-locked loop circuit 2 may be disposed at a front end of the duty cycle correction circuit 1 (as shown in fig. 10) or disposed at a rear end of the duty cycle correction circuit 1 (as shown in fig. 9).

Wherein alternatively the chip of the present embodiment may be a memory chip (e.g., DDR memory chip), the phase-locked loop circuit 2 may be a PLL circuit or a DLL circuit. Referring to fig. 9, when the phase-locked loop circuit 2 is at the front end of the duty cycle correction circuit 1, the duty cycle correction circuit 1 can be used to synchronize the clock signal of the internal circuit of the memory chip with the clock signal of the external circuit to solve the clock skew problem, and the duty cycle of the clock output by the phase-locked loop circuit 2 is adjusted to the target value. Referring to fig. 10, when the phase-locked loop circuit 2 is at the back end of the duty cycle correction circuit 1, the phase-locked loop circuit 2 can synchronize the clock output by the duty cycle correction circuit 1 with the clock of the internal circuit of the memory chip to solve the clock skew problem. The duty ratio of the memory chip can reach 50% due to the adoption of the duty ratio correction circuit 1 of the embodiment, so that the problem that an eye pattern with a large eye and a small eye is seen at a data transmitting end and the problem that data transmission is incomplete can be avoided when the memory chip is subjected to read-write operation based on a clock signal with the duty ratio of 50%.

The foregoing description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way, and any alterations and modifications made by those skilled in the art in light of the above disclosure shall fall within the scope of the present invention.

Claims

1. A duty cycle correction circuit is characterized by comprising a charge pump module, a comparator, a control module, a duty cycle correction module, a frequency division module and a pre-charging module, wherein,

2. The duty cycle correction circuit of claim 1, wherein the pre-charge module comprises a first MOS transistor, a second MOS transistor, a first channel switch, a second channel switch, a first inverter, and a voltage divider circuit; the gate end of the first MOS tube, the input end of the first inverter, the control end of the first channel switch and the control end of the second channel switch are all coupled with the pre-charge control signal; the source and drain ends of the first MOS tube are respectively connected with a power supply voltage and one end of the voltage dividing circuit, the output end of the first inverter is connected with the gate end of the second MOS tube, the source and drain ends of the second MOS tube are respectively connected with the other end of the voltage dividing circuit and the ground, the input end of the first channel switch and the input end of the second channel switch are connected with the output end of the voltage dividing circuit, the output end of the first channel switch is coupled with the first charge and discharge node, and the output end of the second channel switch is coupled with the second charge and discharge node.

3. The duty cycle correction circuit of claim 1, wherein the charge pump module comprises first to fourth current sources, third to sixth MOS transistors, and first and second capacitors; the first current source, the third MOS tube, the fourth MOS tube and the second current source are connected in series to form a first charge-discharge branch, gate ends of the third MOS tube and the fourth MOS tube are both coupled with the second clock signal, the third MOS tube is arranged between the first current source and a first charge-discharge node, the fourth MOS tube is arranged between the first charge-discharge node and the second current source, one end of the first capacitor is connected with the first charge-discharge node, and the other end of the first capacitor is grounded; the third current source, the fifth MOS tube, the sixth MOS tube and the fourth current source are connected in series to form a second charge-discharge branch, gate ends of the fifth MOS tube and the sixth MOS tube are both coupled with the third clock signal, the fifth MOS tube is arranged between the third current source and the second charge-discharge node, the sixth MOS tube is arranged between the second charge-discharge node and the fourth current source, one end of the second capacitor is connected with the second charge-discharge node, and the other end of the second capacitor is grounded.

4. The duty cycle correction circuit of claim 1, wherein the duty cycle correction module comprises a second inverter and a plurality of duty cycle correction units, the input of the second inverter and the input of the plurality of duty cycle correction units are connected to each other to form an input of the duty cycle correction module for accessing an initial clock signal, and the output of the second inverter and the outputs of all the duty cycle correction units are connected to each other to form an output of the duty cycle correction module.

5. The duty cycle correction circuit of claim 1, further comprising a negative feedback module comprising a third inverter, a third channel switch, and a fourth channel switch, wherein the input of the third inverter and the input of the third channel switch are both connected to the output of the comparator, the output of the third inverter is connected to the input of the fourth channel switch, the output of the third channel switch and the output of the fourth channel switch are connected to the same input of the control module, and the control of the third channel switch and the control of the fourth channel switch are connected to control signals that are in anti-phase with each other.

6. The duty cycle correction circuit of any one of claims 1 to 5, further comprising fifth to eighth pass switches coupled between the frequency division module and the charge pump module, respectively, the seventh pass switch coupled between the first charge-discharge node and the non-inverting input of the comparator, the eighth pass switch coupled between the second charge-discharge node and the inverting input of the comparator, the second clock signal being supplied from the frequency division module to the charge pump module when the fifth pass switch is on, the third clock signal being supplied from the frequency division module to the charge pump module when the sixth pass switch is on, the voltage of the first charge-discharge node being supplied to the non-inverting input of the comparator when the seventh pass switch is on, the voltage of the second charge-discharge node being supplied to the inverting input of the comparator when the eighth pass switch is on.

7. The duty cycle correction circuit of claim 6, further comprising ninth to tenth channel switches; the input end of the ninth channel switch is connected with the second charge-discharge node, the output end of the ninth channel switch is connected with the in-phase input end of the comparator, the input end of the tenth channel switch is connected with the first charge-discharge node, and the output end of the tenth channel switch is connected with the inverting input end of the comparator; or, the input end of the ninth channel switch is connected with the input end of the fifth channel switch, the output end of the ninth channel switch is connected with the output end of the sixth channel switch, the input end of the tenth channel switch is connected with the input end of the sixth channel switch, and the output end of the tenth channel switch is connected with the output end of the fifth channel switch.

8. A chip comprising the duty cycle correction circuit of any one of claims 1-7.

9. The chip of claim 8, further comprising a phase-locked loop circuit coupled to the duty cycle correction circuit, the phase-locked loop circuit disposed at a front end of the duty cycle correction circuit or disposed at a back end of the duty cycle correction circuit.

10. The chip of claim 9, wherein the chip is a memory chip and/or the phase-locked loop circuit is a PLL circuit or a DLL circuit.