CN116487364A - Failure morphology analysis system, method and equipment for crystal grains - Google Patents

Failure morphology analysis system, method and equipment for crystal grains Download PDF

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Publication number
CN116487364A
CN116487364A CN202210037601.4A CN202210037601A CN116487364A CN 116487364 A CN116487364 A CN 116487364A CN 202210037601 A CN202210037601 A CN 202210037601A CN 116487364 A CN116487364 A CN 116487364A
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target
wafer
structure diagram
crystal grain
die
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李超
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210037601.4A priority Critical patent/CN116487364A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The embodiment of the disclosure provides a failure morphology analysis system, a failure morphology analysis method and failure morphology analysis equipment of a crystal grain, wherein the system comprises: the graphic drawing module is used for acquiring repair data of the target wafer from the database, generating a wafer map corresponding to the target wafer in the display interface, and determining a grain structure diagram corresponding to each grain in the wafer map; the processing module is used for acquiring the repair information corresponding to the currently selected target crystal grain from the repair data stored in the database when receiving the selection operation triggered by the user in the wafer map, and adding the repair information corresponding to the target crystal grain in a crystal grain structure diagram corresponding to the target crystal grain in a preset mode; and the display module is used for displaying the target grain structure diagram after the target grain is adjusted in the display interface. The embodiment of the disclosure can intuitively display the repair information of the crystal grains in a crystal grain structure diagram in a graphical mode, help a tester to quickly locate the abnormality of each crystal grain, and improve the test efficiency.

Description

Failure morphology analysis system, method and equipment for crystal grains
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a failure morphology analysis system, method and equipment of a crystal grain.
Background
The fabrication of semiconductor devices is very complex, and often requires hundreds or even thousands of different processes to be applied to the wafer surface to produce various semiconductor devices with specific electrical characteristics on the wafer.
In order to ensure the process quality of semiconductor devices, it is often necessary to develop a test program to test the wafer. In the early stage of test program development, a tester needs to adjust parameter current, parameter voltage and the like in the test program by repeatedly analyzing test results. One of the very important parameters is the Fail Bit Count (FBC), and a tester can accurately locate anomalies in each Die (Die) by analyzing the FBC.
Currently, a tester typically analyzes the FBC by using a failure morphology analysis (Fail shape analysis, abbreviated as FSA), however, the FBC can accurately locate the failed memory cell by using the FSA analysis, but the efficiency is very low, which affects the testing efficiency.
Disclosure of Invention
The embodiment of the disclosure provides a failure morphology analysis system, a failure morphology analysis method and failure morphology analysis equipment for crystal grains, which can rapidly locate abnormal conditions of each crystal grain in a graphical mode and improve test efficiency.
In some embodiments, a failure morphology analysis system of a die is provided, comprising:
the graphic drawing module is used for acquiring repair data of a target wafer from the database, generating a wafer map corresponding to the target wafer in the display interface, and determining a grain structure diagram corresponding to each grain in the wafer map;
the processing module is used for acquiring the repair information corresponding to the currently selected target crystal grain from the repair data stored in the database when receiving the selection operation triggered by the user in the wafer map, and adding the repair information corresponding to the target crystal grain in a crystal grain structure diagram corresponding to the target crystal grain in a preset mode;
and the display module is used for displaying the target grain structure diagram after the target grain is adjusted in the display interface.
In a possible implementation, the graphics rendering module is configured to:
determining repaired grains and unrepaired grains in the target wafer according to the repair data of the target wafer;
and generating a wafer map corresponding to the target wafer in a display interface, wherein the repaired crystal grains and the unrepaired crystal grains in the target wafer adopt different display modes in the wafer map.
In a possible implementation, the graphics rendering module is configured to:
acquiring structure configuration information corresponding to each crystal grain in the target wafer according to the product information of each crystal grain in the target wafer;
determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer; the grain structure diagram comprises a plurality of storage arrays, each storage array is divided into a plurality of storage blocks according to rows and columns, and each storage block comprises a plurality of storage units.
In a possible implementation manner, the graphic drawing module is specifically configured to:
clustering the structure configuration information corresponding to each crystal grain in the target wafer, and determining a basic structure diagram corresponding to each type of structure configuration information;
and determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer and the determined basic structure diagram corresponding to each type of structure configuration information.
In a possible embodiment, the processing module is configured to:
according to the number of the repaired word lines or bit lines connected with the repair information corresponding to the target crystal grains and the corresponding relation between the preset number of the repaired word lines or bit lines and each display color, the display color of the repaired word lines or bit lines in the crystal grain structure diagram corresponding to the target crystal grains is adjusted;
The target die comprises a plurality of bit lines and a plurality of word lines, and each bit line and each word line are connected with a plurality of memory cells.
In a possible embodiment, the processing module is configured to:
when a positioning operation triggered by a user is received, determining a target row storage block and/or a target column storage block selected by the positioning operation in the target grain structure diagram;
and adjusting the display color of the repaired word line or bit line in the target row memory block according to the number of the repaired word line or bit line contained in the repair information corresponding to the target crystal grain and the corresponding relation between the preset number of the repaired word line or bit line and each display color.
In a possible embodiment, the method further includes:
and the control module is used for amplifying or reducing the target grain structure diagram according to the scaling operation when receiving the scaling operation triggered by the user.
In a possible embodiment, the method further includes:
the screening module is used for determining the type of the detection result selected by the screening operation in the target grain structure diagram when the screening operation triggered by the user is received;
And adjusting the target grain structure diagram according to the detection result type selected by the screening operation in the target grain structure diagram.
In a possible embodiment, the method further includes:
the data processing module is used for acquiring the repair data of the target wafer, wherein the repair data is unstructured data;
and converting the repair data into structural data and then storing the structural data into the database.
In some embodiments, a method of failure morphology analysis of a die is provided, the method comprising:
obtaining repair data of a target wafer from a database, generating a wafer map corresponding to the target wafer in a display interface, and determining a grain structure map corresponding to each grain in the wafer map;
when receiving a selection operation triggered by a user in the wafer map, acquiring repair information corresponding to a currently selected target crystal grain from repair data stored in the database, and adding the repair information corresponding to the target crystal grain in a crystal grain structure diagram corresponding to the target crystal grain in a preset mode;
and displaying the target grain structure diagram after the target grain is adjusted in the display interface.
In a possible implementation manner, the obtaining the repair data of the target wafer from the database, and generating the wafer map corresponding to the target wafer in the display interface, includes:
Determining repaired grains and unrepaired grains in the target wafer according to the repair data of the target wafer;
and generating a wafer map corresponding to the target wafer in a display interface, wherein the repaired crystal grains and the unrepaired crystal grains in the target wafer adopt different display modes in the wafer map.
In a possible implementation manner, the determining a grain structure diagram corresponding to each grain in the wafer map includes:
acquiring structure configuration information corresponding to each crystal grain in the target wafer according to the product information of each crystal grain in the target wafer;
determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer; the grain structure diagram comprises a plurality of storage arrays, each storage array is divided into a plurality of storage blocks according to rows and columns, and each storage block comprises a plurality of storage units.
In a possible implementation manner, the determining, according to the structural configuration information corresponding to each die in the target wafer, a die structure diagram corresponding to each die in the wafer map includes:
clustering the structure configuration information corresponding to each crystal grain in the target wafer, and determining a basic structure diagram corresponding to each type of structure configuration information;
And determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer and the determined basic structure diagram corresponding to each type of structure configuration information.
In a possible implementation manner, the adding the repair information corresponding to the target die to the die structure diagram corresponding to the target die in a preset manner includes:
according to the number of the repaired word lines or bit lines connected with the repair information corresponding to the target crystal grains and the corresponding relation between the preset number of the repaired word lines or bit lines and each display color, the display color of the repaired word lines or bit lines in the crystal grain structure diagram corresponding to the target crystal grains is adjusted;
the target die comprises a plurality of bit lines and a plurality of word lines, and each bit line and each word line are connected with a plurality of memory cells.
In a possible implementation manner, the adding the repair information corresponding to the target die to the die structure diagram corresponding to the target die in a preset manner includes:
when a positioning operation triggered by a user is received, determining a target row storage block and/or a target column storage block selected by the positioning operation in the target grain structure diagram;
And adjusting the display color of the repaired word line or bit line in the target row memory block according to the number of the repaired word line or bit line contained in the repair information corresponding to the target crystal grain and the corresponding relation between the preset number of the repaired word line or bit line and each display color.
In a possible implementation manner, after the displaying the target grain structure diagram after the target grain adjustment in the display interface, the method further includes:
when a scaling operation triggered by a user is received, the target grain structure diagram is enlarged or reduced according to the scaling operation;
when a screening operation triggered by a user is received, determining a detection result type selected by the screening operation in the target grain structure diagram, and adjusting the target grain structure diagram according to the detection result type selected by the screening operation in the target grain structure diagram.
In some embodiments, an electronic device is provided, comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executes the computer-executable instructions stored by the memory, causing the at least one processor to perform the failure morphology analysis method of the die as provided in the above embodiments.
In some embodiments, a computer readable storage medium having stored therein computer executable instructions that, when executed by a processor, implement a method of failure morphology analysis of a die as provided in the above embodiments.
According to the failure morphological analysis system, method and equipment for the crystal grains, provided by the embodiment of the disclosure, the crystal grain structure diagram of each crystal grain in the wafer diagram is drawn, and the repair information corresponding to the crystal grain is added in the crystal grain structure diagram corresponding to the crystal grain, so that the repair information of the crystal grain can be intuitively displayed in the crystal grain structure diagram in a graphical mode, a tester is helped to quickly locate the abnormality of each crystal grain, and the test efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of an alternative hardware environment in a failure morphology analysis system of a die provided in an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a failure morphology analysis system of a die according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of another architecture of a failure morphology analysis system of a die according to an embodiment of the present disclosure;
FIG. 4 is a wafer map provided in an embodiment of the present disclosure;
FIG. 5 is a schematic layout diagram of a memory chip according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a die structure provided in an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a second die structure provided in an embodiment of the disclosure;
FIG. 8 is a scaled schematic of a wafer structure diagram provided in an embodiment of the present disclosure;
FIG. 9 is a flow chart of a method for analyzing failure morphology of a die according to an embodiment of the present disclosure;
fig. 10 is a schematic hardware structure of an electronic device according to an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. Furthermore, while the disclosure has been presented by way of example only, it should be appreciated that various aspects of the disclosure may be separately implemented in a complete embodiment.
It should be noted that the brief description of the terms in the present disclosure is only for convenience in understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for describing a particular sequential or chronological order, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.
The term "module" as used in this disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and/or software code that is capable of performing the function associated with that element.
The fabrication of semiconductor devices is very complex, and often requires hundreds or even thousands of different processes to be performed on the Wafer (Wafer) surface to produce various semiconductor devices with specific electrical characteristics.
For example, in the field of semiconductor device manufacturing technology, the wafer generally refers to a silicon wafer used for manufacturing an integrated circuit, in the process of manufacturing an integrated circuit on a wafer, the wafer is divided into a plurality of exposure fields (shots), and the shots are generally taken as basic units in production, typically, basic exposure units (photomograms), which are periodically and repeatedly arranged on the wafer. Each basic Shot unit also comprises one or more dies, after the integrated circuits on the wafer are all manufactured, the wafer is cut into a plurality of dies, and each Die comprises an independent integrated circuit capable of realizing the preset function, which is a basic unit for packaging and testing.
In order to ensure the process quality of semiconductor devices, it is often necessary to develop a test program to test the wafer. In the early stage of test program development, a tester needs to adjust parameter current, parameter voltage and the like in the test program by repeatedly analyzing test results. One of the very important parameters is the Fail Bit Count (FBC), and a tester can accurately locate anomalies of each die by analyzing the FBC.
Currently, a tester usually uses a failure morphological analysis (Fail shape analysis, abbreviated as FSA) to analyze the FBC, however, the FSA analysis of the FBC can accurately locate the failed memory cell, but the efficiency is very low, which affects the development efficiency of the test procedure.
In view of the above technical problems, an embodiment of the present disclosure provides a failure morphology analysis system for a die, where the system is configured to draw a wafer map and a die structure diagram of each die in the wafer map, and add repair information corresponding to the die structure diagram corresponding to the die, so that the repair information of the die can be intuitively displayed in the die structure diagram in a graphical manner, thereby helping a tester to quickly locate an abnormality of each die and improving test efficiency. The following will explain in detail the embodiments.
In one possible implementation, referring to fig. 1, fig. 1 is a schematic diagram of an alternative hardware environment in a failure morphology analysis system of a die according to an embodiment of the disclosure. The failure morphology analysis system of the die provided in the embodiment of the present disclosure may be applied to a hardware environment composed of the terminal 101 and the server 102 as shown in fig. 1.
In some embodiments, server 102 is connected to terminal 101 through a network including, but not limited to: the terminal 101 is not limited to a PC ((personal computer, personal computer), mobile phone, tablet computer, notebook computer, etc.), and the server 102 includes, but is not limited to, a single-path server, a multi-path server, and a distributed server.
In some embodiments, the failure morphology analysis system of the die provided by the embodiments of the disclosure may be performed by the server 102, by the terminal 101, or by both the server 102 and the terminal 101. For example, in some embodiments, the user sends an access request to the server 102 through a client in the terminal 101; after receiving the access request, the server 102 generates a task item corresponding to the terminal 101, and automatically distributes the task item to an online server or an offline server according to the type of the generated task item.
The client (or referred to as a client) refers to a program corresponding to the server 102, and provides local services for clients. Except for some applications that only run locally, which are typically installed on the terminal 101, need to run in conjunction with the server 102. More commonly used clients include web browsers such as those used by the world wide web, APP (Application) running in the terminal 101 described above, and the like.
The terminal 102 may provide a display Interface, which may be called a User Interface (UI) for short, and is a medium for interaction and information exchange between the failure morphology analysis system of the die and the User, and it implements conversion between an internal form of information and a human acceptable form, so that the User can conveniently and effectively operate the hardware to achieve bidirectional interaction.
Referring to fig. 2, fig. 2 is a schematic architecture diagram of a failure morphology analysis system of a die according to an embodiment of the disclosure. In one possible embodiment, the failure morphology analysis system of the die includes:
the graphic drawing module 201 is configured to obtain repair data of the target wafer from the database, generate a wafer map corresponding to the target wafer in the display interface, and determine a die structure diagram corresponding to each die in the wafer map.
In some embodiments, the repair data of the target Wafer may be stored in advance in a database, and when the failure morphology analysis is performed on the die in the target Wafer, the repair data of the target Wafer is read from the database, and based on the read repair data of the target Wafer, a corresponding Wafer Map (Wafer Map) of the target Wafer is drawn, and then the Wafer Map is displayed in the display interface.
In some embodiments, a wafer map corresponding to the target wafer may be drawn based on the repair data of the target wafer and in combination with the shape of the target wafer, and the drawn wafer map may be displayed in the display interface.
The wafer map is made of dies, the dies are required to be regularly arranged in two dimensions on the wafer in the process of packaging and testing the wafer, each die has a coordinate (which row and column of the wafer map is located), and the testing procedure can accurately position different dies according to the coordinate and the spacing (the spacing between rows and the spacing between columns).
In some embodiments, after a wafer map corresponding to a target wafer is drawn, a die structure map of each die in the wafer map is drawn.
The processing module 202 is configured to, when receiving a selection operation triggered by a user in the wafer map, obtain repair information corresponding to a currently selected target die from repair data stored in a database, and add the repair information corresponding to the target die to a die structure map corresponding to the target die in a preset manner.
In some embodiments, when a user needs to analyze the failure mode of any die in the wafer map, the die may be selected first in the wafer map displayed in the display interface.
When receiving a selection operation triggered by the user in the wafer map, the processing module 202 obtains repair information corresponding to the currently selected target die from the repair data stored in the database, and adds the repair information corresponding to the target die to the die structure map corresponding to the target die in a preset manner.
Optionally, the repair information corresponding to the target die includes the number of failed bits (hereinafter referred to as failed memory cells) in the target die.
In one possible implementation, the display mode of the repaired word line or bit line in the grain structure diagram corresponding to the target grain can be adjusted according to the number of the failed memory cells in the target grain, wherein when different numbers of failed memory cells exist in the repaired word line or bit line, the corresponding display modes in the display interface are different.
And the display module 203 is configured to display the target grain structure diagram after the target grain adjustment in the display interface.
It can be understood that, because the different display modes of each repaired word line or bit line correspond to the number of the failed memory cells in the target grain structure diagram after the target grain is adjusted, the user can intuitively understand the repair information of the target grain by observing the display modes of each word line or bit line in the target grain structure diagram.
According to the failure morphological analysis system for the crystal grains, provided by the embodiment of the disclosure, the crystal grain structure diagram of each crystal grain in the wafer diagram is drawn, and the repair information corresponding to the crystal grain is added in the crystal grain structure diagram corresponding to the crystal grain, so that the repair information of the crystal grain can be intuitively displayed in the crystal grain structure diagram in a graphical mode, a tester is helped to quickly locate the abnormality of each crystal grain, and the test efficiency is improved.
In one possible implementation, referring to fig. 3, fig. 3 is another architecture diagram of a failure morphology analysis system of a die according to an embodiment of the disclosure. In one possible embodiment, the failure morphology analysis system of the die further includes:
the data processing module 301 is configured to obtain repair data of the target wafer, convert the repair data into structured data, and store the structured data in a database.
In some embodiments, the data processing module 301 may be utilized to load the original repair data of the target wafer, which is typically unstructured data. The repair data may be converted into structured data by the data processing module 301 for facilitating subsequent correlation processing.
The unstructured data may be understood as data which has irregular or incomplete data structure, no predefined data model and is inconvenient to be represented by a two-dimensional logic table of a database. Including office documents in all formats, text, pictures, extensible markup language (Extensible Markup Language, XML), hypertext markup language (Hyper Text Markup Language, HTML), various types of reports, image and audio/video information, and the like.
The above structured data, also referred to as row data, is data logically expressed and implemented by a two-dimensional table structure, strictly following the data format and length specifications.
In some embodiments, the data processing module 301 converts the repair data of the target wafer into the structured data and saves the converted repair data to the database.
Optionally, a relational database may be used to store and manage the repair data after the target wafer conversion.
Wherein a relational database employs a relational model to organize data, which stores data in rows and columns for ease of user understanding, the series of rows and columns of the relational database are referred to as tables, and a set of tables forms the database. The user may retrieve the data in the database by querying.
In the embodiment of the disclosure, the data processing efficiency of the failure morphological analysis system of the crystal grains can be effectively improved by converting the repair data of the target wafer into the structured data; in addition, the converted repair data is stored in the database, so that the converted repair data can be made to be persistent, the time consumption caused by repeated analysis is saved, and meanwhile, the query function and the quick search can be supported.
In some embodiments, when the graph drawing module 201 draws a wafer graph corresponding to the target wafer, the repaired die and the unrepaired die in the target wafer may be determined according to the repair data of the target wafer; and then generating a wafer map corresponding to the target wafer in the display interface, wherein the repaired crystal grains and the unrepaired crystal grains in the target wafer adopt different display modes in the wafer map.
For a better understanding of the disclosed embodiments, reference is made to fig. 4, which is a wafer diagram provided in the disclosed embodiments.
In fig. 4, repaired die are shown in gray in the wafer map and unrepaired die are shown in white in the wafer map.
For simplicity, fig. 4 omits a portion of the die that is not completely fabricated in the peripheral integrated circuit of the wafer map, and only shows the area where the portion of the die that is completely fabricated in the circuit structure after dicing is located.
In the embodiment of the disclosure, the repaired crystal grains and the unrepaired crystal grains in the target wafer are displayed in the wafer map in different display modes, so that a user can be helped to intuitively know which crystal grains in the target wafer have failure storage units and which crystal grains have no failure storage units, and the user can conveniently and quickly select the crystal grains, thereby improving the test efficiency.
In a possible implementation manner, when the graphic drawing module 201 draws a die structure diagram corresponding to each die in the wafer map, the structural configuration information corresponding to each die in the target wafer may be obtained according to the product information of each die in the target wafer; determining a crystal grain structure diagram corresponding to each crystal grain in a wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer; the grain structure diagram comprises a plurality of memory arrays (banks), each memory array is divided into a plurality of memory blocks (subarray) according to rows and columns, and each memory block comprises a plurality of memory cells (bit cells).
It will be appreciated that the interior of each die may be divided into several memory arrays, for example, for some memory chips it may have 4 memory arrays, 8 memory arrays, etc.
In some embodiments, each storage array includes a plurality of storage blocks, where each storage block is arranged in a matrix, and each storage block includes a plurality of storage units.
In some embodiments, each memory cell includes a capacitor and a transistor, and a memory cell may be considered as a bit by powering up or powering down to indicate a 1 or 0.
The target die comprises a plurality of bit lines and a plurality of word lines, and each bit line and each word line are connected with a plurality of memory cells.
For a better understanding of the embodiments of the present application, referring to fig. 5, fig. 5 is a schematic layout diagram of a memory chip according to an embodiment of the present application.
In some embodiments, the memory chip includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, wherein each memory cell is connected to a corresponding one of the word lines WL and one of the bit lines BL.
In some embodiments, the plurality of bit lines are distributed in rows, and the plurality of bit lines may be divided into 128 bit line groups, each having 8 bit lines therein, the bit lines in each bit line group being designated BL0, BL1, BL2 … … BL7 for convenience of description below.
The plurality of word lines are arranged in columns, and the plurality of word lines may be divided into 128 word line groups, each having 8 word lines therein, and the bit lines in each of the bit line groups are denoted as WL0, WL1, WL2 … … WL7 for convenience of description below.
The plurality of memory cells P11-P88 are distributed in a matrix, wherein the memory cells in the first column are all connected with a word line WL0, the memory cells in the second column are all connected with a word line WL1, and the memory cells in the eighth column are all connected with a word line WL7 by analogy; the memory cells of the first row are all connected to bit line BL0, the memory cells of the second row are all connected to bit line BL1, and so on, the memory cells of the eighth row are all connected to bit line BL7, such that each memory cell is connected to one word line WL and one bit line BL.
In some embodiments, each memory cell is uniquely identified by a row number and a column number. Thus, according to a given memory block number, a target memory block can be found, according to a given row number, a row in which a target memory cell is located can be found, and according to a given column number, a column in which the target memory cell is located can be found, thereby also finding the target memory cell to be accessed.
For a better understanding of the disclosed embodiments, referring to fig. 6, fig. 6 is a diagram of a die structure provided in the disclosed embodiments.
In fig. 6, the die structure diagram corresponding to the target wafer includes 4 memory arrays, namely, memory array 0, memory array 1, memory array 2 and memory array 3; each storage array comprises a plurality of storage blocks, and the storage blocks are arranged in a matrix mode.
For simplicity, some memory cells in the memory array are omitted in fig. 6.
In some embodiments, when drawing the structure diagram corresponding to each die in the wafer map, the graphics drawing module 201 may cluster the structure configuration information corresponding to each die in the target wafer, determine the basic structure diagram corresponding to each type of structure configuration information, and then determine the structure diagram corresponding to each die in the wafer map according to the structure configuration information corresponding to each die in the target wafer and the basic structure diagram corresponding to each type of determined structure configuration information.
It can be appreciated that, in the embodiment of the disclosure, by clustering the structural configuration information corresponding to each die in the target wafer, a fewer basic structure diagram can be utilized to draw a die structure diagram corresponding to each die in the wafer diagram, so that requirements of a drawing process on terminal performance can be reduced, and drawing speed can be improved.
Alternatively, in some embodiments, the grain structure diagram may be drawn based on D3js technology using hypertext markup language (Hyper Text Markup Language, abbreviated HTML), cascading style sheets (Cascading Style Sheets, CSS), scalable vector graphics (Scalable Vector Graphics, SVG), and Canvas drawing techniques, without limitation in the embodiments of the present application.
In some embodiments, the repair data for the target wafer may be a logical address or a physical address in location. Therefore, according to the actual requirements, address analysis can be performed on the repair data by combining the corresponding mapping rules, so as to obtain the repair information corresponding to each crystal grain.
In some embodiments, when the repair information corresponding to the target die is added to the die structure diagram corresponding to the target die, the processing module 202 may adjust the display color of each repaired word line or bit line in the die structure diagram corresponding to the target die according to the number of failed memory cells connected to the repaired word line or bit line indicated in the repair information corresponding to the target die and the corresponding relationship between the preset number of failed memory cells and each display color.
In a possible implementation manner, the corresponding relation between the number of the failure storage units and each display color can be preset. For example, the number of the failed storage units corresponding to green is preset to be 1 time, the number of the failed storage units corresponding to blue is preset to be 2 to 63 times, the number of the failed storage units corresponding to red is preset to be 64 to 2047 times, and the number of the failed storage units corresponding to black is preset to be 2048 times or more.
After determining a grain structure diagram corresponding to each grain in the wafer map, according to the number of the repaired word lines or bit lines connected with the corresponding repair information of the target grain and the corresponding relation between the preset number of the failed memory cells and each display color, adjusting the display color of each repaired word line or bit line in the grain structure diagram corresponding to the target grain.
For a better understanding of the embodiments of the present disclosure, referring to fig. 7, fig. 7 is a schematic diagram of a second die structure provided in the embodiments of the present disclosure.
In fig. 7, black indicates that the number of failed memory cells connected to the repaired bit line is a, and gray indicates that the number of failed memory cells connected to the repaired bit line is b, where a+.b.
It should be noted that, for simplicity, only a portion of the repaired bit lines are shown in fig. 7.
In some embodiments, the processing module 202 may be further configured to, upon receipt of a user-triggered positioning operation, determine a target Row (Row) memory block, and/or a target Column (Column) memory block, selected by the positioning operation in a target grain structure diagram; and according to the number of the repaired word lines or bit lines indicated in the repair information corresponding to the target crystal grains and the corresponding relation between the preset number of the repaired word lines or bit lines and each display color, the display color of each repaired word line or bit line in the target row memory block and/or the target column memory block is adjusted, and the display color is sent to the display module 203 for display.
The failure morphological analysis system of the crystal grain provided by the embodiment of the disclosure can help a tester to quickly locate the repair information of any row and/or column storage block through the locating operation.
In some embodiments, the failure morphology analysis system of the die further includes:
and the control module is used for amplifying or reducing the target grain structure diagram according to the scaling operation when receiving the scaling operation triggered by the user.
In one possible embodiment, when the terminal displays the target grain structure diagram after the target grain adjustment in the display interface, the user may control the target grain structure diagram in the display interface to zoom in or zoom out by inputting a zoom operation.
For a better understanding of the embodiments of the present disclosure, reference is made to fig. 8, which is a scaled schematic of a die structure diagram provided in the embodiments of the present disclosure.
In fig. 8, when a zoom operation of a user is detected, the system determines a region currently selected by the user in the display interface, and then enlarges or reduces the selected region in the display interface according to a zoom scale corresponding to the zoom operation.
Illustratively, in some embodiments, it is assumed that the user can operate the target grain structure diagram displayed in the above-described display interface through a mouse and a keyboard, and that the "Ctrl" key in the keyboard is a zoom operation control key. When the terminal detects that a user presses a Ctrl key in the keyboard, the position of a cursor of the mouse in the display interface is determined, and then the crystal grain structure diagram displayed in the display interface is enlarged or reduced by taking the position of the cursor as the center according to the rotation direction and the rotation angle of a roller of the mouse.
According to the failure morphological analysis system for the crystal grains, provided by the embodiment of the disclosure, through the scaling operation, the corresponding repair information of each crystal grain can be presented to a user in a more visual mode, so that the user can be helped to observe the repair condition of each crystal grain on the whole, and the user can be helped to observe the repair condition of each crystal grain on the detail.
In some embodiments, the failure morphology analysis system of the die further includes:
and the screening module is used for determining the type of the detection result selected by the screening operation in the target grain structure diagram when receiving the screening operation triggered by the user, and adjusting the target grain structure diagram according to the type of the detection result selected by the screening operation in the target grain structure diagram.
In one possible implementation manner, each detection result type of the target grain structure diagram and a check box corresponding to each detection result type may be displayed in the display interface, and when a user needs to display one or more detection result types in the target grain structure diagram, the corresponding detection result types may be checked.
In one possible implementation, the types of detection results may be distinguished according to numbers, letters, symbols, etc., and different types of detection results may correspond to different chip qualities.
According to the failure morphological analysis system for the crystal grains, provided by the embodiment of the disclosure, the crystal grain structure diagram of each crystal grain in the wafer diagram is drawn, and the repair information corresponding to the crystal grain is added in the crystal grain structure diagram corresponding to the crystal grain, so that the repair information of the crystal grain can be intuitively displayed in the crystal grain structure diagram in a graphical mode, meanwhile, the crystal grain structure diagram also supports screening operation, scaling operation, positioning operation and the like, so that a tester can be helped to quickly locate the abnormality of each crystal grain, and the test efficiency is improved.
Based on the descriptions in the above embodiments, a method for analyzing failure morphology of a die is also provided in the embodiments of the present disclosure. Referring to fig. 9, fig. 9 is a flow chart of a method for analyzing failure morphology of a die according to an embodiment of the disclosure, where the method for analyzing failure morphology of a die includes:
s901, obtaining repair data of a target wafer from a database, generating a wafer map corresponding to the target wafer in a display interface, and determining a grain structure diagram corresponding to each grain in the wafer map.
S902, when receiving a selection operation triggered by a user in a wafer map, acquiring repair information corresponding to a currently selected target crystal grain from repair data stored in a database, and adding the repair information corresponding to the target crystal grain in a crystal grain structure diagram corresponding to the target crystal grain in a preset mode.
S903, displaying a target crystal grain structure diagram after target crystal grain adjustment in a display interface.
According to the failure morphological analysis method for the crystal grains, provided by the embodiment of the disclosure, the wafer diagram and the crystal grain structure diagram of each crystal grain in the wafer diagram are drawn, and the repair information corresponding to the crystal grain is added into the crystal grain structure diagram corresponding to the crystal grain, so that the repair information of the crystal grain can be intuitively displayed in the crystal grain structure diagram in a graphical mode, a tester is helped to quickly locate the abnormality of each crystal grain, and the test efficiency is improved.
In a possible implementation manner, the obtaining the repair data of the target wafer from the database, and generating the wafer map corresponding to the target wafer in the display interface, includes:
determining repaired grains and unrepaired grains in the target wafer according to the repair data of the target wafer;
and generating a wafer map corresponding to the target wafer in a display interface, wherein the repaired crystal grains and the unrepaired crystal grains in the target wafer adopt different display modes in the wafer map.
In a possible implementation manner, the determining a grain structure diagram corresponding to each grain in the wafer map includes:
Acquiring structure configuration information corresponding to each crystal grain in the target wafer according to the product information of each crystal grain in the target wafer;
determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer; the grain structure diagram comprises a plurality of storage arrays, each storage array is divided into a plurality of storage blocks according to rows and columns, and each storage block comprises a plurality of storage units.
In a possible implementation manner, the determining, according to the structural configuration information corresponding to each die in the target wafer, a die structure diagram corresponding to each die in the wafer map includes:
clustering the structure configuration information corresponding to each crystal grain in the target wafer, and determining a basic structure diagram corresponding to each type of structure configuration information;
and determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer and the determined basic structure diagram corresponding to each type of structure configuration information.
In a possible implementation manner, the adding the repair information corresponding to the target die to the die structure diagram corresponding to the target die in a preset manner includes:
According to the number of the repaired word lines or bit lines connected with the repair information corresponding to the target crystal grains and the corresponding relation between the preset number of the repaired word lines or bit lines and each display color, the display color of the repaired word lines or bit lines in the crystal grain structure diagram corresponding to the target crystal grains is adjusted;
the target die comprises a plurality of bit lines and a plurality of word lines, and each bit line and each word line are connected with a plurality of memory cells.
In a possible implementation manner, the adding the repair information corresponding to the target die to the die structure diagram corresponding to the target die in a preset manner includes:
when a positioning operation triggered by a user is received, determining a target row storage block and/or a target column storage block selected by the positioning operation in the target grain structure diagram;
and adjusting the display color of the repaired word line or bit line in the target row memory block according to the number of the repaired word line or bit line contained in the repair information corresponding to the target crystal grain and the corresponding relation between the preset number of the repaired word line or bit line and each display color.
In a possible implementation manner, after the displaying the target grain structure diagram after the target grain adjustment in the display interface, the method further includes:
when a scaling operation triggered by a user is received, the target grain structure diagram is enlarged or reduced according to the scaling operation;
when a screening operation triggered by a user is received, determining the type of a detection result selected by the screening operation in the target grain structure diagram, and adjusting the target grain structure diagram according to the type of the detection result selected by the screening operation in the target grain structure diagram.
It should be noted that, each step in the failure morphology analysis method of the die described in the embodiments of the present disclosure is consistent with the content executed by each module in the failure morphology analysis system of the die described in the above embodiments, and the specific execution content may refer to the relevant content in the above embodiments, which is not described herein.
Further, based on what is described in the foregoing embodiments, there is also provided in an embodiment of the disclosure an electronic device including at least one processor and a memory; wherein the memory stores computer-executable instructions; the at least one processor executes the computer-executable instructions stored in the memory to implement the steps in the failure morphology analysis method of the die as described in the above embodiment, which is not described herein.
For a better understanding of the embodiments of the present disclosure, referring to fig. 10, fig. 10 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present disclosure.
As shown in fig. 10, the electronic apparatus 100 of the present embodiment includes: a processor 1001 and a memory 1002; wherein:
memory 1002 for storing computer-executable instructions;
the processor 1001 is configured to execute computer-executable instructions stored in the memory to implement each step in the failure morphology analysis method of the die described in the above embodiment, which is not described herein.
Alternatively, the memory 1002 may be separate or integrated with the processor 1001.
When the memory 1002 is provided separately, the device further comprises a bus 1003 for connecting said memory 1002 and the processor 1001.
Further, based on the descriptions in the foregoing embodiments, a computer-readable storage medium is further provided in the embodiments of the present disclosure, where computer-executable instructions are stored in the computer-readable storage medium, and when the processor executes the computer-executable instructions, each step in the failure morphology analysis method of the die described in the foregoing embodiments is implemented, which is not described herein again.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present disclosure may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The integrated units of the modules can be realized in a form of hardware or a form of hardware and software functional units.
The integrated modules, which are implemented in the form of software functional modules, may be stored in a computer readable storage medium. The software functional module is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some of the steps of the methods according to the embodiments of the disclosure.
It should be understood that the above processor may be a central processing unit (english: central Processing Unit, abbreviated as CPU), or may be other general purpose processors, digital signal processors (english: digital Signal Processor, abbreviated as DSP), application specific integrated circuits (english: application Specific Integrated Circuit, abbreviated as ASIC), or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method described in connection with the disclosure may be embodied directly in a hardware processor, or in a combination of hardware and software modules within a processor.
The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile memory NVM, such as at least one magnetic disk memory, and may also be a U-disk, a removable hard disk, a read-only memory, a magnetic disk or optical disk, etc.
The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (Peripheral Component, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present disclosure are not limited to only one bus or to one type of bus.
The storage medium may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC for short). It is also possible that the processor and the storage medium reside as discrete components in an electronic device or a master device.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (18)

1. A failure morphology analysis system of a die, comprising:
the graphic drawing module is used for acquiring repair data of a target wafer from the database, generating a wafer map corresponding to the target wafer in the display interface, and determining a grain structure diagram corresponding to each grain in the wafer map;
The processing module is used for acquiring the repair information corresponding to the currently selected target crystal grain from the repair data stored in the database when receiving the selection operation triggered by the user in the wafer map, and adding the repair information corresponding to the target crystal grain in a crystal grain structure diagram corresponding to the target crystal grain in a preset mode;
and the display module is used for displaying the target grain structure diagram after the target grain is adjusted in the display interface.
2. The system of claim 1, wherein the graphics rendering module is configured to:
determining repaired grains and unrepaired grains in the target wafer according to the repair data of the target wafer;
and generating a wafer map corresponding to the target wafer in a display interface, wherein the repaired crystal grains and the unrepaired crystal grains in the target wafer adopt different display modes in the wafer map.
3. The system of claim 1, wherein the graphics rendering module is configured to:
acquiring structure configuration information corresponding to each crystal grain in the target wafer according to the product information of each crystal grain in the target wafer;
determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer; the grain structure diagram comprises a plurality of storage arrays, each storage array is divided into a plurality of storage blocks according to rows and columns, and each storage block comprises a plurality of storage units.
4. A system according to claim 3, wherein the graphics rendering module is specifically configured to:
clustering the structure configuration information corresponding to each crystal grain in the target wafer, and determining a basic structure diagram corresponding to each type of structure configuration information;
and determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer and the determined basic structure diagram corresponding to each type of structure configuration information.
5. A system according to claim 3, wherein the processing module is configured to:
according to the number of the repaired word lines or bit lines connected with the repair information corresponding to the target crystal grains and the corresponding relation between the preset number of the repaired word lines or bit lines and each display color, the display color of the repaired word lines or bit lines in the crystal grain structure diagram corresponding to the target crystal grains is adjusted;
the target die comprises a plurality of bit lines and a plurality of word lines, and each bit line and each word line are connected with a plurality of memory cells.
6. A system according to claim 3, wherein the processing module is configured to:
When a positioning operation triggered by a user is received, determining a target row storage block and/or a target column storage block selected by the positioning operation in the target grain structure diagram;
and adjusting the display color of the repaired word line or bit line in the target row memory block according to the number of the repaired word line or bit line contained in the repair information corresponding to the target crystal grain and the corresponding relation between the preset number of the repaired word line or bit line and each display color.
7. The system of claim 1 or 5, further comprising:
and the control module is used for amplifying or reducing the target grain structure diagram according to the scaling operation when receiving the scaling operation triggered by the user.
8. The system of claim 1 or 5, further comprising:
the screening module is used for determining the type of the detection result selected by the screening operation in the target grain structure diagram when the screening operation triggered by the user is received;
and adjusting the target grain structure diagram according to the detection result type selected by the screening operation in the target grain structure diagram.
9. The system of claim 1, further comprising:
the data processing module is used for acquiring the repair data of the target wafer, wherein the repair data is unstructured data;
and converting the repair data into structural data and then storing the structural data into the database.
10. A method for failure morphology analysis of a die, the method comprising:
obtaining repair data of a target wafer from a database, generating a wafer map corresponding to the target wafer in a display interface, and determining a grain structure map corresponding to each grain in the wafer map;
when receiving a selection operation triggered by a user in the wafer map, acquiring repair information corresponding to a currently selected target crystal grain from repair data stored in the database, and adding the repair information corresponding to the target crystal grain in a crystal grain structure diagram corresponding to the target crystal grain in a preset mode;
and displaying the target grain structure diagram after the target grain is adjusted in the display interface.
11. The method of claim 10, wherein the obtaining the repair data of the target wafer from the database and generating the wafer map corresponding to the target wafer in the display interface comprise:
Determining repaired grains and unrepaired grains in the target wafer according to the repair data of the target wafer;
and generating a wafer map corresponding to the target wafer in a display interface, wherein the repaired crystal grains and the unrepaired crystal grains in the target wafer adopt different display modes in the wafer map.
12. The method of claim 10, wherein the determining a die structure map for each die in the wafer map comprises:
acquiring structure configuration information corresponding to each crystal grain in the target wafer according to the product information of each crystal grain in the target wafer;
determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer; the grain structure diagram comprises a plurality of storage arrays, each storage array is divided into a plurality of storage blocks according to rows and columns, and each storage block comprises a plurality of storage units.
13. The method of claim 12, wherein determining a die structure map corresponding to each die in the wafer map based on the structural configuration information corresponding to each die in the target wafer comprises:
Clustering the structure configuration information corresponding to each crystal grain in the target wafer, and determining a basic structure diagram corresponding to each type of structure configuration information;
and determining a crystal grain structure diagram corresponding to each crystal grain in the wafer diagram according to the structure configuration information corresponding to each crystal grain in the target wafer and the determined basic structure diagram corresponding to each type of structure configuration information.
14. The method of claim 12, wherein adding the repair information corresponding to the target die to the die structure diagram corresponding to the target die in a preset manner comprises:
according to the number of the repaired word lines or bit lines connected with the repair information corresponding to the target crystal grains and the corresponding relation between the preset number of the repaired word lines or bit lines and each display color, the display color of the repaired word lines or bit lines in the crystal grain structure diagram corresponding to the target crystal grains is adjusted;
the target die comprises a plurality of bit lines and a plurality of word lines, and each bit line and each word line are connected with a plurality of memory cells.
15. The method of claim 12, wherein adding the repair information corresponding to the target die to the die structure diagram corresponding to the target die in a preset manner comprises:
When a positioning operation triggered by a user is received, determining a target row storage block and/or a target column storage block selected by the positioning operation in the target grain structure diagram;
and adjusting the display color of the repaired word line or bit line in the target row memory block according to the number of the repaired word line or bit line contained in the repair information corresponding to the target crystal grain and the corresponding relation between the preset number of the repaired word line or bit line and each display color.
16. The method of claim 10 or 14, further comprising, after the displaying the target grain structure diagram after the target grain adjustment in the display interface:
when a scaling operation triggered by a user is received, the target grain structure diagram is enlarged or reduced according to the scaling operation;
when a screening operation triggered by a user is received, determining a detection result type selected by the screening operation in the target grain structure diagram, and adjusting the target grain structure diagram according to the detection result type selected by the screening operation in the target grain structure diagram.
17. An electronic device, comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the method of failure morphology analysis of a die as recited in any of claims 10-16.
18. A computer readable storage medium having stored therein computer executable instructions which, when executed by a processor, implement the method of failure morphology analysis of a die according to any of claims 10 to 16.
CN202210037601.4A 2022-01-13 2022-01-13 Failure morphology analysis system, method and equipment for crystal grains Pending CN116487364A (en)

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CN202210037601.4A CN116487364A (en) 2022-01-13 2022-01-13 Failure morphology analysis system, method and equipment for crystal grains

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210037601.4A CN116487364A (en) 2022-01-13 2022-01-13 Failure morphology analysis system, method and equipment for crystal grains

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