CN116487361A

CN116487361A - Semiconductor device and method of forming the same

Info

Publication number: CN116487361A
Application number: CN202310321302.8A
Authority: CN
Inventors: 石哲齐; 锺政庭; 林含谕; 温伟源; 廖思雅
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-03-29
Filing date: 2023-03-29
Publication date: 2023-07-25

Abstract

The present invention provides semiconductor devices and methods of forming the same that use high kappa dielectric bonding layers to promote improved thermal conductivity. In at least one example, a device including a first substrate is provided. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. The front side interconnect structure is disposed on the semiconductor device layer, and the bonding layer is disposed on the front side interconnect structure. The second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10W/m-K.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to semiconductor devices and methods of forming the same.

Background

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric, conductive, and semiconductor materials on a semiconductor substrate, and patterning the various material layers using photolithographic techniques to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum component size decreases, additional problems arise that need to be addressed.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a semiconductor device including: a first substrate; a semiconductor device layer in the first substrate, the semiconductor device layer including one or more semiconductor devices; a front side interconnect structure including a front side interconnect structure on a first side of the semiconductor device layer; a backside interconnect structure on a second side of the semiconductor device layer, the second side being opposite the first side; one or more electrical contacts on the backside interconnect structure; and a bonding layer on the front side interconnect structure, the bonding layer having a thermal conductivity greater than 10W/m-K.

According to another aspect of embodiments of the present application, there is provided a method of forming a semiconductor device, comprising: forming a bonding layer on a device wafer, the device wafer comprising a first substrate, a semiconductor device layer on the first substrate, and a front side interconnect structure, the bonding layer having a thermal conductivity greater than 10W/m-K; bonding a second substrate to the bonding layer; forming a thinned first substrate by thinning the first substrate; and forming a backside interconnect structure on a side of the semiconductor device layer opposite the bonding layer.

According to yet another aspect of embodiments of the present application, there is provided a method of forming a semiconductor device, comprising: forming a bonding layer on the device wafer, the bonding layer having a thickness less than 3000nm and a thermal conductivity greater than 10W/m-K; forming a second dielectric layer on the carrier substrate, the second dielectric layer being formed of a different material than the bonding layer; bonding the bonding layer of the device wafer to the second dielectric layer of the carrier substrate; forming a thinned back side by thinning the back side of the device wafer; forming a backside interconnect structure on the thinned backside; and forming one or more electrical contacts on the backside interconnect structure.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

Fig. 1B is a cross-sectional view illustrating a region of the semiconductor device of fig. 1A, in accordance with various embodiments.

Fig. 2A-2D are cross-sectional views illustrating methods of fabricating the semiconductor device shown in fig. 1, according to some embodiments.

Fig. 3 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

Fig. 4A-4D illustrate a method of fabricating the semiconductor device of fig. 3, according to some embodiments.

Fig. 5 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

Fig. 6A-6D illustrate a method of fabricating the semiconductor device of fig. 5, according to some embodiments.

Fig. 7 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

Fig. 8A-8E illustrate methods of fabricating the semiconductor device of fig. 7, according to some embodiments.

Fig. 9 is a diagram illustrating a trans-planar kappa of an AlN layer in accordance with various embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

Embodiments provided herein include semiconductor devices and methods that facilitate improving thermal conductivity, thereby reducing or preventing thermal degradation of the semiconductor devices. Thermal conductivity is improved due to the presence of the high kappa dielectric bonding layer used in the processing of the device (e.g., bonding the device wafer to the carrier wafer). The high kappa dielectric bonding layer may have a thermal conductivity that is greater than the thermal conductivity of silicon dioxide, thereby increasing the thermal conductivity of the bonding layer. In some embodiments, the bonding layer is a high kappa dielectric layer having a thermal conductivity greater than 10W/mK.

Fig. 1A is a cross-sectional view illustrating a semiconductor device 100 according to some embodiments of the present disclosure. Semiconductor device 100 may be any semiconductor device such as, but not limited to, a logic device, a memory device, or any other semiconductor device. As shown in fig. 1A, device 100 includes an optional substrate 102, a bonding layer 104, a backside interconnect structure 106, and a semiconductor device layer 110. In some embodiments, the device 100 may be a semiconductor device package.

The substrate 102 may be any suitable substrate. In some embodiments, the substrate 102 may be a semiconductor wafer. In some embodiments, the substrate 102 may be a single crystal silicon (Si) wafer, an amorphous Si wafer, a gallium arsenide (GaAs) wafer, or any other semiconductor wafer. In some embodiments, the substrate 102 may be a carrier wafer that may be substantially devoid of electrical components and may be used to bond to the device 100 (e.g., to the backside interconnect structure 106 and the semiconductor device layer 110) during processing of the device 100.

Semiconductor device layer 110 includes one or more semiconductor devices. In various embodiments, the semiconductor devices included within semiconductor device layer 110 may be any semiconductor device. In some embodiments, semiconductor device layer 110 includes one or more transistors, which may include any suitable transistor structure, including, for example, finFET, gate-all-around (GAA) transistors, and the like. In some embodiments, the semiconductor device layer 110 includes one or more GAA transistors. In some embodiments, the semiconductor device layer 110 may be a logic layer including one OR more semiconductor devices AND may further include an interconnect structure thereof, the logic layer being configured AND arranged to provide a logic function, such as an AND, OR, XOR, XNOR, OR NOT, OR a storage function, such as a flip-flop OR latch.

In some embodiments, semiconductor device layer 110 may include a memory device, which may be any suitable memory device, such as a Static Random Access Memory (SRAM) device. The memory device may include a plurality of memory cells configured in rows and columns, although other embodiments are not limited to such an arrangement. Each memory cell may include a plurality of transistors (e.g., six) connected between a first voltage source (e.g., VDD) and a second voltage source (e.g., VSS or ground) such that one of the two storage nodes may be occupied by information to be stored while complementary information is stored at the other storage node.

The semiconductor device layer 110 of the semiconductor device 100 may further include various circuits electrically coupled to the semiconductor device layer 110. For example, the semiconductor device layer 110 may include power management circuitry or other circuitry electrically coupled to one or more semiconductor devices of the semiconductor device layer 110. The power management circuitry may include any suitable circuitry for controlling or otherwise managing communication signals (e.g., input power signals) to or from semiconductor devices of semiconductor device layer 110. In some embodiments, the power management circuitry may include power gating circuitry that may reduce power consumption, for example, by cutting off current to unused circuit blocks (e.g., blocks or electrical components in the semiconductor device layer 110), thereby reducing standby power or leakage power. In some embodiments, semiconductor device layer 110 includes one or more switching devices, such as a plurality of transistors, for transmitting electrical signals to or receiving electrical signals from semiconductor devices in semiconductor device layer 11, e.g., turning on and off circuitry (e.g., transistors, etc.) of the semiconductor device layer.

The backside interconnect structure 106 is disposed at a backside of the semiconductor device layer 110, e.g., a lower side as shown in fig. 1A. Backside interconnect structure 106 may include any suitable electrical interconnect structure, circuitry, wiring, etc. suitable for transmitting electrical signals to semiconductor device layer 110 or receiving electrical signals from semiconductor device layer 110.

In some embodiments, the backside interconnect structure 106 includes a backside power rail. The backside power rail may be disposed, for example, between a backside power delivery network and backside vias, which may electrically couple the backside power rail to semiconductor devices in the semiconductor device layer 110.

In some embodiments, the backside power rails of the backside interconnect structure 106 may include a plurality of wires or power rails operable to deliver electrical signals (e.g., power signals or voltage signals) to or receive electrical signals from the semiconductor devices in the semiconductor device layer 110. The backside power rail may be formed of any suitable conductive material. In some embodiments, the backside power rail is formed of or includes metal.

In some embodiments, the backside interconnect structure 106 further includes a front side interconnect structure that may be electrically coupled to each other through one or more conductive vias. The metallization layer extends between the electrical contacts 124 at the back side of the device 100 and the semiconductor device layer 110. In some embodiments, the metallization layer electrically connects the electrical contacts 124 to one or more semiconductor devices in the semiconductor device layer 110. The metallization layers may be electrically coupled to each other by one or more conductive vias.

The backside interconnect structure 106 may also include an insulating layer that covers various components (e.g., conductive components) of the backside interconnect structure 106. For example, an insulating layer may be included that covers or substantially covers the backside power rails, backside vias, and metallization layers of the backside interconnect structure 106. The insulating layer may be formed of any suitable insulating material, and in some embodiments, electrically insulates or isolates the various electrical components within the backside interconnect structure 106 from each other. In some embodiments, the insulating layer may be formed of a dielectric material, which may include silicon dioxide (SiO ₂ ) One or more of SiON, siOC, and SiOCN, or any other suitable insulating material. An insulating layer may be disposed on the semiconductor device layer 110 and in contact with the semiconductor device layer 110.

In some embodiments, the backside interconnect structure 106 has a thickness of less than 10 μm. In some embodiments, the backside interconnect structure 106 has a thickness of less than 5 μm, and in some embodiments, the thickness of the backside interconnect structure 106 is in the range of 0.1 μm to 5 μm.

In some embodiments, the semiconductor device 100 includes a front side interconnect structure 108. In some embodiments, the front-side interconnect structure 108 has an overall thickness (e.g., between the semiconductor device layer 110 and the bonding layer 104) of less than 10 μm. In some embodiments, the front side interconnect structure 108 has a total thickness of less than 5 μm, and in some embodiments, the total thickness of the front side interconnect structure 108 is in the range of 0.1 μm to 5 μm. The front-side interconnect structures 108 may each include a dielectric layer with metallization features (e.g., vias, wires, traces, etc.) embedded therein. The dielectric layer may be a low-k dielectric layer such as SiO ₂ SiON, siOC, siOCN, etc. The metallized component may be or include copper, tungsten, ruthenium, molybdenum, titanium nitride, other metals, alloys thereof, multi-layer combinations thereof, and the like. The front-side interconnect structure 108 may be referred to as a front-side metallization layer 108 or a front-end-of-line (BEOL) structure 108.

The bonding layer 104 bonds the substrate 102 to the semiconductor device layer 110. In some embodiments, the bonding layer 104 bonds the substrate 102 to the front side interconnect structure 108. The bonding layer 104 may be formed of any material to bond the substrate 102 and the front side interconnect structure 108 or the semiconductor device layer 110 as appropriate.

In some embodiments, the bonding layer 104 is a high kappa dielectric layer formed of a high kappa dielectric material. It should be understood that "high kappa" means that the thermal conductivity (kappa) of the material of the bonding layer 104 is higher than the thermal conductivity or selected thermal conductivity level of the selected material. In some embodiments, the bonding layer 104 is a high kappa dielectric layer having a thermal conductivity greater than that of silicon dioxide. In some embodiments, the bonding layer 104 is a high kappa dielectric layer having a thermal conductivity greater than 10W/mK. In some embodiments, the bonding layer 104 is a high kappa dielectric layer comprising one or more of a nitride, a metal oxide, or a carbide. In some embodiments, the bonding layer 104 includes AlN, BN, Y ₂ O ₃ 、YAG、Al ₂ O ₃ One or more of BeO, siC, graphene, or any other suitable high kappa material.

In various embodiments, the high kappa material of the bonding layer 104 may be arranged in any suitable crystal structure, including, for example, cubic, hexagonal, tetragonal, orthorhombic, monoclinic, or triclinic crystals. Furthermore, the high kappa material of the bonding layer 104 may have any suitable crystallinity, including, for example, monocrystalline, polycrystalline, or amorphous.

For example, the use of a high kappa dielectric material for the bonding layer 104 helps to improve the thermal performance of the semiconductor device 100 by preventing or reducing performance degradation of the semiconductor device (e.g., within the semiconductor device layer 110) due to heat. The high kappa dielectric material in the bonding layer 104 may improve heat dissipation, which may protect the semiconductor device layer 110 from thermal degradation, and thus may improve performance and reliability of the chip or semiconductor device 100.

In some embodiments, a dielectric layer 112 may be disposed between the bonding layer 104 and the substrate 102. Dielectric layer 112 may be formed of any suitable dielectric material and may include SiO in some embodiments ₂ One or more of SiN, siON, siCN, siOCN. In some embodiments, dielectric layer 112 may be a silicon dioxide layer. However, the embodiments provided herein are not limited thereto, and any other suitable material for the dielectric layer 112 may be used in various embodiments.

Because the high kappa bond layer 104 is provided on the front side of the semiconductor device 100 for heat dissipation, in some embodiments, there is no need to have external electrical contacts on the front side of the device 100 to transmit signals. In this way, the front side of the semiconductor device 100 may be free of electrical contacts, such as solder bumps, C4 connectors, and the like.

Fig. 1B is a detailed cross-sectional view of region 10 of the chip or semiconductor device 100 of fig. 1A, in accordance with various embodiments.

The region 10 of the chip or semiconductor device 100 includes nanostructure devices 20A, 20B, 20C. In some embodiments, nanostructure devices 20A-20C may include at least N-type FETs (NFETs), P-type FETs, or both.

Referring to fig. 1B, nanostructure devices 20A-20C may be formed on and/or in a substrate, which may be completely or partially removed, wherein fig. 1B illustrates the structure with the substrate completely removed, and thus the substrate is not illustrated. The nanostructure devices 20A-20C generally include gate structures 200A, 200B, 200C (alternately referred to as "nanostructures") that span and/or wrap around the semiconductor channels 22A1-22C3, which may be separated by isolation structures (e.g., shallow trench isolation or "STI," not shown in the view shown in fig. 1B). The channels are labeled "22AX" through "22CX," where "X" is an integer from 1 to 3 corresponding to three nanostructure devices 20A-20C, respectively. The channels 22A1-22C3 are adjacent to corresponding source/drain regions 82. Each gate structure 200A-200C controls the flow of current between the source/drain regions 82 through the channels 22A1-22C 3. Trenches 22A1-22C3 are optionally located over fins (not shown in fig. 1B). In some embodiments, for example, when the fin is removed during formation of the backside interconnect structure 106, the fin is not present. Depending on the context, the source/drain regions may be referred to as source or drain individually or collectively.

The channels 22A1-22C3 comprise a semiconductor material, for example silicon or a silicon compound, such as silicon germanium or the like. In some embodiments, the fin structure comprises silicon. The channels 22A1-22C3 are nanostructures (e.g., having dimensions in the range of a few nanometers) and may also each have an elongated shape and extend in the X-direction. In some embodiments, the channels 22A1-22C3 each have a Nanowire (NW) shape, a nano-sheet (NS) shape, a Nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A1-22C3 may be rectangular, circular, square, circular, oval, hexagonal, or a combination thereof.

In some embodiments, the lengths of the channels 22A1-22C3 (e.g., measured in the X-direction) may be different from one another, for example, due to the gradual taper during the fin etching process. In some embodiments, the length of channel 22A1 may be less than the length of channel 22B1, and the length of channel 22B1 may be less than the length of channel 22C 1. Each of the channels 22A1-22C3 may not have a uniform thickness, for example, due to a channel trimming process for expanding the spacing between the channels 22Al-22C3 (e.g., measured in the Z-direction) to increase the gate structure manufacturing process window. For example, the middle portion of each channel 22A1-22C3 may be thinner than the two ends of each channel 22Al-22C 3. Such shapes may be collectively referred to as "dog bone" shapes, as shown in fig. 1B.

In some embodiments, the spacing between channels 22A1-22C3 (e.g., the spacing between channel 22B2 and channel 22A2 or channel 22C 2) is in a range between about 8 nanometers (nm) and about 12 nm. In some embodiments, the thickness (e.g., measured in the Z direction) of each of the channels 22A1-22C3 is in a range between about 5nm and about 8nm. In some embodiments, the width (e.g., measured in the Y direction orthogonal to the X-Z plane) of each of the channels 22A1-22C3 is at least about 8nm.

Gate structures 200A-200C are disposed over and between channels 22A1-22C3, respectively. In some embodiments, gate structures 200A-200C are disposed over and between channels 22A1-22C3, with channels 22A1-22C3 being silicon channels for N-type devices or germanium-silicon channels for P-type devices. In some embodiments, the gate structures 200A-200C include an Interface Layer (IL) 210, one or more gate dielectric layers 610, one or more work function tuning layers (not shown), and a metal core layer 290, which are shown and described in more detail with reference to fig. 1B.

The source/drain regions 82 may include SiB, siGe, siGeB and may include dopants, such as Ge, sb, B, and the like. In some embodiments, the source/drain regions 82 comprise silicon phosphorus (SiP). In some embodiments, the width of the source/drain regions 82 (e.g., on the Y-axis) is in the range of about 0.5nm to about 100 nm. In some embodiments, the height (e.g., in the Z-axis direction) of the source/drain regions 82 is in the range of about 0.1nm to about 100 nm. The height of the source/drain regions 82 may be measured from the bottommost surface of the lowermost channels 22C1, 22C2, 22C3 to the top of the source/drain regions 82.

Nanostructure devices 20A-20C may include gate spacers 41 and internal spacers 74 disposed on sidewalls of gate dielectric layer 610 and IL 210. An inner spacer 74 is also disposed between channels 22A1-22C 3. The gate spacers 41 and the inner spacers 74 may comprise a dielectric material, for example a low-k material such as SiOCN, siON, siN, siCN or SiOC. In some embodiments, one or more additional spacer layers abut gate spacers 41. In some embodiments, the thickness of the inner spacer 74 (e.g., in the X-axis direction) is in the range of about 3nm to about 10 nm. In some embodiments, the thickness of the gate spacer 41 (e.g., in the X-axis direction) is in the range of about 3nm to about 10 nm. Nanostructure devices 20A-20C may include a bottom isolation structure 84 located under source/drain region 82. In some embodiments, the bottom isolation structure 84 comprises a material such as SiOCN, siON, siN, siCN or SiOC, and has a thickness (e.g., in the Z-axis direction) of about 3nm to about 10 nm. The bottom isolation structure 84 is optional and is not present in some embodiments.

The nanostructure devices 20A-20C may include source/drain contacts 120 over one or more source/drain regions 82. The source/drain contacts 120 may include a first liner layer, a second liner layer, and a core layer, not specifically shown in fig. 1B. The first liner layer may be a dielectric layer, such as SiN, siCN, siOCN, siOC. In some embodiments, the thickness of the first liner layer is in the range of about 3nm to about 10 nm. The core layer may comprise a conductive material such as tungsten, ruthenium, cobalt, copper, molybdenum, and the like. The second liner layer is located between the first liner layer and the core layer. In some embodiments, the aspect ratio (e.g., height/width) of the source/drain contacts 120 is in the range of about 1 to about 8. When the aspect ratio exceeds about 8, voids that occur when forming the source/drain contacts 120 may not be completely removed and may be present in the source/drain contacts 120.

Silicide layer 118 may also be formed between source/drain regions 82 and source/drain contacts 120 to reduce the source/drain contact resistance. In some embodiments, silicide layer 118 is or includes one or more of nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. For example, the silicide layer 118 may be TiSi, tiNiSi, niSi, WSi, coSi, moSi, ruSi or the like. In some embodiments, the thickness (in the Z direction) of the silicide layer 118 is in the range of about 0.5nm to about 10nm, for example in the range of about 3nm to about 10 nm. In some embodiments, the height of the source/drain contacts 120 may be in the range of about 1nm to about 100nm, such as about 10nm to about 100nm.

Nanostructure devices 20A-20C include an interlayer dielectric (ILD) 130 and an etch stop layer 131.ILD 130 provides electrical isolation between the various components of nanostructure devices 20A-20C described above, for example, between gate structures 200A-200C and between source/drain contacts 120 therebetween. The etch stop layer 131 may be formed prior to forming the ILD130 and may be laterally between the ILD130 and the gate spacer 41 and vertically between the ILD130 and the source/drain region 82. In some embodiments, the etch stop layer 131 is or includes SiN, siCN, siC, siOC, siOCN, hfO ₂ 、ZrO ₂ 、ZrAlO _x 、HfAlO _x ，HfSiO _x 、Al ₂ O ₃ Or other suitable material. In some embodiments, the thickness of the etch stop layer 131 is in the range of about 1nm to about 5 nm.

An optional gate cap conductive layer 204, a second ESL 141, a second ILD 140, a third ESL 151, and a third ILD 150 are capped on each gate structure 200A-200C. The gate capping conductive layer 204 may reduce the contact resistance between the gate via 184 and the core layer 290 of the gate structure 200A-200C (e.g., gate structure 200C in fig. 1B). In some embodiments, the gate-covering conductive layer 204 comprises a metal, such as tungsten, molybdenum, cobalt, ruthenium, and the like. The gate cap conductive layer 204 may comprise the same material as the core layer of the source/drain contacts 120. The gate cap conductive layer 204 may comprise the same material as the gate via 184. In some embodiments, the thickness of the thickest portion of the gate-covering conductive layer 204 may be in the range of about 1nm to about 10 nm. In some embodiments, the gate-covering conductive layer 204 is part of the gate structures 200A-200C.

The second ESL 141 and the third ESL 151 may be similar in many respects to ESL 131. In some embodiments, third ESL 151 is thicker than ESL 131, second ESL 141, or both.

The second ILD 140 and the third ILD 150 may be similar in many respects to ILD 130. In some embodiments, the second ILD 140 is thicker than the ILD 130, the third ILD 150, or both.

Conductive feature 280 may be a metal line or trace, with conductive feature 280 being electrically connected to one or more of gate structures 200A-200C through respective gate vias 184 and to one or more of source/drain contacts 120 through respective source/drain vias 183. The conductive member 280 may be embedded in the dielectric layer 160. The conductive feature 280 may be or include the same or different material as the source/drain contact 120 (e.g., core layer), the source/drain via 183, the gate via 184, the gate cap conductive layer 204, or any combination thereof. The thickness of the conductive member 280 may be in the range of about 5nm to about 50 nm. The dielectric layer 160 may be or include SiCN, siO, siCON, siN, siC or other low-k dielectric material (e.g., k < 3.9). The height of the source/drain vias 183 may be in the range of about 3nm to about 30 nm. The height of the gate via 184 may be in the range of about 10nm to about 70 nm. In some embodiments, the conductive feature 280 is a first metallization layer of the front-side interconnect structure 108, and additional metallization layers are vertically stacked on the first metal layer to provide electrical interconnection between one or more of the nanostructure devices 20A-20C and other nanostructure devices of the chip or semiconductor device 100.

As shown in fig. 1B, one or more source/drain vias 183 and one or more gate vias 184 may be landed on source/drain contacts 120 and gate structures 200A-200C, respectively. In the example shown in fig. 1B, source/drain vias 183 land on the source/drain contacts 120 between the nanostructure devices 20A, 20B. Gate via 184 is landed on gate structure 200C (e.g., on gate-capping conductive layer 204 on gate structure 200). The source/drain via 183 may be or include the same material as the source/drain contact 120. For example, the source/drain vias 183 and source/drain contacts 120 may be or include one or more of W, ru, co, cu, ti, tiN, ta, taN, mo, ni, alloys thereof, and the like. In the case of an alloy, the source/drain via 183 and the source/drain contact 120 may be or include an alloy having substantially the same elemental composition and substantially the same proportion of elemental composition. By using substantially the same material for the source/drain contacts 120 and the source/drain vias 183, the contact resistance between the source/source contacts 120 and the source/drain vias 183 is reduced, which enhances the circuit performance of a device (e.g., chip or semiconductor device 100) using the described configuration. In some embodiments, the width of the upper surface of the source/drain via 183 (e.g., in the X direction) is in the range of about 5nm to about 40 nm. The sidewalls of the source/drain vias 183 may be substantially vertical (e.g., perpendicular to the major surface of the semiconductor device layer 110) or may be tapered, as shown in fig. 1B.

The gate via 184 may include two or more of a glue layer, a metal liner layer, and a metal core layer. The gate via 184 extends from the upper surface of the third ILD150, through the third ESL 151 below the third ILD150, through the second ILD140 and the second ESL141, to the upper surface of the gate cap conductive layer 204. Sidewalls of the gate via 184 are in contact with one or more of the second and third ESLs 141 and 151 and the second and third ILDs 140 and 150. The lower surface of the gate via 184 is in contact with the gate cap conductive layer 204.

In some embodiments, the glue layer is or includes one or more of TiN, taN, ru or other suitable materials. A glue layer may be deposited over (e.g., in direct physical contact with) the gate-capping conductive layer 204 over the gate structure 200C. In some embodiments, the thickness of the glue layer may be in the range of about 5 angstroms to about 50 angstroms. In some embodiments, no glue layer is present.

In some embodiments, the metallic liner layer is or includes one or more of W, ru, al, mo, ti, tiN, cu, co or other suitable materials. In some embodiments, the thickness of the metallic liner layer may be in the range of about 2nm to about 20 nm. In some embodiments, the metallic liner layer is in direct contact with the gate cap conductive layer 204. In some embodiments where a glue layer is present, the metallic liner layer contacts the gate cap conductive layer 204 through an opening in the glue layer.

In some embodiments, the metallic core layer has a different composition than the metallic liner layer and is or includes one or more of W, ru, al, mo, ti, tiN, cu, co or other suitable material. In some embodiments, the width of the upper surface of the metal core layer (e.g., in the X-direction) is in the range of about 5nm to about 40 nm. The metallic core layer may be adjacent laterally and underneath the metallic liner layer. In some embodiments where a glue layer, a metallic liner layer, or both are present, the metallic liner layer is in contact with the gate cap conductive layer 204 through an opening in the glue layer, an opening in the metallic liner layer, or both.

In some embodiments, the semiconductor device layer 110 includes layers and components of the structure between the backside interconnect structure 106 and the front side interconnect structure 108, as shown in brackets in fig. 1B. For example, the layers and components may include the channels 22A1-22C3, the gate structures 200A-200C, the source/drain regions 82, the various spacers 41, 74, 84, the source/drain contacts 120, the source vias 183, the gate vias 184, and the various dielectric layers 130, 131, 140, 141, 150, 151, as well as other layers and components described in the preceding paragraphs.

Fig. 2A-2D illustrate a method of manufacturing the device 100 according to some embodiments.

As shown in fig. 2A, the method includes forming a bonding layer 104 on a semiconductor device structure, which may be referred to as a device wafer 200. The device wafer 200 includes a semiconductor device layer 110 and a frontside interconnect structure 108, which may be the same or substantially the same as previously described herein.

The device wafer 200 also includes a substrate 202. The substrate 202 may be any suitable substrate. In some embodiments, the substrate 202 is a semiconductor substrate, such as a silicon substrate. The substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 202 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, gallium arsenide, indium gallium arsenide, gallium indium phosphide, and/or gallium indium phosphide; or a combination thereof. Other substrates may be used, such as single layer substrates, multi-layer substrates, or gradient substrates. Semiconductor device layer 110 may be formed on substrate 202 and/or in substrate 202.

The front side interconnect structure 108 is formed on the semiconductor device layer 110 and may be the structure shown in fig. 1B and described with reference to fig. 1B.

The bonding layer 104 may be formed by any suitable technique. For example, in some embodiments, the bonding layer 104 is formed by depositing a high kappa dielectric material. In some embodiments, the bonding layer 104 is a high kappa dielectric layer deposited by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced CVD (PECVD), or any suitable deposition technique.

In some embodiments, the bonding layer 104 has a thickness of less than 3000 nm. In some embodiments, the bonding layer 104 has a thickness in the range of 10nm to 3000nm, which may facilitate proper bonding between adjacent structures (e.g., to the front-side interconnect structure 108 and the first dielectric layer 112).

As shown in fig. 2B, the method includes forming a first dielectric layer 112 on a substrate 102, which substrate 102 may be a carrier wafer or a carrier substrate. The first dielectric layer 112 may be formed of any suitable dielectric material and may include SiO in some embodiments ₂ One or more of SiN, siON, siCN or SiOCN. In some embodiments, the first dielectric layer 112 may be a silicon dioxide layer. The first dielectric layer 112 may be formed by any suitable technique, including, for example, by PVD, CVD, ALD or any other suitable deposition technique.

In some embodiments, the first dielectric layer 112 has a thickness of less than 3000 nm. In some embodiments, the thickness of the first dielectric layer 112 is in the range of 10nm to 3000 nm. In some embodiments, the first dielectric layer 112 is an organic material, which may be advantageous in providing improved heat dissipation. In some embodiments, the first dielectric layer 112 is an inorganic material, which may be advantageous for processing at higher temperatures (e.g., greater than about 400 degrees celsius) in subsequent processes.

As shown in fig. 2C, the device wafer 200 is bonded to the carrier substrate 102, for example, to protect the front-side interconnect structure 108 during backside processing of the device wafer 200. The device wafer 200 and the carrier substrate 102 may be bonded to each other by any suitable technique. For example, the first dielectric layer 112 on the carrier substrate 102 may be bonded to the bonding layer 104 formed on the device wafer 200. In some embodiments, the carrier substrate 102 is bonded to the device wafer 200 (e.g., by bonding the first dielectric layer 112 and the bonding layer 104) by an ambient bonding process (e.g., using ambient temperature or pressure process parameters in a bonding tool). In some embodiments, the carrier substrate 102 is bonded to the device wafer 200 by a vacuum bonding process (e.g., in a bonding tool having vacuum pressure). However, embodiments are not so limited, and in various embodiments, the bonding of the carrier substrate 102 to the device wafer 200 may be performed by any suitable bonding process.

As shown in fig. 2D, the semiconductor device 100 is formed by forming a backside interconnect structure 106 on the backside of the device 100. The backside interconnect structure 106 may be the same as or similar to that described with reference to fig. 1B. In some embodiments, the formation of the backside interconnect structure 106 includes forming a plurality of conductive features operable to deliver electrical signals to semiconductor devices in the semiconductor device layer 110 or receive electrical signals from semiconductor devices in the semiconductor device layer 110. For example, the backside interconnect structure 106 may include one or more backside power rails, metallization layers, conductive vias, and the like.

In some embodiments, the formation of the backside interconnect structure 106 includes forming an insulating layer on or around the conductive features of the backside interconnect member 106.

In some embodiments, for example, one or more portions of the substrate 202 may be at least partially removed as part of forming the backside interconnect structure 106. In some embodiments, the backside interconnect structure 106 is formed in a portion of the substrate 202 or at least partially comprises a portion of the substrate 202. For example, in some embodiments, conductive features (e.g., backside power rails, metallization layers, conductive vias, etc.) of the backside interconnect structure 106 may be formed within the substrate 202.

The conductive features of the backside interconnect structure 106 may be formed to extend through the substrate 202 or insulating layer and may contact conductive regions or semiconductor regions of semiconductor devices in the semiconductor device layer 110 (e.g., gate contacts of transistors, source/drain regions of transistors, etc.).

Further, as shown in fig. 2D, device 100 is completed by forming electrical contacts 124. The electrical contacts 124 may be formed by any suitable technique, including by deposition, soldering, placement of solder balls, and the like. The electrical contacts 124 may be formed on or in contact with the metallization layer of the backside interconnect structure 106. In some embodiments, the electrical contacts 124 may include power contacts, input/output contacts, or any other contacts for receiving or providing electrical signals. In various embodiments, any number of electrical contacts may be included in semiconductor device 100 and may be coupled to various conductive features or metallization paths, for example, electrically coupled to semiconductor devices in semiconductor device layer 110.

In some embodiments, the substrate 102 is partially or completely removed after the electrical contacts 124 are formed, such as by grinding, etching, polishing, or other suitable process.

Fig. 3 is a cross-sectional view illustrating a semiconductor device 300 according to some embodiments of the present disclosure. The device 300 shown in fig. 3 is substantially identical to the device 100 shown in fig. 1A; however, the device 300 also includes a second dielectric layer 113.

More specifically, device 300 includes optional substrate 102, first dielectric layer 112, bonding layer 104, second dielectric layer 113, front-side interconnect structure 108, semiconductor device layer 110, back-side interconnect structure 106, and electrical contacts 124.

The substrate 102, the first dielectric layer 112, the bonding layer 104, the front-side interconnect structure 108, the semiconductor device layer 110, the back-side interconnect structure 106, and the electrical contacts 124 of the semiconductor device 300 may be the same or substantially the same as previously described herein with respect to the semiconductor device 100 of fig. 1A.

For example, in some embodiments, the bonding layer 104 is a high kappa layer formed of a high kappa dielectric material or other suitable high kappa material. The high kappa dielectric material may be advantageous in preventing electrical shorting between metal lines of the front side interconnect structure 108. In some embodiments, the bonding layer 104 is a high kappa dielectric layer having a thermal conductivity greater than that of silicon dioxide. In some embodiments, the bonding layer 104 is a high kappa dielectric layer having a thermal conductivity greater than 10W/mK. In some embodiments, the tie layer 10 4 is a high kappa dielectric layer comprising one or more of nitride, metal oxide or carbide. In some embodiments, the bonding layer 104 includes AlN, BN, Y ₂ O ₃ 、YAG、Al ₂ O ₃ One or more of BeO, siC, graphene, or any other suitable high kappa material.

The bonding layer 104 is disposed between the first dielectric layer 112 and the second dielectric layer 113, and in some embodiments, the bonding layer 104 may be in direct contact with the first dielectric layer 112 and the second dielectric layer 113. The second dielectric layer 113 may be formed of any suitable dielectric material and may include SiO in some embodiments ₂ One or more of SiN, siON, siCN, siOCN. In some embodiments, the second dielectric layer 113 may be formed of the same material as the first dielectric layer 112. In some embodiments, the second dielectric layer 113 may be a silicon dioxide layer. However, the embodiments provided herein are not limited thereto, and any other suitable material for the second dielectric layer 113 may be used in various embodiments.

The inclusion of the second dielectric layer 113 in the semiconductor device 300 of fig. 3 may facilitate improved bonding by the bonding layer 104. For example, in some embodiments, the bonding layer 104 may be formed of a high kappa dielectric material that is easier to bond with the materials of the first dielectric layer 112 and the second dielectric layer 113, or that exhibits improved bonding or advantageous bonding (e.g., stronger bonding, faster bonding, etc.) with the bonding of the first dielectric layer 112 and the second dielectric layer 113, and when the second dielectric layer 113 is included in the semiconductor device 300, the bonding layer 104 may be or include a metal layer that includes high thermal conductivity.

In addition, the use of a high kappa dielectric material for the bonding layer 104 helps to improve the thermal performance of the semiconductor device 300, for example, by preventing or reducing performance degradation of the semiconductor device (e.g., within the semiconductor device layer 110) due to heat. The high kappa dielectric material in the bonding layer 104 may improve heat dissipation, which may protect the semiconductor device layer 110 from thermal degradation, and thus may improve performance and reliability of the chip or semiconductor device 300.

Fig. 4A-4D illustrate a method of manufacturing a device 300 according to some embodiments.

As shown in fig. 4A, the method includes forming a second dielectric layer 113 over a semiconductor device structure, which may be referred to as a device wafer 400. The device wafer 400 includes a substrate 202, a semiconductor device layer 110, and a frontside interconnect structure 108, which may be the same or substantially the same as previously described herein.

The second dielectric layer 113 may be formed of any suitable dielectric material and may include SiO in some embodiments ₂ One or more of SiN, siON, siCN or SiOCN. In some embodiments, the second dielectric layer 113 may be a silicon dioxide layer. The second dielectric layer 113 may be formed by any suitable technique, including, for example, by PVD, CVD, ALD or any other suitable deposition technique.

In some embodiments, the second dielectric layer 113 has a thickness of less than 3000 nm. In some embodiments, the thickness of the second dielectric layer 113 is in the range of 10nm to 3000 nm.

The method further includes forming a bonding layer 104 on the second dielectric layer 113. The bonding layer 104 may be formed by any suitable technique. For example, in some embodiments, the bonding layer 104 is formed by depositing a high kappa dielectric material. In some embodiments, the bonding layer 104 is a high kappa dielectric layer deposited by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced CVD (PECVD), or any suitable deposition technique.

In some embodiments, the bonding layer 104 has a thickness of less than 3000 nm. In some embodiments, the bonding layer 104 has a thickness in the range of 10nm to 3000nm, which may facilitate proper bonding between adjacent structures (e.g., to the first dielectric layer 112).

As shown in fig. 4B, the method includes forming a first dielectric layer 112 on a substrate 102, which substrate 102 may be a carrier wafer or a carrier substrate. The first dielectric layer 112 may be formed of any suitable dielectric material and may include SiO in some embodiments ₂ One or more of SiN, siON, siCN or SiOCN. In some embodiments, the first dielectric layer 112 may be twoAnd a silicon oxide layer. The first dielectric layer 112 may be formed by any suitable technique, including, for example, by PVD, CVD, ALD or any other suitable deposition technique.

In some embodiments, the thickness of the first dielectric layer 112 is less than 3000nm. In some embodiments, the thickness of the first dielectric layer 112 is in the range of 10nm to 3000nm.

As shown in fig. 4C, the device wafer 400 is bonded to the carrier substrate 102. The device wafer 400 and the carrier substrate 102 may be bonded to each other by any suitable technique. For example, the first dielectric layer 112 on the carrier substrate 102 may be bonded to the high kappa bonding layer 104 formed on the device wafer 400. In some embodiments, the carrier substrate 102 is bonded to the device wafer 400 by an ambient bonding process (e.g., using ambient temperature or pressure process parameters in a bonding tool) (e.g., by bonding the bonding layer 104 to the first dielectric layer 112). In some embodiments, the carrier substrate 102 is bonded to the device wafer 400 by a vacuum bonding process (e.g., in a bonding tool having vacuum pressure). However, embodiments are not so limited, and in various embodiments, the bonding of the carrier substrate 102 to the device wafer 400 may be performed by any suitable bonding process.

As shown in fig. 4D, semiconductor device 300 is formed by forming backside interconnect structures 106 on the backside of semiconductor device 300. In some embodiments, the formation of the backside interconnect structure 106 includes forming a plurality of conductive features operable to deliver electrical signals to semiconductor devices in the semiconductor device layer 110 or receive electrical signals from semiconductor devices in the semiconductor device layer 110. For example, the backside interconnect structure 106 may include one or more backside power rails, metallization layers, conductive vias, and the like.

In some embodiments, one or more portions of the substrate 202 may be at least partially removed, for example, as part of the formation of the backside interconnect structure 106. In some embodiments, the backside interconnect structure 106 is formed in the substrate 202 or at least partially comprises a portion of the substrate 202. For example, in some embodiments, conductive features (e.g., backside power rails, metallization layers, conductive vias, etc.) of the backside interconnect structure 106 may be formed within the substrate 202.

Further, as shown in fig. 4D, device 300 is completed by forming electrical contacts 124. The electrical contacts 124 may be formed by any suitable technique, including by deposition, soldering, placement of solder balls, and the like. The electrical contacts 124 may be formed on or in contact with the metallization layer of the backside interconnect structure 106. In some embodiments, the electrical contacts 124 may include power contacts, input/output contacts, or any other contacts for receiving or providing electrical signals. In various embodiments, any number of electrical contacts may be included in semiconductor device 300 and may be coupled to various conductive features or metallization paths, for example, electrically coupled to semiconductor devices in semiconductor device layer 110.

The use of the second dielectric layer 113 in the semiconductor device 300 may help improve bonding through the bonding layer 104, for example, in embodiments where the high kappa material of the bonding layer 104 advantageously adheres to the dielectric material of the second dielectric layer 113 and advantageously bonds to the dielectric material of the first dielectric layer 112. This may provide, for example, improved bonding (e.g., stronger or faster bonding) between the device wafer 400 and the substrate 102, while also preventing or reducing thermal degradation of the semiconductor device 300 due to the presence of the high kappa dielectric bonding layer 104.

Fig. 5 is a cross-sectional view illustrating a semiconductor device 500 according to some embodiments of the present disclosure. The device 500 shown in fig. 5 is substantially identical to the device 100 shown in fig. 1A; however, device 500 does not include dielectric layer 112.

More specifically, semiconductor device 500 includes optional substrate 102, bonding layer 104, front side interconnect structure 108, semiconductor device layer 110, back side interconnect structure 106, and electrical contacts 124.

The substrate 102, the bonding layer 104, the front-side interconnect structure 108, the semiconductor device layer 110, the back-side interconnect structure 106, and the electrical contacts 124 of the semiconductor device 500 may be the same or substantially the same as previously described with respect to the device 100 of fig. 1A.

For example, in some embodiments, the bonding layer 104 is a high kappa dielectric layer formed of a high kappa dielectric material. In some embodiments, the bonding layer 104 is a high kappa dielectric layer having a thermal conductivity greater than that of silicon dioxide. In some embodiments, the bonding layer 104 is a high kappa dielectric layer having a thermal conductivity greater than 10W/mK. In some embodiments, the bonding layer 104 is a high kappa dielectric layer comprising one or more of a nitride, a metal oxide, or a carbide. In some embodiments, the bonding layer 104 includes AlN, BN, Y ₂ O ₃ 、YAG、Al ₂ O ₃ One or more of BeO, siC, graphene, or any other suitable high kappa material.

The bonding layer 104 is disposed between the substrate 102 and the front side interconnect structure 108, and in some embodiments, the bonding layer 104 may be in direct contact with the substrate 102 and the back side interconnect structure 108.

In some embodiments, the bonding layer 104 is a multilayer structure. For example, as described in further detail later herein, the bonding layer 104 may include a first bonding layer 103 and a second bonding layer 105 bonded to each other, thereby providing bonding of the high kappa dielectric material to the high kappa dielectric material.

In some embodiments, the bonding layer 104 provides a suitable bond between the substrate 102 and the front-side interconnect structure 108, e.g., does not include a dielectric layer such as the first or second dielectric layers 112, 113 previously described.

For example, the use of a high kappa dielectric material for the bonding layer 104 helps to improve the thermal performance of the semiconductor device 500 by preventing or reducing performance degradation of the semiconductor device (e.g., within the semiconductor device layer 110) due to heat. The high kappa dielectric material in the bonding layer 104 may improve heat dissipation, which may protect the semiconductor device layer 110 from thermal degradation, and thus may improve performance and reliability of the chip or semiconductor device 500.

In addition, the omission of a dielectric layer in the device 500 of fig. 5 may help reduce the overall thickness or height of the semiconductor device 500. For example, in some embodiments, the bonding layer 104 may be formed of a high kappa dielectric material that is suitably bonded to the material of the front side interconnect structure 108 and the substrate 102, thereby facilitating the omission of additional layers for bonding, such as a dielectric layer.

Fig. 6A-6D illustrate methods of fabricating a semiconductor device 500 according to some embodiments.

As shown in fig. 6A, the method includes forming a first bonding layer 103 on a semiconductor device structure, which may be referred to as a device wafer 600. The device wafer 600 includes a substrate 202, a semiconductor device layer 110, and a frontside interconnect structure 108, which may be the same or substantially the same as previously described herein.

The first bonding layer 103 may form a first portion or first sub-layer of the bonding layer 104 of the device 500. The first bonding layer 103 may be formed by any suitable technique. For example, in some embodiments, the first bonding layer 103 is formed by depositing a high kappa dielectric material. In some embodiments, the first bonding layer 103 is a high kappa dielectric layer deposited by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced CVD (PECVD), or any suitable deposition technique.

In some embodiments, the first bonding layer 103 has a thickness of less than 3000 nm. In some embodiments, the first bonding layer 103 has a thickness in the range of 10nm to 3000nm, which may facilitate proper bonding between adjacent structures (e.g., to the front-side interconnect structure 108 and the second bonding layer 105 or substrate 102).

As shown in fig. 6B, the method may include forming a second bonding layer 105 on the substrate 102, which substrate 102 may be a carrier wafer or a carrier substrate. In some embodiments, the second bonding layer 105 may form a second portion or a second sub-layer of the bonding layer 104 of the semiconductor device 500. The second bonding layer 105 may be formed by any suitable technique, including, for example, by depositing a high kappa dielectric material. In some embodiments, the second bonding layer 105 is a high kappa dielectric layer deposited by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced CVD (PECVD), or any suitable deposition technique. In some embodiments, the second bonding layer 105 is formed of the same material as the first bonding layer 103.

In some embodiments, the second bonding layer 105 has a thickness of less than 3000 nm. In some embodiments, the second bonding layer 105 has a thickness in the range of 10nm to 3000nm, which may facilitate proper bonding between adjacent structures (e.g., to the first bonding layer 103 and the substrate 102).

In some embodiments, the second bonding layer 105 may be omitted. For example, the first bonding layer 103 may be the same as the bonding layer 104 of the semiconductor device 500, and the first bonding layer 104 may be directly bonded to the substrate 102. In embodiments including both the first bonding layer 103 and the second bonding layer 105, the first bonding layer 103 and the second bonding layer 105 may together form the bonding layer 104, and may have an overall thickness in the range of 10nm to 3000 nm.

As shown in fig. 6C, the device wafer 600 is bonded to the carrier substrate 102. The device wafer 600 and the carrier substrate 102 may be bonded to each other by any suitable technique. For example, the first bonding layer 103 on the device wafer 600 may be bonded to the second bonding layer 105 on the carrier substrate 102. In some embodiments, the bonding layer 104 is formed by omitting the first bonding layer 103 and the second bonding layer 105. In such embodiments, the bonding layer 104 may be formed on the device wafer 600 (e.g., on the one or more metal layers 108), and the carrier substrate 102 may be directly bonded to the bonding layer 104.

In some embodiments, the carrier substrate 102 is bonded to the device wafer 600 by an ambient bonding process (e.g., using ambient temperature or pressure process parameters in a bonding tool). In some embodiments, the carrier substrate 102 is bonded to the device wafer 600 by a vacuum bonding process (e.g., in a bonding tool having vacuum pressure). However, embodiments are not so limited, and in various embodiments, the bonding of the carrier substrate 102 to the device wafer 600 may be performed by any suitable bonding process.

As shown in fig. 6D, semiconductor device 500 is formed by forming backside interconnect structure 106 on the backside of device 500. In some embodiments, the formation of the backside interconnect structure 106 includes forming a plurality of conductive features operable to deliver electrical signals to semiconductor devices in the semiconductor device layer 110 or receive electrical signals from semiconductor devices in the semiconductor device layer 110. For example, the backside interconnect structure 106 may include one or more backside power rails, metallization layers, conductive vias, and the like.

In some embodiments, one or more portions of the substrate 202 may be at least partially removed, for example, as part of the formation of the backside interconnect structure 106. In some embodiments, the backside interconnect structure 106 is formed in a portion of the substrate 202 or at least partially comprises a portion of the substrate 202. For example, in some embodiments, conductive features (e.g., backside power rails, metallization layers, conductive vias, etc.) of the backside interconnect structure 106 may be formed within the substrate 202.

Further, as shown in fig. 6D, the semiconductor device 500 is completed by forming the electrical contacts 124. The electrical contacts 124 may be formed by any suitable technique, including by deposition, soldering, placement of solder balls, and the like. The electrical contacts 124 may be formed on or in contact with the metallization layer of the backside interconnect structure 106. In some embodiments, the electrical contacts 124 may include power contacts, input/output contacts, or any other contacts for receiving or providing electrical signals. In various embodiments, any number of electrical contacts may be included in semiconductor device 500 and may be coupled to various conductive features or metallization paths, for example, electrically coupled to semiconductor devices in semiconductor device layer 110.

The use of the second dielectric layer 113 in the semiconductor device 300 may help improve bonding through the bonding layer 104, for example in embodiments where the high kappa material of the bonding layer 104 advantageously bonds with the dielectric materials of the first and second dielectric layers 112, 113. This may provide, for example, improved bonding (e.g., stronger or faster bonding) between the device wafer 400 and the substrate 102, while also preventing or reducing thermal degradation of the semiconductor device 300 due to the presence of the high kappa dielectric bonding layer 104.

As previously described herein, the use of a high kappa dielectric material for the bonding layer 104 helps to improve the thermal performance of the semiconductor device 500, while omitting the dielectric layer in the semiconductor device 500 may help to reduce the overall thickness or height of the device 500.

Fig. 7 is a cross-sectional view illustrating a semiconductor device 700 according to some embodiments of the present disclosure. The device 700 shown in fig. 7 is substantially identical to the device 100 shown in fig. 1A; however, the device 700 has a different bonding structure including the first bonding layer 301, the second bonding layer 302, and the third bonding layer 303. Furthermore, in some embodiments, semiconductor device 700 does not include dielectric layer 112.

In some embodiments, the semiconductor device 700 includes the substrate 102, the front side interconnect structure 108, the semiconductor device layer 110, the back side interconnect structure 106, and the electrical contacts 124. The substrate 102, front side interconnect structure 108, semiconductor device layer 110, back side interconnect structure 106, and electrical contacts 124 of the semiconductor device 700 may be the same or substantially the same as previously described with respect to the device 100 of fig. 1A. In some embodiments, the substrate 102 is optional and the substrate 102 may be removed, either completely or partially, for example, by a suitable removal operation (e.g., grinding, etching, CMP, or a combination thereof). During the removal operation, the semiconductor device 700 may be attached to a suitable carrier, such as a carrier wafer. The carrier may be attached to the electrical contacts 124 during the removal operation, and then the carrier may be removed after the removal operation is completed. Removing the substrate 102 completely or partially may be advantageous in reducing the overall thickness of the device 700. The substrate 102 may similarly be removed completely or partially in the semiconductor device 100, 300, 500.

In some embodiments, the first bonding layer 301 and the second bonding layer 302 may be formed of the same or substantially the same materials as previously described herein with respect to the bonding layer 104. For example, in some embodiments, each of the first bonding layer 301 and the second bonding layer 302 may be a high kappa dielectric layer formed of a high kappa dielectric material. In some embodiments, the first bonding layer 301 and the second bonding layer 302 are high kappa dielectric layers having a thermal conductivity greater than that of silicon dioxide. In some embodiments, the first bonding layer 301 and the second bonding layer 302 are high kappa dielectric layers having a thermal conductivity greater than 10W/mK. In some embodiments, the first bonding layer 301 and the second bonding layer 302 are high kappa dielectric layers comprising one or more of nitrides, metal oxides, or carbides. In some embodiments, each of the first bonding layer 301 and the second bonding layer 302 includes AlN, BN, Y ₂ O ₃ 、YAG、Al ₂ O ₃ One or more of BeO, siC, graphene, or any other suitable high kappa material. In some embodiments, the first bonding layer 301 and the second bonding layer 302 are formed of the same material.

In some embodiments, the third bonding layer 303 is formed of a different material than one or both of the first bonding layer 301 and the second bonding layer 302. In some embodiments, the third bonding layer 303 is a semiconductor layer or includes one or more semiconductor materials. In some embodiments, the third bonding layer 303 comprises at least one of Si, se, siGe or any other semiconductor material. In some embodiments, the third bonding layer 303 comprises an organic material, which may be advantageous for improving thermal conductivity. In some embodiments, the third bonding layer may comprise an inorganic material, which may be advantageous for withstanding higher temperatures in subsequent processes. In some embodiments, the third bonding layer 303 is or includes a metal layer, which may be advantageous for increasing thermal conductivity. However, embodiments are not limited thereto, and in various embodiments, the third bonding layer 303 may be formed of any material suitable for bonding with the high kappa dielectric materials of the first and second bonding layers 301 and 302.

The first bonding layer 301 is disposed between the front side interconnect structure 108 and the third bonding layer 303, and in some embodiments, the first bonding layer 302 may be in direct contact with the front side interconnect structure 106 and the third bonding layer 303.

The second bonding layer 302 is disposed between the carrier substrate 102 and the third bonding layer 303, and may be in direct contact with the carrier substrate 102 and the third bonding layer 302 in some embodiments.

In some embodiments, the thickness of the third bonding layer 303 is less than the thickness of at least one of the first bonding layer 301 or the second bonding layer 302. In some embodiments, the thickness of the third bonding layer 303 is less than the thickness of each of the first bonding layer 301 or the second bonding layer 302.

The inclusion of the third bonding layer 303 in the device 700 of fig. 7 may help improve bonding by the bonding structures (e.g., including the first, second, and third bonding structures 301, 302, 303). For example, in some embodiments, the first bonding layer 301 and the second bonding layer 302 may be formed of a high kappa dielectric material that bonds more readily with the material of the third bonding layer 303, or may exhibit improved bonding or advantageous bonding (e.g., stronger bonding, faster bonding, etc.) with the third bonding layer 303. This is particularly advantageous in embodiments where a direct bond between the high kappa dielectric materials of the first and second bonding layers 301, 302 is unsuitable or undesirable, or where it is desired to improve the bond between the first and third bonding layers 301 and 302. For example, the first and second bonding layers 301, 302, while of the same material, may have surface characteristics that increase the difficulty of forming a strong bond therebetween. The third bonding layer 303 may serve as a glue or otherwise provide an adhesive or improved bond with the high kappa dielectric material of the first bonding layer 301 and the second bonding layer 302.

In addition, the use of high kappa dielectric materials for the first and second bonding layers 301, 302 helps to improve the thermal performance of the semiconductor device 700, for example, by preventing or reducing performance degradation of the semiconductor device (e.g., within the semiconductor device layer 110) due to heat. The high kappa dielectric material in the first and second bonding layers 301, 302 may improve heat dissipation, which may protect the semiconductor device layer 110 from thermal degradation, and thus may improve performance and reliability of the chip or semiconductor device 700.

Fig. 8A-8E illustrate methods of fabricating a semiconductor device 700 according to some embodiments.

As shown in fig. 8A, the method includes forming a first bonding layer 301 on a semiconductor device structure, which may be referred to as a device wafer 800. The device wafer 800 includes a substrate 202, a semiconductor device layer 110, and a frontside interconnect structure 108, which may be the same or substantially the same as previously described herein.

The first bonding layer 301 may be formed by any suitable technique. For example, in some embodiments, the first bonding layer 301 is formed by depositing a high kappa dielectric material. In some embodiments, the first bonding layer 301 is a high kappa dielectric layer deposited by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced CVD (PECVD), or any suitable deposition technique.

In some embodiments, the first bonding layer 301 has a thickness of less than 3000 nm. In some embodiments, the first bonding layer 301 has a thickness in the range of 10nm to 3000nm, which may facilitate proper bonding between adjacent structures (e.g., to the front-side interconnect structure 108 and the third bonding layer 303).

As shown in fig. 8B, the method includes forming a second bonding layer 302 on the substrate 102, which substrate 102 may be a carrier wafer or a carrier substrate. The second bonding layer 302 may be formed by any suitable technique. For example, in some embodiments, the second bonding layer 302 is formed by depositing a high kappa dielectric material. In some embodiments, the second bonding layer 302 is a high kappa dielectric layer deposited by Physical Vapor Deposition (PVD), chemical vapor deposition, atomic Layer Deposition (ALD), plasma Enhanced CVD (PECVD), or any suitable deposition technique.

In some embodiments, the second bonding layer 302 has a thickness of less than 3000 nm. In some embodiments, the thickness of the second bonding layer 302 is in the range of 10nm to 3000nm, which may facilitate proper bonding between adjacent structures (e.g., to the substrate 102 and the third bonding layer 303).

In some embodiments, the first bonding layer 301 and the second bonding layer 302 are formed of the same material. In some embodiments, the first bonding layer 301 and the second bonding layer 302 may have the same or substantially the same thickness.

As shown in fig. 8C, a third bonding layer 303 is formed. In various embodiments, the third bonding layer 303 may be formed on one or both of the first bonding layer 301 and the second bonding layer 302.

For example, as shown in fig. 8C, the third bonding layer 303 may be formed directly on the first bonding layer 301 on the device wafer 800. In some embodiments, the third bonding layer 303 is formed only on the first bonding layer 301 on the device wafer 800, and the carrier wafer may be bonded, for example, by directly bonding the third bonding portion 303 of the device wafer 800 to the second bonding portion 302 on the carrier substrate 102.

In some embodiments, the third bonding layer 303 may be formed directly on the second bonding layer 302 on the carrier substrate 102. In some embodiments, the third bonding layer 303 is formed only on the second bonding layer 302 on the carrier substrate, and the device wafer 800 may be bonded, for example, by directly bonding the third bonding layer 303 on the carrier substrate 102 to the first bonding layer 301 on the device wafer 800.

In some embodiments, the third bonding layer 303 may be a multi-layer structure including portions formed on each of the carrier substrate 102 and the device wafer 800. For example, a first sub-layer of the third bonding layer 303 may be formed directly on the first bonding layer 301 on the device wafer 800, and a second sub-layer of the third bonding layer 303 may be formed directly on the second bonding layer 302 on the carrier substrate 102.

In some embodiments, the third bonding layer 303 has a thickness of less than 50 nm. In some embodiments, the third bonding layer 303 has a thickness in the range of 0.5nm to 50nm, which may facilitate proper bonding between adjacent structures (e.g., to the first bonding layer 301 and the second bonding layer 302) while having a small thickness.

In some embodiments, the thickness of the third bonding layer 303 is less than the thickness of the first bonding layer 301 and less than the thickness of the second bonding layer 302. In some embodiments, the relatively small thickness of third bonding layer 303 increases the overall thermal conductivity of device 700 because third bonding layer 303 may be formed of a material having a lower thermal conductivity than first bonding layer 301 and second bonding layer 302.

As shown in fig. 8D, device wafer 800 is bonded to carrier substrate 102. The device wafer 800 and the carrier substrate 102 may be bonded to each other by any suitable technique. For example, in some embodiments, a first portion of the third bonding layer 303 on the device wafer 800 may be bonded to the second bonding layer 303 on the carrier substrate 102. In some embodiments, the third bonding layer 303 is formed only on the first bonding layer 301 on the device wafer 800, and the second bonding layer 302 on the carrier substrate 102 may be bonded to the third bonding layer 303. In some embodiments, the third bonding layer 303 is formed only on the second bonding layer 302 on the carrier substrate, and the device wafer 800 may be bonded by directly bonding the third bonding layer 303 on the carrier substrate 102 to the first bonding layer 301 on the device wafer 800.

In some embodiments, the carrier substrate 102 is bonded to the device wafer 800 by an ambient bonding process (e.g., using ambient temperature or pressure process parameters in a bonding tool). In some embodiments, the carrier substrate 102 is bonded to the device wafer 800 by a vacuum bonding process (e.g., in a bonding tool having vacuum pressure). However, embodiments are not so limited, and in various embodiments, the bonding of the carrier substrate 102 to the device wafer 800 may be performed by any suitable bonding process.

As shown in fig. 8E, the semiconductor device 700 is formed by forming the backside interconnect structure 106 on the backside of the semiconductor device 700. In some embodiments, the formation of the backside interconnect structure 106 includes forming a plurality of conductive features operable to deliver electrical signals to semiconductor devices in the semiconductor device layer 110 or receive electrical signals from semiconductor devices in the semiconductor device layer 110. For example, the backside interconnect structure 106 may include one or more backside power rails, metallization layers, conductive vias, and the like.

Further, as shown in fig. 8E, the semiconductor device 700 is completed by forming the electrical contact 124. The electrical contacts 124 may be formed by any suitable technique, including by deposition, soldering, placement of solder balls, and the like. The electrical contacts 124 may be formed on or in contact with the metallization layer of the backside interconnect structure 106. In some embodiments, the electrical contacts 124 may include power contacts, input/output contacts, or any other contacts for receiving or providing electrical signals. In various embodiments, any number of electrical contacts may be included in semiconductor device 700 and may be coupled to various conductive features or metallization paths, for example, electrically coupled to semiconductor devices in semiconductor device layer 110.

In some embodiments, the bonding layer may be formed by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD). In some embodiments, the cross-plane kappa (κ) of the bonding layer may vary slightly depending on the deposition method. "trans-planar kappa" means a thermal conductivity that includes along an axis perpendicular to the major surface of the material layer. For example, the major surface of the first bonding layer 301 may be in the X-Y plane, and its cross-plane kappa may be measured along the Z-axis. For example, as shown in fig. 9, alN layers (which may be high kappa dielectric bonding layers in some embodiments) having the same or substantially the same thickness, use CVD as the cross-plane kappa for the deposition process is lowest, ALD as the deposition process is next highest, and PVD as the deposition process is highest. The difference in trans-planar kappa based deposition methods is due to the crystallinity of the deposited tie layer. For example, PVD deposition may result in a more crystalline bonding layer, while CVD and ALD deposition may result in a bonding layer that is more amorphous than that produced by PVD deposition. Thus, in some embodiments, the bonding layer of any of the embodiments provided herein may be formed by PVD, which may be advantageous for reasons discussed herein.

In various embodiments provided herein, the bonding layer (e.g., one or both of bonding layer 104, bonding layers 301, 302) has a thermal conductivity greater than 10W/m·k. In some embodiments, the bonding layer may have a thermal conductivity greater than 50W/mK, and in some embodiments, greater than 100W/mK. In some embodiments, the thermal conductivity may depend on the thickness of the bonding layer. For example, in embodiments where the junction layer is AlN formed by PVD, the cross-plane kappa of the junction layer may decrease gradually with increasing thickness, e.g., from about 150W/mK at a thickness of about 100nm to about 38W/mK at a thickness of about 1.2 μm.

In some embodiments, the bonding layer has a thickness of less than 3000 nm. In some embodiments, the bonding layer has a thickness of less than 1000 nm. In some embodiments, the thickness of the bonding layer is in the range of 10nm to 3000nm, which may facilitate proper bonding between adjacent structures while also advantageously providing increased thermal conductivity. In some embodiments, the thickness of the bonding layer is in the range of 50nm to 500nm, which may result in an even greater improvement in thermal conductivity.

Embodiments of the present disclosure provide several advantages. For example, in various embodiments, the use of high kappa dielectric materials for the bonding layer helps to improve the thermal performance of the semiconductor device or package, such as by preventing or reducing performance degradation of the semiconductor device due to heat within the semiconductor device layer. The high kappa dielectric material in the bonding layer may improve heat dissipation, which may protect the semiconductor device layer from thermal degradation, and thus may improve performance and reliability.

According to one embodiment, a semiconductor device includes a first substrate. The semiconductor device layer is disposed on and/or in the first substrate, and the semiconductor device layer includes one or more semiconductor devices. A front-side interconnect structure including a front-side interconnect structure is disposed on a first side of the semiconductor device layer. The backside interconnect structure is disposed on a second side of the semiconductor device layer opposite the first side. One or more electrical contacts are disposed on the backside interconnect structure. A thermally conductive bonding layer is disposed on the front side interconnect structure. The thermally conductive bonding layer has a thermal conductivity greater than 10W/mK.

According to some embodiments, a semiconductor device includes: a first substrate; a semiconductor device layer in the first substrate, the semiconductor device layer including one or more semiconductor devices; a front side interconnect structure including a front side interconnect structure on a first side of the semiconductor device layer; a backside interconnect structure on a second side of the semiconductor device layer, the second side being opposite the first side; one or more electrical contacts on the backside interconnect structure; and a bonding layer on the front side interconnect structure, the bonding layer having a thermal conductivity greater than 10W/m-K.

In the above semiconductor device, further comprising a first dielectric layer disposed between the front-side interconnect structure and the bonding layer.

In the above semiconductor device, the semiconductor device further includes a second dielectric layer, and the bonding layer is disposed between the second dielectric layer and the first dielectric layer.

In the above semiconductor device, the bonding layer is directly between and in direct contact with the front-side interconnect structure and the second substrate.

In the above semiconductor device, the junction layer includes AlN, BN, Y ₂ O ₃ 、YAG、Al ₂ O ₃ One or more of BeO, siC or graphene.

In the above semiconductor device, the thickness of the bonding layer is in the range of 10nm to 3000 nm.

In the above semiconductor device, further comprising: and a semiconductor bonding layer, wherein the bonding layer includes a first bonding layer portion and a second bonding layer portion, the semiconductor bonding layer being disposed directly between the first bonding layer portion and the second bonding layer portion.

In the above semiconductor device, the thickness of the semiconductor bonding layer is smaller than the thickness of each of the first bonding layer portion and the second bonding layer portion.

In the above semiconductor device, the front side of the semiconductor device has no electrical contact.

In the above semiconductor device, further comprising: and a second substrate, a bonding layer disposed between the second substrate and the front side interconnect structure.

In another embodiment, a method is provided that includes forming a thermally conductive bonding layer on a device wafer. The device wafer includes a first substrate, a semiconductor device layer on the first substrate, and a front side interconnect structure. The thermally conductive bonding layer has a thermal conductivity greater than 10W/mK. The second substrate is bonded to the thermally conductive bonding layer. The method further comprises the steps of: forming a thinned first substrate by thinning the first substrate; and forming a backside interconnect structure on a side of the semiconductor device layer opposite the thermally conductive bonding layer.

According to some embodiments, a method of forming a semiconductor device includes: forming a bonding layer on a device wafer, the device wafer comprising a first substrate, a semiconductor device layer on the first substrate, and a front side interconnect structure, the bonding layer having a thermal conductivity greater than 10W/m-K; bonding a second substrate to the bonding layer; forming a thinned first substrate by thinning the first substrate; and forming a backside interconnect structure on a side of the semiconductor device layer opposite the bonding layer.

In the above method, further comprising: a first dielectric layer is formed between the front side interconnect structure and the bonding layer.

In the above method, further comprising: a second dielectric layer is formed between the bonding layer and the second substrate.

In the above method, forming the bonding layer includes forming the bonding layer directly between the front-side interconnect structure and the second substrate and in direct contact with the front-side wiring structure and the second substrate.

In the above method, the method further comprises removing the second substrate while leaving the bonding layer in place.

In the above method, further comprising: forming a semiconductor bonding layer on the device wafer, wherein bonding the second substrate to the bonding layer includes bonding the second substrate to the semiconductor bonding layer.

In the above method, forming the bonding layer includes forming a first bonding layer portion on the device wafer and forming a second bonding layer portion on the second substrate, the method further comprising: a semiconductor bonding layer is formed on one of the first bonding layer portion or the second bonding layer portion.

In the above method, forming the bonding layer includes forming a first bonding layer portion on the device wafer and forming a second bonding layer portion on the second substrate, the method further comprising: forming a first semiconductor bonding layer on the first bonding layer portion; and forming a second semiconductor bonding layer on the second bonding layer portion.

In yet another embodiment, a method includes forming a first dielectric layer on a device wafer. The first dielectric layer is a high kappa dielectric layer having a thickness of less than 3000nm and a thermal conductivity of greater than 10W/mK. The second dielectric layer is formed on the carrier substrate, and the second dielectric layer is formed of a different material than the first dielectric layer. The first dielectric layer of the device wafer is bonded to the second dielectric layer of the carrier substrate. The method further comprises the steps of: forming a thinned back side by thinning the back side of the device wafer; forming a backside interconnect structure on the thinned backside; and forming one or more electrical contacts on the backside interconnect structure.

According to some embodiments, a method of forming a semiconductor device includes: forming a bonding layer on the device wafer, the bonding layer having a thickness less than 3000nm and a thermal conductivity greater than 10W/m-K; forming a second dielectric layer on the carrier substrate, the second dielectric layer being formed of a different material than the bonding layer; bonding the bonding layer of the device wafer to the second dielectric layer of the carrier substrate; forming a thinned back side by thinning the back side of the device wafer; forming a backside interconnect structure on the thinned backside; and forming one or more electrical contacts on the backside interconnect structure.

In the above method, further comprising: forming a third dielectric layer on the device wafer, wherein forming the bonding layer includes forming the bonding layer directly on the third dielectric layer; wherein the third dielectric layer is formed of a different material than the first dielectric layer.

In the above method, the bonding layer is in direct contact with the second dielectric layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

The various embodiments described above may be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the present application, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the application, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A semiconductor device, comprising:

a first substrate;

a semiconductor device layer in the first substrate, the semiconductor device layer comprising one or more semiconductor devices;

a front side interconnect structure on a first side of the semiconductor device layer;

a backside interconnect structure on a second side of the semiconductor device layer, the second side opposite the first side;

one or more electrical contacts on the backside interconnect structure; and

and a bonding layer on the front side interconnect structure, the bonding layer having a thermal conductivity greater than 10W/m-K.

2. The semiconductor device of claim 1, further comprising a first dielectric layer disposed between the front side interconnect structure and the bonding layer.

3. The semiconductor device of claim 2, further comprising a second dielectric layer, the bonding layer disposed between the second dielectric layer and the first dielectric layer.

4. The semiconductor device of claim 1, wherein the bonding layer is directly between and in direct contact with the front side interconnect structure and the second substrate.

5. The semiconductor device of claim 1, wherein the junction layer comprises AlN, BN, Y ₂ O ₃ 、YAG、Al ₂ O ₃ One or more of BeO, siC or graphene.

6. The semiconductor device of claim 1, wherein a thickness of the bonding layer is in a range of 10nm to 3000 nm.

7. The semiconductor device of claim 1, further comprising:

a semiconductor bonding layer is provided on the substrate,

wherein the bonding layer comprises a first bonding layer portion and a second bonding layer portion, the semiconductor bonding layer being disposed directly between the first bonding layer portion and the second bonding layer portion.

8. The semiconductor device of claim 7, wherein a thickness of the semiconductor bonding layer is less than a thickness of each of the first and second bonding layer portions.

9. A method of forming a semiconductor device, comprising:

forming a bonding layer on a device wafer, the device wafer comprising a first substrate, a semiconductor device layer on the first substrate, and a front side interconnect structure, the bonding layer having a thermal conductivity greater than 10W/m-K;

bonding a second substrate to the bonding layer;

forming a thinned first substrate by thinning the first substrate; and

a backside interconnect structure is formed on a side of the semiconductor device layer opposite the bonding layer.

10. A method of forming a semiconductor device, comprising:

forming a bonding layer on the device wafer, the bonding layer having a thickness of less than 3000nm and a thermal conductivity of greater than 10W/m-K;

forming a second dielectric layer on the carrier substrate, the second dielectric layer being formed of a different material than the bonding layer;

bonding the bonding layer of the device wafer to the second dielectric layer of the carrier substrate;

forming a thinned back side by thinning the back side of the device wafer;

forming a backside interconnect structure on the thinned backside; and

one or more electrical contacts are formed on the backside interconnect structure.