CN116487272A

CN116487272A - Board level manufacturing method of semiconductor structure based on wafer

Info

Publication number: CN116487272A
Application number: CN202210050538.8A
Authority: CN
Inventors: 周文武
Original assignee: SIPLP Microelectronics Chongqing Ltd
Current assignee: SIPLP Microelectronics Chongqing Ltd
Priority date: 2022-01-17
Filing date: 2022-01-17
Publication date: 2023-07-25

Abstract

The application provides a board-level manufacturing method of a semiconductor structure based on a wafer. The manufacturing method comprises the following steps: providing a plurality of wafers and a first carrier plate, wherein the wafers comprise a plurality of connected first chips, and the front surfaces of the first chips are provided with first welding pads; cutting one side of the wafer close to the first welding pad to form a gap with depth smaller than the thickness of the wafer between adjacent first chips; forming a protective layer on the wafer, wherein the material of the protective layer enters the gap; mounting a plurality of wafers on a first carrier plate, wherein the protection layer faces the first carrier plate; the first carrier plate is a panel-level carrier plate; forming a first plastic sealing layer at least covering the side surface of the wafer; stripping the first carrier plate, attaching the obtained first plastic package structure to the second carrier plate, and enabling the protective layer to deviate from the second carrier plate; forming a first rewiring structure for leading out the first welding pad on the protective layer; stripping the second carrier plate to obtain a semiconductor intermediate structure; and cutting the semiconductor intermediate structure to obtain a plurality of semiconductor structures comprising at least one first chip.

Description

Board level manufacturing method of semiconductor structure based on wafer

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure on a board level based on a wafer.

Background

In the prior art, in order to improve the processing precision in the process of panel-level fan-out packaging processing of chips, wafer-level packaging equipment is required to be adopted to firstly perform wiring on a wafer, the distance between adjacent bonding pads of the chips is enlarged, then the wafer is cut to obtain a plurality of chips, and then the chips are attached to a panel-level carrier plate and fan-out packaging is performed by adopting the panel-level packaging equipment.

That is, in the prior art, both the panel-level device and the wafer-level device are required, resulting in higher packaging cost.

Disclosure of Invention

The embodiment of the application provides a board-level manufacturing method of a semiconductor structure based on a wafer. The wafer-based semiconductor structure board-level manufacturing method comprises the following steps:

providing a plurality of wafers and a first carrier plate, wherein the wafers comprise a plurality of connected first chips, and the front surfaces of the first chips are provided with a plurality of first welding pads;

cutting one side of the wafer, which is close to the first welding pad, so that a gap is formed between the adjacent first chips, and the depth of the gap is smaller than the thickness of the wafer;

forming a protection layer on one side of the wafer close to the first welding pad, wherein the material of the protection layer enters the gap;

Mounting the plurality of wafers on the first carrier plate, wherein the front surface of the first chip faces the first carrier plate; the first carrier plate is a panel-level carrier plate;

forming a first plastic layer, wherein the first plastic layer at least covers the side surface of the wafer;

peeling the first carrier plate to obtain a first plastic package structure, and attaching the first plastic package structure to a second carrier plate, wherein the front surface of the first chip faces away from the second carrier plate;

forming a first rewiring structure for leading out the first welding pad on the front surface of the first chip;

stripping the second carrier plate to obtain a semiconductor intermediate structure;

and cutting the semiconductor intermediate structure to obtain a plurality of semiconductor structures, wherein the semiconductor structures comprise at least one first chip.

In one embodiment, the first rewiring structure comprises a first rewiring layer electrically connected with the first welding pad and a first conductive post positioned on one side of the first rewiring layer away from the first chip; the first rewiring layer comprises a plurality of first conductive traces, each first welding pad is electrically connected with one first conductive trace, and one side, away from the first chip, of each first conductive trace is provided with a first conductive column; the minimum distance between the adjacent first welding pads is smaller than the minimum distance between the two first conductive posts electrically connected with the first welding pads.

In one embodiment, the first rewiring structure comprises a first rewiring layer electrically connected with the first welding pad and a first conductive post positioned on one side of the first rewiring layer away from the first chip; after the semiconductor intermediate structure is cut to obtain a plurality of semiconductor structures, the board-level manufacturing method of the semiconductor structure based on the wafer further comprises the following steps:

mounting the plurality of semiconductor structures on a third carrier, wherein the first conductive columns deviate from the third carrier; the third carrier plate is a panel-level carrier plate;

forming a second plastic layer, wherein the second plastic layer covers the side surface of the semiconductor structure and the surface deviating from the third carrier, and the first conductive column exposes the second plastic layer;

forming a second rewiring structure on the surface of the second plastic sealing layer, which faces away from the first chip, wherein the second rewiring structure is electrically connected with the first conductive post;

stripping the third carrier plate to obtain a semiconductor packaging structure;

and cutting the semiconductor packaging structure to obtain a plurality of substructures, wherein each substructure comprises at least one first chip.

In one embodiment, the second rewiring structure comprises a second rewiring layer and a second conductive post positioned on one side of the second rewiring layer away from the first chip; the orthographic projection of the second conductive column on the surface of the first chip, which is away from the second conductive column, is positioned outside the first chip; and/or, the minimum spacing between adjacent second conductive posts is greater than the minimum spacing between adjacent first conductive posts; and/or the number of the second conductive posts is greater than the number of the first conductive posts.

In one embodiment, the first rewiring structure comprises a first rewiring layer electrically connected with the first welding pads, the first rewiring layer comprises a plurality of first conductive traces, and each first welding pad is electrically connected with one first conductive trace; the method for manufacturing the wafer-based semiconductor structure at the board level before the peeling of the second carrier plate further comprises:

forming an insulating layer covering the first rewiring layer;

forming a plurality of first openings in said insulating layer, each of said first openings exposing a portion of one of said first conductive traces; the minimum distance between the adjacent first welding pads is smaller than the minimum distance between the first openings corresponding to the two first conductive traces connected with the first welding pads;

after the semiconductor intermediate structure is cut to obtain a plurality of semiconductor structures, the board-level manufacturing method of the semiconductor structure based on the wafer further comprises the following steps:

mounting the plurality of semiconductor structures on a fourth carrier plate, wherein the first opening faces the fourth carrier plate; the fourth carrier plate is a panel-level carrier plate;

forming a third plastic layer, wherein the third plastic layer at least covers the side surface of the semiconductor structure;

Stripping the fourth carrier plate to obtain a second plastic package structure;

and forming a second rewiring structure on the surface, close to the first opening, of the second plastic sealing layer, wherein the second rewiring structure is electrically connected with the first rewiring structure through the first opening.

In one embodiment, the method for fabricating a board-level semiconductor structure based on a wafer further includes, prior to the forming of the first molding layer: taking the gaps as alignment marks, attaching a plurality of second chips on one sides of the plurality of wafers, which are away from the first welding pads, wherein the back of each first chip is respectively provided with one second chip; a second welding pad is arranged on the surface, away from the first chip, of the second chip;

the semiconductor structure comprises the first chip and the second chip; after the semiconductor intermediate structure is cut to obtain a plurality of semiconductor structures, the board-level manufacturing method of the semiconductor structure based on the wafer further comprises the following steps:

mounting the plurality of semiconductor structures on a fifth carrier, the first rewiring structure facing away from the fifth carrier; the fifth carrier plate is a panel-level carrier plate;

forming a fourth plastic sealing layer, wherein the fourth plastic sealing layer at least covers the side surface of the semiconductor structure;

Forming a third rewiring structure on one side of the fourth plastic sealing layer, which is away from the fifth carrier, wherein the third rewiring structure is electrically connected with the first rewiring structure, and the orthographic projection part of the third rewiring structure on the fifth carrier is positioned outside the orthographic projection of the first chip on the fifth carrier;

stripping the fifth carrier plate, and forming a second opening exposing part of the third rewiring structure on the fourth plastic sealing layer;

and forming a first connecting column positioned in the second opening hole and a fourth rewiring structure positioned on the surface of the first plastic sealing layer, which is away from the first chip, wherein the fourth rewiring structure is electrically connected with the third rewiring structure through the first connecting column, and the fourth rewiring structure is electrically connected with the second welding pad.

In one embodiment, the method for fabricating a board-level semiconductor structure based on a wafer further includes, prior to the forming of the first molding layer:

and thinning the sides of the wafers, which are away from the first welding pads, so as to expose the gaps.

In one embodiment, after the thinning process is performed on the side of the plurality of wafers facing away from the first bonding pad to expose the gap, the method for manufacturing a board level of the wafer-based semiconductor structure further includes:

Forming a metal layer on one side of the plurality of wafers away from the protective layer; the second chip is attached to the metal layer;

after the fifth carrier is peeled off, the board-level manufacturing method of the wafer-based semiconductor structure further includes:

forming a third opening exposing a portion of the metal layer on the first molding layer;

and forming a second connecting column positioned in the third opening and a radiating fin positioned on the second connecting column and deviating from the first chip, wherein the radiating fin is electrically connected with the metal layer through the second connecting column.

In one embodiment, the metal layer does not cover the gap; or,

the metal layer covers the gap, and the metal layer forms a recess at the gap; the step of using the gaps as alignment marks, attaching a plurality of second chips on one side of the plurality of wafers away from the first bonding pads, includes:

and taking the concave formed at the gap of the metal layer as an alignment mark, and attaching a plurality of second chips on one side of the plurality of wafers, which is away from the first welding pad.

In one embodiment, the material of the metal layer is silver paste or copper paste; after the plurality of second chips are attached to the sides, facing away from the first bonding pads, of the plurality of wafers, the board-level manufacturing method of the wafer-based semiconductor structure further comprises the following steps:

And curing the silver paste or the copper paste, wherein the second chips are attached to the plurality of wafers through the silver paste or the copper paste.

The main technical effects achieved by the embodiment of the application are as follows:

according to the board-level manufacturing method of the semiconductor structure based on the wafer, a plurality of wafers are mounted on a first carrier board of a panel level to obtain a first plastic package structure, the first plastic package structure is mounted on a second carrier board of the panel level, and a positioning structure of the wafers is used as an alignment mark to form a first rewiring structure on the front face of a first chip; the manufacturing process of the semiconductor structure can adopt panel-level equipment, and compared with the scheme of adopting wafer-level equipment to form a first rewiring structure on a wafer, the manufacturing method of the wafer-based semiconductor structure provided by the embodiment of the invention can reduce the manufacturing cost on the premise of ensuring the precision of a product; the wafer-based semiconductor structure board-level manufacturing method provided by the embodiment of the application can simultaneously package chips of a plurality of wafers, and the packaging efficiency is greatly improved; compared with the scheme that a plurality of chips are obtained by cutting a wafer and then plastic packaging is carried out, the manufacturing steps of the semiconductor structure can be simplified, and the efficiency is improved. Before the first rewiring structure is formed, the relative positions of the chips in the same wafer are not changed due to the steps of cutting, forming the first plastic sealing layer or filling the protective layer, and the like, and the chip mounting is not performed, so that the manufacturing precision of the first rewiring layer is well ensured. Meanwhile, the embodiment of the application cuts one side of the wafer close to the first welding pad, so that a gap smaller than the thickness of the wafer is formed between the adjacent first chips, and a protective layer is formed on one side of the wafer close to the first welding pad, so that materials of the protective layer enter the gap, the chips in the wafer can keep unchanged relative positions, buffer is achieved between the materials of the wafer and the materials of the first plastic sealing layer, and the wafer is prevented from cracking due to the difference of expansion coefficients of the plastic sealing layer and the wafer.

Drawings

FIG. 1 is a flow chart of a method of fabricating a wafer-based semiconductor structure at a board level according to an exemplary embodiment of the present application;

FIG. 2 is a schematic perspective view of a wafer according to an exemplary embodiment of the present application;

FIG. 3 is a schematic perspective view of a first intermediate structure provided in an exemplary embodiment of the present application;

FIG. 4 is a schematic structural view of a first intermediate structure provided in an exemplary embodiment of the present application;

FIG. 5 is a schematic structural view of a second intermediate structure provided in an exemplary embodiment of the present application;

FIG. 6 is a schematic perspective view of a third intermediate structure provided in an exemplary embodiment of the present application;

FIG. 7 is a schematic structural view of a third intermediate structure provided in an exemplary embodiment of the present application;

FIG. 8 is a schematic structural view of a fourth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 9 is a schematic structural view of a fifth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 10 is a schematic partial structure of a sixth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 11 is a schematic partial structure of a sixth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 12 is a schematic view of a perspective partial structure of a seventh intermediate structure provided in an exemplary embodiment of the present application;

FIG. 13 is another perspective partial structure schematic view of a seventh intermediate structure provided in an exemplary embodiment of the present application;

FIG. 14 is a partial schematic view of an eighth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 15 is a partial schematic view of a ninth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 16 is a partial schematic view of a tenth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 17 is a partial schematic view of an eleventh intermediate structure provided in an exemplary embodiment of the present application;

fig. 18 is a schematic structural view of a semiconductor intermediate structure according to an exemplary embodiment of the present application;

fig. 19 is a schematic structural view of a semiconductor structure according to an exemplary embodiment of the present application;

fig. 20 is a schematic structural view of a semiconductor structure provided in another exemplary embodiment of the present application;

FIG. 21 is a schematic view of a partial structure of an eleventh intermediate structure according to an exemplary embodiment of the present application;

FIG. 22 is a schematic view of an eleventh intermediate structure provided in accordance with an exemplary embodiment of the present application from another perspective;

fig. 23 is a schematic view of a partial structure of a semiconductor structure provided in accordance with yet another exemplary embodiment of the present application;

FIG. 24 is a schematic structural view of a thirteenth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 25 is a schematic structural view of a fourteenth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 26 is a schematic structural view of a fifteenth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 27 is a schematic illustration of a sixteenth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 28 is a schematic structural view of a seventeenth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 29 is a schematic diagram of a substructure provided in an exemplary embodiment of the present application;

FIG. 30 is a partial schematic view of an eighteenth intermediate structure provided in an exemplary embodiment of the present application;

fig. 31 is a schematic structural view of a nineteenth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 32 is a schematic diagram of a twenty-first intermediate structure provided in an exemplary embodiment of the present application;

FIG. 33 is a schematic diagram of a twenty-first intermediate structure provided in an exemplary embodiment of the present application;

FIG. 34 is a schematic diagram of a twenty-second intermediate structure provided in an exemplary embodiment of the present application;

FIG. 35 is a schematic structural view of a substructure provided in an exemplary embodiment of the present application;

FIG. 36 is a schematic structural view of a twenty-third intermediate structure provided in an exemplary embodiment of the present application;

FIG. 37 is a schematic structural view of a twenty-fourth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 38 is a schematic structural view of a twenty-fifth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 39 is a schematic diagram of a twenty-sixth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 40 is a schematic structural view of a twenty-seventh intermediate structure provided in an exemplary embodiment of the present application;

FIG. 41 is a schematic diagram of a twenty-eighth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 42 is a schematic diagram of a twenty-ninth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 43 is a partial structural schematic diagram of a twenty-ninth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 44 is a schematic view of a thirty-first intermediate structure provided in an exemplary embodiment of the present application;

fig. 45 is a schematic structural view of a semiconductor structure provided in yet another exemplary embodiment of the present application;

FIG. 46 is a schematic structural view of a thirty-first intermediate structure provided in an exemplary embodiment of the present application;

FIG. 47 is a schematic view of a thirty-second intermediate structure provided in an exemplary embodiment of the present application;

FIG. 48 is a schematic diagram of a thirty-third intermediate structure provided in an exemplary embodiment of the present application;

FIG. 49 is a schematic view of a thirty-fourth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 50 is a schematic illustration of a thirty-fifth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 51 is a schematic structural view of a thirty-sixth intermediate structure provided in an exemplary embodiment of the present application;

FIG. 52 is a schematic diagram of a thirty-seventh intermediate structure provided in an exemplary embodiment of the present application;

FIG. 53 is a schematic structural view of a thirty-eighth intermediate structure provided in an exemplary embodiment of the present application;

fig. 54 is a schematic structural view of a substructure provided in another exemplary embodiment of the present application.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.

The embodiment of the application provides a board-level manufacturing method of a semiconductor structure based on a wafer. Among them, the board-level manufacturing method refers to a method of manufacturing a semiconductor structure using panel-level equipment. Referring to fig. 1, the method for fabricating a wafer-based semiconductor structure at a board level includes the following steps 110 to 190.

In step 110, a plurality of wafers and a first carrier are provided, wherein the wafers include a plurality of connected first chips, and a plurality of first pads are disposed on the front surface of the first chips.

In step 120, a side of the wafer, which is close to the first bonding pad, is cut, so that a gap is formed between the adjacent first chips, and the depth of the gap is smaller than the thickness of the wafer.

In step 130, a protection layer is formed on a side of the wafer close to the first bonding pad, and a material of the protection layer enters the gap.

In step 140, the plurality of wafers are mounted on the first carrier, and the protection layer faces the first carrier; the first carrier plate is a panel-level carrier plate.

In step 150, a first molding layer is formed, the first molding layer at least covering a side surface of the wafer.

In step 160, the first carrier is peeled off to obtain a first plastic package structure, the first plastic package structure is attached to a second carrier, and the protective layer faces away from the second carrier.

In step 170, a first rewiring structure is formed on the protective layer that leads the first bond pad out.

In step 180, the second carrier is peeled off to obtain a semiconductor intermediate structure.

In step 190, the semiconductor intermediate structure is diced to obtain a plurality of semiconductor structures, the semiconductor structures including at least one of the first chips.

The following describes in detail each step of the board-level manufacturing method for a wafer-based semiconductor structure provided in the embodiment of the present application.

Embodiment one:

In one embodiment, as shown in FIG. 2, wafer 10 is a circular structure. The wafer includes a plurality of chips connected to each other. The plurality of chips are connected to each other means that at least part of the film layers of the plurality of chips are in an integrated structure.

By this step a first intermediate structure as shown in fig. 3 and 4 is obtained. As shown in fig. 2 and 3, gaps 12 are formed between adjacent first chips 11. Since the depth of the gap 12 is smaller than the thickness of the wafer 10, the plurality of first chips 11 of the wafer 10 are still connected together after the wafer 10 is diced to form the gap 12.

The side of the wafer 10 near the first bonding pad refers to the side of the wafer 10 provided with the first bonding pad, that is, the side of the wafer 10 located on the front side of the first chip 11. Through this step a second intermediate structure is obtained. The protection layer covers the side of the wafer 10 where the first bonding pad is disposed, and the protection layer covers the bonding pad.

The process temperature is higher when the first plastic layer is formed in step 150, the expansion coefficient of the first plastic layer is higher, and the expansion coefficient of the wafer is lower, so that the material of the protective layer entering into the gap 12 can play a role in buffering, and the wafer 10 is prevented from being broken due to the difference between the expansion coefficients of the first plastic layer and the wafer 10.

In one embodiment, the protective layer is one or more layers of insulating material, and the material of the protective layer may be plastic packaging film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar characteristics. The protective layer may be formed on the wafer 10 by lamination, spin coating, printing, molding, or other suitable means.

In one embodiment, after the step of forming the protective layer on the side of the wafer adjacent to the first bonding pad, the method for manufacturing the wafer-based semiconductor structure further includes: and thinning the back surface of the wafer.

The back side of the wafer may be thinned by grinding. After the back surface of the wafer is thinned, the gap 12 may be exposed, or the gap 12 may not be exposed. The second intermediate structure obtained when the gap 12 is exposed after wafer thinning is shown in fig. 5.

The panel-level carrier refers to a large carrier used in the panel-level packaging process. The panel-level carrier may be rectangular or other shape. The panel-level carrier may be a stainless steel plate substrate, a polymer substrate, or the like.

A third intermediate structure as shown in fig. 6 and 7 is obtained by step 140. As shown in fig. 6 and 7, a plurality of wafers 10 may be mounted on the first carrier 20. The wafer 10 may be attached to the first carrier 20 by the adhesive layer 21, and the adhesive layer 21 may be made of a material that is easily peeled so as to peel the first carrier 20 from the wafer 10 later, for example, the adhesive layer 21 may be made of a thermally separated material that can be made to lose its adhesiveness by heating.

A fourth intermediate structure as shown in fig. 8 may be obtained by step 150. As shown in fig. 8, the first plastic layer 14 covers the side surfaces of each wafer 10 and the back surface of each wafer 10. In other embodiments, the first plastic layer 14 may cover only the sides of each wafer 10.

In one embodiment, before forming the first plastic layer 14, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the wafer 10 and the first carrier 20, so that the first plastic layer 14 can be more closely connected to the wafer 10 and the first carrier 20, and delamination or cracking is prevented.

In one embodiment, the first plastic layer 14 may be a polymer, a resin composite, a polymer composite. For example, the first plastic layer 14 may be a resin having a filler, wherein the filler is an inorganic particle. The first molding layer 14 may be formed by laminating an epoxy resin film, or may be formed by injection molding, compression molding, transfer molding, or the like of an epoxy resin compound.

Wherein the second carrier plate is a panel-level carrier plate.

In this step, after the first carrier is peeled off, the protective layer 13 is exposed. In some embodiments, the first carrier 20 may be mechanically peeled directly from the first plastic layer 14 and the wafer 10. In other embodiments, the first plastic layer 14, the wafer 10 and the first carrier 20 are bonded by the adhesive layer 21, and when the material of the adhesive layer 21 is a heat separation material, the adhesive layer 21 may be further reduced in viscosity after being heated by heating, so as to peel off the first carrier 20.

A fifth intermediate structure as shown in fig. 9 is obtained by step 160. As shown in fig. 9, the first plastic sealing structure is attached to the second carrier 22 by the adhesive layer 23, and the adhesive layer 23 may be made of a material that is easy to peel, so that the second carrier 22 is peeled off from the first plastic sealing layer 14 later, for example, the adhesive layer may be made of a heat-separating material that can lose its adhesiveness by heating.

In step 170, the positioning structure is used as an alignment mark, and a first rewiring structure for leading out the first welding pad is formed on the protection layer.

In one embodiment, the method of fabricating a wafer-based semiconductor structure at the board level further comprises, prior to step 170: and forming a through hole exposing the first welding pad on the protective layer.

By this step, a sixth intermediate structure as shown in fig. 10 and 11 can be obtained, wherein fig. 11 is a partial structure enlarged view of the sixth intermediate structure. As shown in fig. 10 and 11, a plurality of through holes 131 are formed in the protective layer 13, and each through hole 131 exposes one pad 15.

In one embodiment, the positioning structure may be a target point of the front side arrangement of the wafer. The positioning structure is used as the alignment mark, so that the position of the formed first rewiring structure can be prevented from being shifted, and the precision of the first rewiring structure is improved.

In one embodiment, the first rewiring structure comprises a first rewiring layer electrically connected with the first welding pad and a first conductive post positioned on one side of the first rewiring layer away from the first chip. The first rewiring layer comprises a plurality of first conductive traces, each first welding pad is electrically connected with one first conductive trace, and one side, away from the first chip, of each first conductive trace is provided with a first conductive column.

In one embodiment, a minimum pitch between adjacent ones of the first pads is less than a minimum pitch between two of the first conductive pillars to which it is electrically connected. By the arrangement, the minimum distance between the conductive columns led out by the first welding pad is increased, and the accuracy requirement on a subsequent rewiring layer formed on the basis of the first rewiring layer can be reduced.

Further, the area of the first conductive post is larger than the area of the first bonding pad electrically connected with the first conductive post. Thus, the accuracy requirement of the re-wiring layer formed on the basis of the first re-wiring layer later is also facilitated to be reduced.

In one embodiment, the step 170 may be accomplished by:

first, a first rewiring layer is formed on the side of the protective layer 13 facing away from the first chip 11.

By this step, a seventh intermediate structure as shown in fig. 12 and 13 can be obtained, and fig. 12 and 13 are both partial enlarged views of the seventh intermediate structure. As shown in fig. 12 and 13, the first rewiring layer includes a plurality of first conductive traces 161, and the first conductive traces 161 are electrically connected through conductive portions 132 located in the through holes 131. In some embodiments, the conductive portion 132 and the first conductive trace 161 may be formed in the same process step. In this way, the conductive portion 132 and the first conductive trace 161 can be formed simultaneously through one process step, which helps to simplify the semiconductor packaging process. In other embodiments, the conductive portion 132 and the first conductive trace 161 may not be formed simultaneously, and the conductive portion 132 may be formed first and then the first conductive trace 161 may be formed.

Subsequently, an insulating layer is formed covering the first conductive trace 161 and the exposed protective layer 13.

By this step, an eighth intermediate structure as shown in fig. 14 can be obtained, and fig. 14 is a partially enlarged view of the eighth intermediate structure. As shown in fig. 14, the insulating layer 17 covers each of the first conductive traces 161 and the exposed protective layer 13.

Subsequently, a via hole exposing the first conductive trace 161 is formed on the insulating layer.

By this step, a ninth intermediate structure as shown in fig. 15 can be obtained, and fig. 15 is a partially enlarged view of the ninth intermediate structure. As shown in fig. 15, a via 171 exposing the first conductive trace 161 is formed on the insulating layer 17. The vias 171 may be in one-to-one correspondence with the first conductive traces 161, with each via 171 exposing a corresponding first conductive trace 161.

Subsequently, a first conductive pillar is formed within the via 171 of the insulating layer 17, resulting in a first rewiring layer comprising the first conductive pillar and the first conductive trace.

By this step, a tenth intermediate structure as shown in fig. 16 can be obtained, and fig. 16 is a partially enlarged view of the tenth intermediate structure. As shown in fig. 16, the first conductive pillars 162 are formed within the through holes 171, and the first conductive pillars 162 are in direct contact with the first conductive traces 161. The first rewiring layer 16 includes a first conductive pillar 162 and a first conductive trace 161.

In some embodiments, the first conductive trace 161 and the first conductive post 162 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The material of the first conductive trace 161 and the first conductive pillar 162 may be a metal material, such as metallic copper.

In one embodiment, after step 170, the method for fabricating a wafer-based semiconductor structure at a board level further comprises: and forming a solder ball on one side of the first conductive column away from the first chip.

By this step, an eleventh intermediate structure as shown in fig. 17 can be obtained, and fig. 17 is a partially enlarged view of the eleventh intermediate structure. As shown in fig. 17, the solder balls 18 are located on a side of the first conductive pillars 162 facing away from the first chip 11. The solder balls 18 may facilitate soldering of the resulting semiconductor structure to other components. The material of the solder balls 18 may be tin.

The semiconductor intermediate structure shown in fig. 18 can be obtained by step 180.

In one embodiment, the second carrier plate 22 may be mechanically peeled directly from the first plastic layer 14. In other embodiments, the first plastic sealing layer 14 and the second carrier 22 are adhered by the adhesive layer 23, and when the material of the adhesive layer 23 is a heat separation material, the adhesive layer 23 can be further reduced in viscosity after being heated by heating, so as to peel off the second carrier 22.

The semiconductor structure shown in fig. 19 or fig. 20 can be obtained by the steps. As shown in fig. 19 and 20, the semiconductor structure includes a first chip 11, a first molding layer 14 located on the back side of the first chip 11, and a first rewiring structure 16 located on the front side of the first chip 11. The semiconductor structure shown in fig. 19 and 20 includes a first chip 11. In other embodiments, the semiconductor structure may comprise two or more first chips 11.

According to the board-level manufacturing method of the semiconductor structure based on the wafer, the plurality of wafers are mounted on the first carrier board of the panel level, and the first rewiring structure is manufactured by adopting panel-level equipment, so that the manufacturing cost can be reduced, chip packaging of the plurality of wafers can be simultaneously carried out, and the packaging efficiency is greatly improved; before the first rewiring structure is formed, the relative positions of the chips in the same wafer are not changed due to the steps of cutting, forming the first plastic sealing layer or filling the protective layer, and the like, and the chip mounting is not performed, so that the manufacturing precision of the first rewiring layer is well ensured. Meanwhile, the embodiment of the application cuts one side of the wafer close to the first welding pad, so that a gap smaller than the thickness of the wafer is formed between the adjacent first chips, and a protective layer is formed on one side of the wafer close to the first welding pad, so that materials of the protective layer enter the gap, the chips in the wafer can keep unchanged relative positions, buffer is achieved between the materials of the wafer and the materials of the first plastic sealing layer, and the wafer is prevented from cracking due to the difference of expansion coefficients of the plastic sealing layer and the wafer.

Example two

In the second embodiment, only the differences from the first embodiment are described, and the details of the differences from the first embodiment are not described. In this embodiment, a minimum pitch between adjacent ones of the first pads is smaller than a minimum pitch between two of the first conductive pillars electrically connected thereto.

In this embodiment, a twelfth intermediate structure as shown in fig. 21 and 22 can be obtained by step 170. As shown in fig. 21 and 22, the first rewiring structure 16 includes a first rewiring layer electrically connected to the first pad 15, and a first conductive pillar 162 located on a side of the first rewiring layer facing away from the first chip 11. The first rewiring layer includes a plurality of first conductive traces 161, each of the first pads 15 is electrically connected to one of the first conductive traces 161, and the first conductive pillars 162 are disposed on a side of each of the first conductive traces 161 facing away from the first chip 11. The present embodiment is different from the first embodiment in that the insulating layer is not formed in the process of forming the first rewiring layer in the present embodiment. After the step 190 of dicing the semiconductor intermediate structure to obtain a plurality of semiconductor structures, a semiconductor structure as shown in fig. 23 is obtained.

In one embodiment, after the step 190 of dicing the semiconductor intermediate structure to obtain a plurality of semiconductor structures, the method for manufacturing a board level of the wafer-based semiconductor structure further includes:

firstly, mounting the plurality of semiconductor structures on a third carrier, wherein the first conductive columns face away from the third carrier; the third carrier plate is a panel-level carrier plate.

By this step a thirteenth intermediate structure as shown in fig. 24 is obtained. As shown in fig. 24, the semiconductor structure is mounted on the third carrier 28 by an adhesive layer 29. The adhesive layer 29 may be made of a material that is easily peelable in order to later peel the third carrier plate 28 from the semiconductor structure, for example, the adhesive layer 29 may be made of a thermally separable material that is made to lose adhesiveness by heating. The third carrier plate can support the semiconductor structure, so that the subsequent packaging process is convenient to carry out; the third carrier is a panel-level carrier, and the panel-level equipment can be used for subsequent packaging process.

And then forming a second plastic sealing layer, wherein the second plastic sealing layer coats the side surface of the semiconductor structure and the surface deviating from the third carrier, and the first conductive posts are exposed out of the second plastic sealing layer.

Fig. 25 is a schematic structural view of a fourteenth intermediate structure obtained after forming the second molding layer, and fig. 26 is a schematic structural view of a fifteenth intermediate structure obtained after thinning the second molding layer. As shown in fig. 25, the first formed second molding layer 31 encapsulates the side portion of the semiconductor structure and the first conductive pillars 162. After the second plastic layer 31 is thinned, the surface of the first conductive pillar 162 facing away from the first chip 11 exposes the second plastic layer 31.

In one embodiment, the second plastic layer 31 may be a polymer, a resin composite, a polymer composite. For example, the second plastic layer 31 may be a resin having a filler, wherein the filler is an inorganic particle. The second molding layer 31 may be formed by laminating an epoxy resin film, or may be formed by injection molding, compression molding, transfer molding, or the like of an epoxy resin compound.

And then, forming a second rewiring structure on the surface of the second plastic sealing layer, which faces away from the first chip, wherein the second rewiring structure is electrically connected with the first conductive post.

By this step, a sixteenth intermediate structure as shown in fig. 27 can be obtained. As shown in fig. 27, the second rewiring structure 19 includes a second conductive trace 191 and a second conductive post 192 located on a side of the second conductive trace 191 facing away from the first chip 11. Each second conductive trace 191 may have a second conductive post 192 formed thereon, and each second conductive trace 191 may be in direct contact with one first conductive trace 161.

In one embodiment, an orthographic projection of the second conductive post on a surface of the first chip facing away from the second conductive post is located outside the first chip. And/or, the minimum spacing between adjacent second conductive posts is greater than the minimum spacing between adjacent first conductive posts. And/or, in one embodiment, the number of second conductive posts is greater than the number of first conductive posts. Thus, the second conductive post is more convenient to electrically connect with other structures.

In one embodiment, the second conductive trace 191 and the second conductive post 192 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The material of the second conductive trace 191 and the second conductive post 192 may be a metal material, such as metallic copper.

In one embodiment, after forming the second rewiring structure, the semiconductor structure manufacturing method may further include: and forming an insulating material layer covering the second rewiring structure, wherein the insulating material layer is exposed from the surface of the second conductive post, which faces away from the first chip. A seventeenth intermediate structure as shown in fig. 28 may be obtained after forming the layer of insulating material.

As shown in fig. 28, a layer of insulating material 193 covers the second rewiring structure 19, and the surface of the second conductive pillars 192 facing away from the first chip 11 exposes the layer of insulating material 193. The insulating material layer 193 may protect the second rewiring structure 19.

The distance from the side of the insulating material layer 193 facing away from the first chip 11 to the first chip 11 is substantially the same as the distance from the side of the second conductive pillars 192 facing away from the first chip 11 to the first chip 11, such that the surfaces of the second conductive pillars 192 are just exposed to the insulating material layer 193. During formation of the insulating material layer 193, the first insulating material layer 193 may encapsulate the surfaces and sides of the second conductive pillars 192, followed by a thinning process of the insulating material layer 193 to expose the surfaces of the second conductive pillars 192 facing away from the first chip 11.

In one embodiment, an orthographic projection of the second conductive post 192 on a surface of the first chip 11 facing away from the second conductive post 192 is located outside the first chip 11. This arrangement may allow the density of the second conductive posts 192 to be reduced, facilitating connection of the second conductive posts 192 to other structures.

And then, stripping the third carrier plate to obtain the semiconductor packaging structure.

And then cutting the semiconductor packaging structure to obtain a plurality of substructures, wherein each substructure comprises at least one first chip.

The substructure shown in fig. 29 can be obtained by this step. As shown in fig. 29, the substructure includes a first chip 11. In other embodiments, the substructure may also include two or more first chips 11.

The board-level manufacturing method of the semiconductor structure based on the wafer has the same effect as that of the first embodiment, and the manufacturing cost can be reduced, the chip packaging of the wafers can be simultaneously carried out, and the packaging efficiency is greatly improved by attaching the wafers on the first carrier board of the panel level and adopting the panel level equipment to manufacture the first rewiring structure; before the first rewiring structure is formed, the relative positions of the chips in the same wafer are not changed due to the steps of cutting, forming the first plastic sealing layer or filling the protective layer, and the like, and the chip mounting is not performed, so that the manufacturing precision of the first rewiring layer is well ensured. Meanwhile, the embodiment of the application cuts one side of the wafer close to the first welding pad, so that a gap smaller than the thickness of the wafer is formed between the adjacent first chips, and a protective layer is formed on one side of the wafer close to the first welding pad, so that materials of the protective layer enter the gap, the relative positions of the chips in the wafer can be kept unchanged, buffer is achieved between the materials of the wafer and the materials of the first plastic sealing layer, and the wafer is prevented from being broken due to the difference of expansion coefficients of the plastic sealing layer and the wafer;

In addition, the wafer is cut to form the semiconductor structure with the first rewiring structure, and after the semiconductor structure is mounted on the third carrier, the panel-level equipment is used for carrying out subsequent packaging steps including forming the second rewiring structure. Although the relative position between the chips is undesirably changed due to dicing, mounting of the semiconductor structure, and formation of the second plastic layer before the second rewiring structure is formed, the accuracy of the package can be ensured because the preceding steps can already reduce the accuracy requirement for forming the second rewiring layer on the first rewiring layer; in addition, the second conductive posts with larger spacing, larger area and more number can be formed in the embodiment, so that the second conductive posts are more beneficial to the electric connection with other structures.

Embodiment III:

in the third embodiment, only the first difference from the first embodiment is described, and the details of the first difference from the first embodiment will not be described.

In this embodiment, the first rewiring structure comprises a first rewiring layer electrically connected to the first pads, the first rewiring layer comprising a plurality of first conductive traces, each of the first pads being electrically connected to one of the first conductive traces. Prior to the step 180 of peeling the second carrier, the method for manufacturing a board level of the wafer-based semiconductor structure further includes:

Forming an insulating layer covering the first rewiring layer;

a plurality of first openings are formed in the insulating layer, each of the first openings exposing a portion of one of the first conductive traces.

By this step, an eighteenth intermediate structure shown in fig. 30 can be obtained, and fig. 30 is a partially enlarged view of the eighteenth intermediate structure. As shown in fig. 30, a first opening 171 exposing the first conductive trace 161 is formed on the insulating layer 17. The first openings 171 may correspond to the first conductive traces 161 one-to-one, and each first opening 171 exposes a corresponding first conductive trace 161.

In one embodiment, the minimum distance between the adjacent first pads 15 is smaller than the minimum distance between the first openings 171 corresponding to the two first conductive traces 161 connected thereto. This arrangement helps to reduce the requirement for precision of the subsequently formed second rewiring structure. In one embodiment, the dicing of the semiconductor intermediate structure results in a plurality of semiconductor structures including insulating layer 17. After the step 180 of dicing the semiconductor intermediate structure to obtain a plurality of semiconductor structures, the board-level manufacturing method of the wafer-based semiconductor structure further includes:

Firstly, mounting the plurality of semiconductor structures on a fourth carrier, wherein the first opening faces the fourth carrier; the fourth carrier plate is a panel-level carrier plate.

By this step, a nineteenth intermediate structure as shown in fig. 31 can be obtained. As shown in fig. 31, a plurality of semiconductor structures may be attached to the fourth carrier plate 24 by an adhesive layer 25. The adhesive layer 25 may be made of a material that is easily peeled so that the first carrier plate 20 is peeled off from other structures later, for example, the adhesive layer 25 may be made of a thermally-separable material that can be made to lose adhesiveness by heating.

And then forming a third plastic sealing layer, wherein the third plastic sealing layer at least covers the side face of the semiconductor structure.

By this step, a twentieth intermediate structure as shown in fig. 32 can be obtained. As shown in fig. 32, the third plastic layer 18 encapsulates the side surface of the semiconductor structure and the surface of the semiconductor structure facing away from the first opening 171.

In one embodiment, the third plastic layer 18 may be a polymer, a resin composite, a polymer composite. For example, the third plastic layer 18 may be a resin with a filler, wherein the filler is an inorganic particle. The third molding layer 18 may be formed by laminating an epoxy resin film, or may be formed by injection molding, compression molding, transfer molding, or the like of an epoxy resin compound.

And then, stripping the fourth carrier plate to obtain a second plastic package structure.

In one embodiment, the fourth carrier plate 24 may be mechanically peeled directly from the third plastic layer 18 and the insulating layer 17. In other embodiments, the third plastic sealing layer 18, the insulating layer 17 and the fourth carrier 24 are bonded by the adhesive layer 25, and when the material of the adhesive layer 25 is a heat separation material, the adhesive layer can be further reduced in viscosity after being heated by heating, so as to peel off the fourth carrier 24.

And then, forming a second rewiring structure on the surface, close to the first opening, of the third plastic sealing layer, wherein the second rewiring structure is electrically connected with the first rewiring structure through the first opening.

In one embodiment, before forming the second rewiring structure, the second plastic sealing layer may be first mounted on a sixth carrier, which is a panel-level carrier. The sixth carrier plate can support the second plastic package structure, and the sixth carrier plate is a panel-level carrier plate, so that the second rewiring structure can be formed by adopting panel-level equipment.

The twenty-first intermediate structure shown in fig. 33 can be obtained after the second plastic package structure is mounted on the sixth carrier and the second rewiring structure is formed. As shown in fig. 33, the third plastic sealing layer 18 is attached to the sixth carrier plate 26 through the adhesive layer 27; the second rewiring structure 19 comprises a second conductive trace 191 and a second conductive post 192 located on a side of the second conductive trace 191 facing away from the first chip 11. Each second conductive trace 191 may have a second conductive post 192 formed thereon, and each second conductive trace 191 may be electrically connected to one first conductive trace 161 through a conductive portion 172 in one first opening 171.

In one embodiment, the conductive portion 172 and the second conductive trace 191 may be formed in the same process step. In this way, the conductive portion 172 and the second conductive trace 191 can be formed simultaneously through one process step, which helps to simplify the semiconductor packaging process. In other embodiments, the conductive portion 172 and the second conductive trace 191 may not be formed simultaneously, and the conductive portion 172 may be formed first and then the second conductive trace 191 may be formed.

In one embodiment, the conductive portion 172, the second conductive trace 191, and the second conductive post 192 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The material of the conductive portion 172, the second conductive trace 191, and the second conductive post 192 may be a metal material, such as metallic copper.

In one embodiment, after forming the second rewiring structure, the semiconductor structure manufacturing method may further include: and forming an insulating material layer covering the second rewiring structure, wherein the insulating material layer is exposed out of the surfaces of the second conductive posts. A twenty-second intermediate structure as shown in fig. 34 can be obtained after the formation of the insulating material layer.

As shown in fig. 34, a layer of insulating material 193 covers the second rewiring structure 19, the exposed insulating layer 17, and the exposed third molding layer 18, and the surface of the second conductive pillars 192 facing away from the first chip 11 exposes the layer of insulating material 193. The insulating material layer 193 may protect the second rewiring structure 19.

The distance from the side of the insulating material layer 193 facing away from the first chip 11 to the first chip 11 is substantially the same as the distance from the side of the second conductive pillars 192 facing away from the first chip 11 to the first chip 11, such that the surfaces of the second conductive pillars 192 are just exposed to the insulating material layer 193. During the formation of the insulating material layer 193, the first insulating material layer 193 may encapsulate the surfaces and sides of the second conductive pillars 192, and then the insulating material layer 193 is thinned to expose the surfaces of the second conductive pillars 192 facing away from the first chip 11.

In one embodiment, an orthographic projection of the second conductive post 192 on a surface of the first chip 11 facing away from the second conductive post 192 is located outside the first chip 11. And/or, a minimum spacing between adjacent second conductive posts 192 is greater than a minimum spacing between adjacent first openings 171. And/or the number of the second conductive posts 192 is greater than the number of the first openings 171. So configured, the second conductive post 192 is conveniently connected to other structures.

In one embodiment, after the step of forming the insulating material layer covering the second rewiring structure, the method of manufacturing a board level of the wafer-based semiconductor structure further comprises:

Stripping the sixth carrier plate to obtain a semiconductor packaging structure;

cutting the obtained semiconductor packaging structure to obtain a plurality of substructures, wherein each semiconductor packaging substructures comprises at least one first chip.

The substructure shown in fig. 35 can be obtained by this step. As shown in fig. 35, the substructure includes a first chip 11.

In this embodiment, the conductive portion 172 and the second conductive trace 191 may be formed in the same process step, which helps to simplify the manufacturing process.

Example IV

In the fourth embodiment, only the first difference from the first embodiment is described, and the same points as the first embodiment will not be described again.

In this embodiment, before the step 150 of forming the first molding layer, the board-level manufacturing method of the wafer-based semiconductor structure further includes the following steps:

and thinning the side, away from the first welding pad, of the wafer so as to expose the gap.

A twenty-third intermediate structure as shown in fig. 36 can be obtained by the above steps. As shown in fig. 36, the gap 12 exposes a surface of the wafer 10 facing away from the protective layer 13, and the gap penetrates the wafer 10. A plurality of first chips 11 of the same wafer 10 are bonded together through a protective layer 13.

In one embodiment, after the step of thinning the side of the wafer facing away from the first pad to expose the gap, the method further includes:

and forming a metal layer on one side of the wafer, which is away from the protective layer.

By this step, a twenty-fourth intermediate structure as shown in fig. 37 can be obtained. As shown in fig. 37, the metal layer 32 covers the surface of the wafer 10 facing away from the protective layer 13.

In one embodiment, the metal layer 32 may be formed by applying a silver paste or a copper paste to the surface of the wafer 10 facing away from the protective layer 13. Alternatively, a DAF film (Die attach film) may be attached to the surface of the wafer 10 facing away from the protective layer 13.

In one embodiment, the metal layer 32 does not cover the gap 12, i.e., the metal layer 32 is a patterned film. Alternatively, as shown in fig. 37, the metal layer 32 covers the gap 12, and the metal layer 32 forms a recess 321 at the gap 12.

taking the gaps as alignment marks, attaching a plurality of second chips on one side of the wafer, which is away from the first welding pads, wherein the back surface of each first chip is respectively provided with one second chip; and a second welding pad is arranged on the surface, away from the first chip, of the second chip.

By this step a twenty-fifth intermediate structure as shown in fig. 38 can be obtained. As shown in fig. 38, one second chip 33 is provided on each back surface of the first chip 11. By using the gap 12 as the alignment mark, the mounting accuracy of the second chip 33 can be improved, the second chip 33 is prevented from being offset, and the mounting accuracy of the second chip 33 is improved.

In one embodiment, when the material of the metal layer 32 is copper paste or silver paste, after the step of attaching the plurality of second chips on the side of the wafer facing away from the first bonding pad, the board-level manufacturing method of the wafer-based semiconductor structure further includes: the metal layer 32 is cured, and the second chip is mounted on the wafer by the silver paste or copper paste. By curing the metal layer 32, the second chip 33 can be fixed more firmly on the metal layer 32.

In one embodiment, the metal layer covers the gap, and when the metal layer forms a recess at the gap, the step of using the gap as an alignment mark and attaching a plurality of second chips on a side of the wafer away from the first bonding pad includes: and taking the concave formed at the gap of the metal layer as an alignment mark, and attaching a plurality of second chips on one side of the wafer, which is away from the first welding pad.

In the present embodiment, a twenty-sixth intermediate structure as shown in fig. 39 can be obtained by step 140. As shown in fig. 39, the wafer 10 is attached to the first carrier 20 by the adhesive layer 21, and the adhesive layer 21 may be made of a material that is easy to peel, so that the first carrier 20 is peeled off from the wafer 10 later, for example, the adhesive layer 21 may be made of a thermally separated material that can be made to lose its adhesiveness by heating. The second chip 33 faces away from the first carrier 20.

In this embodiment, a twenty-seventh intermediate structure as shown in fig. 40 can be obtained by step 150. As shown in fig. 40, the first molding layer 14 encapsulates the sides of the wafer 10 and the second chip 33 and the surface of the second chip 33 facing away from the first chip 11, and the second chip 33 is not exposed out of the first molding layer 14.

In the present embodiment, a twenty-eighth intermediate structure as shown in fig. 41 can be obtained through step 160. As shown in fig. 41, the first plastic package structure includes a wafer 10 and a second chip 33, where the first plastic package structure is attached to the second carrier 22 by an adhesive layer 23, and the adhesive layer 23 may be made of a material that is easy to peel, so that the second carrier 22 is peeled from the first plastic package layer 14 later, for example, the adhesive layer may be made of a thermally separated material that can lose its adhesion by heating.

In the embodiment of the present application, the twenty-eighth intermediate structure shown in fig. 42 and 43 is obtained after forming a plurality of through holes 131 on the protective layer 13 of the twenty-eighth intermediate structure shown in fig. 41, and fig. 43 is a partially enlarged view of the twenty-ninth intermediate structure. As shown in fig. 42 and 43, a plurality of through holes 131 are formed in the protective layer 13, and each through hole 131 exposes one first pad 15.

In the embodiment of the present application, the thirty-first intermediate structure shown in fig. 44 is obtained through step 170, and fig. 44 is a partial enlarged view of the thirty-first intermediate structure. As shown in fig. 30, the first rewiring structure 16 includes a first rewiring layer and a first conductive pillar 162, the first rewiring layer includes a plurality of first conductive traces 161, each of the first pads 15 is electrically connected with one of the first conductive traces 161, and the first conductive pillars 162 are disposed on a side of each of the first conductive traces 161 facing away from the first chip 11; the first conductive trace 161 is electrically connected to the first pad 15 through the conductive portion 132 located in the via 131.

In an embodiment of the present application, a semiconductor structure as shown in fig. 45 may be obtained by step 190. As shown in fig. 44, the semiconductor structure includes the first chip 11 and the second chip 33.

In one embodiment, after the step 190 of dicing the semiconductor intermediate structure to obtain a plurality of semiconductor structures, the method for manufacturing a board level of the wafer-based semiconductor structure further includes the steps of:

firstly, mounting the plurality of semiconductor structures on a fifth carrier, wherein the first rewiring structure is away from the fifth carrier; the fifth carrier plate is a panel-level carrier plate.

By this step, a thirty-first intermediate structure as shown in fig. 46 can be obtained. As shown in fig. 46, the semiconductor structure is mounted on the fifth carrier 41 by the adhesive layer 42. The fifth carrier 41 may support the semiconductor structure for further packaging with panel-level devices.

And then forming a fourth plastic sealing layer, wherein the fourth plastic sealing layer at least covers the side face of the semiconductor structure.

By this step, a thirty-second intermediate structure as shown in fig. 47 can be obtained. As shown in fig. 47, the fourth plastic layer 43 encapsulates the side surface of the semiconductor structure and the surface of the semiconductor structure facing away from the fifth carrier 41, and the first conductive pillars 162 of the first rewiring structure 16 expose the fourth plastic layer 43.

In one embodiment, the first conductive pillars 162 may be formed on a surface of the first molding layer 43 facing away from the first chip 11, and the surface of the first conductive pillars 162 facing away from the first chip 11 may be exposed to the fourth molding layer 43 by thinning the fourth molding layer 43. The fourth plastic sealing layer 43 may be thinned by grinding.

And then, forming a third rewiring structure on one side of the fourth plastic sealing layer, which is away from the fifth carrier, wherein the third rewiring structure is electrically connected with the first rewiring structure, and the orthographic projection part of the third rewiring structure on the fifth carrier is positioned outside the orthographic projection of the first chip on the fifth carrier.

By this step a thirty-third intermediate structure as shown in fig. 48 is obtained. As shown in fig. 48, the third rewiring structure 44 includes a third rewiring layer and third conductive pillars 442, the third rewiring layer includes a plurality of third conductive traces 441, and a surface of each third conductive trace 441 facing away from the first chip 11 is provided with a third conductive pillar 442; each third conductive trace 441 is in direct contact with one of the first conductive posts 162. The portion of the third conductive trace 441 and the orthographic projection portion of the third conductive post 442 on the fifth carrier 41 are located outside the orthographic projection of the first chip 11 on the fifth carrier 41.

In one embodiment, after the step of forming the third rewiring structure, the method of manufacturing a wafer-based semiconductor structure at a board level further comprises: and forming an insulating film layer, wherein the insulating film layer covers the third rewiring structure, and the surface of the third conductive post, which is away from the first chip, is exposed out of the insulating film layer.

By this step, a thirty-fourth intermediate structure as shown in fig. 49 can be obtained. As shown in fig. 49, the insulating film 49 covers the exposed side surfaces of the fourth plastic sealing layer 43, the third conductive trace 441 and the third conductive post 442, and the surface of the third conductive post 442 facing away from the first chip 11 exposes the insulating film 49. The insulating film layer 49 may protect the third rewiring structure 44.

And then, stripping the fifth carrier plate, and forming a second opening exposing part of the first rewiring structure on the fourth plastic sealing layer.

In one embodiment, after the fifth carrier is peeled off, the obtained package structure may be mounted on a seventh carrier, and the third rewiring structure faces the seventh carrier; the seventh carrier is a panel-level carrier. By this step a thirty-fifth intermediate structure as shown in fig. 50 can be obtained. As shown in fig. 50, the insulating film layer 45 is attached to the seventh carrier plate 46 by an adhesive layer 47. The seventh carrier 46 may serve as a support, and the seventh carrier is a panel-level carrier, and may be further packaged using panel-level equipment.

In one embodiment, after the package structure obtained after the fifth carrier is peeled off is attached to the seventh carrier, the board-level manufacturing method of the wafer-based semiconductor structure further includes: and forming a third opening exposing part of the metal layer on the first plastic sealing layer.

In one embodiment, after the package structure obtained after the fifth carrier is peeled off is attached to the seventh carrier, the board-level manufacturing method of the wafer-based semiconductor structure further includes: fourth openings exposing the second bonding pads are formed on the first molding layer.

After forming the second, third and fourth openings, a thirty-sixth intermediate structure as shown in fig. 51 can be obtained. As shown in fig. 51, the second opening 431 exposes a portion of the third conductive trace 441 of the third rewiring structure 44, the third opening 141 exposes a portion of the metal layer 32, and the fourth opening 142 exposes a pad of the second chip 33.

In one embodiment, the second, third and fourth openings 431, 141 and 142 may be formed by etching the molding layer.

And then, forming a first connecting column positioned in the second opening and a fourth rewiring structure positioned on the surface of the first plastic sealing layer, which is away from the first chip, wherein the fourth rewiring structure is electrically connected with the third rewiring structure through the first connecting column, and the fourth rewiring structure is electrically connected with the second welding pad.

In one embodiment, the method for fabricating a wafer-based semiconductor structure at a board level further comprises: and forming a second connecting column positioned in the third opening and a radiating fin positioned on the second connecting column and deviating from the first chip, wherein the radiating fin is electrically connected with the metal layer through the second connecting column.

A thirty-seventh intermediate structure as shown in fig. 52 can be obtained after forming the first connection post, the fourth rewiring structure, the second connection post, and the heat sink. As shown in fig. 52, one end of the first connection pillar 51 located in the second opening 431 is electrically connected to the third rewiring structure 44, and the other end is electrically connected to the fourth rewiring structure 54 located on the side of the first molding layer 14 facing away from the first chip 11; one end of the second connection post 52 located in the third opening 141 is electrically connected to the metal layer 32, and the other end is electrically connected to the heat sink 55; the fourth rewiring structure 54 is electrically connected to the second pads of the second chip 33 through the third connection stud 53 located within the fourth hole 142.

That is, the second pads of the second chip 33 are electrically connected to the first pads 15 of the first chip 11 through the third connection post 53, the fourth rewiring structure 54, the first connection post 51, the third rewiring structure 44, and the first rewiring structure 16 in this order, thereby realizing interconnection of the first chip 11 and the second chip 33. The heat sink 55 is electrically connected to the metal layer 32 through the second connection post 52, and the metal layer 32 is located between the back surface of the first chip 11 and the back surface of the second chip 33, so that the heat generated by the first chip 11 and the second chip 33 can be conducted to the heat sink 55 through the metal layer 32, and the heat sink 55 dissipates the heat.

In one embodiment, a conductive contact layer 54 is formed between the heat sink 55 and the first molding layer 14, and the heat sink 55 is electrically connected to the second connection post 52 through the conductive contact layer 54. The fourth rewiring structure may include a plurality of fourth conductive traces, and the conductive contact layer 54 and the fourth conductive traces may be formed simultaneously.

In one embodiment, after forming the heat sink 55, the method of fabricating a wafer-based semiconductor structure at a board level further comprises: an insulating material film layer is formed, and the insulating material film layer covers the heat sink and the fourth rewiring structure.

By this step, a thirty-eighth intermediate structure as shown in fig. 53 can be obtained. As shown in fig. 53, the insulating material film 57 covers the heat sink 55, the fourth rewiring structure 54, the exposed first molding layer 14, and the exposed fourth molding layer 43, and the surface of the heat sink 55 facing away from the first chip 11 exposes the insulating material film 57.

In one embodiment, after the step of forming the insulating material film layer, the method for manufacturing a wafer-based semiconductor structure at a board level further includes the steps of:

stripping the seventh carrier plate to obtain a semiconductor packaging structure;

and cutting the semiconductor packaging structure to obtain a plurality of substructures, wherein each substructure comprises at least one first chip and at least one second chip.

The substructure shown in fig. 54 can be obtained by the above steps. As shown in fig. 54, the substructure includes a first chip 11 and a second chip 33.

In one embodiment, the second chip 33 may be an unpackaged chip, a packaged chip, or a passive device.

According to the wafer-based semiconductor structure board-level manufacturing method, when the second chip is mounted, the gap is used as an alignment mark, so that the mounting precision of the second chip can be improved, the second chip is prevented from being offset, and the mounting precision of the second chip is improved; the simultaneous packaging of a plurality of chips and the interconnection of different chips are realized; by arranging the radiating fins and the metal layer, the metal layer conducts heat generated by the first chip 11 and the second chip 33 to the heat dissipation, and the radiating fins radiate the heat, so that the performance of the semiconductor structure is improved.

It should be noted that, the drawings provided in the embodiments of the present application are only schematic, and some differences may exist from the actual structure, for example, the bonding pads on the front surface of the chip are not illustrated in some drawings, and in practice, the bonding pads on the front surface of the chip are electrically connected to the rewiring structure.

It is noted that in the drawings, the size of layers and regions may be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer or element may also be present. Like reference numerals refer to like elements throughout.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A method of fabricating a wafer-based semiconductor structure at a board level, comprising:

attaching the plurality of wafers to the first carrier plate, wherein the protection layer faces the first carrier plate; the first carrier plate is a panel-level carrier plate;

peeling the first carrier plate to obtain a first plastic package structure, attaching the first plastic package structure to a second carrier plate, and enabling the protective layer to deviate from the second carrier plate;

forming a first rewiring structure for leading out the first welding pad on the protective layer;

2. The method of claim 1, wherein the first rewiring structure comprises a first rewiring layer electrically connected to the first pad, and a first conductive stud located on a side of the first rewiring layer facing away from the first chip; the first rewiring layer comprises a plurality of first conductive traces, each first welding pad is electrically connected with one first conductive trace, and one side, away from the first chip, of each first conductive trace is provided with a first conductive column; the minimum distance between the adjacent first welding pads is smaller than the minimum distance between the two first conductive posts electrically connected with the first welding pads.

3. The method of claim 2, wherein the first rewiring structure comprises a first rewiring layer electrically connected to the first pad, and a first conductive stud located on a side of the first rewiring layer facing away from the first chip; after the semiconductor intermediate structure is cut to obtain a plurality of semiconductor structures, the board-level manufacturing method of the semiconductor structure based on the wafer further comprises the following steps:

4. The method of fabricating a wafer-based semiconductor structure of claim 3, wherein the second rewiring structure comprises a second rewiring layer and a second conductive pillar on a side of the second rewiring layer facing away from the first chip; the orthographic projection of the second conductive column on the surface of the first chip, which is away from the second conductive column, is positioned outside the first chip; and/or, the minimum spacing between adjacent second conductive posts is greater than the minimum spacing between adjacent first conductive posts; and/or the number of the second conductive posts is greater than the number of the first conductive posts.

5. The method of claim 1, wherein the first rewiring structure comprises a first rewiring layer electrically connected to the first pads, the first rewiring layer comprising a plurality of first conductive traces, each of the first pads being electrically connected to a respective one of the first conductive traces; the method for manufacturing the wafer-based semiconductor structure at the board level before the peeling of the second carrier plate further comprises:

forming an insulating layer covering the first rewiring layer;

6. The method of claim 1, wherein prior to forming the first molding layer, the method further comprises: taking the gaps as alignment marks, attaching a plurality of second chips on one sides of the plurality of wafers, which are away from the first welding pads, wherein the back of each first chip is respectively provided with one second chip; a second welding pad is arranged on the surface, away from the first chip, of the second chip;

7. The method of claim 6, wherein prior to forming the first molding layer, the method further comprises:

8. The method of claim 7, wherein after the thinning of the side of the plurality of wafers facing away from the first bond pad to expose the gap, the method further comprises:

9. The method of fabricating a wafer-based semiconductor structure of claim 8, wherein the metal layer does not cover the gap; or,

10. The method of manufacturing a wafer-based semiconductor structure according to claim 8, wherein the material of the metal layer is silver paste or copper paste; after the plurality of second chips are attached to the sides, facing away from the first bonding pads, of the plurality of wafers, the board-level manufacturing method of the wafer-based semiconductor structure further comprises the following steps: