CN116486890A - Solid state disk FTL method, system, equipment and medium based on check multiplexing - Google Patents
Solid state disk FTL method, system, equipment and medium based on check multiplexing Download PDFInfo
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Abstract
The invention provides a solid state disk FTL method, a system, equipment and a medium based on check multiplexing, which comprises the following steps: and (3) data writing: step A1: calculating CRC16 check codes of the data, and performing pre-deduplication; step A2: calculating SHA1-256 check codes of the data, and performing deduplication; step A3: if the repetition is found, directly returning to the successful writing; otherwise, performing the step A4; step A4: encoding the data; step A5: and writing the data and other information into the NAND flash memory of the SSD. Reading data: step B1: data and other information are read from the NAND flash memory of the SSD with a certain flash memory read accuracy. Step B2: the data is decoded and the CRC16 check code is used to assist in decoding. Step B3: if the decoding is successful, returning the data to the host, and if the reading is successful; if decoding fails, improving the reading precision of the flash memory, and performing the step B1; and after the decoding times exceed a certain number, returning to the reading failure. The invention can reduce the data read-write delay and increase the read-write bandwidth of the whole disk.
Description
Technical Field
The invention relates to the technical field of computer system structures, in particular to a solid state disk FTL method, a system, equipment and a medium based on check multiplexing.
Background
Flash memory was invented by Toshiba corporation in the 80 s of the 20 th century. Subsequently, intel corporation introduced the first commercial flash memory chip worldwide for use in computer data storage. After entering the 21 st century, flash solid state drives (flash memory based solid state drives, SSDs) entered the developing fast lanes, which comprehensively exceeded mechanical hard drives in terms of performance, storage capacity, etc. Flash solid state drives are gradually replacing mechanical hard drives, and are widely used as external storage devices in various embedded devices, personal computers, data centers and the like.
There are four Nand flash memories currently used for producing solid state disks, single level memory (SLC), multi-level memory (MLC, typically dual-level memory), triple level memory (TLC, also known as 3-bit MLC), and quad level memory (QLC), respectively. SLC, MLC, TLC, QLC, the read-write speed is sequentially from fast to slow, the service life is sequentially from long to short, the cost is sequentially from high to low, and the number of error correction bits (ECC) needed is reversely from low to high. Currently, nand flash memory with SLC has a write lifetime of only 10,000 cycles, 3,000 times if MLC is used, 1,000 times if TLC is used, and even 300 times if QLC is used. At present, the enterprise-level solid state disk storage system is basically a solid state disk adopting an MLC or TLC technology, and a personal consumption level user generally adopts a flash memory product based on TLC. The flash memory product of QLC is still under development because of its lower lifetime.
The major reliability challenges faced by flash memory media are mainly due to their unique physical characteristics. Unlike mechanical disks, solid state disks use Nand flash memory cells as storage media. Nand flash memory may be subject to errors due to external environmental factors or workload variations. Specifically, different types of Nand flash memory cells have different voltage bits, and if some external factor exists, the voltage bit size of the Nand flash memory can be changed, which may eventually lead to the generation of errors.
FIG. 5 is a different type of NAND voltage measurement bit. When a flash memory cell is disturbed by an error source, the voltage value represented by the flash memory cell changes, thereby causing errors in the data content represented by the flash memory cell. Currently, flash memory cells are subject to error effects mainly including: retention time, program disturb, read disturb, physical disturb, etc. A particularly resulting error condition of the flash memory cell is shown in fig. 6. Therefore, in order to avoid data errors caused by an error source and improve data reliability, the solid state disk adopts error correction codes to realize correction and recovery after data errors.
Currently, error correction codes for solid state disks are mainly of 2 types: BCH (Bose-Chaudhuri-Hocquenghem) and LDPC (Low-density parity-check). The efficiency of error correction codes depends on whether they can effectively recover erroneous data and reduce the data error rate to JEDEC standards. Because the BCH error correction capability is lower, the BCH error correction method is mainly applied to a solid state disk or an embedded flash memory device with lower manufacturing process precision and lower flash memory cell density. Aiming at LDPC, the LDPC is widely applied to solid state disks with higher process precision, higher density and higher reliability requirements, such as TLC and QLC solid state disks.
The LDPC adopts 2 modes to carry out data error correction, including hard decision and soft decision, and the implementation process is as follows: firstly, the solid state disk controller uses LDPC to perform decoding error correction, and returns data content if decoding is successful. If the hard decision fails, the LDPC soft decision process is entered. Soft decision obtains soft information of flash memory cell data through read operation of different detection voltages. The soft information indicates the probability that the flash memory cell stores data of "0" or "1". According to the soft information data, LDPC decodes the error correction again, if decoding succeeds, return the data content, otherwise adjust the detection voltage of the read operation, thus obtain more soft information. At present, a great deal of related work has been proposed to optimize the LDPC error correction overhead.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a solid state disk FTL method, a system, equipment and a medium based on check multiplexing.
According to the method, the system, the equipment and the medium for the solid state disk FTL based on the check multiplexing, which are provided by the invention, the scheme is as follows:
in a first aspect, a solid state disk FTL method based on check multiplexing is provided, the method includes: writing and reading data;
wherein the data writing includes:
step A1: calculating CRC16 check codes of the data, and performing pre-deduplication; if the same CRC16 value is found, performing step A2; if the same CRC16 value is not found, performing step A4;
step A2: calculating SHA1-256 check codes of the data, and performing deduplication; if the same SHA1-256 values are found, performing the step A3; if the same SHA1-256 values are not found, performing the step A4;
step A3: directly returning the success of writing;
step A4: LDPC encoding the data;
step A5: writing the data and other information into the NAND flash memory of the SSD together;
the data reading includes:
step B1: reading data and other information from the NAND flash memory of the SSD with flash memory reading precision;
step B2: decoding the data and using a CRC16 check code to assist in decoding;
step B3: if the decoding is successful, returning the data to the host, and if the reading is successful; if decoding fails, improving the flash memory reading precision, and performing step B1; and returning to the reading failure after the decoding times exceed the set times.
Preferably, in the data writing, step A1 includes:
step a1.1: dividing the DATA into DATA blocks with the same size according to the type of the page to be written, and dividing the DATA into N blocks to obtain DATA [0], DATA [1], … and DATA [ N-1];
step a1.2: respectively calculating CRC16 values of the N blocks of data;
step a1.3: searching fingerprint storage for whether the fingerprint has the same CRC16 value; if the same is used for the first time, step A2 is carried out; if not, a new fingerprint is generated and inserted into the fingerprint store, step A4 is performed.
Preferably, the step A2 includes: calculating SHA1-256 check codes of the data, and performing deduplication; if the same SHA1-256 values are found, performing step A3; if the same SHA1-256 values are not found, the SHA1-256 check code in the fingerprint is replaced by the SHA1-256 values of the currently written data page, and step A4 is performed.
Preferably, the step A5 includes: and writing the encoded data into the corresponding physical address of the SSD NAND flash memory, and storing the N CRC16 values of the page, the 1 SHA1-256 check code values and the related metadata information including the logical address of the page into the corresponding OOB area of the NAND flash memory.
Preferably, in the data reading, step B1 includes:
step B1.1: reading out voltage values of corresponding positions on the SSD NAND flash memory according to the given flash memory reading precision;
step B1.2: mapping the voltage value to a data value of 0,1, and obtaining a data page and other information.
Preferably, in the data reading, step B2 includes:
step B2.1: partitioning the data and calculating CRC16 value of each block of data;
step B2.2: comparing the CRC16 value read from the SSD with the calculated CRC16 value, and correcting and updating the LLR value of the data;
step B2.3: the corrected data LLR values are input to an LDPC decoder for decoding.
Preferably, in the data reading, step B3 includes:
step B3.1: judging whether the decoding is successful or not;
step B3.2: different schemes are carried out according to whether decoding is successful or not;
if the decoding is successful, returning the data, and if the reading is successful;
if the decoding fails, judging whether the current decoding times exceeds the maximum decoding times; if the maximum decoding times are exceeded, returning an NVME instruction with failed reading; if the maximum decoding frequency is not exceeded, setting a higher reading precision of the NAND flash memory, returning to the step B1, re-reading the voltage value of the data hall, and decoding.
In a second aspect, a solid state disk FTL system based on check multiplexing is provided, the system includes: a data writing module and a data reading module;
wherein, the data write module includes:
module A1: calculating CRC16 check codes of the data, and performing data pre-deduplication;
module A2: calculating SHA1-256 check codes of the data, and performing data deduplication;
module A3: LDPC encoding the data;
module A4: writing the data and other information into the NAND flash memory of the SSD together;
the data reading module includes:
module B1: reading data and other information from the NAND flash memory of the SSD with the accuracy of flash memory reading;
module B2: correcting LLR values of the data by using CRC16 check codes;
module B3: LDPC decoding the data;
module B4: detecting whether the decoding is successful, if so, returning data to the host, and if the reading is successful; if decoding fails, the flash memory reading precision is improved, and a module B1 is carried out; and after the decoding times exceed the set times, returning the NVME instruction with the failed reading.
In a third aspect, a computer readable storage medium storing a computer program is provided, which when executed by a processor implements steps in the verification multiplexing based solid state disk FTL method.
In a fourth aspect, an electronic device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program implementing steps in the verification multiplexing-based solid state disk FTL method when executed by the processor.
Compared with the prior art, the invention has the following beneficial effects:
1. aiming at the solid state disk using the novel flash memory particles, the invention can well reduce the data read-write delay and increase the read-write bandwidth of the whole disk;
2. the method can be adapted to the existing solid state disk FTL method, reduces the erasing times of the solid state disk, prolongs the service life of the solid state disk, effectively relieves the problems of low maximum erasing times and short service life of the novel solid state disk with flash memory particles, and has good market prospect and application value.
Other advantages of the present invention will be set forth in the description of specific technical features and solutions, by which those skilled in the art should understand the advantages that the technical features and solutions bring.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of the overall module of the device in an embodiment of the invention;
FIG. 2 is a schematic diagram of a data writing process according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a data structure of a finger print storage according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a data reading process according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of different types of NAND voltage measurement bits of the present invention;
FIG. 6 is a schematic diagram of a flash cell error condition.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.
The embodiment of the invention provides a solid state disk FTL method based on check multiplexing, which is shown by referring to FIG. 1 and comprises the following specific contents:
writing and reading data;
wherein the data writing includes:
step A1: calculating CRC16 check codes of the data, and performing pre-deduplication; if the same CRC16 value is found, performing step A2; if the same CRC16 value is not found, performing step A4;
in data writing, the step A1 includes:
step a1.1: dividing the DATA into DATA blocks with the same size according to the type of the DATA, namely the page to be written, and obtaining DATA [0], DATA [1], … and DATA [ N-1] on the premise that the number of the blocks obtained by dividing the DATA is N;
specifically, for a page with a higher error rate, such as Upper page in a three-layer storage (TLC) SSD, center Upper Page and Upper page of the SSD in a four-layer storage (QLC), the number of blocks N of the data partition may be set to be larger; for pages with Lower error rate, such as Lower page in three-layer storage (TLC) SSD, lower page and Center Lower Page of SSD in four-layer storage (QLC), the number of blocks of data partition N may be set smaller.
Step a1.2: the CRC16 value of the N blocks of data is calculated, respectively.
For the first block DATA, the initial value used to calculate the CRC16 value is 0, and for the 2 nd to nth block DATA, the initial value used to calculate the CRC16 value is the result of CRC16 for their previous block DATA, i.e., HASH (DATA [0 ])=crc 16 (0, DATA [0 ]), HASH (DATA [ i ])=crc 16 (0, DATA [ i-1 ]) (i=1, …, N-1).
Step a1.3: searching fingerprint storage for whether the fingerprint has the same CRC16 value; if the same is used for the first time, step A2 is carried out; if not, a new fingerprint is generated and inserted into the fingerprint store, step A4 is performed.
Specifically, the last of the N CRC16 values, that is, HASH (DATA N-1), is used to represent the CRC16 value of the entire DATA page to perform the pre-deduplication operation, specifically, whether the fingerprint with the same CRC16 value is found in the fingerprint storage, if the fingerprint with the same CRC16 value is found, the content in the fingerprint is recorded, (in the specific embodiment, the DATA structure of the fingerprint and the content of each fingerprint will be described), and step A2 is performed; if no fingerprint of the same CRC16 value is found, a new fingerprint is generated, the CRC16 value of the data page is recorded and inserted into the fingerprint storage, and step A4 is performed.
Step A2: calculating SHA1-256 check codes of the data, and performing deduplication; if the same SHA1-256 values are found, performing step A3; if the same SHA1-256 values are not found, the SHA1-256 check code in the fingerprint is replaced by the SHA1-256 values of the currently written data page, and step A4 is performed.
Specifically, after the SHA1-256 check codes of the whole data page are calculated, comparing the SHA1-256 check codes with the SHA1-256 check codes in the fingerprint found in the step 1, if the two check codes are the same, indicating that the data page with the same content as the data page exists in the NAND flash memory of the SSD, and performing the step A3; if the two check codes are different, it is indicated that the NAND flash memory of the SSD does not have to store the data page with the same content as the data page, and the SHA1-256 check codes in the fingerprint are replaced by SHA1-256 values of the data page currently written, so as to perform the step A4.
Step A3: directly returning the success of writing;
step A4: LDPC encoding the data;
step A5: writing the data and metadata information (such as the number of logical pages corresponding to the current physical page and the addresses of a plurality of logical pages) into the NAND flash memory of the SSD together by ECC check codes of the data pages;
the step A5 specifically comprises the following steps: and writing the encoded data into the corresponding physical address of the SSD NAND flash memory, and storing the N CRC16 values of the page, the 1 SHA1-256 check code values and the related metadata information including the logical address of the page into the corresponding OOB area of the NAND flash memory.
The data reading includes:
step B1: reading data and other information from the NAND flash memory of the SSD with a given flash memory reading accuracy;
in the data reading, the step B1 includes:
step B1.1: if the page is read for the first time in the reading process, setting an initial reading precision according to the type of the physical page where the read page is located, and reading a voltage value from the corresponding position of the NAND flash memory of the SSD by using the precision; if the page is not read for the first time in the reading process, reading the voltage value according to the given precision;
step B1.2: and mapping the voltage value into a data value of 0 and 1 to obtain a data page and metadata information (such as the number of logical pages corresponding to the current physical page, addresses of a plurality of logical pages) and an ECC check code of the data page.
The step B1.2 comprises:
mapping the voltage value into corresponding LLR value according to LLR_TABLE, and then according to the positive and negative of LLR value, setting the position of positive LLR value as 0 and the position of negative LLR value as 1 to obtain CRC16 check code, SHA1-256 check code and some metadata information in data page and OOB.
Step B2: decoding the data and using a CRC16 check code to assist in decoding;
in the data reading, step B2 includes:
step B2.1: partitioning the data and calculating CRC16 value of each block of data;
according to the page type stored in the data, determining the number of CRC16 values as N, dividing the data page into N blocks with the same size, and calculating according to the method of step 1.2 in the data writing process to obtain N CRC16 values.
Step B2.2: and comparing the CRC16 value read from the SSD with the calculated CRC16 value, and correcting and updating the LLR value of the data.
The N CRC16 values read out of the OOB area of the NAND flash memory are compared with the N CRC16 values obtained in step B2.1. If the values of the ith CRC16 are the same, the LLR value of the corresponding data block is set to LLR_MAX or LLR_MAX, the bit corresponding to 1 in the data block is set to LLR_MAX, and the bit corresponding to 0 is set to LLR_MAX.
Step B2.3: the corrected data LLR values are input to an LDPC decoder for decoding.
Step B3: if the decoding is successful, returning the data to the host, and if the reading is successful; if decoding fails, improving the flash memory reading precision, and performing step B1; and returning to the reading failure after the decoding times exceed the set times.
Step B3 includes:
step B3.1: judging whether the decoding is successful or not; the decoded data is multiplied by the check matrix of the LDPC to detect whether the decoding is successful.
Step B3.2: different schemes are carried out according to whether decoding is successful or not; if the decoding is successful, returning the data, and if the reading is successful; if the decoding fails, judging whether the current decoding times exceeds the maximum decoding times; if the maximum decoding times are exceeded, returning an NVME instruction with failed reading; if the maximum decoding frequency is not exceeded, setting a higher reading precision of the NAND flash memory, returning to the step B1, re-reading the voltage value of the data hall, and decoding.
The invention also provides a solid state disk FTL system based on check multiplexing, which can be realized by executing the flow steps of the solid state disk FTL method based on check multiplexing, namely, a person skilled in the art can understand the solid state disk FTL method based on check multiplexing as a preferred implementation mode of the solid state disk FTL system based on check multiplexing. The system specifically comprises: a data writing module and a data reading module;
wherein, the data write module includes:
module A1: calculating CRC16 check codes of the data, and performing data pre-deduplication;
module A2: calculating SHA1-256 check codes of the data, and performing data deduplication;
module A3: LDPC encoding the data;
module A4: writing the data and other information into the NAND flash memory of the SSD together;
the data reading module includes:
module B1: reading data and other information from the NAND flash memory of the SSD with the accuracy of flash memory reading;
module B2: correcting LLR values of the data by using CRC16 check codes;
module B3: LDPC decoding the data;
module B4: detecting whether the decoding is successful, if so, returning data to the host, and if the reading is successful; if decoding fails, the flash memory reading precision is improved, and a module B1 is carried out; and after the decoding times exceed the set times, returning the NVME instruction with the failed reading.
Next, the present invention will be described in more detail.
The invention provides a solid state disk FTL method based on check multiplexing, as shown in figure 1, a data writing path comprises three modules:
the pre-deduplication module, after calculating the CRC16 value of the data, looks up whether there is a page with the same CRC16 value in the fingerprint storage, if so, indicates that it is possible to store the same copy in the flash memory.
And the de-duplication module is used for further calculating the SHA1-256 values of the data, comparing the SHA1-256 values in the fingerprint just found in the pre-de-duplication module with the SHA1-256 values in the fingerprint just found in the pre-duplication module, and if the SHA1-256 values are the same, indicating that the same copy is already stored in the flash memory, and directly returning the same.
And an LDPC encoder for LDPC encoding the data.
As shown in fig. 2, a flow of data writing is shown.
After receiving a write request, the SSD copies data from the host to the DRAM cache in the SSD through the DMA, and as in the data writing step a1.1, the method described in step a1.2 calculates the CRC16 value by partitioning the data, uses the last CRC16 value, and searches the fingerprint storage for whether the same CRC16 value exists.
As shown in fig. 3, for a specific data storage manner of fingerprint storage, the CRC16 hash value is first logically divided into 1024 segments, and for a given data page, the CRC16 hash value f is mapped onto segment f mod 1024, so that the hash function randomness ensures that the CRC16 value is uniformly distributed over 1024 segments. Each segment is a linked list of buckets, each bucket is a fixed number of slots, each slot is a fingerprint, and the stored information is: CRC16 hash (16 bits), SHA1-256 hash (256 bits), physical address (64 bits), reference number, i.e. the number of logical pages (8 bits) corresponding to the physical page. When the number of logical pages corresponding to one physical page is more than 255, 255 is substituted, that is, they are not further distinguished in heat. The fingerprints in a bucket are ordered by the value of CRC16 for a fast binary search at lookup. The number of buckets may be determined by the SSD manufacturer at the discretion of the size of the on-chip cache space.
The fingerprint is stored in an on-chip cache of the SSD maintaining the highest reference rate fingerprint. In the starting process of SSD, after the mapping table is established, fingerprint storage is also reconstructed by scanning the mapping table and metadata in the flash memory to load CRC16 hash values, SHA1-256 hash values, physical addresses and reference numbers into the memory. Initially there is no bucket, allocated in the fingerprint storage area. When a slot is inserted, an empty bucket is allocated and connected to the linked list of the corresponding segment. This bucket is continually inserted with the CRC16 value of the same remainder and the corresponding SHA1-256 hash value, physical address and reference number are modified until the bucket is full, and then another bucket is allocated until there are no more buckets. At this point, the newly inserted CRC16 value replaces the fingerprint (i.e., the cold one) in the bucket with the smallest reference number, unless its reference number is smaller than the reference number in any other slot in the bucket. We choose the inserted buckets in a cyclic manner to ensure that the hot/cold fingerprints are distributed relatively evenly among the buckets within a segment. In this way we can include fingerprints with high reference numbers. Although we may miss some because if there is no opportunity to identify a copy of their fingerprint that is not in memory, we consider this probability to be low and not affect the overall deduplication effect.
As shown in fig. 2, after the segment number corresponding to the CRC16 value of the current page is calculated, it is possible to search whether fingerprints with the same CRC16 value exist in the fingerprint storage, scan the linked list of the corresponding buckets one by one, and meanwhile, we provide three methods for accelerating the search:
(1) And (3) range searching: before performing a binary search in a bucket, we first compare the CRC16 value to the minimum CRC16 value and the maximum CRC16 value from the bucket, and if not within that range, the bucket may be skipped.
(2) Recombination based on heat: slots may be arranged in a linked list of buckets in descending order according to their references, which may bring hotter fingerprints closer to the linked list head, possibly reducing the number of scanned buckets.
(3) Bucket level binary search: fingerprints across buckets may be reorganized in ascending order of CRC16 values using merge ordering. For each segment we maintain an array of pointers for each bucket in a bucket list, we can perform a binary search at the bucket level, recursively selecting the middle bucket to check if the CRC16 value to be found is in the smallest maximum range of that bucket. In this way we can quickly find the target bucket and skip most buckets.
If a fingerprint of the same CRC16 value is not found, the fingerprint is inserted into the corresponding bucket, ready for LDPC encoding and data writing. If a fingerprint with the same CRC16 value is found, the SHA1-256 values of the data page are further calculated and compared: if the two mapping tables are the same, the NVME instruction which is successfully written can be returned after the information of the reference number in the fingerprint is modified after the copy with the same content is stored in the SSD flash memory; if it is different, the SHA1-256 values in the fingerprint are modified, the count value, physical address are referenced, and the fingerprint is reinserted into the corresponding bucket and is ready for LDPC encoding and data writing.
And writing the encoded data into the NAND flash memory, and simultaneously writing the corresponding N CRC16 hash values, 1 SHA1-256 hash values, the logical address of the page and other metadata information into the corresponding OOB area of the NAND flash memory.
As shown in fig. 1, the data read path includes three modules:
LLR value correction module: and correcting the LLR value of each data bit according to the comparison result of the N pairs of CRC16 hash values.
LDPC decoder: and taking the LLR value of each data bit as an input, and performing LDPC decoding.
And a verification module: and checking whether the decoded data accords with a check equation, if so, returning the data, if not, and if the reading precision of the current data does not exceed the highest reading precision, reading the voltage value with higher precision again, and reentering the LLR value correction module, otherwise, returning an NVME instruction with failed reading.
As shown in fig. 4, the flow of data reading:
after receiving a read request, the SSD end finds a corresponding physical address in the mapping table through a logical address to be read, the page type storing the page data can be analyzed and known according to the read physical address, an initial read precision is selected according to the page type, for example, low read precision is selected for Lower page in TLC SSD, and higher read precision is selected for Center page and Upper page. After the voltage value of the corresponding physical page is read from the flash memory of the SSD, the voltage value of the corresponding OOB portion of the physical page is also read.
According to the LLR conversion table, the voltage values are converted into LLR values, the mathematical representation of the LLR values being LLR (x) =log (P (x=0)/P (x=1)), representing the probability that the data bit is 0 or 1: if LLR (x) >0, the data bit is 0, the larger the absolute value of LLR value, the greater the probability of 0; if LLR (x) <0, the data bit is 1, the larger the absolute value of LLR value, the greater the probability of being expressed as 1. The LLR conversion table is a table for converting voltage values into LLR values, and is backed up by manufacturers of general SSDs.
After the data page N CRC16 values are obtained, we convert them to 0,1 data values in the manner described above. The data page is divided into N blocks, N CRC16 values are calculated according to the method described in the writing step a1.2, and compared with the N CRC16 values just read, and for the data blocks having the same CRC16 hash value, the LLR values of their data bits are set to llr_max or-llr_max to indicate the correctness of these bits.
And then, the LLR value after data correction can be sent to an LDPC decoder for decoding, so as to obtain decoded data. Multiplying the decoded data by a check equation, if the result is 0, indicating that the check is successful, returning the data to the host, and returning an NVME instruction of which the reading is successful; if the result is not 0, the verification failure is indicated, the reading precision of the data is improved, the voltage value is read again with higher precision, the LLR value is corrected again, and the LDPC is decoded and verified. And returning the NVME instruction with the read failure until the read precision of the data exceeds the preset highest precision.
Using the CRC16 value, on the one hand, pre-deduplication may be performed. Because the calculated amount of the CRC16 hash value is far smaller than the calculated amount of SHA1-256, most data written into SSD flash memory according to statistics are not repeated, and only a small number of data pages are repeated, CRC16 is used for pre-deduplication, the problem that SHA1-256 fingerprints are calculated for each written data page is avoided, the problem of high writing delay caused by direct use of SHA1-256 deduplication is solved, meanwhile, most losses are avoided on the deduplication effect, the total data writing amount of SSD is reduced, writing delay is reduced, and the service life of SSD is prolonged.
And on the other hand, the CRC16 value is used, and on the other hand, the LLR value of the corrected data can be assisted, so that the LDPC decoder is assisted in positioning the position range of the bit with the overturn, the decoding success probability is increased, the decoding strength of the LDPC code is increased, the SSD can read the data with lower precision and then successfully decode, and the reading delay is greatly reduced. Particularly for a page with a higher error rate in the TLC, QLC SSD, using the CRC16 hash value can effectively reduce the read delay when repeatedly reading the page.
Because the storage of the CRC16 hash value causes one data page to store relatively more information in the OOB area, the space overhead increases, but for TLC's that are larger in space but higher in bit error rate, QLC SSDs, the above two advantages of using the CRC16 hash value are completely greater than the disadvantages of increasing some of the space overhead.
The embodiment of the invention provides a solid state disk FTL method, a system, equipment and a medium based on check multiplexing, which can well reduce data read-write delay and increase read-write bandwidth of a whole disk aiming at a solid state disk using novel flash memory particles; the method can be adapted to the existing solid state disk FTL method, reduces the erasing times of the solid state disk, prolongs the service life of the solid state disk, effectively relieves the problems of low maximum erasing times and short service life of the novel solid state disk with flash memory particles, and has good market prospect and application value.
Those skilled in the art will appreciate that the invention provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.
Claims (10)
1. The utility model provides a solid state disk FTL method based on check multiplexing which is characterized in that the method comprises the following steps: writing and reading data;
wherein the data writing includes:
step A1: calculating CRC16 check codes of the data, and performing pre-deduplication; if the same CRC16 value is found, performing step A2; if the same CRC16 value is not found, performing step A4;
step A2: calculating SHA1-256 check codes of the data, and performing deduplication; if the same SHA1-256 values are found, performing the step A3; if the same SHA1-256 values are not found, performing the step A4;
step A3: directly returning the success of writing;
step A4: LDPC encoding the data;
step A5: writing the data and other information into the NAND flash memory of the SSD together;
the data reading includes:
step B1: reading data and other information from the NAND flash memory of the SSD according to a given flash memory reading precision;
step B2: decoding the data and using a CRC16 check code to assist in decoding;
step B3: if the decoding is successful, returning the data to the host, and if the reading is successful; if decoding fails, improving the flash memory reading precision, and performing step B1; and returning to the reading failure after the decoding times exceed the set times.
2. The method of verifying multiplexing-based FTL of claim 1, wherein in the data writing, step A1 comprises:
step a1.1: dividing the DATA into DATA blocks with the same size according to the type of the page to be written, and dividing the DATA into N blocks to obtain DATA [0], DATA [1], … and DATA [ N-1];
step a1.2: respectively calculating CRC16 values of the N blocks of data;
step a1.3: searching fingerprint storage for whether the fingerprint has the same CRC16 value; if the same is used for the first time, step A2 is carried out; if not, a new fingerprint is generated and inserted into the fingerprint store, step A4 is performed.
3. The method of verifying multiplexing-based FTL of claim 1, wherein the step A2 comprises: calculating SHA1-256 check codes of the data, and performing deduplication; if the same SHA1-256 values are found, performing step A3; if the same SHA1-256 values are not found, the SHA1-256 check code in the fingerprint is replaced by the SHA1-256 values of the currently written data page, and step A4 is performed.
4. The method of verifying multiplexing-based FTL of claim 1, wherein said step A5 comprises: and writing the encoded data into the corresponding physical address of the SSD NAND flash memory, and storing the N CRC16 values of the page, the 1 SHA1-256 check code values and the related metadata information including the logical address of the page into the corresponding OOB area of the NAND flash memory.
5. The method for FTL based on check multiplexing of claim 1, wherein in the data reading, step B1 includes:
step B1.1: reading out voltage values of corresponding positions on the SSD NAND flash memory according to the given flash memory reading precision;
step B1.2: mapping the voltage value to a data value of 0,1, and obtaining a data page and other information.
6. The method for FTL based on check multiplexing of claim 1, wherein in the data reading, step B2 includes:
step B2.1: partitioning the data and calculating CRC16 value of each block of data;
step B2.2: comparing the CRC16 value read from the SSD with the calculated CRC16 value, and correcting and updating the LLR value of the data;
step B2.3: the corrected data LLR values are input to an LDPC decoder for decoding.
7. The method for FTL based on check multiplexing of claim 1, wherein in the data reading, step B3 includes:
step B3.1: judging whether the decoding is successful or not;
step B3.2: different schemes are carried out according to whether decoding is successful or not;
if the decoding is successful, returning the data, and if the reading is successful;
if the decoding fails, judging whether the current decoding times exceeds the maximum decoding times; if the maximum decoding times are exceeded, returning an NVME instruction with failed reading; if the maximum decoding frequency is not exceeded, setting a higher reading precision of the NAND flash memory, returning to the step B1, re-reading the voltage value of the data hall, and decoding.
8. The utility model provides a solid state disk FTL system based on check-up multiplexing which characterized in that includes: a data writing module and a data reading module;
wherein, the data write module includes:
module A1: calculating CRC16 check codes of the data, and performing data pre-deduplication;
module A2: calculating SHA1-256 check codes of the data, and performing data deduplication;
module A3: LDPC encoding the data;
module A4: writing the data and other information into the NAND flash memory of the SSD together;
the data reading module includes:
module B1: reading data and other information from the NAND flash memory of the SSD according to a given flash memory reading accuracy;
module B2: correcting LLR values of the data by using CRC16 check codes;
module B3: LDPC decoding the data;
module B4: detecting whether the decoding is successful, if so, returning data to the host, and if the reading is successful; if decoding fails, the flash memory reading precision is improved, and a module B1 is carried out; and after the decoding times exceed the set times, returning the NVME instruction with the failed reading.
9. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the steps of the check multiplexing based solid state disk FTL method of any of claims 1 to 7.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the computer program when executed by the processor implements the steps of the check multiplexing based solid state disk FTL method of any of claims 1 to 7.
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