CN116486858A - Memory device - Google Patents

Abstract

A memory device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The memory device also includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to the data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

Description

Memory device

Technical Field

Embodiments of the present application relate to a memory device.

Background

The integrated circuit processor needs to fetch data from memory. Dynamic Random Access Memory (DRAM) is often used. However, DRAM is not efficient in terms of access speed and power consumption. The inefficiency of data access is referred to as a "memory wall". High performance computing processors must overcome the "memory wall".

Disclosure of Invention

According to an aspect of embodiments of the present application, there is provided a memory device including: a write bit line and a read bit line extending in a first direction; a first write word line and a first read word line extending in a second direction perpendicular to the first direction; and a first memory cell, the first memory cell comprising: a first write transistor, the first write transistor comprising: a first gate connected to the first write word line; a first source/drain connected to the write bit line; and a second source/drain connected to the first data storage node; and a first read transistor, the first read transistor comprising: a second gate connected to the first data storage node; a third source/drain connected to the read bit line; and a fourth source/drain connected to the first read word line.

According to another aspect of embodiments of the present application, there is provided a memory device including: a memory array, the memory array comprising: a plurality of memory cell pairs arranged in a plurality of columns and a plurality of rows, wherein each memory cell pair of the plurality of memory cell pairs comprises: a first memory cell, the first memory cell comprising: a first write transistor configured to write first input data to the first data storage node in response to a first write signal; a first read transistor configured to output first output data to a read bit line in response to the first input data and a first read signal on the first data storage node; and a second memory unit including: a second write transistor configured to write second input data to the second data storage node in response to a second write signal; and a second read transistor configured to output second output data to the read bit line in response to the second input data and a second read signal on the second data storage node.

According to yet another aspect of embodiments of the present application, there is provided a memory device including: a write bit line and a read bit line extending in a first direction; a write word line and a read word line extending in a second direction perpendicular to the first direction; a memory cell, the memory cell comprising: a write transistor, comprising: a first gate connected to the write word line; a first source/drain connected to the write bit line; and a second source/drain connected to the data storage node; and a read transistor including: a second gate connected to the data storage node; a third source/drain connected to the read bit line; and a fourth source/drain connected to the read word line; the power supply node is a VDD node or a VSS node; and a pseudo transistor, the pseudo transistor comprising: a third gate connected to the power supply node; and a fifth source/drain connected to the data storage node.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a schematic diagram of a memory array according to some embodiments.

FIG. 2A illustrates a circuit diagram of a memory cell pair according to some embodiments.

FIG. 2B illustrates a circuit diagram of a plurality of memory cell pairs in adjacent rows, in accordance with some embodiments.

Fig. 3 illustrates a layout of a pair of memory cells including a dummy transistor in accordance with some embodiments.

Fig. 4 and 5 illustrate write operations of pairs of memory cells according to some embodiments.

FIG. 6 illustrates a read operation of a pair of memory cells according to some embodiments.

Fig. 7 illustrates a circuit diagram of a memory cell pair including a dummy transistor, in accordance with some embodiments.

Fig. 8 illustrates a circuit diagram of two adjacent pairs of memory cells sharing a dummy transistor, in accordance with some embodiments.

Fig. 9A and 9B illustrate layouts of a single fin memory cell pair and a multi-fin memory cell pair, respectively, including shared dummy transistors, in accordance with some embodiments.

FIG. 10 illustrates a layout of a memory cell pair including an elongated gate, according to some embodiments.

Fig. 11 illustrates a circuit diagram of a pair of memory cells formed using n-type transistors, in accordance with some embodiments.

Fig. 12 illustrates a layout of a pair of memory cells formed using n-type transistors, in accordance with some embodiments.

Fig. 13 and 14 illustrate write and read operations, respectively, of a pair of memory cells formed using n-type transistors, in accordance with some embodiments.

Fig. 15 illustrates a layout of a multi-fin memory cell pair formed using n-type transistors, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

A memory cell is provided, as well as a corresponding pair of memory cells and memory array. According to some embodiments of the present disclosure, a memory cell includes a write transistor configured to write input data to a data storage node in response to a write signal, and a read transistor configured to output data in response to data stored at the data storage node and a read signal. The write transistor has a first source/drain region (which may be a source region or a drain region) connected to the write bit line, and a second source/drain region connected to the data storage node. The first gate of the write transistor is connected to a write word line. The read transistor has a second gate connected to the data storage node, a third source/drain region connected to the read word line, and a fourth source/drain region connected to the read bit line. The memory cells may or may not include dummy transistors. Due to the small number of transistors (as few as two), the memory cell has a high operating speed and a small size. The embodiments discussed herein provide examples to make or use the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the intended scope of the different embodiments. Like reference numerals are used to denote like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Referring to fig. 1, a memory array 20 is formed. The memory array 20 includes a plurality of Memory Cell Pairs (MCPs), the MCPs being allocated into a plurality of rows and a plurality of columns. The total number of rows of memory cell pairs is m, m being an integer. The rows of memory cell pairs are thus denoted row-1, row-2. The integer m may be a multiple of 2 and may be a number selected from, for example, 64, 128, 256, 512, 1024, etc. Since each of the plurality of memory cell pairs MCP includes two memory cells, the total number of memory cells in the memory array is equal to 2*m.

The total number of columns of memory cell pairs is n, n being an integer. Columns of memory cell pairs are thus denoted as column-1, column-2. The integer n may also be a multiple of 2 and may be a number selected from, for example, 64, 128, 256, 512, 1024, etc. The locations of the memory cell pairs MCPs are indicated by their corresponding row numbers followed by column numbers. For example, a memory cell pair in m rows and n columns is identified as a memory cell pair MCPmn (or mcpm_n). It should be noted that when one or both of the row number and the column number include more than one bit, the row number and the column number may be separated by a symbol "_". For example, the memory cells MCP at row 10 and column 12 may be referred to as mcp10_12, rather than MCP1012. The total number of memory cell pairs is thus equal to (m n), while the total number of memory cells in the memory array 20 is equal to (2 m n).

Fig. 2A illustrates a circuit diagram of a two transistor (2T) memory cell pair MCP, in accordance with some embodiments. The memory cell pair MCP includes a memory cell MC0 and a memory cell MC1. Memory cells MC0 and MC1 may be mirror images of each other. Therefore, the memory cells MC0 and MC1 are sometimes also referred to as being line symmetric with each other. According to some embodiments, each of memory cells MC0 and MC1 includes two transistors, and thus corresponding memory cells MC0 and MC1 are referred to as 2T gain cells. According to alternative embodiments, each of memory cells MC0 and MC1 may include more than two transistors, such as 2.5 transistors, three transistors, and so forth.

The memory cell MC0 includes a write transistor MW0 and a read transistor MR0. The memory cell MC1 includes a write transistor MW1 and a read transistor MR1. A first terminal (e.g., source) of write transistor MW0 is coupled to (and may be directly connected to) write bit line WBL. A second terminal (e.g., drain) of write transistor MW0 is coupled to (and may be directly connected to) data storage node NS0. The control terminal (gate) of write transistor MW0 is coupled to (and may be directly connected to) write word line WWL0.

A first terminal (e.g., source) of the read transistor MR0 is coupled to (and may be directly connected to) the read bit line RBL. A second terminal (e.g., drain) of the read transistor MR0 is coupled to (and may be directly connected to) the read word line RWL0. The control terminal (gate) of the read transistor MR0 is coupled to (and may be directly connected to) the data storage node NS0.

The memory cell MC1 includes a write transistor MW1 and a read transistor MR1. A first terminal (e.g., source) of write transistor MW1 is coupled to write bit line WBL. A second terminal (e.g., drain) of write transistor MW1 is coupled to data storage node NS1. The control terminal (gate) of write transistor MW1 is coupled to write word line WWL1.

A first terminal (e.g., source) of the read transistor MRl is coupled to the read bit line RBL. A second terminal (e.g., drain) of the read transistor MR1 is coupled to the read word line RWL1. The control terminal (gate) of the first read transistor MR1 is coupled to the data storage node NS1.

According to some embodiments, the connection of the write transistor MW0 and the read transistor MR0 to the read bit line, write bit line, read word line, write word line, etc. is a direct connection, without additional devices such as resistors, capacitors, etc. According to alternative embodiments, some of the connections of the write transistor MW0 and the read transistor MR0 to the read bit line, write bit line, read word line, write word line, etc. are indirect connections, which may include additional devices such as resistors, capacitors, etc.

According to some embodiments, all transistors in the memory cell pair CMP (including the write transistors MW0 and MWl and the read transistors MR0 and MRl) are of the same type, e.g., p-type (with p-type source and drain regions) or n-type (with n-type source and drain regions). Furthermore, all transistors in a memory cell pair may have the same structure, such as planar transistor structures, fin field effect transistor (FinFET) structures, full-gate-all-around (GAA) transistor structures, and the like.

Fig. 2B illustrates a circuit diagram of a plurality of adjacent two transistor (2T) memory cell pairs MCP in the same column, in accordance with some embodiments. Multiple memory cell pairs MCP share the same write bit line WBL and the same read bit line RBL, and have separate write bit lines and read bit lines.

According to some embodiments, adjacent rows of memory cell pairs MCP may be separated from each other by dummy transistors MDl and/or MD2. The dummy transistors MD1 and MD2 are transistors that function completely normally and are turned off all the time during operation of the memory array 20. According to some embodiments in which the dummy transistors MD1 and MD2 are p-type transistors, a high voltage (such as VDD) may be connected to the gates of the dummy transistors MD1 and MD2 to turn off these transistors. The source and drain regions of dummy transistors MD1 and MD2 are connected to data storage nodes NS0 and NS1 in adjacent pairs of memory cells MCP. The function of the dummy transistors MD1 and MD2 can be found in the discussion of fig. 3 which follows. The dummy transistors MD1 and MD2 may have the same conductivity type as the write transistors MW0 and MW1 and the transistors MR0 and MR1, or have the opposite conductivity type.

Fig. 3 illustrates an example layout of the embodiment shown in fig. 2B. It will be appreciated that the layout shown in fig. 3 (as well as the layout in the other figures) is also a top view of memory devices formed on a physical wafer, such as a silicon wafer. The layout shown uses finfets as an example, but other types of transistors may be used.

A plurality of (semiconductor) FINs (labeled FIN, including a plurality of FINs FIN0 and FIN 1) are formed parallel to each other and extend in the Y direction. A plurality of gate stacks (gates) extend in the X-direction. The gate stacks include gate stack GD, which is a gate stack of dummy transistors MD1 and MD2. The gate stack GD may be connected to the positive power supply voltage VDD when the dummy transistors MD1 and MD2 are p-type transistors, and may be connected to the power supply voltage VSS (electrical ground) when the dummy transistors MD1 and MD2 are n-type transistors. The gate stack further includes a gate stack GF, which is a gate stack including functional transistors of the write transistors MW0 and MW1 and the read transistors MR0 and MR1.

The data storage nodes NS0 and NS1 may be formed between adjacent gate stacks GF and GD. According to some embodiments, the data storage nodes NS0 and NS1, the read word lines RWL0 and RWL1, the read bit line RBL, and the write bit line WBL may include source/drain regions and corresponding source/drain contact plugs.

As shown in fig. 3, three pairs of memory cells MCP11, MCP21, and MCP31 are located in adjacent rows. In each of the memory cell pairs MCP11, MCP21, and MCP31, the memory cells MC0 and MC1 are line-symmetrical to each other with respect to a straight line that is located in the middle of the corresponding memory cell pair and extends in the X direction. For example, memory cells MC0 and MC1 in memory cell pair MCP11 are line symmetric about line 26. Alternatively, the memory cells MC0 and MC1 in each memory cell pair are inverted with respect to a first straight line (a straight line extending in the X direction) located in the middle of the corresponding memory cell pair.

According to some embodiments, the write transistors MW0 and MWl of all pairs of memory cells in the same column share the same semiconductor FIN (such as FIN 0) that can be turned off at a selected location. The read transistors MR0 and MR1 of all memory cell pairs in the same column share the same semiconductor FIN (such as FIN 1). Further, the semiconductor FIN0 is connected to the write bit line WBL and extends into all memory cells in the same column. The semiconductor FIN1 is connected to the read bit line RBL and extends into all memory cells in the same column.

As shown in fig. 3, the data storage node NS0 in the memory cell pair MCP11 is adjacent to the data storage node NS1 in the memory cell pair MCP21 by a small distance due to the compact size of the memory cell pair. The dummy transistor MD1 is formed between adjacent data storage nodes NS0 and NS1. According to some embodiments in which the dummy transistor MD1 is a p-type transistor, the voltage VDD is applied to the gate GD of the dummy transistor MD1. The dummy transistor MD1 is turned off and thus electrically and signally disconnects the data storage node NS0 in the memory cell pair MCP11 from the data storage node NS1 in the memory cell pair MCP 21.

According to an alternative embodiment, instead of electrically disconnecting two adjacent data storage nodes NS0 and NS1 by means of the dummy transistor MD1, the FIN0 may be physically cut at the location of the gate GD, such that the adjacent data storage nodes NS0 and NS1 are physically (and also electrically) separated from each other. In this case, the dummy gate GD of the dummy transistor MD1 will not be formed. The corresponding circuit diagram is similar to that shown in fig. 2B, except that the dummy transistor MD1 will not be formed.

Similarly, the read word line RWL0 in the memory cell pair MCP11 is adjacent to the read word line RWL1 in the memory cell pair MCP21 by a small distance due to the compact size of the memory cell pair. The dummy transistor MD2 is formed between adjacent read word lines RWL0 and RWL1. According to some embodiments in which the dummy transistor MD2 is a p-type transistor, the voltage VDD is applied to the gate GD of the dummy transistor MD2. The dummy transistor MD2 is turned off, and the read word line RWL0 in the memory cell pair MCP11 is electrically disconnected from the read word line RWL1 in the memory cell pair MCP21 and the signal is turned off.

According to an alternative embodiment, instead of electrically disconnecting two adjacent read word lines RWL0 and RWL1 by the dummy transistor MD2, the fin FINl may be physically cut at the location of the gate GD, so that the adjacent read word lines RWL0 and RWL1 are physically (and also electrically) separated from each other. In this case, the dummy gate GD of the dummy transistor MD2 will not be formed. The corresponding circuit diagram is similar to that shown in fig. 2B, except that the dummy transistor MD2 will not be formed.

An example write operation according to some embodiments is discussed below with reference to fig. 4 and 5. Fig. 4 illustrates the corresponding signals for the write operation, while fig. 5 illustrates a table showing the lines and nodes in the memory cell pair MCP and the corresponding signals/voltages during the write operation. The example transistor discussed with reference to fig. 4 is a p-type transistor.

Referring to fig. 4, assuming that at a time, to write the memory cell MC0, the write transistor MW0 is selected by the write signal SW0, the write signal SW0 may be equal to the voltage VSS as shown in fig. 5. Thus, the write transistor MW0 is turned on. The write transistor MW0 writes the first input data DIN0 on the write bit line WBL to the data storage node NS0. Therefore, the logic value on the data storage node NS0 is written with the same logic value as the logic value of the input data DIN 0. The stored data may be "H" (high) or "L" (low) corresponding to a high voltage signal (such as VDD) and a low voltage signal (such as VSS), respectively.

At the time of performing the write operation, the read signal DR0 (fig. 4) on the read word line RWL0 is equal to the low voltage VSS. Therefore, no current is flowing on the read bit line RBL regardless of the logic value (high or low, as in FIG. 5) on the data storage node NS0. Thus, power consumption during write operations is reduced.

Fig. 4 and 6 in combination illustrate example read operations according to some embodiments. Fig. 4 illustrates corresponding signals for a read operation, and fig. 6 illustrates a table showing lines and nodes and corresponding signals during a read operation. Assuming that at a time, to read the memory cell MC0, the write transistor MW0 is selected by the first write signal SW0 (sw0=vdd) on the write word line WWL0. Thus, the write transistor MW0 is turned off. Data node NS0 is now a floating node. The read signal DR0 is applied to the read word line RWL0. The read signal DR0 is equal to the read voltage Vread, which is a non-zero voltage. The read voltage Vread is a voltage greater than VSS, and may be equal to or less than the voltage VDD. The read voltage Vread may be generated by a voltage source 22.

When the data storage node NS0 stores the data "H", the read transistor MR0 is turned off (fig. 6). Thus, the output data on the read bit line RBL is associated with "no current" on the read bit line RBL. Conversely, when the data storage node NS0 stores the data "L", the read transistor MR0 is turned on (fig. 6). Thus, the output data on the read bit line RBL is associated with a "read current" on the read bit line RBL. The current on the read bit line RBL can be detected by a current detection circuit 24 connected to the read bit line RBL. The "read current" is related to the voltage Vread, the higher the current on the read bit line RBL. In order to reduce power consumption, the voltage Vread is reduced as long as the generated current can be reliably detected by the current detection circuit. For example, the voltage Vread may be in a range between about (1/5) x VDD and VDD, and according to some embodiments, may also be in a range between about (1/5) x VDD and about (4/5) x VDD. The operation of memory cell MC1 is essentially the same as memory cell MC 0.

Referring back to fig. 1, control circuitry 28 is connected to memory array 20 and controls the operation of memory array 20. For example, write operations and read operations of the memory array 20 are controlled by the control circuit 28. The circuitry of control circuit 28 may include a word line controller, a bit line controller, a voltage source (including voltage source 22 in fig. 4), current detection circuit 24 in fig. 4, the turn-off of a dummy transistor, and the like. The control circuitry 28 may control and synchronize write operations and read operations of the memory array 20.

Fig. 7 illustrates a three transistor (3T) memory cell pair MCP, where each of memory cells MC0 and MC1 includes a write transistor (MW 0 or MW 1), a read transistor (MR 0 or MR 1), and a dummy transistor (MD 0 or MD 1). The gates of the dummy transistors MD0 and MD1 are connected to a high voltage such as the voltage VDD. Thus, during the entire operation of memory array 20, dummy transistors MD0 and MD1 are always turned off by voltage VDD. The dummy transistors MD0 and MD1 function to prevent the memory cells and/or nodes in the memory cell pair (such as data storage node NS0 and data storage node NS 1) from interfering with their neighboring memory cells or memory cell pairs. The operation of the write transistors MW0 and MW1 and the read transistors MR0 and MR1 during the read operation and the write operation is the same as that discussed with reference to fig. 4, 5 and 6, and will not be repeated here.

Fig. 8 illustrates a circuit diagram of portions of memory cell pairs MCPA and MCPB in adjacent pairs of memory cells (in adjacent rows) in accordance with some embodiments. These embodiments are similar to the embodiment shown in fig. 7, except that instead of having dedicated dummy transistors in each memory cell MC0 and MC1, two dummy transistors MD1 and MD2 are formed, shared by adjacent pairs of memory cells MCPA and MCPB, respectively. This can also be considered as having half of each dummy transistor MD1 and MD2 per memory cell MC. Thus, each memory cell MC has on average three transistors, including one write transistor, one read transistor, and half of each of the two dummy transistors MD1 and MD2. Similarly, the write word line WWL is connected to the gate of the write transistor MW. The write bit line WBL is connected to the source/drain region of the write transistor MW. The read bit line RBL is connected to the source/drain region of the read transistor MR. The read word line RWL is connected to the source/drain region of the read transistor MR.

The dummy transistors MD1 and MD2 are also turned off during the entire operation of the memory cell and corresponding memory array 20 (fig. 1). According to some embodiments, the dummy transistors MD1 and MD2 are p-type transistors, and the high voltage VDD may be connected to the gates of the p-type dummy transistors MD1 and MD2 to turn them off. According to an alternative embodiment, two n-type dummy transistors MD1 and MD2 are formed and their gates are connected to the voltage VSS such that the n-type dummy transistors MD1 and MD2 are turned off. The source/drain region of the dummy transistor MD1 is connected to adjacent data storage nodes NS in adjacent memory cell pairs MCPA and MCPB, thus electrically and signally decoupling adjacent data storage nodes NS from each other. The source/drain regions of dummy transistor MD2 are connected to read word lines RWL0 and RWL1, thus electrically and signal-decoupling read word lines RWL0 and RWL1 in adjacent pairs of memory cells MCPA and CMPB from each other.

Fig. 9A illustrates a layout of the circuit shown in fig. 8. It can be observed that the gate GD of the dummy transistor MD1 extends over the semiconductor FIN 1. The portion of the semiconductor FIN1 in the memory cell pair MCPA is connected to a data storage node NS (labeled NSA). The portion of the semiconductor FIN1 in the memory cell pair MCPB is connected to a data storage node NS (labeled NSB). Thus, the dummy transistor MD1 electrically decouples the data storage nodes NSA and NSB from each other. The gate GD of the dummy transistor MD2 is on the semiconductor FIN 0. The portion of the semiconductor FIN0 in the memory cell pair MCPA is connected to a read word line RWL (labeled RWLA). A portion of the semiconductor FIN1 in the memory cell pair MCPB is connected to a read word line RWL (labeled RWLB). Thus, the dummy transistor MD2 electrically decouples the read word lines RWLA and RWLB from each other. According to some embodiments, dummy transistors MD1 and MD2 in the same row share the same gate GD, which is an elongated gate that extends into all columns of memory array 20.

Fig. 9B illustrates a layout of the circuit shown in fig. 8. The layout is similar to that shown in fig. 9A, except that fig. 9B illustrates a multi-fin transistor, while fig. 9A illustrates a single-fin transistor. Further, in fig. 9B, a plurality of semiconductor FINs FIN2 are connected to and serve as the write bit lines WBL in one column. The plurality of semiconductor FINs FIN3 are connected to and serve as the read bit lines RBL in one column. The response speed and the output current value of the memory cell may increase with the number of semiconductor fins. According to some embodiments, the pair of memory cells based on FINs FIN0 and FIN1 are symmetric to the pair of memory cells based on FINs FIN2 and FIN 3.

Fig. 10 illustrates a layout of the memory cell pairs MCP11 and MCP 21. According to these embodiments, a single gate stack GD in the memory cell pair MCP21 extends to both semiconductor FINs FIN0 and FIN1, and thus forms both dummy transistors MD1 and MD2.

Fig. 11 illustrates portions of a memory cell pair MCPA and MCPB in accordance with some embodiments. These embodiments are similar to the embodiment shown in fig. 8, except that instead of using p-type transistors, n-type transistors are used to form pairs of memory cells MC and MCP and MCPB. The illustrated portion includes half of the memory cell pair MCPA and half of the memory cell pair MCPB. The overall structure of each memory cell pair MCPA and MCPB is similar to the memory cell pair shown in fig. 2A, 2B, and 4, with the transistor changed to an n-type transistor.

According to some embodiments, two n-type dummy transistors MDl and MD2 are formed, shared by two memory cell pairs MCPA and MCPB, respectively. This can also be considered as having half of each dummy transistor MD1 and MD2 per memory cell MC. Thus, each memory cell MC has on average three transistors, including one write transistor, one read transistor, and half of each of the two dummy transistors MD1 and MD2. Similarly, the write word line WWL is connected to the gate of the write transistor MW. The write bit line WBL is connected to the source/drain region of the write transistor MW. The read bit line RBL is connected to the source/drain region of the read transistor MR. The read word line RWL is connected to the source/drain region of the read transistor MR.

The dummy transistors MD1 and MD2 are also turned off during the entire operation of the memory cell and the corresponding memory array 20. According to some embodiments, n-type dummy transistors MD1 and MD2 are used, and a low voltage (such as voltage VSS) may be connected to the gates of n-type dummy transistors MD1 and MD2 to turn them off. The source/drain region of the dummy transistor MD1 is connected to adjacent data storage nodes NS in adjacent memory cell pairs MCPA and MCPB, thus electrically and signally decoupling adjacent data storage nodes NS from each other. The source/drain regions of dummy transistor MD2 are connected to adjacent read word lines RWL, thus electrically and signally decoupling the read word lines RWL in adjacent memory cell pairs MCPA and CMPB from each other. According to an alternative embodiment, two p-type dummy transistors MD1 and MD2 may be used in the structure shown in fig. 11, and the gates of the p-type dummy transistors MD1 and MD2 are connected to a high voltage such as the voltage VDD, so that the p-type dummy transistors MD1 and MD2 are turned off.

Fig. 12 shows a layout of the circuit shown in fig. 11. It can be observed that the gate GD of the dummy transistor MD1 extends over the semiconductor FIN 1. The portion of the semiconductor FIN1 in the memory cell pair MCPA is connected to a data storage node NS (labeled NSA). The portion of the semiconductor FIN1 in the memory cell pair MCPB is connected to a data storage node NS (labeled NSB). Thus, the dummy transistor MD1 electrically decouples the data storage nodes NSA and NSB from each other. The gate GD of the dummy transistor MD2 extends over the semiconductor FIN 0. The portion of the semiconductor FIN0 in the memory cell pair MCPA is connected to a read word line RWL (labeled RWLA). A portion of the semiconductor FIN1 in the memory cell pair MCPB is connected to a read word line RWL (labeled RWLB). Thus, the dummy transistor MD2 electrically decouples the read word lines RWLA and RWLB from each other.

According to some embodiments, example write operations of an MCP cell formed by an n-type transistor (fig. 11) are discussed below. FIG. 13 illustrates a table showing lines and nodes in a memory cell pair MCP and corresponding signals during a write operation.

Assuming that at a time, the memory cell MC is to be written, the write transistor MW is selected by the write signal SW, which may be equal to the voltage VDD, as shown in fig. 13. Thus, the write transistor MW is turned on. The write transistor MW writes the input data on the write bit line WBL to the corresponding data storage node NS. Thus, the logical value on the data storage node NS is written with the same value as the logical value of the input data. The stored data may be "H" (high) or "L" (low) corresponding to a high voltage signal (such as voltage VDD) and a low voltage signal (such as voltage VSS), respectively.

At the time of performing the write operation, the read signal DR on the corresponding read word line RWL is equal to a low voltage (such as voltage VSS). Therefore, no current is present on the read bit line RBL regardless of the logic value (high or low, as shown in FIG. 5) on the data storage node NS. Thus, power consumption during write operations is reduced.

FIG. 14 illustrates an example read operation in accordance with some embodiments. FIG. 14 illustrates a table showing lines and nodes in corresponding memory cells during a read operation. Assume that at a time, to read memory cell MC (fig. 11), write transistor MW is selected by signal SW, which is low voltage VSS. Thus, the write transistor MW is turned off. The data node NS is now a floating node. The read signal DR is applied to the read word line RWL. The read signal is equal to the read voltage Vread, which is a non-zero voltage. The read voltage Vread is a voltage greater than VSS, and may be equal to or less than the voltage VDD. The read voltage Vread may be generated by a voltage source 25 (fig. 11) in a control circuit 28 (fig. 1).

When the data storage node NS stores the data "L", the read transistor MR is turned off (fig. 11). Thus, the output data on the read bit line RBL is associated with "no current" on the read bit line RBL. Conversely, when the data storage node NS stores the data "H", the read transistor MR is turned on (fig. 11). Accordingly, the output data on the read bit line RBL is associated with a "read current" on the read bit line RBL, which can be detected by a current detection circuit 24 (fig. 4) connected to the read bit line RBL. The "read current" is related to the voltage Vread, and the higher the voltage Vread, the higher the current generated on the read bit line RBL. In order to reduce power consumption, the voltage Vread is kept low as long as the generated current can be reliably detected by the current detection circuit. For example, according to some embodiments, the voltage Vread may be in a range between about (1/5) x VDD and VDD, and may also be in a range between about (1/5) x VDD and about (4/5) x VDD.

Fig. 15 illustrates a layout of the circuit shown in fig. 11. The layout is similar to that shown in fig. 9B, except that the source/drain regions of the transistor are n-type source/drain regions doped with n-type dopants. The transistors in the memory cells are multi-fin transistors. Accordingly, the response speed and the output current value of the memory cell will increase with an increase in the number of semiconductor fins.

Embodiments of the present disclosure have some advantageous features. Memory cells according to embodiments of the present invention have a small number of transistors. The operating speed of the corresponding memory array is improved. Increasing the density of the memory array. The memory array may thus be used as a cache memory for a high performance computing processor.

According to some embodiments of the present disclosure, a memory device includes: a write bit line and a read bit line extending in a first direction; a first write word line and a first read word line extending in a second direction perpendicular to the first direction; a first memory cell comprising a first write transistor, the first write transistor comprising: a first gate connected to the first write word line; a first source/drain connected to the write bit line; a second source/drain connected to the first data storage node; a first read transistor, the first read transistor comprising: a second gate connected to the first data storage node; a third source/drain connected to the read bit line; a fourth source/drain connected to the first read word line. In one embodiment, the first gate is connected to the first write word line by a direct connection; the first source/drain is connected to the write bit line by a direct connection; the second gate is connected to the first data storage node by a direct connection; and the third source/drain is connected to the read bit line by a direct connection.

In one embodiment, the total number of transistors in the first memory cell is equal to two. In one embodiment, the first write transistor and the first read transistor are both p-type transistors. In one embodiment, the first write transistor and the first read transistor are both n-type transistors. In one embodiment, the memory device further comprises: a second write word line and a second read word line extending in a second direction; and a second memory cell having the same structure as the first memory cell, wherein the second memory cell is connected to the write bit line, the read bit line, the second write word line, and the second read word line, and wherein the first memory cell and the second memory cell are combined to form a first memory cell pair. In one embodiment, the memory device further comprises: a second pair of memory cells adjacent to the first pair of memory cells; and a dummy transistor connected between the first memory cell pair and the second memory cell pair.

In one embodiment, a dummy transistor includes: a first source/drain region connected to a first data storage node of a first memory cell of the first memory cell pair; and a second source/drain region connected to a second data storage node of a second memory cell of the second pair of memory cells. In one embodiment, a dummy transistor includes: a first source/drain region connected to a first read word line of a first memory cell of the first memory cell pair; and a second source/drain region connected to a second read word line of a second memory cell of the second pair of memory cells. In one embodiment, the memory device further includes a current sense circuit connected to the read bit line. In one embodiment, the memory device further comprises a voltage source circuit connected to the first write word line, wherein the voltage source circuit is configured to output a non-zero voltage that is lower than the positive power supply voltage VDD.

According to some embodiments of the present disclosure, a memory device includes a memory array including a plurality of memory cell pairs arranged in a plurality of columns and a plurality of rows, wherein each of the plurality of memory cell pairs includes a first memory cell, the first memory cell including: a first write transistor configured to write first input data to the first data storage node in response to a first write signal; a first read transistor configured to output first output data to a read bit line in response to first input data and a first read signal on a first data storage node; a second memory cell, the second memory cell comprising: a second write transistor configured to write second input data to the second data storage node in response to a second write signal; and a second read transistor configured to output second output data to the read bit line in response to the second input data and the second read signal on the second data storage node. In one embodiment, the first memory cell and the second memory cell are located in adjacent rows of the memory array.

In one embodiment, the memory device further includes a VDD voltage node; and a p-type dummy transistor including a source/drain region connected to the first data storage node, wherein the p-type dummy transistor includes a gate connected to the VDD voltage node. In one embodiment, the memory device further comprises: a VSS voltage node; and an n-type dummy transistor including a source/drain region connected to the first data storage node, wherein the n-type dummy transistor includes a gate connected to the VSS voltage node. In one embodiment, the memory device further comprises: and a current detection circuit connected to the read bit line, wherein the current detection circuit is configured to measure a current on the read bit line.

According to some embodiments of the present disclosure, a memory device includes: a write bit line and a read bit line extending in a first direction; a write word line and a read word line extending in a second direction perpendicular to the first direction; a memory cell, comprising: a first gate connected to the write word line; a first source/drain connected to the write bit line; and a second source/drain connected to the data storage node; and a read transistor including: a second gate connected to the data storage node; a third source/drain connected to the read bit line; and a fourth source/drain connected to the read word line; the power supply node is a VDD node or a VSS node; and a pseudo transistor comprising: a third gate connected to the power supply node; and a fifth source/drain connected to the data storage node. In one embodiment, the dummy transistor is a p-type transistor, and wherein the power supply node is a VDD node. In one embodiment, the dummy transistor is an n-type transistor, and wherein the power supply node is a VSS node. In one embodiment, the memory cell is a two transistor cell.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A memory device, comprising:

a write bit line and a read bit line extending in a first direction;

a first write word line and a first read word line extending in a second direction perpendicular to the first direction; and

a first memory cell, the first memory cell comprising:

a first write transistor, the first write transistor comprising:

a first gate connected to the first write word line;

a first source/drain connected to the write bit line; and

a second source/drain connected to the first data storage node; and

a first read transistor, the first read transistor comprising:

a second gate connected to the first data storage node;

a third source/drain connected to the read bit line; and

and a fourth source/drain connected to the first read word line.

2. The memory device of claim 1, wherein:

the first gate is connected to the first write word line by a direct connection;

the first source/drain is connected to the write bit line by a direct connection;

the second gate is connected to the first data storage node by a direct connection; and is also provided with

The third source/drain is connected to a read bit line by a direct connection.

3. The memory device of claim 1, wherein a total number of transistors in the first memory cell is equal to two.

4. The memory device of claim 1, wherein the first write transistor and the first read transistor are both p-type transistors.

5. The memory device of claim 1, wherein the first write transistor and the first read transistor are both n-type transistors.

6. The memory device of claim 1, further comprising:

a second write word line and a second read word line extending in the second direction; and

a second memory cell having the same structure as the first memory cell, wherein the second memory cell is connected to the write bit line, the read bit line, the second write word line, and the second read word line, and wherein the first memory cell and the second memory cell are combined to form a first memory cell pair.

7. The memory device of claim 6, further comprising:

a second pair of memory cells adjacent to the first pair of memory cells; and

and a dummy transistor connected between the first memory cell pair and the second memory cell pair.

8. The memory device of claim 7, wherein the pseudo transistor comprises:

a first source/drain region connected to the first data storage node of the first memory cell pair; and

a second source/drain region connected to a second data storage node of the second memory cell of the second pair of memory cells.

9. A memory device, comprising:

a memory array, the memory array comprising:

a plurality of memory cell pairs arranged in a plurality of columns and a plurality of rows, wherein each of the plurality of memory cell pairs comprises:

a first memory cell, the first memory cell comprising:

a first write transistor configured to write first input data to the first data storage node in response to a first write signal;

a first read transistor configured to output first output data to a read bit line in response to the first input data and a first read signal on the first data storage node; and

a second memory cell, the second memory cell comprising:

a second write transistor configured to write second input data to the second data storage node in response to a second write signal; and

a second read transistor configured to output second output data to the read bit line in response to the second input data and a second read signal on the second data storage node.

10. A memory device, comprising:

a write bit line and a read bit line extending in a first direction;

a write word line and a read word line extending in a second direction perpendicular to the first direction;

a memory cell, the memory cell comprising:

a write transistor, the write transistor comprising:

a first gate connected to the write word line;

a first source/drain connected to the write bit line; and

a second source/drain connected to the data storage node; and

a read transistor, the read transistor comprising:

a second gate connected to the data storage node;

a third source/drain connected to the read bit line; and

a fourth source/drain connected to the read word line;

a power supply node, wherein the power supply node is a VDD node or a VSS node; and

a dummy transistor, the dummy transistor comprising:

a third gate connected to the power supply node; and

and a fifth source/drain connected to the data storage node.