CN116486851A - Data control circuit and memory device - Google Patents

Abstract

A data control circuit includes a first latch circuit, a self-resistance circuit, a second latch circuit, a third latch circuit, a first data timing mark signal generating circuit, and a second data timing mark signal generating circuit. The first latch circuit is used for receiving the data window signal. The self-resistance circuit is coupled to the first latch circuit and is used for generating a protection signal. The second latch circuit is coupled to the self-resistance circuit and is used for outputting a first data time sequence marking signal. The third latch circuit is coupled to the second latch circuit and is used for outputting a second data timing mark signal. The first data timing mark signal generating circuit is used for generating a third data timing mark signal. The second data timing mark signal generating circuit is used for generating a fourth data timing mark signal.

Description

Data control circuit and memory device

Technical Field

The present invention relates to a double data rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR SDRAM), and more particularly, to a data control circuit for increasing a maximum and minimum tolerance of skew (skew) between data strobe (DQS) signals and clock pulse signals during a write operation, and a related memory device.

Background

With the development of DDR SDRAM, tDQSS, which limits the relative relationship between the rising edge of the data strobe signal and the rising edge of the clock pulse signal during a write operation, that is, tDQSS represents the maximum tolerance value and the minimum tolerance value of skew between the data strobe signal and the clock pulse signal during a write operation, is defined in the specification of DDR SDRAM due to the increase in data transfer speed. By limiting the size of tDQSS, DDR SDRAM can be operated correctly and erroneous data can be prevented from being written to DDR SDRAM, however, the value of tDQSS is also increased in the specification of DDR SDRAM in response to the faster and faster data transfer speed of DDR SDRAM. In the specification of DDR2 SDRAM, tDQSS is required to be greater than ± 0.25 clock cycle time (tCK). In the specification of DDR3 SDRAM, tDQSS increases in value to ±0.27 tck. In a later development of DDR4 SDRAM, tDQSS2 is defined when DDR4 SDRAM is operated in 2-fold clock pre-mode (2-clock preamble mode), and the value of tDQSS2 may reach + -0.5 tCK.

Manufacturers of DDR SDRAM will set the design targets of tDQSS to be larger than that defined in DDR SDRAM specifications, in the prior art, tDQSS can be processed up to ±0.4tck, however, after tDQSS2 appears, the requirements of DDR4 SDRAM specifications cannot be met according to the prior art, and in addition, in the prior art, it is often required to precisely reach the design targets of tDQSS, which results in poor design flexibility. Therefore, there is a strong need for a data control circuit for increasing the maximum and minimum tolerance of the deviation between the data strobe signal and the clock pulse signal during the data writing period, and related memory device.

Disclosure of Invention

It is therefore one of the objectives of the present invention to provide a data control circuit for increasing the maximum and minimum tolerance of the deviation between the data strobe signal and the clock pulse signal during the data writing period, and a related memory device for solving the above-mentioned problems.

According to an embodiment of the present invention, a data control circuit is provided for increasing a maximum tolerance value and a minimum tolerance value of a deviation between a data strobe signal and a clock pulse signal during data writing. The data control circuit may include a first latch circuit, a self-resistance circuit, a second latch circuit, a third latch circuit, a first data timing mark signal generating circuit, and a second data timing mark signal generating circuit. The first latch circuit has a first clock pulse port for receiving a first clock pulse derived from a data strobe signal, a first input port for receiving a data window signal, and a first output port. The self-resistance circuit may be coupled to the first output port of the first latch circuit and configured to generate the protection signal according to the self-resistance signal and an output at the first output port of the first latch circuit. The second latch circuit has a second clock port for receiving a second clock signal derived from the data strobe signal, a second input port coupled to the self-impedance circuit for receiving the protection signal, and a second output port for outputting the first data timing mark signal. The third latch circuit has a third clock port for receiving the first clock, a third input port coupled to the second output port of the second latch circuit for receiving the first data timing mark signal, and a third output port for outputting the second data timing mark signal. The first data timing mark signal generating circuit may be coupled to the third output port of the third latch circuit and configured to generate a third data timing mark signal according to the second data timing mark signal. The second data timing mark signal generating circuit may be coupled to the first data timing mark signal generating circuit and configured to generate a fourth data timing mark signal according to the third data timing mark signal.

According to one embodiment of the present invention, a memory device is provided. The memory device may include a command input interface, a command decoder, memory cell circuitry, a data input/output interface, and data processing circuitry. The command input interface is operable to receive a plurality of command signals. The command decoder is coupled to the command input interface and is configured to receive and decode a plurality of command signals to generate a data window signal and a control signal, wherein the data window signal corresponds to the write command. The memory cell circuit may be coupled to the command decoder and have a plurality of memory banks, wherein the memory cell circuit is controlled by the control signal. The data input/output interface is used for receiving a plurality of data signals and a data strobe signal, wherein the plurality of data signals correspond to a plurality of data to be written and are transmitted in a serial communication mode. The data processing circuit may include a serial-to-parallel circuit and a data control circuit. The serial-to-parallel circuit is coupled to the data input/output interface and the memory cell circuit and is configured to convert a plurality of data signals into a plurality of data input signals according to the data strobe signal, the second data timing mark signal and the fourth data timing mark signal, wherein the plurality of data input signals are transmitted to the memory cell circuit in parallel communication. The data control circuit may be coupled to the command decoder, the data input/output interface, and the serial-to-parallel circuit.

One of the benefits of the present invention is that by using the data control circuit provided by the present invention, the maximum and minimum tolerance of skew between and in the data strobe signal during write operations can be increased and the requirements of the size of tDQSS2 defined in the specification of DDR4 SDRAM can be met, furthermore, for the tDQSS case, the pulse width of the data window signal can reach 1 tck in the prior art, which can handle the value of tDQSS up to ±0.4tck in the specification of DDR SDRAM, in fact, it is difficult to precisely make the pulse width of the data window signal exactly 1 tck. However, once the pulse width of the data window signal is greater than 1 tck, the DDR SDRAM can be easily manufactured by the manufacturer of the DDR SDRAM, and the data control circuit provided by the present invention can easily achieve the pulse width of the data window signal greater than 1 tck, and various pulse widths (e.g., 1.3 tck, 1.4 tck, or 1.5 tck) can be selected, so the present invention has high design flexibility.

Drawings

FIG. 1 is a block diagram of a memory device according to one embodiment of the invention.

FIG. 2 is a block diagram of the data processing circuit shown in FIG. 1 according to one embodiment of the present invention.

FIG. 3 is a schematic diagram of the data control circuit shown in FIG. 2 according to one embodiment of the present invention.

FIG. 4 is a timing diagram of clock signals, data strobe signals, data window signals, and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS2 according to one embodiment of the invention.

FIG. 5 is a timing diagram of clock signals, data strobe signals (which first rise after the operation timing of a write command), data window signals, and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS2 according to one embodiment of the invention.

FIG. 6 is a timing diagram of clock signals, data strobe signals (which first rise before the operation timing of a write command), data window signals, and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS2 according to one embodiment of the invention.

FIG. 7 is a timing diagram of clock signals, data strobe signals, data window signals, and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS according to one embodiment of the invention.

FIG. 8 is a timing diagram of clock signals, data strobe signals (which first rise after the operation timing of a write command), data window signals, and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS according to one embodiment of the invention.

FIG. 9 is a timing diagram of clock signals, data strobe signals (which first rise before the operation timing of a write command), data window signals, and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS according to one embodiment of the invention.

FIG. 10 is a timing diagram of clock signals, data strobe signals, data window signals and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS2 according to another embodiment of the invention.

Detailed Description

FIG. 1 is a block diagram of a memory device 100 according to one embodiment of the invention. The memory device 100, such as a double data rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR SDRAM), may include a command input interface 10, a command decoder 12, a memory cell (memory cell) circuit 14, an input/output (I/O) interface 16, and a data processing circuit 18. The COMMAND input interface 10 may be configured to receive a plurality of COMMAND SIGNALs command_signal, wherein the COMMAND SIGNALs command_signal may include a write COMMAND WR, a differential pair of memory clock SIGNALs (i.e., a true clock SIGNAL ck_t and a complementary clock SIGNAL ck_c), a clock enable SIGNAL CKE, a chip select SIGNAL cs_n, and a plurality of address SIGNALs (e.g., BG0, BG1, BA0, BA1, and A0-a 13), and so on. The COMMAND decoder 12 may be coupled to the COMMAND input interface 10 and may be configured to receive and decode a COMMAND SIGNAL command_signal to generate a data window SIGNAL CAIWSP (corresponding to a write COMMAND WR) and a control SIGNAL CS, wherein the data window SIGNAL CAIWSP may be configured to inform the data processing circuit 18 that the memory device 100 is operated in a write mode, to control a data path and to represent a maximum tolerance value and a minimum tolerance value of skew (skew) between a data strobe (DQS) SIGNAL and a clock pulse SIGNAL (e.g., a real clock pulse SIGNAL ck_t), and the control SIGNAL CS is generated according to a plurality of address SIGNALs.

The memory cell circuit 14 may be coupled to the command decoder 12 and the data processing circuit 18, and may have a plurality of memory BANKs (memory BANKs) bank_0 to bank_n, wherein the memory cell circuit 14 is controlled by a control signal CS, the control signal CS may be used to determine a memory address of one of the memory BANKs bank_0 to bank_n, and a write operation corresponding to the write command WR may be performed on the memory address. The data input/output interface 16 may be configured to receive a plurality of data (data, DQ) signals DQ0 through DQ7, a plurality of data signals DQ8 through DQ15, a differential pair of an upper data strobe signal (i.e., an upper real data strobe signal udqs_t and an upper complementary data strobe signal udqs_c) and a differential pair of a lower data strobe signal (i.e., a lower real data strobe signal ldqs_t and a lower complementary data strobe signal ldqs_c), wherein the differential pair of the upper data strobe signal and the differential pair of the lower data strobe signal correspond to the data signals DQ8 through DQ15 and the data signals DQ0 through DQ7, respectively, and the data signals DQ0 through DQ7 and the data signals DQ8 through DQ15 correspond to a plurality of data to be written. The data processing circuit 18 is coupled to the command decoder 12, the memory cell circuit 14 and the data input/output interface 16, and is configured to receive the data window signals CAIWSP, the data signals DQ 0-DQ 7, the data signals DQ 8-DQ 15, the differential pair of the upper data strobe signal and the differential pair of the lower data strobe signal, and write a plurality of data to be written to the memory cell circuit 14 (especially the memory cells at the memory addresses determined by the control signal CS) according to the data window signal CAIWSP.

FIG. 2 is a block diagram of the data processing circuit 18 shown in FIG. 1 according to one embodiment of the present invention. As shown in fig. 2, the data processing circuit 18 shown in fig. 1 may include a data control circuit 200 and a serial-to-parallel (serial to parallel) circuit 202, wherein the data control circuit 200 is coupled to the serial-to-parallel circuit 202. In the present embodiment, the data signals DQ0 through DQ7 may be transmitted to the serial-to-parallel circuit 202, and the lower data strobe signal LDQS may be transmitted to the data control circuit 200 and the serial-to-parallel circuit 202, wherein the data signals DQ0 through DQ7 are transmitted in serial communication (series communication), and the lower data strobe signal LDQS may be generated by transmitting the lower real data strobe signal ldqs_t to the data control circuit 200 and the serial-to-parallel circuit 202 through an input buffer of the data input/output interface 16, but the present invention is not limited thereto. In some embodiments, the data signals DQ 8-DQ 15 may be transmitted to the serial-to-parallel circuit 202 and an upper data strobe signal UDQS may be transmitted to the data control circuit 200 and the serial-to-parallel circuit 202, wherein the upper data strobe signal UDQS may be generated by transmitting the upper real data strobe signal UDQS_t to the data control circuit 200 and the serial-to-parallel circuit 202 through the input buffer of the data input/output interface 16.

In this embodiment, the data control circuit 200 is configured to generate the second data timing mark signal Q05 and the fourth data timing mark signal Q25 according to the following data strobe signal LDQS, and transmit the second data timing mark signal Q05 and the fourth data timing mark signal Q25 to the serial-to-parallel circuit 202, wherein the timings of the plurality of data to be written are marked by the second data timing mark signal Q05 and the fourth data timing mark signal Q25, respectively. The serial-to-parallel circuit 202 may be configured to convert the DATA signals DQ0 through DQ7 transmitted in serial communication into the DATA input signals DATA0 through DATA63 transmitted in parallel communication (parallel communication) according to the following DATA strobe signal LDQS, the second DATA timing mark signal Q05 and the fourth DATA timing mark signal Q25, respectively, and to transmit the DATA input signals DATA0 through DATA63 to the memory cell circuit 14, for example, the DATA signal DQ0 is converted into the DATA input signals DATA0 through DATA7 of the DATA input signals DATA0 through DATA63, and the DATA signal DQ1 is converted into the DATA input signals DATA8 through DATA15 of the DATA input signals DATA0 through DATA63, which are not repeated herein for brevity.

Fig. 3 is a schematic diagram of the data control circuit 200 shown in fig. 2 according to an embodiment of the present invention, wherein the data control circuit 200 shown in fig. 2 can be implemented by the data control circuit 300 shown in fig. 3. In the present embodiment, the data control circuit 300 may be configured to generate the first data timing mark signal Q00, the second data timing mark signal Q05, the third data timing mark signal Q15 and the fourth data timing mark signal Q25 according to the real clock signal ck_t and the lower data strobe signal LDQS, wherein the real clock signal ck_t belongs to a clock domain (clock-domain), and the lower data strobe signal LDQS, the first data timing mark signal Q00, the second data timing mark signal Q05, the third data timing mark signal Q15 and the fourth data timing mark signal Q25 belong to a data strobe domain (DQS-domain), but the invention is not limited thereto. In addition, the data control circuit 300 may be configured to convert the data window signal CAIWSP (which corresponds to the write command WR) from the clock domain to the data strobe domain.

As shown in fig. 3, the data control circuit 300 may include a plurality of latch circuits 20, 24 and 26, a self-blocking circuit 22 and two data timing mark signal generating circuits 28 and 30. Latch circuit 20 has a first clock pulse port, which is operable to receive an inverse of the lower data strobe signal LDQS (labeled "(LDQS in FIG. 3), a first input port D, and a first output port Q ^- ") and the first input port D is operable to receive a data window signal CAIWSP. The self-resistance circuit 22 may be coupled to the first output port Q of the latch circuit 20 and may be configured to generate the protection signal PS according to an output (which is labeled as "PQ05" in fig. 3; hereinafter referred to as a signal PQ05 for brevity) at the first output port Q of the latch circuit 20 and a self-resistance signal SBS, wherein the self-resistance signal SBS is generated according to the second data timing mark signal Q05, the third data timing mark signal Q15 and the fourth data timing mark signal Q25.

For example, in the present embodiment, the self-resistance circuit 22 may include an NOR gate 21 AND an AND gate 23, wherein the NOR gate 21 may be configured to receive the second data timing mark signal Q05, the third data timing mark signal Q15 AND the fourth data timing mark signal Q25 to generate the self-resistance signal SBS, AND the gate 23 may be coupled to the first output port Q of the latch circuit 20 AND the NOR gate 21, AND may be configured to receive the signal PQ05 AND the self-resistance signal SBS to generate the protection signal PS.

The latch circuit 24 has a second clock port for receiving the lower data strobe signal LDQS, a second input port D coupled to the self-impedance circuit 22 for receiving the protection signal PS, and a second output port Q for outputting the first data timing mark signal Q00. The latch circuit 26 has a third clock port for receiving an inverse of the lower data strobe signal LDQS, a third input port D coupled to the second output port Q of the latch circuit 24 for receiving the first data timing mark signal Q00, and a third output port Q for outputting the second data timing mark signal Q05.

The data timing mark signal generating circuit 28 may be coupled to the third output port Q of the latch circuit 26 and may be configured to generate the third data timing mark signal Q15 according to the second data timing mark signal Q05, in this embodiment, the data timing mark signal generating circuit 28 may include two latch circuits 27 and 29, the latch circuit 27 has a fourth clock port, a fourth input port D and a fourth output port Q, wherein the fourth clock port may be configured to receive the lower data strobe signal LDQS, and the fourth input port D may be coupled to the third output port Q of the latch circuit 26 and may be configured to receive the second data timing mark signal Q05. The latch circuit 29 has a fifth clock pulse port operable to receive an inverse of the lower data strobe signal LDQS, a fifth input port D operable to be coupled to the fourth output port Q of the latch circuit 27 and to receive an output at the fourth output port Q of the latch circuit 27, and a fifth output port Q operable to output the third data timing mark signal Q15.

The data timing mark signal generating circuit 30 may be coupled to the data timing mark signal generating circuit 28 and may be configured to generate the fourth data timing mark signal Q25 according to the third data timing mark signal Q15, in this embodiment, the data timing mark signal generating circuit 30 may include two latch circuits 31 and 32, the latch circuit 31 has a sixth clock port, a sixth input port D and a sixth output port Q, wherein the sixth clock port may be configured to receive the lower data strobe signal LDQS, and the sixth input port D may be coupled to the data timing mark signal generating circuit 28 (particularly, the fifth output port Q of the latch circuit 29 in the data timing mark signal generating circuit 28) and may be configured to receive the third data timing mark signal Q15. The latch circuit 32 has a seventh clock pulse port, a seventh input port D, and a seventh output port Q, wherein the seventh clock pulse port is operable to receive an inverse of the lower data strobe signal LDQS, the seventh input port D is coupled to the sixth output port Q of the latch circuit 31 and is operable to receive an output at the sixth output port Q of the latch circuit 31, and the seventh output port Q is operable to output the fourth data timing mark signal Q25.

Further, it should be noted that each of the latch circuits 20, 24, 26, 27, 29, 31, and 32 is a D-type latch circuit, but the present invention is not limited thereto.

Fig. 4 is a timing diagram of clock signals, data strobe signals, data window signals, and a plurality of data timing mark signals acquired by the data control circuit 300 shown in fig. 3 in the case of tDQSS2 according to an embodiment of the present invention. It is assumed that after the write command WR is operated, data signals DQ0 to DQ7 (DQ 1 to DQ7 are not shown in fig. 4) corresponding to 8 pieces of write data (labeled "D1 to D8" in fig. 4) are transferred to the data processing circuit 18. It should be noted that 8 write data are transmitted to the data processing circuit 18 in a serial communication manner in one period from the time point T9 to the time point T13, and the timings of the 8 write data are marked by the second data timing mark signal Q05 and the fourth data timing mark signal Q25, respectively, however, after the time point T13, the 8 write data are transmitted to the memory cell circuit 14 in a parallel communication manner.

As shown in fig. 4, the write command WR is issued at a time point T0, and the write delay WL is equal to 9 (i.e., the write command WR is first operated at the time point T9, and the data signals DQ0 to DQ7 start to be transmitted at the time point T9), in the present embodiment, the column-to-column delay time (column to column delay time, tCCD) is equal to 4, that is, the time interval between the operation timings of two adjacent write commands is 4×clock cycle time (tCK). In addition, the BLOCK signal BLOCK is the sum of the second data timing mark signal Q05, the third data timing mark signal Q15 and the fourth data timing mark signal Q25 (for example, the result of performing an OR operation on the second data timing mark signal Q05, the third data timing mark signal Q15 and the fourth data timing mark signal Q25), and is the inverse of the self-BLOCK signal SBS. The signals shown above the dashed line L1 (i.e., the real clock signal ck_t and the lower real data strobe signal ldqs_t) are external signals of the memory device 100, and the signals shown below the dashed line L1 (i.e., the data window signal CAIWSP, the lower data strobe signal LDQS, the signal PQ05, the protection signal PS, the first data timing mark signal Q00, the second data timing mark signal Q05, the third data timing mark signal Q15, the fourth data timing mark signal Q25 and the blocking signal BLOCK) are internal signals of the data control circuit 300.

In addition, the pulse width of the data window signal CAIWSP is 2×tck, and the lower data strobe signal LDQS is 8 write data switched (toggle) 4 times (i.e., from low level to high level 4 times) every 4 time periods (e.g., from time point T9 to time point T13). Ideally, the rising edge (rising edge) of the lower data strobe signal LDQS should strobe (strobe) the data window signal CAIWSP just at the time point T9, however, since the lower data strobe signal LDQS may be generated by transmitting the lower real data strobe signal ldqs_t to the data control circuit 300 through the input buffer, the rising edge of the lower data strobe signal LDQS gates the data window signal CAIWSP near the time point T9.

Considering the case where the latch circuit 24 is directly coupled to the latch circuit 20 (i.e., the case where the data control circuit 300 is modified to delete the self-resistance circuit 22 therefrom), since the signal PQ05 is gated by the high level of the lower data strobe signal LDQS and the signal PQ05 has the high level at a position a shown in fig. 4, the first data timing mark signal Q00 remains at the high level until a time point T11, which may cause 8 write data to be written to the memory cell circuit 14 at the time of the error timing, that is, the timings of the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 may be erroneous. Further, since the signal PQ05 is gated by the high level of the lower data strobe signal LDQS and the signal PQ05 has a high level at the position B shown in fig. 4, the first data timing mark signal Q00 may remain at the high level until the time point T15, which may also cause 8 write data to be written to the memory cell circuit 14 at the time of the error timing.

In the present embodiment with the self-blocking circuit 22 implemented in the data control circuit 300, the blocking signal BLOCK can be used to avoid the situation described above, AND the signal PQ05 is blocked at the position C AND a position D shown in fig. 4, that is, the protection signal PS (obtained by performing AND (or) operation on the signal PQ05 AND the inverse signal of the blocking signal BLOCK (i.e., the self-blocking signal SBS)) has a low level in the timing region covered by the position C AND the position D. Since the protection signal PS has a low level at the position a and the position B and is gated by a high level of the lower data strobe signal LDQS, the level of the first data timing mark signal Q00 becomes low at the position a and the position B, so that timings of the first data timing mark signal Q00, the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 may be correct, and 8 write data may be correctly written to the memory cell circuit 14 using the data control circuit 300 of the present invention.

FIG. 5 is a timing diagram of clock signals, data strobe signals (which first rise after the operation timing of a write command), data window signals, and a plurality of data timing mark signals obtained by the data control circuit 300 shown in FIG. 3 in the case of tDQSS2 according to one embodiment of the invention. The difference between fig. 4 and fig. 5 is that the first rising edge of the data strobe signal LDQS in fig. 5 is near the middle timing between the time point T9 and the time point T10 (which is still in the range of the data window signal CAIWSP), instead of near the time point T9, and similar descriptions are not repeated here for brevity. If the data control circuit 300 is modified to delete the self-resistance circuit 22 therefrom, at the position a shown in fig. 5, since the signal PQ05 is a high level signal and is gated by the high level of the lower data strobe signal LDQS, the level of the first data timing mark signal Q00 is changed from low to high before the correct timing (i.e., the timing close to the intermediate timing between the time point T13 and the time point T14), which may cause 8 write data to be written to the memory cell circuit 14 at the error timing.

In the present embodiment with the self-impedance circuit 22 implemented in the data control circuit 300, since the BLOCK signal BLOCK has a high level at the position a, the protection signal PS (which is obtained by performing AND (AND) operation on the signal PQ05 AND the inverse signal of the BLOCK signal BLOCK (i.e., the self-impedance signal SBS)) remains low at the position a, which makes the first data timing mark signal Q00 still a low level signal until the correct timing (i.e., the timing near the intermediate timing between the time points T13 AND T14), so that the timings of the second data timing mark signal Q05, the third data timing mark signal Q15 AND the fourth data timing mark signal Q25 can be correct, AND the data control circuit 300 of the present invention can be utilized to correctly write 8 pieces of write data to the memory cell circuit 14.

FIG. 6 is a timing diagram of clock signals, data strobe signals (which first rise before the operation timing of a write command), data window signals, and a plurality of data timing mark signals obtained by the data control circuit shown in FIG. 3 in the case of tDQSS2 according to one embodiment of the invention. The difference between fig. 4 and fig. 6 is that the first rising edge of the lower data strobe signal LDQS in fig. 6 is close to the intermediate timing between the time point T8 and the time point T9 (which is still in the range of the data window signal CAIWSP), instead of close to the time point T9, and similar descriptions are not repeated here for brevity. In case the data control circuit 300 is modified to delete the self-resistance circuit 22 therefrom, at the position a shown in fig. 6, since the signal PQ05 is a high level signal and is gated by a high level of the lower data strobe signal LDQS, the first data timing mark signal Q00 keeps a high level until the timing approaching the intermediate timing between the time point T10 and the time point T11, which may cause 8 write data to be written to the memory cell circuit 14 at the error timing, that is, the timings of the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 may be erroneous. In addition, at the position B shown in fig. 6, since the signal PQ05 is a high level signal and is gated by the high level of the lower data strobe signal LDQS, the first data timing mark signal Q00 keeps a high level until the timing approaching the intermediate timing between the time point T14 and the time point T15, which may also cause 8 write data to be written to the memory cell circuit 14 at the error timing.

In the present embodiment having the self-resistance circuit 22 implemented in the data control circuit 300, since the BLOCK signal BLOCK has a high level at the positions a AND B, the protection signal PS (which is obtained by performing AND (AND) operation on the inverse signals of the signal PQ05 AND the BLOCK signal BLOCK (i.e., the self-resistance signal SBS)) has a low level at the positions a AND B, which makes the first data timing mark signal Q00 a low level signal at the positions a AND B, so that the timings of the second data timing mark signal Q05, the third data timing mark signal Q15, AND the fourth data timing mark signal Q25 can be correct, AND 8 write data can be correctly written to the memory cell circuit 14 using the data control circuit 300 of the present invention.

For the tDQSS case, in the prior art, the pulse width of the data window signal may reach 1 tck, which may process the value of tDQSS up to ±0.4tck in the specification of DDR SDRAM, and in fact, it is difficult to precisely make the pulse width of the data window signal exactly 1 tck. Fig. 7 is a timing diagram of clock signals, data strobe signals, data window signals, and a plurality of data timing mark signals acquired by the data control circuit 300 shown in fig. 3 in the tDQSS case according to an embodiment of the present invention. In this embodiment, the pulse width of the data window signal CAIWSP is increased to 1.5 tck, so that the manufacturer of the DDR SDRAM can manufacture the DDR SDRAM more easily once the pulse width of the data window signal is greater than 1 tck. It should be noted that 1.5 tCK is merely exemplary of the pulse width of the data window signal CAIWSP that can be achieved by the data control circuit 300 of the present invention, and in fact, the pulse width of the data window signal CAIWSP may be other tCK lengths (e.g., 1.3 tCK or 1.4 tCK), so that the design flexibility of the present invention is higher than that of the prior art. The details of the signals shown in fig. 7 have been described in the above embodiments, and similar descriptions are not repeated here for the sake of brevity.

In the present embodiment, the signal PQ05 is blocked by the blocking signal BLOCK at the position C AND the position D, that is, the protection signal PS (obtained by performing AND (or) operation on the inverse signals of the signal PQ05 AND the blocking signal BLOCK (i.e., the self-blocking signal SBS)) is a low level signal at the timing region covered by the position C AND the position D. At the position a and the position B, since the protection signal PS is a low level signal and is gated by a high level of the lower data strobe signal LDQS, the first data timing mark signal Q00 is also a low level signal, so that timings of the first data timing mark signal Q00, the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 can be correct, and 8 write data can be correctly written to the memory cell circuit 14 using the data control circuit 300 of the present invention.

FIG. 8 is a timing diagram of clock signals, data strobe signals (which first rise after the operation timing of a write command), data window signals, and a plurality of data timing mark signals obtained by the data control circuit 300 shown in FIG. 3 in the case of tDQSS according to one embodiment of the invention. The difference between fig. 7 and fig. 8 is that the first rising edge of the data strobe signal LDQS in fig. 8 is near the middle timing between the time point T9 and the time point T10 (which is still in the range of the data window signal CAIWSP), instead of near the time point T9, and similar descriptions are not repeated here for brevity. If the data control circuit 300 is modified to delete the self-resistance circuit 22 therefrom, at the position a shown in fig. 8, since the signal PQ05 is a high level signal and is gated by a high level of the lower data strobe signal LDQS, the level of the first data timing mark signal Q00 is changed from low to high before the correct timing (i.e., the timing close to the intermediate timing between the time point T13 and the time point T14), which may cause 8 write data to be written to the memory cell circuit 14 at the error timing.

In the present embodiment with the self-impedance circuit 22 implemented in the data control circuit 300, since the BLOCK signal BLOCK has a high level at the position a, the protection signal PS (which is obtained by performing AND (AND) operation on the signal PQ05 AND the inverse signal of the BLOCK signal BLOCK (i.e., the self-impedance signal SBS)) remains low at the position a, which makes the first data timing mark signal Q00 still a low level signal until the correct timing (i.e., the timing near the intermediate timing between the time points T13 AND T14), so that the timings of the second data timing mark signal Q05, the third data timing mark signal Q15 AND the fourth data timing mark signal Q25 can be correct, AND the data control circuit 300 of the present invention can be utilized to correctly write 8 pieces of write data to the memory cell circuit 14.

Fig. 9 is a timing diagram of clock signals, data strobe signals (which first rise before the operation timing of a write command), data window signals, and a plurality of data timing mark signals acquired by the data control circuit 300 shown in fig. 3 in the tDQSS case according to one embodiment of the present invention. The difference between fig. 7 and fig. 9 is that the first rising edge of the lower data strobe signal LDQS in fig. 9 is close to the intermediate timing between the time point T8 and the time point T9 (which is still in the range of the data window signal CAIWSP), instead of being close to the time point T9, and similar descriptions are not repeated here for brevity. In case the data control circuit 300 is modified to delete the self-resistance circuit 22 therefrom, at the position a shown in fig. 9, since the signal PQ05 is a high level signal and is gated by a high level of the lower data strobe signal LDQS, the first data timing mark signal Q00 keeps a high level until the timing approaching the intermediate timing between the time point T10 and the time point T11, which may cause 8 write data to be written to the memory cell circuit 14 at the error timing, that is, the timings of the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 may be erroneous. In addition, at the position B shown in fig. 9, since the signal PQ05 is a high level signal and is gated by the high level of the lower data strobe signal LDQS, the first data timing mark signal Q00 keeps a high level until the timing approaching the intermediate timing between the time point T14 and the time point T15, which may also cause 8 write data to be written to the memory cell circuit 14 at the error timing.

In the present embodiment having the self-resistance circuit 22 implemented in the data control circuit 300, since the blocking signal BLOCK has a high level at the positions a AND B, the protection signal PS (which is obtained by performing AND (AND) operation on the inverted signals (i.e., the self-resistance signal SBS) of the signal PQ05 AND the blocking signal BLOCK) has a low level at the positions a AND B, which makes the first data timing mark signal Q00 a low level signal at the positions a AND B, so that the timings of the second data timing mark signal Q05, the third data timing mark signal Q15, AND the fourth data timing mark signal Q25 can be correct, AND 8 write data can be correctly written to the memory cell circuit 14 using the data control circuit 300 of the present invention.

List one

Write format	Barrier Signal Width
		BL4	1*tCK
BL8	3*tCK
		BL4 in CRC mode	4*tCK
BL8 in CRC mode	4*tCK

For different burst lengths (burst lengths), the write formats of the DDR4 SDRAM (e.g., BL4, BL8, BL4 in cyclic redundancy check (cyclic redundancy check, CRC) mode, or BL8 in cyclic redundancy check mode) may be used by the data control circuit provided by the present invention, for example, the write commands corresponding to 4 write data for use by the write format BL4 may be used by the data control circuit provided by the present invention. The first graph shows the width of the BLOCK signal BLOCK used in the data control circuit of the present invention for different write formats of DDR4 SDRAM. For the write format BL4, the lower data strobe signal LDQS switches for 4 write data 2 times and the width of the BLOCK signal BLOCK is 1 tck; for the write format BL8 (which is applied to the above embodiment), the lower data strobe signal LDQS is switched 4 times for 8 write data and the width of the blocking signal BLOCK is 3 tck; and for BL4 in CRC mode and BL8 in CRC mode, the lower data strobe LDQS is switched 5 times for 9 write data and the width of the blocking signal BLOCK is 4 tCK.

Fig. 10 is a timing diagram of clock signals, data strobe signals, data window signals, and a plurality of data timing mark signals acquired by the data control circuit 300 shown in fig. 3 in the case of tDQSS2 according to another embodiment of the present invention. Assume that data signals DQ0 through DQ7 (DQ 1 through DQ7 are not shown in fig. 10) corresponding to 4 write data (i.e., write format BL 4) are transferred to the data control circuit 300, wherein the 4 write data are labeled "D1 through D4" in fig. 10, respectively. As shown in fig. 10, the write command WR corresponding to the write format BL4 is issued at the time point T0, and the write delay WL is equal to 9, only the second data timing mark signal Q05 is used to mark 4 write data (i.e., the constant levels of the third data timing mark signal Q15 and the fourth data timing mark signal Q25 are all equal to 0) in the period from the time point T9 to the time point T13, and the BLOCK signal BLOCK is equal to the second data timing mark signal Q05 due to the OR operation.

In the present embodiment with the self-impedance circuit 22 implemented in the data control circuit 300, since the blocking signal BLOCK has a high level at the position a, the protection signal PS (which is obtained by performing an AND (AND) operation on the signal PQ05 AND the inverse signal of the blocking signal BLOCK (i.e., the self-impedance signal SBS)) has a low level at the position a, which makes the first data timing mark signal Q00 a low level signal at the position a, so that the timings of the second data timing mark signal Q05, the third data timing mark signal Q15, AND the fourth data timing mark signal Q25 can be correct, AND 4 write data can be correctly written to the memory cell circuit 14 using the data control circuit 300 of the present invention. After the time point T13, the writing format is changed from the writing format BL4 to the writing format BL8, and similar descriptions are not repeated here for the sake of brevity.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

[ description of the symbols ]

100: memory device

10: command input interface

12: command decoder

14: memory cell circuit

16: data input/output interface

18: data processing circuit

Command_signal: command signal

CS: control signal

CAIWSP: data window signal

Bank_0 to bank_n: memory bank

DQ 0-DQ 7, DQ 8-DQ 15: data signal

Ldqs_t: lower true data strobe signal

Ldqs_c: lower complementary data strobe signal

UDQS_t: upper true data strobe signal

Udqs_c: upper complementary data strobe signal

200,300: data control circuit

202: sequence-to-parallel circuit

Q00, Q05, Q15, Q25: data timing mark signal

DATA 0-DATA 63: data input signal

LDQS: lower data strobe signal

20,24,26,27,29,31,32: latch circuit

21: NOR gate circuit

22: self-resistance circuit

23: AND gate circuit

28,30: data time sequence marking signal generating circuit

SBS: self-blocking signal

PS: protecting signals

Ck_t: real clock pulse signal

BLOCK: blocking signal

Claims (12)

1. A data control circuit comprising:

A first latch circuit having a first clock pulse port for receiving a first clock pulse derived from a data strobe signal, a first input port for receiving a data window signal, and a first output port;

a self-resistance circuit coupled to the first output port of the first latch circuit and configured to generate a protection signal according to an output at the first output port of the first latch circuit and a self-resistance signal;

a second latch circuit having a second clock port for receiving a second clock derived from the data strobe signal, a second input port coupled to the self-impedance circuit for receiving the protection signal, and a second output port for outputting a first data timing mark signal;

a third latch circuit having a third clock port for receiving the first clock, a third input port coupled to the second output port of the second latch circuit for receiving the first data timing mark signal, and a third output port for outputting a second data timing mark signal;

A first data timing mark signal generating circuit coupled to the third output port of the third latch circuit and configured to generate a third data timing mark signal according to the second data timing mark signal; and

the second data timing mark signal generating circuit is coupled to the first data timing mark signal generating circuit and is used for generating a fourth data timing mark signal according to the third data timing mark signal.

2. The data control circuit of claim 1, wherein the data window signal represents a maximum tolerance value and a minimum tolerance value of skew between a memory clock signal and the data strobe signal.

3. The data control circuit of claim 1, wherein the timing of the plurality of data to be written transferred to the memory cell circuit is sequentially marked by the second data timing mark signal and the fourth data timing mark signal.

4. The data control circuit of claim 1, wherein the self-resistance circuit is further configured to generate the self-resistance signal according to the second data timing mark signal, the third data timing mark signal, and the fourth data timing mark signal.

5. The data control circuit of claim 4, wherein the self-resistance circuit comprises:

an NOR gate for receiving the second data timing mark signal, the third data timing mark signal and the fourth data timing mark signal to generate the self-resistance signal; and

and the AND gate circuit is coupled to the first output port of the first latch circuit and the NOT gate circuit and is used for receiving the output of the first output port of the first latch circuit and the self-resistance signal so as to generate the protection signal.

6. The data control circuit of claim 1, wherein each of the first latch circuit, the second latch circuit, and the third latch circuit is a D-type latch circuit.

7. The data control circuit of claim 1, wherein the first data timing mark signal generating circuit comprises:

a fourth latch circuit having a fourth clock port, a fourth input port and a fourth output port, wherein the fourth clock port is used for receiving the second clock, and the fourth input port is coupled to the third output port of the third latch circuit and is used for receiving the second data timing mark signal; and

A fifth latch circuit having a fifth clock port for receiving the first clock, a fifth input port coupled to the fourth output port of the fourth latch circuit and for receiving an output at the fourth output port of the fourth latch circuit, and a fifth output port for outputting the third data timing mark signal.

8. The data control circuit of claim 7, wherein each of the first latch circuit, the second latch circuit, the third latch circuit, the fourth latch circuit, and the fifth latch circuit is a D-type latch circuit.

9. The data control circuit of claim 1, wherein the second data timing mark signal generating circuit comprises:

a fourth latch circuit having a fourth clock port, a fourth input port and a fourth output port, wherein the fourth clock port is used for receiving the second clock, and the fourth input port is coupled to the first data timing mark signal generating circuit and is used for receiving the third data timing mark signal; and

A fifth latch circuit having a fifth clock port for receiving the first clock, a fifth input port coupled to the fourth output port of the fourth latch circuit and for receiving an output at the fourth output port of the fourth latch circuit, and a fifth output port for outputting the fourth data timing mark signal.

10. The data control circuit of claim 9, wherein each of the first latch circuit, the second latch circuit, the third latch circuit, the fourth latch circuit, and the fifth latch circuit is a D-type latch circuit.

11. The data control circuit of claim 1, wherein the first clock pulse is an inverse of the data strobe signal and the second clock pulse is the data strobe signal.

12. A memory device, comprising:

a command input interface for receiving a plurality of command signals;

a command decoder coupled to the command input interface and configured to receive and decode the plurality of command signals to generate a data window signal and a control signal, wherein the data window signal corresponds to a write command;

A memory cell circuit coupled to the command decoder and having a plurality of memory banks, wherein the memory cell circuit is controlled by the control signal;

a data input/output interface for receiving a plurality of data signals and a data strobe signal, wherein the plurality of data signals correspond to a plurality of data to be written and are transmitted in a serial communication manner; and

a data processing circuit comprising:

a serial-to-parallel circuit coupled to the data input/output interface and the memory cell circuit for converting the plurality of data signals into a plurality of data input signals according to the data strobe signal, the second data timing mark signal and the fourth data timing mark signal, wherein the plurality of data input signals are transmitted to the memory cell circuit in a parallel communication manner; and

a data control circuit coupled to the command decoder, the data input/output interface and the serial-to-parallel circuit, and comprising:

a first latch circuit having a first clock pulse port for receiving a first clock pulse derived from the data strobe signal, a first input port for receiving the data window signal, and a first output port;

A self-resistance circuit coupled to the first output port of the first latch circuit and configured to generate a protection signal according to an output at the first output port of the first latch circuit and a self-resistance signal;

a second latch circuit having a second clock port for receiving a second clock derived from the data strobe signal, a second input port coupled to the self-impedance circuit for receiving the protection signal, and a second output port for outputting a first data timing mark signal;

a third latch circuit having a third clock port for receiving the first clock, a third input port coupled to the second output port of the second latch circuit for receiving the first data timing mark signal, and a third output port for outputting the second data timing mark signal;

a first data timing mark signal generating circuit coupled to the third output port of the third latch circuit and configured to generate a third data timing mark signal according to the second data timing mark signal; and

The second data timing mark signal generating circuit is coupled to the first data timing mark signal generating circuit and is used for generating the fourth data timing mark signal according to the third data timing mark signal.