CN116483614A - Cyclic Redundancy Check (CRC) retry for computing a memory system in a fast link (CXL) device - Google Patents

Abstract

The present application relates to Cyclic Redundancy Check (CRC) retry for computing a memory system in a fast link (CXL) device, providing a computing system including a memory system in communication with a host and for storing data therein, and including a memory having a plurality of memory components and a memory array and coupled to the controller via a memory interface. Each memory component includes a memory cyclic redundancy check, CRC, engine that performs CRC checking of data during read and write operations between the host and the memory array. The memory system also includes a controller having a plurality of controller CRC engines and in communication with the memory components to control data transfer among the memory, the host, and the memory array.

Description

Cyclic Redundancy Check (CRC) retry for computing a memory system in a fast link (CXL) device

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional patent application No. 63/301,988 entitled "CRC retry in LP5 component of CXL device using CRC-RAID RAS," filed on month 21 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to memory systems and methods, and more particularly, to a Cyclic Redundancy Check (CRC) retry method for preventing errors in links between a controller and memory of a memory system during data read and write operations within a CRC-RAID (redundant array of independent disks) environment.

Background

Memory devices (also referred to as "memory media devices") are widely used to store information in a variety of electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states.

For example, a binary memory cell may be programmed to one of two support states, typically corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any of which may be stored by the memory cell. To access information stored by the memory device, the component may read or sense the state of one or more memory cells within the memory device. To store information, a component may write or program one or more memory cells within a memory device to a corresponding state.

It is desirable to have memory systems and methods that enable retry operations within an ASIC environment during read and write operations that increase memory speed and accuracy, resulting in higher reliability of CXL devices.

Disclosure of Invention

One aspect of the present application provides a computing system, comprising: a memory system in communication with a host and configured to store data therein, the memory system comprising: a memory including a plurality of memory components and a memory array and coupled to the controller via a memory interface; wherein each of the memory components includes a memory cyclic redundancy check, CRC, engine configured to perform CRC checking of data during read and write operations between the host and the memory array; and a controller including one or more controller CRC engines and configured to communicate with the memory components to control data transfer between the memory, the host, and the memory array.

Another aspect of the present application provides a method comprising: disposing a memory CRC engine in a memory and a controller CRC engine in a controller that controls data transfer between the memory and a host in communication therewith; wherein each memory component of the memory includes a memory CRC engine of the plurality of CRC engines; and performing a CRC check of data via a memory CRC engine and a controller CRC engine during read and write operations between the host and a memory array of the memory.

Another aspect of the present application provides a memory system, comprising: a memory including one or more memory components and a memory array; wherein each of the memory components includes a memory cyclic redundancy check, CRC, engine configured to perform CRC checking of data during read and write operations between a host and the memory array; and a controller (i) including one or more controller CRC engines, and (ii) configured to communicate with the memory components to control data transfers among the memory, the host, and the memory array.

Drawings

FIG. 1 is a block diagram illustrating a typical Application Specific Integrated Circuit (ASIC) architecture for CRC-RAID.

FIG. 2 is a block diagram of a computing system in accordance with one or more exemplary embodiments of the present disclosure.

FIG. 3 is a flowchart illustrating an example method of CRC retry operations including the computing system of FIG. 2, according to one or more exemplary embodiments of the present disclosure.

Fig. 4 is a flowchart illustrating the example read method of fig. 3 including a CRC retry operation in a read direction in accordance with one or more exemplary embodiments of the present disclosure.

Fig. 5 is a flowchart illustrating an example write method of fig. 3 including a CRC retry operation in a write direction in accordance with one or more exemplary embodiments of the present disclosure.

FIG. 6 is a detailed block diagram illustrating a CRC check performed within each of the CRC engine of the controller and the memory components as shown in FIG. 3, according to one or more exemplary embodiments of the disclosure.

FIG. 7 is a diagram illustrating a RAID method for retrieving data to be read from memory in a memory system as discussed in FIG. 4 in accordance with one or more exemplary embodiments of the present disclosure.

FIG. 8 is a diagram illustrating a RAID method for writing data to memory in a memory system as discussed in FIG. 5 in accordance with one or more exemplary embodiments of the present disclosure.

The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Novel aspects of the presently described technology will become apparent to those of ordinary skill in the art in view of the following heuristic description of the drawings. This detailed description uses numerical and letter designations to refer to features in the drawings. The same or similar reference numerals in the drawings and description have been used to refer to the same or similar parts of the embodiments of the presently described technology.

Detailed Description

Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine readable medium. The processor may perform the necessary tasks.

FIG. 1 is a block diagram illustrating an Application Specific Integrated Circuit (ASIC) architecture 10 for CRC-RAID. A typical ASIC architecture 10 for CRC-RAID includes a memory system 11 having a front end 12, a central controller 14, and a back end 16. Front end 12 is comprised of a CXL controller 18 and a physical layer 19 and interfaces with a host (not shown). The central controller 20 includes a cache 20 for temporarily storing data, AES 22, RAID 24, and a plurality of CRC engines 25.

The back end 16 includes a plurality of memory components 28, and physical layers 30 and memory arrays 31 thereof. The memory components 28 are organized in channels and banks. Architecture 10 also includes an interconnect or bus 32 that connects to several other components 34 as shown. Conventionally, read and write operations of data or media are performed via the central controller 14.

In the read direction, retrieving data from the memory array 31 and sending the data to the host; and in the write direction, data is transferred from the host and sent to the memory component 28 of the memory array 31 via the memory interface or link 36. In this type of integrated circuit architecture, link protection against errors is typically performed using link ECC in the memory component 28. Instead of using link ECC, in the present disclosure, dynamic link switching protocol (DLEP) is used in the LP5 component to transfer information.

FIG. 2 is a computing system 100 including a host 102 in communication with a memory system 104, according to an embodiment. Host 102 may be a host system including, for example, a personal laptop computer, a desktop computer, a mobile device (e.g., a cellular telephone), a web server, a memory card reader, a camera, or any other suitable type of host system or device.

According to an embodiment, the memory system 104 is of the ASIC type. The memory system 104 includes a controller 106 that includes a central controller 108 that includes a pool of CRC engines 109, a memory controller 110, and a physical hierarchy 112. Alternatively, according to other embodiments of the present disclosure, CRC engine 109 may be disposed within memory controller 110.

The controller 106 and its components may be implemented in hardware, firmware, and software, or any combination thereof. The controller 106 is coupled to the host 102 via a host interface 103 for transferring data between the memory system 104 and the host 102. Host interface 103 is a standard interface such as serial technology attachment (SATA), peripheral component interconnect express (PCIe), or Universal Serial Bus (USB), or other type of connector or interface. The host 102 and the memory system 104 each include compatible receptors for transmitting data and other signals via the host interface 103.

The memory system 104 further includes a memory 120 that includes a plurality of memory components 122 coupled to the controller 106 via a memory interface 130 (e.g., link/bus). The controller 106 and the memory 120 also each include a receiver compatible with the memory interface 130 for transmitting data and other signals to each other. The memory 120 is configured to write data to the memory array 140 and to read data from the memory array 140.

The memory component 122 may include a die, chip, etc. that provides a storage volume for the memory system 104. According to one or more embodiments of the invention, the memory component 122 may be a low power (LP 5) or Double Data Rate (DDR) type memory component. Thus, the memory interface 130 may be an associated link based on the type of memory component 122, such as a DDR or LP5 link, DRAM, HRAM, or any other type of memory component and interface suitable for the purposes set forth herein.

The memory components 122 each include a CRC engine 124 similar to the CRC engine of the central controller 108, and wherein data or media is organized in channels and banks. Additional details regarding communication between the host 102 and the controller 106 and memory 120 of the memory system 104 will be discussed below with reference to fig. 3-6.

Fig. 3 is a flow diagram illustrating a data transfer method performed between a host and a memory system therein within the computing system of fig. 2, according to one or more exemplary embodiments of the present disclosure. As shown in fig. 3, the controller 106 is configured to communicate with the memory components 122 of the memory 120 to control data transfers (e.g., data reads, writes, erases, and other operations) between the memory 120 and the host 102 and the memory array 140.

As mentioned above, the central controller 108 of the controller 106 includes the CRC engine 109 and each memory component 122 includes the CRC engine 124. These CRC engines 109 and 124 are configured to perform retry operations when errors are detected at the memory interface 130 (e.g., LP5 link). CRC engine 109 includes CRC generator 114 and CRC check component 116.

Similarly, CRC engine 124 of memory device 122 includes a CRC check component 128 and a CRC generator 126.

In the read direction, once a command is sent from host 102 to memory component 122 via central controller 108, data is retrieved from array 140 and sent to CRC generator 126 and CRC check component 116.CRC check component 116 acts as a receiver and recalculates the CRC parity as CRC generator 114 begins from the data bits it received, and then compares the resulting CRC parity to the CRC parity received by CRC generator 126, which acts as a transmitter in this embodiment. According to an embodiment, the CRC parity is a vector of bits calculated starting from the bits of the data packet to be protected. Once CRC check component 116 completes the comparison process and if the CRC check indicates a match, the data is sent to host 102.

According to an embodiment, CRC generators 114 and 124 are CRC encoders, and CRC checks 116 and 128 of the memory elements are CRC decoders. The CRC decoder is a CRC encoder that includes a comparator for CRC parity, as shown in fig. 6.

In another embodiment, in the write direction, the data is sent to CRC generator 114, which acts as a transmitter, and CRC check component 128, which acts as a receiver, and the resulting data (CRC parity) from CRC generator 114 is then compared to the CRC parity recalculated at CRC check component 128, and if it indicates a match, the data is sent to memory array 140. If there is alternatively no match, a retry request is sent back to the central controller 108. The central controller 108 retransmits the data a second time to account for (random) link noise. More details regarding the read and write methods and the operation of CRC engines 109 and 124 are discussed below with reference to FIGS. 4-6.

FIG. 4 is a flowchart illustrating the example read method 400 of FIG. 3 including a CRC retry operation in a read direction (arrow 'A') from the memory component 122 to the central controller 108 via the memory interface 130 (e.g., an LP5 link). The method 400 will be described below with reference to fig. 3 and begins at operation 402, where the controller 106 sends a command for data or media to the memory 120.

At operation 404, after reading data from the array 140, the memory component 122 sends the data. At operation 406, the controller 108 performs a CRC check via the CRC engine 109 to detect whether there is an error at the memory interface 130. The CRC code is used to detect errors and determine its location in the data stripes within RAID. The host 102 sees the memory array 140 as an array with multiple locations. Each location is marked as an address and the CRC RAID mechanism defines a partition of the location as a stripe.

All locations in the stripe are linked together by zero and a relationship, and the zero and condition is obtained by RAID parity. The amount of data required by the host 102 is a User Data Block (UDB), e.g., 64 bytes of data, and each UDB is a stripe within a stripe. The UDBs of the same RAID stripe are stored in different components and channels. If no errors are found at the memory interface 130, the method continues to operation 408 where the data is sent to the host 102. If the controller 108 performs a CRC check via the CRC engine 109 and an error is detected on the memory interface 130, a determination is made at operation 410 as to whether this is the first occurrence or test. If this is the first failure of the CRC, the cause of the failure may be link noise. In this case, a retry of the transmission (i.e., the second transmission) is performed. If the second transmission is correct, the data may be transmitted towards the host 102.

If an error is detected, the controller 108 performs a CRC retry operation towards the memory component 122 via the CRC engine 109 at operation 412. The CRC retry operation cancels the error on the memory interface in the read direction and repeats operation 402. If the CRC engine 109 detects an error and it is not the first test, a RAID recovery operation is activated to retrieve the data at operation 414.

Referring forward to the graph 700 in fig. 7, in a RAID method, all remaining stripes 701 of the stripe 710 to which the required UDB belongs are read, and the missing pattern is retrieved by adding (XOR) complementary stripes 701 in the stripe 710. If they match, the data is retrieved (as depicted in chart 700 shown in FIG. 7). If all the complementary stripes are correct, the complementary stripes of the stripes are bit-xored together to obtain a pattern that is used to replace the corruption pattern provided by the accessed UDB. The correctness is checked by CRC. If an uncorrectable error occurs, such as more than one UDB being incorrect in the stripe, a poison bit is set to inform the host 102 (as depicted in FIG. 3) that there is an uncorrectable error in the data that is returned to the host 102.

FIG. 5 is a flow chart illustrating the example write method 500 of FIG. 3 including a CRC retry operation in the write direction (indicated by arrow 'B'). As shown in fig. 5, the method 500 begins at operation 502, where the controller 108 sends data to the memory component 122. At operation 504, memory component 122 performs a CRC check via CRC engine 124 to detect whether there are any errors on memory interface 130. If no errors are found, a write operation is performed in the array 140 at operation 508.

If an error is detected via CRC engine 124 during a CRC check, then a determination is made at operation 510 as to whether it is the first instance or trial. If so, a CRC retry operation is performed via CRC engine 124 of memory component 122 toward controller 109 to counteract errors found in memory interface 130 in the write direction, and operation 502 is repeated. If it is determined at operation 510 that it is not the first test, then a write operation is performed in the array 140 via a RAID method at operation 508 (as depicted in the chart 800 shown in FIG. 8).

As depicted, when performing a write operation, the UDB needs to update the RAID parity of the stripe to which the UDB belongs. When an error is detected, the remaining stripes 801 of RAID stripe 810 are read and if there is a match, the data may be written to the appropriate location within the memory array 140. When writing a UDB, the remaining stripes 801 are read and compared to the new UDB pattern provided by the host 102, and then the RAID parity 812 is updated by adding the comparison to the stored RAID parity 812 pattern. If there is an error when reading a UDB stored in the media subsystem, RAID parity 812 is updated by first reading all complementary stripes 801 of stripe 810.

Fig. 6 is a detailed block diagram illustrating further details regarding CRC checks performed within each of the CRC engines 109 and 124 of the controller 108 and the memory component 122 as shown in fig. 3, according to one or more exemplary embodiments of the present disclosure.

As shown in fig. 6, CRC generators 114, 126 of CRC engines 109 and 124 of controller 108 and each memory component 122 each include a CRC parity generator 600. The CRC parity generator 600 receives data based on the payload of the CRC and performs a combinational logic operation based on a generator polynomial (e.g., 64 bits to 32 bits) to obtain the CRC parity. The CRC check components 116, 128 transmit the received data to the CRC parity generator 600 to calculate a CRC parity, which is then compared to the CRC parity received via the comparator 600 to determine if a data match exists. If there is a data match, it is determined that no error has occurred. According to an embodiment of the present invention, the received CRC parity is a CRC parity generated by CRC generators 114 and 126. The CRC parity works like a signature. CRC generators 114 and 126 calculate a signature corresponding to the data to be transmitted. Both the data and the signature (i.e., CRC parity) are then transmitted. The CRC check components 116 and 128 recalculate the signature from the received data (i.e., recalculate the CRC parity) and determine that the transmission is correct if the received signature is the same as the signature recalculated from the data by the CRC check component 116 or 128.

The various embodiments of the present disclosure provide benefits such as increasing memory speed and accuracy within CXL devices during read and write operations. Embodiments of the present disclosure avoid triggering RAID in the event of a link error. Thus, the method of the present disclosure also improves latency and bandwidth by enabling retry operations after a CRC fails to correct a link error, and allows data to be corrected immediately without invoking RAID.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative manner, and not a restrictive one.

Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. The scope of various embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing detailed description, certain features have been grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure have to use more features than are expressly recited in each claim. Indeed, as reflected in the appended claims, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims (20)

1. A computing system, comprising:

a memory system in communication with a host and configured to store data therein, the memory system comprising:

a memory including a plurality of memory components and a memory array and coupled to the controller via a memory interface;

wherein each of the memory components includes a memory cyclic redundancy check, CRC, engine configured to perform CRC checking of data during read and write operations between the host and the memory array; a kind of electronic device with high-pressure air-conditioning system

A controller including one or more controller CRC engines and configured to communicate with the memory components to control data transfer among the memory, the host, and the memory array.

2. The computing system of claim 1, wherein the memory CRC engine and the controller CRC engine are configured to perform a retry operation when an error is detected via the memory interface.

3. The computing system of claim 2, wherein each memory CRC engine and controller CRC engine comprises a CRC generator and a CRC check component;

wherein the CRC generator comprises a CRC parity generator for receiving data and performing a combinational logic operation to obtain a CRC parity; a kind of electronic device with high-pressure air-conditioning system

Wherein the CRC component is configured to transmit the received data to the CRC parity generator and compare, via a comparator, a calculated CRC parity of the CRC parity generator with the CRC parity to determine if there is a data match.

4. The computing system of claim 3, wherein during a read operation, the controller is configured to send commands for data from the host to the memory.

5. The computing system of claim 4, wherein the memory component is configured to retrieve the data from the memory array and send the retrieved data to the CRC generator to generate the CRC parity;

wherein the generated CRC parity is compared to the CRC parity of the data; a kind of electronic device with high-pressure air-conditioning system

Wherein data is sent to the host when there is a match of data.

6. The computing system of claim 3, wherein during a write operation, the controller is configured to send data to the memory component to be written;

wherein the memory component is configured to perform a CRC check on the data received via the CRC check component of the CRC engine to detect errors on the memory interface;

wherein the data is sent to the controller CRC generator to (i) generate a CRC parity and (ii) compare the generated CRC parity to a CRC parity received at the CRC check component of the memory CRC engine; a kind of electronic device with high-pressure air-conditioning system

Wherein data is sent to the memory array when there is a match of data.

7. The computing system of claim 6, wherein when an error is detected during a CRC check of the write operation, the memory component is configured to perform a CRC retry operation via the memory CRC engine that cancels the error when the error is a first test.

8. The computing system of claim 7, wherein the data is retrieved via a RAID recovery operation when the detected error is not a first test.

9. A method, comprising:

disposing a memory CRC engine in a memory and a controller CRC engine in a controller that controls data transfer between the memory and a host in communication therewith;

wherein each memory component of the memory includes a memory CRC engine of the plurality of CRC engines; a kind of electronic device with high-pressure air-conditioning system

During read and write operations between the host and the memory array of the memory, a CRC check of data is performed via a memory CRC engine and a controller CRC engine.

10. The method of claim 9, wherein the read operation comprises:

sending a command for data from the host to the memory via a controller, and retrieving the data from the memory array via the memory component; a kind of electronic device with high-pressure air-conditioning system

Send the data to (i) a CRC generator of the memory CRC engine for generating CRC parity, and (ii) a CRC check component of the controller CRC engine; a kind of electronic device with high-pressure air-conditioning system

Comparing the generated CRC parity with a CRC parity for the data; and sending the data to the host when a match of the data occurs.

11. The method of claim 10, wherein when an error is detected at the memory interface during a CRC check of the read operation, performing a CRC retry operation at the controller via the controller CRC engine to cancel the error when it is a first test, and wherein when it is determined not to be a first test, then retrieving the data via a redundant array of independent disks RAID recovery operation.

12. The method of claim 10, wherein the write operation comprises:

sending data to the memory component to be written via a command of the controller, and performing a CRC check via the memory component on the data received via the CRC check component of the memory CRC engine to detect whether there are any errors on the memory interface; a kind of electronic device with high-pressure air-conditioning system

Send the data to the controller CRC generator to generate CRC parity and to the CRC check component of the memory CRC engine for comparing the generated CRC parity with received CRC parity;

wherein data is sent to the memory array when a match of the data occurs.

13. The method of claim 12, wherein when an error is detected at the memory interface during a CRC check of the write operation, performing a CRC retry operation at the memory component via the memory CRC engine to cancel the error when the error is a first test.

14. The method of claim 13, wherein the data is retrieved via a RAID recovery operation when the error is not a first test.

15. A memory system, comprising:

a memory including one or more memory components and a memory array;

wherein each of the memory components includes a memory cyclic redundancy check, CRC, engine configured to perform CRC checking of data during read and write operations between a host and the memory array; a kind of electronic device with high-pressure air-conditioning system

A controller (i) including one or more controller CRC engines, and (ii) configured to communicate with the memory components to control data transfers among the memory, the host, and the memory array.

16. The memory system of claim 15, wherein the memory CRC engine and the controller CRC engine are configured to perform a retry operation when an error is detected via the memory interface.

17. The memory system of claim 16, wherein each memory CRC engine and controller CRC engine comprises a CRC generator and a CRC check component,

wherein the CRC generator comprises a CRC parity generator for receiving data and performing a combinational logic operation to obtain a CRC parity; a kind of electronic device with high-pressure air-conditioning system

Wherein the CRC component is configured to (i) transmit the received data to the CRC parity generator, and (ii) compare, via a comparator, a calculated CRC parity of the CRC parity generator with a CRC parity received from the CRC generator of the memory CRC engine to determine whether a data match occurs.

18. The memory system of claim 17, wherein during a read operation, the controller is configured to send a command for data from the host to the memory;

wherein the memory component is configured to retrieve the data from the memory array and send the data to the CRC generator for generating the CRC parity and to send the data to the CRC component of the controller CRC engine;

wherein the generated CRC parity is compared to the CRC parity of the data; a kind of electronic device with high-pressure air-conditioning system

Wherein data is sent to the host when a match of data occurs.

19. The memory system of claim 18, wherein when an error is detected at the memory interface during a CRC check of the read operation, the controller is configured to perform a CRC retry operation via the controller CRC engine; a kind of electronic device with high-pressure air-conditioning system

Wherein the CRC retry operation cancels the error when the error is the first test.

20. The memory system of claim 19, wherein the data is retrieved via a redundant array of independent disks RAID recovery operation when the error is not a first test.