CN116483282A - Data caching system for discontinuous NVMe address transmission - Google Patents

Data caching system for discontinuous NVMe address transmission Download PDF

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Publication number
CN116483282A
CN116483282A CN202310468964.8A CN202310468964A CN116483282A CN 116483282 A CN116483282 A CN 116483282A CN 202310468964 A CN202310468964 A CN 202310468964A CN 116483282 A CN116483282 A CN 116483282A
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China
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address
data
cache
memory
packet
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CN202310468964.8A
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Chinese (zh)
Inventor
付溢华
李瑞东
刘奇浩
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Shandong Sinochip Semiconductors Co Ltd
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Shandong Sinochip Semiconductors Co Ltd
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Priority to CN202310468964.8A priority Critical patent/CN116483282A/en
Publication of CN116483282A publication Critical patent/CN116483282A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/222—Non-volatile memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The invention provides a data caching system for discontinuous address transmission of NVMe, and belongs to the technical field of data storage. And expanding a single source address or a destination address of direct memory access in the NVMe controller, and configuring the single source address or the destination address into a descriptor format for containing multiple addresses and configuration information. The designed data caching system receives read address or write address information sent by direct memory access, namely configured descriptor information, analyzes the read address or write address information, acquires a plurality of sections of addresses required to be transmitted by data, and reads or writes the data. The system can internally comprise a plurality of data caching subsystems and data caching spaces, so that the requirement of parallel data processing is met, and the data transmission performance is improved. The system can support the feedback of the internal execution state and the running error information at the same time, so that the processor and the external module can sense the data transmission state and debug and analyze in use.

Description

Data caching system for discontinuous NVMe address transmission
Technical Field
The invention relates to a data caching system for discontinuous address transmission of NVMe, and belongs to the technical field of data storage.
Background
The non-volatile memory host controller interface (NVMe) is a low-latency, internally concurrency bus transport protocol (tcp) specification, and is commonly used in storage systems such as Solid State Disks (SSDs). NVMe can connect hosts (host) and memory subsystems and provide high-speed, non-uniform memory access optimized, highly scalable transport. The NVMe controller often performs data movement through direct memory access (Direct memory access), so as to realize bidirectional transmission of data between the host end and the memory subsystem. Currently common direct memory access often enables data transfer by configuring a source address and a destination address, however this greatly limits the flexibility of data transfer. In practical applications, to achieve flexible management of memory space, it is often necessary for data to be stored in the memory subsystem as non-contiguous addresses. At this time, the direct memory access cannot meet the transmission requirement of multi-source address or multi-destination address.
Disclosure of Invention
The invention aims to provide a data caching system for discontinuous address transmission of NVMe, which improves the flexibility of an NVMe storage system.
The invention aims to achieve the aim, and the aim is achieved by the following technical scheme:
the system comprises a direct memory access module, a data cache module, a memory subsystem and a microprogram controller; the micro-program controller is connected with the direct memory access, the data cache module and the memory subsystem, and the direct memory access and the memory subsystem are also connected with the data cache module;
the micro program controller configures a source address or a destination address of direct memory access as a descriptor and sends the descriptor to a data cache module; when host reads data, the source address of direct memory access is a memory address; when host writes data, the destination address of direct memory access is a memory address;
the direct memory access takes the descriptor as an access address and sends the access address to the data caching module;
the data caching module divides data, caches and transmits the data by taking a caching packet as a unit, the caching packet is provided with an identifier, the size of the identifier is an integer multiple of the number of logic blocks, and the data caching module receives descriptors sent by a direct access memory and analyzes the descriptors to acquire data transmission address information;
the memory subsystem provides memory for the system.
Preferably, the descriptor includes a memory base address, a buffer packet identifier, a buffer packet number, an address mode, and configuration information of the data buffer module.
Preferably, the address modes in the descriptor include a cache packet address mode and a cache packet address linked list mode, wherein the cache packet address mode stores the cache packet in the memory subsystem continuously, and the cache packet address linked list mode stores the cache packet in the memory subsystem discontinuously.
Preferably, in the cache packet address mode, the micro program controller configures a memory base address BA, a cache packet identifier BID and cache packet number BN information in the descriptor, and the data cache module calculates a memory head address corresponding to each cache packet according to the descriptor and BS configured by the micro program controller, and continuously stores BN cache packets into the memory, where the memory head address=ba+bid.
Preferably, in the buffer packet address linked list mode, the microprogrammed controller configures an address stored in a memory base address BA and an address chain in a descriptor, writes address chain information in the address, and the data buffer module firstly acquires the address chain storage address from the descriptor, then acquires a plurality of address chain information from the address chain storage address, and analyzes the address of the buffer packet; the address range indicated by each address chain is continuous, and the address chain list is stored in the memory subsystem or the data cache module.
Preferably, in the buffer packet address linked list mode, the address chain information comprises buffer packet identifiers BIDs of buffer packets, buffer packet numbers BN and linked list connection information, wherein the linked list information comprises a next address chain address and linked list ending symbol information; the address chain is defined as either continuous storage in the address space or discontinuous storage by indicating the next linked list address in the address chain.
Preferably, in the buffer packet address linked list mode, the data buffer module calculates a memory head address pointed by each address chain according to the buffer packet identifier BID and the buffer packet quantity BN information in each linked list, and continuously stores BN buffer packets into the memory, wherein the address chain points to the memory head address=ba+bid.
Preferably, the data caching module comprises one or more data caching sub-modules; and a buffer space for buffering transmission data is configured in the data buffer module.
The invention has the advantages that: the invention realizes the segmented storage of the data in the memory subsystem and has a certain address flexibility which can be managed by the processor. The designed system can internally comprise a plurality of data caching subsystems and data caching spaces, so that the requirement of data parallel processing is met, and the data transmission performance is improved. The system can support the feedback of the internal execution state and the running error information at the same time, so that the processor and the external module can sense the data transmission state and debug and analyze in use.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention.
Fig. 1 is a schematic diagram of a data buffer system for NVMe discontinuous address transmission according to the present invention.
FIG. 2 is a diagram showing the correspondence between memory subsystem addresses and the BID of the cache packet identifier according to the present invention.
FIG. 3 is a diagram illustrating a memory address range indicated by a descriptor in a buffered packet address mode according to the present invention.
FIG. 4 is a diagram showing a descriptor indicating an address where an address chain is located and an address chain indicating a memory address range in a buffer packet address chain table mode according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A data buffer system for non-continuous address transmission of NVMe (network video Messaging) expands a single source address or destination address of direct memory access in an NVMe controller, and configures the single source address or destination address into a descriptor format for containing multiple addresses and configuration information. The designed data caching system receives read address or write address information sent by direct memory access, namely configured descriptor information, analyzes the read address or write address information, acquires a plurality of sections of addresses required to be transmitted by data, and reads or writes the data. The system can internally comprise a plurality of data caching subsystems and data caching spaces, so that the requirement of parallel data processing is met, and the data transmission performance is improved. The system can support the feedback of the internal execution state and the running error information at the same time, so that the processor and the external module can sense the data transmission state and debug and analyze in use.
The system comprises a direct memory access module, a data cache module, a memory subsystem and a microprogram controller; the micro-program controller is connected with the direct memory access, the data cache module and the memory subsystem, and the direct memory access and the memory subsystem are also connected with the data cache module;
the data caching module divides data, caches and transmits the data by taking a caching packet as a unit, the caching packet is provided with an identifier, the size of the identifier is an integer multiple of the number of logic blocks, and the data caching module receives and analyzes the descriptor sent by the micro-program controller to acquire data transmission address information; the data caching module comprises one or more data caching sub-modules; and a buffer space for buffering transmission data is configured in the data buffer module.
The micro program controller configures a source address or a destination address of direct memory access as a descriptor and sends the descriptor to a data cache module; when host reads data, the source address of direct memory access is a memory address; when host writes data, the destination address of direct memory access is a memory address; the descriptor comprises a memory base address, a buffer packet identifier, the number of buffer packets, an address mode and configuration information of a data buffer module. The address modes in the descriptor comprise a cache packet address mode and a cache packet address linked list mode, wherein the cache packet address mode continuously stores cache packets in the memory subsystem, and the cache packet address linked list mode discontinuously stores the cache packets in the memory subsystem.
The memory subsystem provides memory for the system.
In the buffer packet address mode, the micro program controller configures BA, BID and BN information in the descriptor, and the data buffer module calculates a memory head address corresponding to each buffer packet according to the descriptor and BS configured by the micro program controller, and continuously stores BN buffer packets into the memory, where the memory head address=ba+bid.
In the buffer packet address chain list mode, the microprogrammed controller configures addresses stored in BA and address chain in the descriptor, and writes address chain information in the addresses, the data buffer module firstly acquires the address chain storage address from the descriptor, then acquires a plurality of address chain information from the address chain storage address, and analyzes the address of the buffer packet; wherein the address ranges indicated by each address chain are consecutive. The address chain information comprises BID, BN and link list connection information of the cache packet, wherein the link list information comprises the address of the next address chain and link list terminator information; the address chain is defined as either continuous storage in the address space or discontinuous storage by indicating the next linked list address in the address chain. The data caching module calculates a memory head address pointed by each address chain according to BID and BN information in each linked list, and continuously stores BN cache packets into a memory, wherein the address chain points to the memory head address=BA+BID.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. The data caching system for the discontinuous address transmission of the NVMe is characterized by comprising a direct memory access module, a data caching module, a memory subsystem and a micro-program controller; the micro-program controller is connected with the direct memory access, the data cache module and the memory subsystem, and the direct memory access and the memory subsystem are also connected with the data cache module;
the micro program controller configures a source address or a destination address of direct memory access as a descriptor and sends the descriptor to a data cache module; when host reads data, the source address of direct memory access is a memory address; when host writes data, the destination address of direct memory access is a memory address;
the direct memory access takes the descriptor as an access address and sends the access address to the data caching module;
the data caching module divides data, caches and transmits the data by taking a caching packet as a unit, the caching packet is provided with an identifier, the size of the identifier is an integer multiple of the number of logic blocks, and the data caching module receives descriptors sent by a direct access memory and analyzes the descriptors to acquire data transmission address information;
the memory subsystem provides memory for the system.
2. The data caching system for non-contiguous address transmission of NVMe according to claim 1, wherein the descriptor includes a memory base address, a cache packet identifier, a number of cache packets, an address pattern, and data caching module configuration information.
3. The data caching system for non-contiguous address transmission of NVMe according to claim 1, wherein the address patterns in the descriptor include a cache packet address pattern and a cache packet address linked list pattern, the cache packet address pattern storing cache packets in the memory subsystem in succession, the cache packet address linked list pattern storing cache packets in the memory subsystem in non-succession.
4. The data caching system for non-continuous address transmission of NVMe according to claim 3, wherein in the cache packet address mode, the micro-program controller configures a base memory address BA, a cache packet identifier BID, and a cache packet number BN information in the descriptor, and the data caching module calculates a memory head address corresponding to each cache packet according to the descriptor and a cache packet size BS configured by the micro-program controller, and continuously stores BN cache packets into the memory, where the memory head address=ba+bid.
5. The data caching system for discontinuous NVMe address transmission according to claim 3, wherein in the cache packet address linked list mode, the micro program controller configures an address stored in the memory base address BA and the address chain in the descriptor, writes address chain information in the address, and the data caching module first obtains the address chain stored address from the descriptor, then obtains a plurality of address chain information from the address chain stored address, and resolves the address of the cache packet; the address range indicated by each address chain is continuous, and the address chain list is stored in the memory subsystem or the data cache module.
6. The data caching system for non-continuous address transmission of NVMe according to claim 5, wherein in the cache packet address linked list mode, the address chain information includes a cache packet identifier BID of the cache packet, a number BN of the cache packet, and linked list connection information, wherein the linked list information includes a next address chain address, and linked list terminator information; the address chain is defined as either continuous storage in the address space or discontinuous storage by indicating the next linked list address in the address chain.
7. The data caching system for non-continuous NVMe address transmission according to claim 6, wherein in the cache packet address linked list mode, the data caching module calculates a memory head address pointed by each address chain according to the cache packet identifier BID and the number of cache packets BN information in each linked list, and continuously stores BN cache packets into the memory, wherein the address chain points to the memory head address=ba+bid.
8. The data caching system for non-continuous address transmission of NVMe according to claim 1, wherein the data caching module comprises one or more data caching sub-modules; and a buffer space for buffering transmission data is configured in the data buffer module.
CN202310468964.8A 2023-04-27 2023-04-27 Data caching system for discontinuous NVMe address transmission Pending CN116483282A (en)

Priority Applications (1)

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CN202310468964.8A CN116483282A (en) 2023-04-27 2023-04-27 Data caching system for discontinuous NVMe address transmission

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