CN116470906A - Power supply interference suppression circuit for phase-locked loop and phase-locked loop circuit - Google Patents

Abstract

The invention discloses a power supply interference suppression circuit and a phase-locked loop circuit for a phase-locked loop, wherein the phase-locked loop is powered by an external power supply, and the power supply interference suppression circuit comprises a first noise suppression module for suppressing noise in the external power supply provided to an analog unit in the phase-locked loop; the first noise suppression module includes: a source follower, a first capacitor, and a first switch; the source follower comprises a control end, an input end and an output end; the input end is connected with an external power supply, and the output end is connected with an analog unit in the phase-locked loop; the first capacitor is connected between the control end and the ground; the first switch is connected between the control end and the input end; the source follower is used for transmitting an external power supply to an analog unit in the phase-locked loop; the first switch is used for being closed or opened according to a control signal so as to enable an external power supply to supplement the electric leakage of the control end of the source follower; the first capacitor is used for filtering power supply noise conducted to the control end of the source follower. The scheme of the invention can reduce the power supply noise of the phase-locked loop.

Description

Power supply interference suppression circuit for phase-locked loop and phase-locked loop circuit

Technical Field

The invention relates to the technical field of circuits, in particular to a power supply interference suppression circuit for a phase-locked loop and a phase-locked loop circuit.

Background

As the application of the phase-locked loop in the chip is more and more widespread, the working frequency is continuously improved, and how to reduce the phase noise of the phase-locked loop and the jitter caused by the power noise becomes the key research content. In applications such as System on Chip (SoC) Chip and sensor Chip, because of numerous digital modules and analog modules in the Chip, a pll circuit very sensitive to power supply noise is easily interfered by external noise if not designed with strong power supply suppression, and especially for a pll with the largest SoC application, the pll becomes a module which is mainly considered to solve the problem of power supply interference due to the gain from high power supply fluctuation to output frequency.

The method of power supply disturbance rejection that is widely used in phase locked loops is to isolate the power supply using a low dropout linear regulator (low dropout regulator, LDO) 10, as shown in fig. 1, where VDDH is an external high voltage power supply, typically an analog voltage domain, and generate a power supply PLLVDD for the phase locked loop that is much lower in noise than the external high voltage power supply VDDH through the LDO, and the power supply is a power supply, and is simultaneously provided to a Phase Frequency Detector (PFD) and a frequency Divider (DIV) in a digital module 11 of the phase locked loop, and a Voltage Controlled Oscillator (VCO) and a Charge Pump (CP) in an analog module 12.

The problem of the circuit structure shown in fig. 1 is mainly that the noise crosstalk problem of different modules is mainly solved, the reference noise generated by the digital module pulling current is easy to generate ripple on the phase-locked loop power supply so as to deteriorate the output jitter generated by the oscillator and the charge pump, and larger current is required to be consumed for supplying power to all the modules, so that the sizes of the power tube in the low dropout linear voltage regulator 10 and the voltage stabilizing capacitor of the phase-locked loop power supply PLLVDD are required to be large.

For this reason, in an improved structure shown in fig. 2, the low dropout linear regulator 10 only supplies power to the analog module 12, and the digital module 11 is connected to the external low voltage power supply VDDL to solve the problem of reference noise, but in general, the power supply rejection performance of the low dropout linear regulator 10 has a larger loss at the sensitive frequency band (near the bandwidth of the phase-locked loop) of the voltage-controlled oscillator than at the low frequency, so that the low dropout linear regulator with full-band high power supply rejection is more difficult to design, and especially the isolation effect of the low dropout linear regulator is reduced when the external power supply interference is stronger.

In the prior art, as shown in fig. 3, the circuit structure does not have a low dropout linear regulator between the external high voltage power supply VDDH and the voltage-controlled oscillator 31 to perform power supply rejection, and the voltage-controlled oscillator 31 directly works in the high voltage domain.

As shown in fig. 3, the voltage-controlled oscillator 31 includes a voltage-to-current conversion circuit 311 and a ring oscillator 312 in a cascade structure, the voltage-to-current conversion circuit 311 is designed in a cascade structure using a voltage margin sufficient for a high voltage domain, and the phase-locked loop filter 32 is changed to be between control voltages Vctrl and VDDH, so that the voltage-to-current conversion circuit 311 achieves high power supply rejection, but the circuit has a problem in that the phase frequency detector and the charge pump have to operate in a high voltage domain at this time, or the phase frequency detector operates in a low voltage domain and outputs a signal to the charge pump through a high-speed level shifter, both of which generate a large instantaneous current in the high voltage domain and generate a large interference to other analog modules on the same chip. In addition, the power supply rejection performance of the voltage-to-current conversion circuit 311 is still greatly lost in the vco sensitive frequency band (near the pll bandwidth).

Disclosure of Invention

The embodiment of the invention provides a power supply interference suppression circuit for a phase-locked loop and the phase-locked loop circuit, which are used for improving the power supply interference suppression effect and reducing the power supply noise of the phase-locked loop.

In one aspect, an embodiment of the present invention provides a power supply interference suppression circuit for a phase-locked loop, where the phase-locked loop is powered by an external power supply, and the power supply interference suppression circuit includes a first noise suppression module, where the first noise suppression module is configured to suppress noise in the external power supply provided to an analog unit in the phase-locked loop;

the first noise suppression module includes: a source follower, a first capacitor, and a first switch; the source follower comprises a control end, an input end and an output end; the input end is connected with an external power supply, and the output end is connected with an analog unit in the phase-locked loop; the first capacitor is connected between the control end and the ground; the first switch is connected between the control end and the input end;

the source follower is used for transmitting the external power supply to an analog unit in the phase-locked loop;

the first switch is used for being closed or opened according to a control signal so that the external power supply supplements the electric leakage of the control end of the source follower;

the first capacitor is used for filtering power supply noise conducted to the control end of the source follower.

Optionally, the source follower includes a single or multiple MOS transistors.

Optionally, the source follower includes a first NMOS transistor; the grid of the first NMOS tube is the control end of the source follower, the drain electrode of the first NMOS tube is the input end of the source follower, and the source of the first NMOS tube is the output end of the source follower.

Optionally, the power supply interference suppression circuit further includes: and the control module is used for generating the control signal.

Optionally, the control signal is a periodic pulse signal, and is used for controlling the first switch to be turned on and off periodically after the external power supply is powered on.

Optionally, the on-off frequency of the first switch is smaller than the bandwidth of the phase-locked loop.

Optionally, the first noise suppression module further includes: and the grid electrode and the drain electrode of the second NMOS tube are connected with the external power supply, and the source electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube.

Optionally, the control signal is a pulse signal, and is used for controlling the first switch to be turned on and turned off after a set time when the external power supply is powered on.

Optionally, the first noise suppression module further includes: and the second capacitor is connected between the output end and the ground and is used for filtering voltage ripples generated at the output end of the source follower.

Optionally, the capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor.

Optionally, the analog unit comprises a voltage controlled oscillator.

Optionally, the circuit further comprises a second noise suppression module for suppressing noise in a power supply provided to the digital unit and/or the charge pump in the phase locked loop.

Optionally, the structure of the second noise suppression module is the same as the structure of the first noise suppression module.

Optionally, the digital unit includes: a phase frequency detector.

In another aspect, an embodiment of the present invention further provides a phase-locked loop circuit, including: a voltage controlled oscillator operating in the high voltage domain, a phase frequency detector, a charge pump, a loop filter, a frequency divider and a buffer operating in the low voltage domain, and the aforementioned power supply disturbance rejection circuit.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

according to the power supply interference suppression circuit and the phase-locked loop circuit for the phase-locked loop, provided by the embodiment of the invention, the noise suppression module is utilized to suppress the noise of the external power supply of the analog unit in the phase-locked loop, so that the noise crosstalk between sensitive modules in the same external voltage domain can be effectively avoided, the power supply interference suppression effect is improved, and the power supply noise of the phase-locked loop is reduced.

Furthermore, considering that the voltage-controlled oscillator and the charge pump both need to work in a high-voltage domain, the phase frequency detector in the phase-locked loop digital unit also works in the high-voltage domain, and meanwhile, certain power supply noise suppression is provided for the phase frequency detector and the charge pump and is isolated from the power supply noise suppression of the voltage-controlled oscillator, so that the high-speed level converter arranged between the phase frequency detector and the charge pump is avoided, and the influence on a sensitive module in the same voltage domain as the phase frequency detector is also avoided.

Drawings

FIG. 1 is a schematic diagram of a prior art power supply disturbance rejection circuit for a phase locked loop;

FIG. 2 is a schematic diagram of another prior art power supply disturbance rejection circuit for a phase locked loop;

FIG. 3 is a schematic diagram of another prior art power supply disturbance rejection circuit for a phase locked loop;

FIG. 4 is a schematic block diagram of a power supply disturbance rejection circuit for a phase locked loop provided by an embodiment of the present invention;

fig. 5 is a schematic diagram of a specific structure of a first noise suppression module in a power supply interference suppression circuit for a phase locked loop according to an embodiment of the present invention;

fig. 6 is a schematic diagram of another specific structure of a first noise suppression module in a power supply interference suppression circuit for a phase locked loop according to an embodiment of the present invention;

FIG. 7 is another schematic block diagram of a power supply disturbance rejection circuit for a phase locked loop provided by an embodiment of the present invention;

fig. 8 is a schematic diagram of a specific structure of a power supply interference suppression circuit for a phase locked loop according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Aiming at the problems that the power supply interference suppression circuit applied to the phase-locked loop in the prior art has noise crosstalk problems of different modules in a mode of providing power supply noise suppression by using a low-dropout linear voltage regulator, and the mode of realizing high power supply noise suppression by designing a voltage-current conversion circuit of a voltage-controlled oscillator into a cascade structure can generate larger instantaneous current on a high-voltage domain so as to generate great interference with other analog modules in a chip, the embodiment of the invention provides the power supply interference suppression circuit for the phase-locked loop, which utilizes a noise suppression module to perform noise suppression on an external power supply of an analog unit in the phase-locked loop, can effectively avoid noise crosstalk among sensitive modules in the same voltage domain, improves the power supply interference suppression effect and reduces the power supply noise of the phase-locked loop.

Fig. 4 is a schematic block diagram of a power supply interference suppression circuit for a phase locked loop according to an embodiment of the present invention.

The power supply disturbance rejection circuit 50 comprises a first noise rejection module 501 for rejecting noise in an external power supply VDDH provided to the analog unit 42 in the phase locked loop 40.

The phase-locked loop 40 includes a digital unit 41 and an analog unit 42, wherein the digital unit 41 mainly includes a frequency divider 411 and a phase frequency detector 412, and the analog unit 42 mainly includes a charge pump 421 and a voltage controlled oscillator 422.

In this example, the digital unit 41 may operate in the same voltage domain as the analog unit 42, or may operate in a different voltage domain, such as in the example of fig. 4, in which the digital unit 41 operates in a low voltage domain and the module unit 42 operates in a high voltage domain, and the operation of each module in two different voltage domains may be ensured by a level shift design between the digital unit 41 and the analog unit 42.

In practical applications, the first noise suppression module 50 may perform power supply noise suppression on the charge pump 421 and the voltage-controlled oscillator 422 in the analog unit 42 at the same time.

Further, considering that the charge pump is less sensitive to external power supply noise, in one non-limiting embodiment, the first noise suppression module 501 may also perform power supply noise suppression only for the voltage controlled oscillator 422 in the analog unit 42. The specific structure of the first noise suppression module 501 will be described in detail below by taking this as an example.

Referring to fig. 5, fig. 5 is a schematic diagram of a specific structure of a first noise suppression module in a power supply interference suppression circuit for a phase locked loop according to an embodiment of the present invention.

In this embodiment, the first noise suppression module 501 includes: a source follower 511, a first capacitor C1, and a first switch SW1. Wherein: the source follower 511 includes a control terminal, an input terminal, and an output terminal; the input is connected to an external power supply VDDH and the output is connected to a voltage controlled oscillator 422 in the phase locked loop.

The first capacitor C1 is connected between the control end and the ground; the first switch SW1 is connected between the control terminal and the input terminal.

In this embodiment, the source follower M1 is used to transmit the external power supply VDDH to the voltage controlled oscillator 422.

The first switch SW1 is configured to be turned on or off according to a control signal, so that the external power supply VDDH supplements the leakage of the control terminal of the source follower 511; the first capacitor C1 is used to filter out power supply noise conducted to the control terminal of the source follower 511.

In a specific application, the source follower 511 may be implemented by a MOS transistor, and may include a single or multiple MOS transistors.

For example, as shown in fig. 5, the source follower 511 includes a first NMOS transistor M1. The gate of the first NMOS transistor M1 is the control end of the source follower 511, the drain of the first NMOS transistor M1 is the input end of the source follower 511, and the source of the first NMOS transistor M1 is the output end of the source follower 511.

It should be noted that, in the case that the source follower 511 includes a plurality of MOS transistors, for example, two NMOS transistors, the gates of the two NMOS transistors are connected to serve as the control end of the source follower 511, the drain of one NMOS transistor serves as the input end of the source follower 511 to be connected to the external power supply VDDH, the source is connected to the drain of the other NMOS transistor, and the source of the other NMOS transistor serves as the output end of the source follower 511 to be connected to the voltage-controlled oscillator 422.

In this embodiment, a control signal is input to the gate of the first NMOS transistor M1, where the control signal is a periodic pulse signal, and is used to control the first switch SW1 to be turned on and off periodically after the external power supply VDDH is powered on.

The working principle thereof is explained below with reference to fig. 5.

Referring to fig. 5, the first switch SW1 is periodically turned on under the control of a periodic pulse signal to supplement the slow leakage of the gate of the first NMOS transistor M1, and ideally the capacity of supplementing the first switch SW1 with charges is equal to the leakage of the gate of the first NMOS transistor M1.

In this way, a potential which is hardly interfered by the external power supply VDDH is generated for the gate of the first NMOS transistor M1, so that the first NMOS transistor M1 forms a source follower, and the effect of suppressing the external power supply interference is achieved.

Because the grid electrodes of the NMOS tubes are thick gate oxide tubes, the electric leakage of the grid electrode of the first NMOS tube M1 is very small, so that the on-resistance of the first switch SW1 should take a larger value to prevent the strong sampling effect on external power noise during the on process, and further influence on the grid voltage of the first NMOS tube M1, otherwise, the voltage entering the grid electrode of the first NMOS tube M1 becomes noise with the frequency of the sampling frequency of the first switch SW1, and the worst case is in a square wave shape. In addition, the on-off frequency of the first switch SW1 should be far smaller than the bandwidth of the phase-locked loop, so as to prevent the sampling noise from being transmitted to the phase-locked loop output through the oscillator.

In another non-limiting embodiment, as shown in fig. 5, the first noise suppression module 501 further includes a second capacitor C2, where the second capacitor C2 is connected between the output terminal of the source follower 511 and ground, and is used to filter out the voltage ripple generated at the output terminal of the source follower 511. The voltage ripple refers to a power frequency alternating current component contained in the output direct current voltage.

In practical applications, the capacitance of the second capacitor C2 may be smaller than that of the first capacitor C1, i.e., the capacitance of the second capacitor C2 is smaller than that of the first capacitor C1. Of course, the two may take the same value, and the embodiment of the present invention is not limited thereto.

Fig. 6 is a schematic diagram of another specific structure of the first noise suppression module in the power supply interference suppression circuit for a phase-locked loop according to the embodiment of the present invention.

In this embodiment, the first noise suppression module 50 includes: the first NMOS transistor M1, the second NMOS transistor M2, the first capacitor C1 and the second capacitor C2.

The connection relationship between the first NMOS transistor M1, the second NMOS transistor M2, the first capacitor C1, and the second capacitor C2 is the same as that in the embodiment shown in fig. 5, and will not be described herein.

The gate and the drain of the second NMOS transistor M2 are both connected to the external power supply VDDH, and the source of the second NMOS transistor M2 is connected to the gate of the first NMOS transistor M1.

In this embodiment, the control signal applied to the gate of the first NMOS transistor M1 is a pulse signal for controlling the first switch SW1 to be turned off after a set time when the external power supply VDDH is powered on. The specific working principle is as follows:

in this embodiment, the second NMOS transistor M2 is connected by a diode, and functions as a small signal resistor. Since the gate-source voltage of the second NMOS transistor M2 connected to the diode is almost 0, the equivalent impedance is very high, resulting in very slow establishment of the first capacitor C1, and therefore, it is necessary to close the first switch SW1 for a period of time in the initial stage of power-up, the period of time is determined by the time for charging the first capacitor C1 to VDDH, which is typically several microseconds, so as to ensure establishment of the gate voltage of the first NMOS transistor M1, and the second NMOS transistor M2 with very high impedance and the first capacitor C1 form low-pass filtering with very low pole after the first switch SW1 is disconnected, so that external power noise conducted to the gate of the first NMOS transistor M1 in this path can be filtered, and a potential hardly interfered by the external power supply VDDH is generated to the gate of the first NMOS transistor M1. In addition, the second NMOS transistor M2 with a large impedance is used to supplement the possible leakage current of the gate of the first NMOS transistor M1.

Since the first NMOS transistor M1 and the second NMOS transistor M2 are thick gate oxide transistors when operating in the high voltage domain, the leakage current is very slow in general, and therefore, devices with very large equivalent impedance can be used to supplement the leakage current. When the impedance formed by the second NMOS transistor M2 is large, the power supply rejection of the source follower formed by the first NMOS transistor M1 is positively correlated with the ratio of the first capacitance C1 to the gate-drain capacitance Cgd1 of the first NMOS transistor M1, so the first capacitance C1 should be made as large as possible within the area allowance range. Since the oscillator current is relatively stable, the voltage ripple generated at the source of the first NMOS transistor M1 is relatively small, and thus the second capacitor C2 may take a relatively small value with respect to the first capacitor C1.

In addition, since the first NMOS transistor M1 consumes a certain voltage margin, the first NMOS transistor M1 may be a low threshold transistor when the voltage margin requirement of the voltage-controlled oscillator 422 is high.

In the embodiments of fig. 5 and 6, the first NMOS transistor M1 may form the source follower by applying the periodic pulse signal and the aperiodic pulse signal to the gate of the first NMOS transistor M1, so as to achieve the effect of suppressing the external power supply interference. By reasonably designing the sizes of the first NMOS transistor M1, the first capacitor C1, the second capacitor C2, and the first switch SW1, the power supply suppression effects of the embodiments shown in fig. 5 and 6 can be substantially identical.

In another non-limiting embodiment of the power supply interference suppression circuit of the present invention, the power supply interference suppression circuit 50 may further comprise: a control module (not shown) for generating the control signal. Corresponding to the first noise suppression module 501 in the embodiment shown in fig. 5, the control module generates a periodic pulse signal to control the periodic on-off of the first switch SW 1; corresponding to the first noise suppression module 501 in the embodiment shown in fig. 6, the control module generates an aperiodic pulse signal to control the first switch SW1 to be turned off after a set time when the external power is powered on.

Fig. 7 is another schematic block diagram of a power supply interference suppression circuit for a phase locked loop according to an embodiment of the present invention.

In this embodiment, the power supply interference suppression circuit 50 includes a first noise suppression module 501 and a second noise suppression module 502, where the first noise suppression module 501 is configured to suppress noise in the power supply VDD1 provided to the analog unit 42 of the phase-locked loop 40, and the second noise suppression module 502 is configured to suppress noise in the power supply VDD2 provided to the digital unit 41 of the phase-locked loop 40, and further to avoid the influence of noise generated by the operation of the digital unit 41 of the phase-locked loop on other sensitive analog modules.

Note that, the power supply VDD1 and the power supply VDD2 may be the same or different, which is not limited to the embodiment of the present invention.

In another non-limiting embodiment, the power supply noise of the voltage controlled oscillator 422 and the charge pump 421 may also be suppressed by the first noise suppression module 501 and the second noise suppression module 502, respectively.

As mentioned above, the digital unit 41 may operate in the high voltage domain VDDH or in the low voltage domain VDDL. If operating in the low voltage domain VDDL, a high-speed level shifter is required between the phase frequency detector 412 and the charge pump 421 to ensure proper operation of both in the different voltage domains.

Since the voltage controlled oscillator 422 is operating in the high voltage domain VDDH, the charge pump also needs to operate in the high voltage domain VDDH. Since the signal output from the phase frequency detector 412 to the charge pump 421 is a narrow pulse, the phase frequency detector in the digital unit 41 can be operated in the high voltage domain VDDH in order to avoid the design of a high-speed level shifter with high cost, and thus only a low-speed level shifter is needed at the input end of the phase frequency detector 412, which will be described in detail below with reference to fig. 8.

Referring to fig. 8, a schematic diagram of a specific structure of a power supply interference suppression circuit for a phase locked loop according to an embodiment of the present invention is shown.

In this embodiment, the vco 422 and the charge pump 421 operate in the high voltage domain VDDH, and the phase frequency detector 412 also operates in the high voltage domain VDDH, so that a low-speed level shifter is used at the input of the phase frequency detector 412.

Since the instantaneous current of the phase frequency detector 412 can reach several milliamperes, in order to avoid the influence on the sensitive module under the external same voltage domain, a certain power supply noise suppression is provided for the phase frequency detector 412 and the charge pump 421, and in addition, the reference noise generated by the phase frequency detector 412 is prevented from affecting the voltage-controlled oscillator 422, and the second noise suppression module 502 is introduced to separately suppress the power supply noise of the phase frequency detector 412 and the charge pump 421 and isolate the power supply noise from the voltage-controlled oscillator 422. The first noise suppression module 501 alone suppresses the supply noise of the voltage controlled oscillator 422.

In this embodiment, the first noise suppression module 501 may adopt the structure of the embodiment shown in fig. 5 or fig. 6, the specific structure of the second noise suppression module 502 may also adopt the structure of the first noise suppression module 501 shown in fig. 5 or fig. 6, and both may adopt the same structure at the same time, or one may adopt the structure shown in fig. 5, and the other adopts the structure shown in fig. 6.

As shown in fig. 8, the second noise suppression module 502 includes a third NMOS transistor M3, a fourth NMOS transistor M4, a third capacitor C3, a fourth capacitor C4, and a second switch SW2, and the operation mode and principle thereof can refer to the description of the first noise suppression module 501 in fig. 6, except that the values of the capacitors C3 and C4 are different from those of the capacitors C1 and C2.

Since the phase frequency detector 412 and the charge pump 421 have low sensitivity to power supply noise, the capacitance of the capacitor C3 may be suitably small relative to the capacitance C1. In addition, since the instantaneous current of the phase frequency detector 412 generates a voltage ripple at the source of the third NMOS transistor M3, the capacitance C4 can be appropriately larger than the capacitance C3.

Since the power consumption of the phase frequency detector 412 and the charge pump 421 is much smaller than that of the voltage controlled oscillator 422, the size of the third NMOS transistor M3 may take a smaller value than that of the first NMOS transistor M1.

In this embodiment, the suppression of the instantaneous current peak of the phase frequency detector 412 results from the voltage margin sacrificed by the third NMOS transistor M3 and the voltage stabilizing effect of the capacitor C4.

In another non-limiting embodiment, a control module (not shown) may also be provided in the embodiment shown in fig. 8, for generating a control signal to control the on/off of the first switch SW1 and the second switch SW2, respectively.

According to the power supply interference suppression circuit for the phase-locked loop, provided by the embodiment of the invention, the noise suppression module is utilized to suppress the noise of the external power supply of the analog unit in the phase-locked loop, so that the noise crosstalk between sensitive modules in the same external voltage domain can be effectively avoided, the power supply interference suppression effect is improved, and the power supply noise of the phase-locked loop is reduced.

Furthermore, considering that the voltage-controlled oscillator and the charge pump both need to work in a high-voltage domain, the phase frequency detector in the phase-locked loop digital unit also works in the high-voltage domain, and meanwhile, certain power supply noise suppression is provided for the phase frequency detector and the charge pump and is isolated from the power supply noise suppression of the voltage-controlled oscillator, so that the high-speed level converter arranged between the phase frequency detector and the charge pump is avoided, and the influence on a sensitive module in the same voltage domain as the phase frequency detector is also avoided.

Correspondingly, the embodiment of the invention also provides a phase-locked loop circuit, as shown in fig. 9, which is a schematic structural diagram of the phase-locked loop circuit.

The phase-locked loop is a negative feedback control system which uses the voltage generated by phase synchronization to tune the voltage-controlled oscillator to generate the target frequency, is a typical feedback control circuit, and uses the externally input reference signal to control the frequency and phase of the oscillation signal in the loop, so as to realize the automatic tracking of the output signal frequency to the input signal frequency.

The phase-locked loop circuit includes: a voltage controlled oscillator 422 operating in the high voltage domain, a phase frequency detector 412, a charge pump 421, a loop filter 433, a frequency divider and a level shifter 432 operating in the low voltage domain, wherein the frequency divider includes an input frequency divider 431, an output frequency divider 434, and a loop frequency divider 435. In addition, the phase-locked loop circuit further includes the power supply interference suppression circuit 50.

The power supply interference suppression circuit 50 includes a first noise suppression module 501 and a second noise suppression module 502, where the first noise suppression module 501 performs power supply noise suppression on the voltage-controlled oscillator 422, and the second noise suppression module 502 performs power supply noise suppression on the phase frequency detector 412 and the charge pump 421.

In this embodiment, the functions of the above modules are as follows:

input divider 431: a clock signal REFCLK is received from outside the phase-locked loop, and a down-converted reference clock signal suitable for phase-locked loop applications is output.

Level shifter 432: for level converting said reference clock signal, i.e. converting the reference clock signal in the low voltage domain into the reference clock signal in the high voltage domain.

Phase frequency detector 412: the reference clock signal and the feedback clock signal FBCLK output by the loop divider 435 are received, and the phase difference between the two is compared to output corresponding up and down signals. If the phase difference of the reference clock compared with the feedback clock is negative, namely the reference clock signal is behind the feedback clock signal, the down signal is high, and the up signal is low; if the phase difference of the reference clock compared with the feedback clock is positive, i.e. the reference clock signal leads the feedback clock signal, the up signal is high and the down signal is low; if the reference clock arrives at the same time as the feedback clock, the output up and down signals are both high and low for a period of time, which is typically determined by a delay circuit in the phase frequency detector circuit.

Charge pump 421: receiving the up signal and the down signal from the output of the phase frequency detector 412, and if the up signal is at a high level and the down signal is at a low level, the charge pump circuit 421 outputs a charging current to the loop filter 433, so that the output voltage of the loop filter 433 is increased, and the frequency of the voltage-controlled oscillator 422 is increased; if the up signal is low and the down signal is high, the charge pump circuit 421 draws a discharge current from the loop filter 433, so that the output voltage of the loop filter 433 is reduced, and the frequency of the voltage-controlled oscillator 422 is reduced; if the up signal and the down signal are at high level at the same time, the charge and discharge currents are simultaneously turned on, and if there is no mismatch between the charge and discharge currents, the output voltage of the loop filter 433 remains unchanged, and the output frequency of the voltage-controlled oscillator 422 remains unchanged; if the up signal and the down signal are both low, and the charge and discharge currents are simultaneously turned off, the output voltage of the loop filter 433 remains unchanged, and the output frequency of the voltage-controlled oscillator 422 remains unchanged.

Loop filter 433: the current signal output by the charge pump 421 is received and converted into a voltage signal to be output to the voltage-controlled oscillator 422, and the voltage-controlled oscillator 422 changes its output frequency according to the magnitude of the voltage signal.

Voltage controlled oscillator 422: the output voltage from the loop filter 433 is received, and a clock signal of a corresponding frequency fout is output according to the magnitude of the output voltage.

Loop divider 435: the clock signal fout from the output of the voltage controlled oscillator 422 is received, and the down-converted feedback clock signal FBCLK is output.

Output divider 434: the clock signal fout from the output of the voltage controlled oscillator 422 is received, the down-converted clock signal fclk is output, and the clock signal fclk is provided to a module other than the phase-locked loop.

It should be noted that the above-mentioned phase-locked loop circuit structure is only an example, and of course, in practical applications, the phase-locked loop circuit may have other modified structures, and the power supply interference suppression circuit 50 provided in the embodiment of the present invention may also be applicable to phase-locked loops with other modified structures.

In a specific implementation, regarding each apparatus and each module/unit included in each product described in the above embodiments, it may be a software module/unit, or a hardware module/unit, or may be a software module/unit partially, or a hardware module/unit partially.

For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least part of the modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the rest (if any) of the modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented by using hardware such as a circuit, different modules/units may be located in the same component (for example, a chip, a circuit module, or the like) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program, where the software program runs on a processor integrated inside the terminal, and the remaining (if any) part of the modules/units may be implemented by using hardware such as a circuit.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.

The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order division is used, nor does it indicate that the number of the devices in the embodiments of the present application is particularly limited, and no limitation on the embodiments of the present application should be construed.

The "connection" in the embodiments of the present application refers to various connection manners such as direct connection or indirect connection, so as to implement communication between devices, which is not limited in any way in the embodiments of the present application.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. A power supply interference suppression circuit for a phase locked loop, the phase locked loop being powered by an external power supply, the power supply interference suppression circuit comprising a first noise suppression module for suppressing noise in the external power supply provided to an analog unit in the phase locked loop;

the first noise suppression module includes: a source follower, a first capacitor, and a first switch; the source follower comprises a control end, an input end and an output end; the input end is connected with an external power supply, and the output end is connected with an analog unit in the phase-locked loop; the first capacitor is connected between the control end and the ground; the first switch is connected between the control end and the input end;

the source follower is used for transmitting the external power supply to an analog unit in the phase-locked loop;

the first switch is used for being closed or opened according to a control signal so that the external power supply supplements the electric leakage of the control end of the source follower;

the first capacitor is used for filtering power supply noise conducted to the control end of the source follower.

2. The power supply disturbance rejection circuit for a phase locked loop according to claim 1, wherein the source follower comprises a single or multiple MOS transistors.

3. The power supply disturbance rejection circuit for a phase locked loop according to claim 2, wherein the source follower comprises a first NMOS transistor; the grid of the first NMOS tube is the control end of the source follower, the drain electrode of the first NMOS tube is the input end of the source follower, and the source of the first NMOS tube is the output end of the source follower.

4. A power supply disturbance rejection circuit for a phase locked loop according to claim 3, wherein said power supply disturbance rejection circuit further comprises:

and the control module is used for generating the control signal.

5. The power supply disturbance rejection circuit for a phase locked loop according to claim 4, wherein the control signal is a periodic pulse signal for controlling the first switch to be periodically turned on and off after the external power supply is powered on.

6. The power supply disturbance rejection circuit for a phase locked loop according to claim 5, wherein an on-off frequency of the first switch is less than a bandwidth of the phase locked loop.

7. The power supply disturbance rejection circuit for a phase locked loop according to claim 4, wherein said first noise suppression module further comprises: and the grid electrode and the drain electrode of the second NMOS tube are connected with the external power supply, and the source electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube.

8. The power supply disturbance rejection circuit for a phase locked loop according to claim 7, wherein the control signal is a pulse signal for controlling the first switch to open after a set time period when the external power supply is powered on.

9. The power supply disturbance rejection circuit for a phase locked loop according to claim 1, wherein the first noise suppression module further comprises: and the second capacitor is connected between the output end and the ground and is used for filtering voltage ripples generated at the output end of the source follower.

10. The power supply disturbance rejection circuit for a phase locked loop according to claim 9, wherein a capacitance value of the second capacitor is smaller than a capacitance value of the first capacitor.

11. A power supply disturbance rejection circuit for a phase locked loop according to any of claims 1 to 10 wherein the analogue unit comprises a voltage controlled oscillator.

12. The power supply disturbance rejection circuit for a phase locked loop according to claim 11, further comprising a second noise rejection module for rejecting noise in a power supply provided to a digital unit and/or a charge pump in the phase locked loop.

13. The power supply disturbance rejection circuit for a phase locked loop according to claim 12, wherein the second noise rejection module is configured identically to the first noise rejection module.

14. The power supply disturbance rejection circuit for a phase locked loop according to claim 12, wherein the digital unit comprises: a phase frequency detector.

15. A phase-locked loop circuit, the phase-locked loop circuit comprising: voltage controlled oscillators, phase frequency detectors, charge pumps, loop filters operating in the high voltage domain, frequency dividers and level shifters operating in the low voltage domain, and power supply disturbance rejection circuits according to any one of claims 1 to 14.