CN116470760A - Power supply circuit, voltage stabilizing device, power management chip and electronic equipment - Google Patents

Power supply circuit, voltage stabilizing device, power management chip and electronic equipment Download PDF

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Publication number
CN116470760A
CN116470760A CN202310430126.1A CN202310430126A CN116470760A CN 116470760 A CN116470760 A CN 116470760A CN 202310430126 A CN202310430126 A CN 202310430126A CN 116470760 A CN116470760 A CN 116470760A
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CN
China
Prior art keywords
voltage
transistor
circuit
sub
electrically connected
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CN202310430126.1A
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Chinese (zh)
Inventor
郑鹏
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Beijing Eswin Computing Technology Co Ltd
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Beijing Eswin Computing Technology Co Ltd
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Priority to CN202310430126.1A priority Critical patent/CN116470760A/en
Publication of CN116470760A publication Critical patent/CN116470760A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The disclosure provides a power supply circuit, a voltage stabilizing device, a power management chip and electronic equipment, which belong to the technical field of power control systems, wherein the power supply circuit is configured to provide a first voltage for a voltage stabilizer and comprises a frequency modulation sub-circuit, a logic control module, a voltage regulation sub-circuit and a detection sub-circuit; a detection sub-circuit configured to detect an electric signal output from a signal output terminal of the voltage regulator and generate a feedback signal; the frequency modulation sub-circuit is configured to perform frequency modulation according to a feedback signal fed back by the detection sub-circuit and generate a clock signal; a logic control module configured to generate a first control signal from a clock signal; and the voltage regulating sub-circuit is configured to convert the second voltage into the first voltage according to the first control signal.

Description

Power supply circuit, voltage stabilizing device, power management chip and electronic equipment
Technical Field
The disclosure belongs to the technical field of power control systems, and particularly relates to a power supply circuit, a voltage stabilizing device, a power management chip and electronic equipment.
Background
With the rapid development of electronic products, the requirements on the performance of power management chips in the fields of computers, communication, consumer electronics and the like are increasing. The power management chip has the development trend of smaller and smaller volume, higher and higher conversion efficiency and more frequent transient conversion. The switching power supply gradually becomes the first choice of the power management chip by virtue of higher conversion efficiency, simple circuit structure and the like. DC/DC converters are voltage converters that convert an input voltage and effectively output a fixed voltage, and are classified into three types: step-up DC/DC converter, step-down DC/DC converter, and step-up DC/DC converter.
In recent years, due to rapid development of portable devices, there is an increasing demand for display panels. In both liquid crystal (Liquid Crystal Display) display and Organic Light-Emitting Diode (OLED) display technologies, various input voltage values are required for driving the internal circuit module of the chip, for example, an Active-matrix Organic Light-Emitting Diode (Active-Matrix Organic Light-Emitting Diode) panel requires a large voltage and a wide input voltage range, so various DC/DC converters are required to convert the voltage of the lithium battery, however, the existing DC/DC converters have the problems of low efficiency in Light load and large output voltage difference in heavy load.
Disclosure of Invention
The present disclosure aims to solve at least one of the technical problems in the prior art, and provides a power supply circuit, a voltage stabilizing device, a power management chip and an electronic device.
In a first aspect, embodiments of the present disclosure provide a power supply circuit configured to provide a first voltage to a voltage regulator, the power supply circuit including a frequency modulation sub-circuit, a logic control module, a voltage regulation sub-circuit, and a detection sub-circuit;
the detection subcircuit is configured to detect an electric signal output by a signal output end of the voltage stabilizer and generate a feedback signal;
The frequency modulation sub-circuit is configured to perform frequency modulation according to a feedback signal fed back by the detection sub-circuit and generate a clock signal;
the logic control module is configured to generate a first control signal according to the clock signal;
the voltage regulating sub-circuit is configured to convert a second voltage into the first voltage according to the first control signal.
In some embodiments, the logic control module includes a logic control sub-circuit and a drive sub-circuit;
the logic control sub-circuit is configured to generate a second control signal subjected to logic operation according to the clock signal;
the driving sub-circuit is configured to generate the first control signal according to the second control signal to drive the voltage regulating sub-circuit.
In some embodiments, the drive sub-circuit comprises a first drive sub-circuit and a second drive sub-circuit, the first control signal comprising a first control sub-signal and a second control sub-signal, and the two being 180 ° out of phase;
the first drive sub-circuit is configured to generate the first control sub-signal in dependence on the second control signal, and the second drive sub-circuit is configured to generate the second control sub-signal in dependence on the second control signal.
In some embodiments, the voltage regulation subcircuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance, and a second capacitance; the switching characteristics of the first transistor, the second transistor, the third transistor and the fourth transistor are all the same;
the first pole of the first transistor is configured to receive the second voltage, the second pole of the first transistor is electrically connected to the second pole of the third transistor and the first pole of the first capacitor, the control pole of the first transistor is electrically connected to the first drive sub-circuit, the first pole of the third transistor is electrically connected to a first reference voltage terminal, the control pole of the third transistor is electrically connected to the second drive sub-circuit, the second pole of the second transistor is electrically connected to a second reference voltage terminal, the first pole of the second transistor is electrically connected to the second pole of the first capacitor and the first pole of the fourth transistor, the control pole of the second transistor is electrically connected to the first drive sub-circuit, the second pole of the fourth transistor is electrically connected to the first pole of the second capacitor and the voltage regulator, and the control pole of the fourth transistor is electrically connected to the second sub-circuit, the second pole of the second capacitor is electrically connected to a third reference voltage terminal.
In some embodiments, the detection subcircuit includes a first sampling unit, a voltage dividing unit, a current mirror circuit, and a second sampling unit;
the first sampling unit is configured to reduce the electric signal output by the signal output end of the voltage stabilizer by K1 times, generate a first detection current, and output the first detection current to the voltage dividing unit;
the voltage division unit is configured to reduce the first detection current by K2 times to generate a second detection current;
the current mirror circuit is configured to mirror the second detection current, generate the feedback signal, and output the feedback signal to the second sampling unit;
the second sampling unit is configured to output the feedback signal to the frequency modulation subcircuit.
In some embodiments, the first sampling unit includes a first sampling transistor; the current mirror circuit includes a first current source, a second current source, a fifth transistor, and a sixth transistor; the voltage dividing unit comprises a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor; the second sampling unit comprises a second sampling transistor;
the control electrode of the first sampling transistor is electrically connected with the voltage stabilizer, the first electrode of the first sampling transistor is electrically connected with the signal output end of the voltage stabilizer, and the second electrode of the first sampling transistor is electrically connected with the first end of the second voltage dividing resistor;
A first electrode of the fifth transistor is electrically connected to the first current source and the control electrode of the second sampling transistor, and a control electrode of the fifth transistor is electrically connected to the control electrode of the sixth transistor and the first electrode of the sixth transistor; a second electrode of the fifth transistor is electrically connected with a first end of the first voltage dividing resistor;
the second end of the first voltage dividing resistor is electrically connected with the first end of the second voltage dividing resistor, and the second end of the second voltage dividing resistor is electrically connected with the voltage regulating sub-circuit;
the first electrode of the sixth transistor is electrically connected with the second current source, the second electrode of the sixth transistor is electrically connected with the first end of the third voltage dividing resistor and the second electrode of the second sampling transistor, and the second end of the third voltage dividing resistor is electrically connected with the voltage regulating subcircuit; the first electrode of the second sampling transistor is electrically connected with the frequency modulation subcircuit.
In some embodiments, the detection subcircuit includes not only the structure described above, but also a seventh transistor and an eighth transistor; the control electrode of the seventh transistor is electrically connected with a fifth reference voltage end, the first electrode of the seventh transistor is electrically connected with the frequency modulation sub-circuit, the second electrode of the seventh transistor is electrically connected with the second sampling unit and the first electrode of the eighth transistor, and the second electrode of the eighth transistor is electrically connected with the voltage regulation sub-circuit.
In a second aspect, embodiments of the present disclosure further provide a voltage regulator device comprising the power supply circuit of any one of the above embodiments and a voltage regulator, the power supply circuit configured to provide a first voltage to the voltage regulator.
In some embodiments, the voltage regulator includes a switching unit, a feedback network, and an operational amplifier;
the feedback network is configured to sample an electric signal output by the signal output end of the voltage stabilizer to generate a feedback voltage, and output the feedback voltage to the operational amplifier;
the operational amplifier is configured to compare the feedback voltage with a reference voltage and generate a third control signal according to a comparison result;
the switching unit is configured to regulate the first voltage according to the third control signal and output the first voltage through a signal output end of the voltage stabilizer.
In some embodiments, the feedback network includes a fourth voltage dividing resistor and a fifth voltage dividing resistor; the first end of the fourth voltage dividing resistor is electrically connected with the signal output end of the voltage stabilizer, the switch unit and the detection sub-circuit, the second end of the fourth voltage dividing resistor is electrically connected with the first end of the fifth voltage dividing resistor and the operational amplifier, and the second end of the fifth voltage dividing resistor is electrically connected with the fourth reference voltage end.
In some embodiments, the non-inverting input of the operational amplifier is electrically connected to the feedback network, the inverting input of the operational amplifier is electrically connected to a reference voltage terminal, and the output of the operational amplifier is electrically connected to the switching unit and the detection subcircuit.
In some embodiments, the switching unit includes a ninth transistor; the first electrode of the ninth transistor is electrically connected with the feedback network, the second electrode of the ninth transistor is electrically connected with the voltage regulator sub-circuit, and the control electrode of the ninth transistor is electrically connected with the operational amplifier and the detection sub-circuit.
In a third aspect, an embodiment of the present disclosure further provides a power management chip, including the voltage stabilizing device according to any one of the foregoing embodiments.
In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, which includes the power management chip in the foregoing embodiment.
Drawings
Fig. 1 is a schematic diagram of a power supply circuit according to an embodiment of the disclosure;
FIG. 2 is a waveform diagram illustrating operation of the power supply circuit of FIG. 1;
fig. 3 is a schematic diagram of a detection sub-circuit according to an embodiment of the disclosure;
fig. 4 is a schematic circuit diagram of a voltage stabilizing device according to an embodiment of the disclosure.
Wherein the reference numerals are as follows: 1. a frequency modulation sub-circuit; 2. a logic control module; 3. a voltage regulator sub-circuit; 4. a detection sub-circuit; 5. a voltage stabilizer; l1, a signal output end; isense, feedback signal; CLK, clock signal; AVIN, second voltage; VCP, first voltage; 21. a logic control sub-circuit; 22. a drive sub-circuit; 221. a first drive sub-circuit; 222. a second drive sub-circuit; p1, a first transistor; n1, a second transistor; n2, third transistor; n3, fourth transistor; cfly, a first capacitance; cl, a second capacitor; 41. a first sampling unit; 42. a voltage dividing unit; 43. a current mirror circuit; 44. a second sampling unit; n4, a first sampling transistor; i1, a first current source; i2, a second current source; n5, fifth transistor; n6, sixth transistor; r1, a first voltage dividing resistor; r2, a second voltage dividing resistor; r3, a third voltage dividing resistor; n7, a second sampling transistor; n8, seventh transistor; n9, eighth transistor; 51. a switching unit; 52. a feedback network; EA. An operational amplifier; en_cp, charge pump circuit enable signal; en_ldo, low dropout linear regulator enable signal; iload, load current; r4, a fourth voltage dividing resistor; r5, a fifth voltage dividing resistor; vr, reference voltage; vfb, feedback voltage; n10, ninth transistor.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Reference in the present disclosure to "a plurality of" or "a number" means two or more than two. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
The inventor finds that the existing DC/DC converter has the problems of low efficiency in light load and large output voltage difference in heavy load. In view of this, the disclosed embodiments provide a power supply circuit configured to supply a first voltage to a voltage regulator and adjust an operating switching frequency of a voltage regulator sub-circuit by detecting an electrical signal output by a signal output terminal of the voltage regulator. The charge pump is capable of realizing conversion of multiple positive voltages and negative voltages, which is an important structure of a switching power supply in a power management chip, and there is also a problem that, for convenience of description and understanding, the voltage regulating sub-circuit in the embodiments of the present disclosure will be described in detail by taking the charge pump negative voltage generating circuit as an example, however, the voltage regulating sub-circuit in the embodiments of the present disclosure is not limited thereto, and for example, the voltage regulating sub-circuit may also be a charge pump positive voltage generating circuit, a BOOST circuit, or the like.
It should be noted that, the voltage regulator includes, but is not limited to, a Low dropout linear regulator (Low-dropout regulator, LDO), and for convenience of description and understanding, the voltage regulator in the embodiments of the present disclosure is exemplified by the Low dropout linear regulator; in addition, the first voltage provided by the power supply circuit to the voltage regulator is actually the input voltage of the voltage regulator.
It should be noted that the LDO is a linear voltage regulator with low voltage difference between input voltage and output voltage. Linear voltage regulators have two basic forms: a series voltage regulator and a shunt voltage regulator. The LDO is a series regulator, which is located between a power supply and a load, and adjusts the resistance of a variable resistor according to the change of an input voltage or an output current, so as to keep the output voltage stable. When the output of the LDO is fixed, stable power supply can be realized as long as the power supply voltage is larger than the differential voltage of the output value.
In a first aspect, an embodiment of the present disclosure provides a power supply circuit, and fig. 1 is a schematic diagram of a power supply circuit provided in an embodiment of the present disclosure, where, as shown in fig. 1, the power supply circuit is configured to provide a first voltage VCP to a voltage regulator 5, and the power supply circuit includes a frequency modulation sub-circuit 1, a logic control module 2, a voltage adjustment sub-circuit 3, and a detection sub-circuit 4.
Specifically, the detection sub-circuit 4 is configured to detect an electric signal output by the signal output terminal L1 of the voltage regulator 5, and generate a feedback signal Isense; the frequency modulation sub-circuit 1 is configured to perform frequency modulation according to a feedback signal Isense fed back by the detection sub-circuit 4, generate a clock signal CLK, and output the clock signal CLK to the logic control module 2; the logic control module 2 is configured to generate a first control signal according to the clock signal CLK and output the first control signal to the voltage regulating sub-circuit 3; the voltage regulating sub-circuit 3 is configured to convert the second voltage AVIN into a first voltage VCP according to the first control signal, and output the first voltage VCP to the voltage regulator 5.
It should be noted that, in the embodiment of the present disclosure, the second voltage AVIN is actually an input voltage of the voltage regulator sub-circuit 3, and the first voltage VCP is actually an output voltage of the voltage regulator sub-circuit 3, and the voltage regulator sub-circuit 3 uses the output first voltage VCP as an input voltage of the voltage regulator 5.
It should be noted that, in the embodiment of the present disclosure, the electrical signal output by the signal output terminal L1 of the voltage stabilizer 5 may be a voltage signal, or may be a current signal. For example, the electric signal detected by the detection sub-circuit 4 at the signal output terminal L1 of the voltage regulator 5 is the load current Iload, that is, when the load changes, the detection sub-circuit 4 detects the change of the load current Iload.
In the embodiment of the present disclosure, the voltage regulator sub-circuit 3 is a charge pump negative voltage generating circuit, hereinafter simply referred to as a charge pump circuit. The embodiments of the present disclosure can adjust the operating switching frequency of the charge pump circuit by sampling the load current Iload of the voltage regulator 5 and processing the load current Iload, for example, by reducing the load current Iload. By means of the working mode of the power supply circuit in the embodiment of the disclosure, when the load current Iload changes, a part of the difference value between the input voltage and the output voltage of the charge pump circuit can be fixed, and the difference value between the input voltage and the output voltage of the charge pump circuit is only related to the load current Iload and the on-resistance of a power tube in the circuit. Meanwhile, the power supply circuit in the embodiment of the disclosure can reduce switching loss and improve efficiency due to low switching frequency in a light load mode, and can make the difference between the input voltage and the output voltage smaller in a heavy load mode.
Fig. 2 is a waveform diagram illustrating the operation of the power supply circuit in fig. 1, and the power supply circuit will be described in detail with continued reference to fig. 1 and 2. In the embodiment of the present disclosure, the voltage regulator sub-circuit 3 is a charge pump negative pressure generating circuit, and takes the charge pump negative pressure generating circuit to realize negative 1-time voltage conversion as an example. When the charge pump circuit enable signal is pulled up, the charge pump circuit starts to start, and at this time, the first voltage VCP starts to drop until the first voltage VCP is equal to the second voltage AVIN. Then, after the enable signal of the voltage regulator 5 is pulled high, the voltage regulator 5 starts to start until reaching its preset output voltage value. When the start-up of the voltage regulator 5 is completed and reaches its preset output voltage value, load change starts. When the load changes, the detection sub-circuit 4 detects the electric signal output from the signal output terminal L1 of the voltage regulator 5, and generates a feedback signal Isense. The feedback signal Isense is input to the frequency modulator In the circuit 1, the frequency of the clock signal CLK output by the frequency modulation sub-circuit 1 is changed, and the switching frequency of the charge pump circuit is changed. By the control mode of the power supply circuit described above, it is possible to realize that the charge pump switching frequency increases when the load current Iload becomes large, and decreases when the load current Iload is small. When idling, the charge pump operates at a lower frequency, in this disclosure I Lower limit of And (3) representing.
Further, in the embodiment of the disclosure, after the detection sub-circuit 4 detects the load current Iload, the load current Iload is scaled, and the scaled load current Iload is input into the frequency modulation sub-circuit 1, so as to change the frequency of the clock signal CLK output by the frequency modulation sub-circuit 1, and further change the switching frequency of the charge pump circuit. By the scaling processing of the load current Iload by the detection sub-circuit 4, when the load current Iload is larger, the voltage difference between the second voltage AVIN and the first voltage VCP of the voltage regulator sub-circuit 3 is smaller, that is, the voltage difference between the input voltage and the output voltage is smaller.
In some embodiments, as shown in FIG. 1, logic control module 2 includes logic control subcircuit 21 and drive subcircuit 22; wherein the logic control sub-circuit 21 is configured to generate a second control signal subjected to a logic operation from the clock signal CLK; the driving sub-circuit 22 is configured to generate the first control signal to drive the voltage regulating sub-circuit 3 in accordance with the second control signal.
In the embodiment of the present disclosure, the logic control module 2 generates a first control signal according to the clock signal CLK, and inputs the first control signal into the voltage regulator sub-circuit 3 to control the switching operation frequency of the voltage regulator sub-circuit 3. Specifically, the logic control module 2 includes a logic control sub-circuit 21 and a driving sub-circuit 22, the logic control sub-circuit 21 generates a second control signal subjected to logic operation according to the clock signal CLK, and the driving sub-circuit 22 generates a first control signal according to the second control signal to drive the voltage regulating sub-circuit 3. By the refinement of the logic control module 2 described above, a more accurate control of the switching frequency of the voltage regulator sub-circuit 3 can be achieved.
In some embodiments, as shown in fig. 1, the drive sub-circuit 22 includes a first drive sub-circuit 221 and a second drive sub-circuit 222, the first control signal includes a first control sub-signal and a second control sub-signal, and the two are 180 ° out of phase; the first drive sub-circuit 221 is configured to generate a first control sub-signal from the second control signal and the second drive sub-circuit 222 is configured to generate a second control sub-signal from the second control signal.
In the disclosed embodiment, the logic control module 2 includes a logic control sub-circuit 21 and a driving sub-circuit 22, and the driving sub-circuit 22 includes a first driving sub-circuit 221 and a second driving sub-circuit 222; the first driving sub-circuit 221 generates a first control sub-signal according to the second control signal output from the logic control sub-circuit 21, and inputs the first control sub-signal to the voltage regulator sub-circuit 3; the second driving sub-circuit 222 generates a second control sub-signal according to the second control signal output from the logic control sub-circuit 21, and inputs the second control sub-signal to the voltage regulator sub-circuit 3. By the refinement of the driving sub-circuit 22, different control signals can be output, thereby realizing more accurate control of the switching operating frequency of the voltage regulator sub-circuit 3. For example, in the embodiment of the present disclosure, the first control sub-signal and the second control sub-signal are complementary signals that are 180 ° out of phase.
In some embodiments, the voltage regulator sub-circuit 3 includes a first transistor P1, a second transistor N1, a third transistor N2, a fourth transistor N3, a first capacitance Cfly, and a second capacitance Cl; the switching characteristics of the first transistor P1, the second transistor N1, the third transistor N2, and the fourth transistor N3 are all the same.
The first pole of the first transistor P1 is configured to receive the second voltage AVIN, the second pole of the first transistor P1 is electrically connected to the second pole of the third transistor N2 and the first pole of the first capacitor Cfly, the control pole of the first transistor P1 is electrically connected to the first driving sub-circuit 221, the first pole of the third transistor N2 is electrically connected to the first reference voltage terminal, the control pole of the third transistor N2 is electrically connected to the second driving sub-circuit 222, the second pole of the second transistor N1 is electrically connected to the second reference voltage terminal, the first pole of the second transistor N1 is electrically connected to the second pole of the first capacitor Cfly and the first pole of the fourth transistor N3, the control pole of the second transistor N1 is electrically connected to the first pole of the second capacitor Cl and the voltage stabilizer 5, the control pole of the fourth transistor N3 is electrically connected to the second driving sub-circuit 222, and the third pole of the second capacitor Cl is electrically connected to the third reference voltage terminal.
Specifically, in the embodiment of the disclosure, the switching characteristics of the first transistor P1, the second transistor N1, the third transistor N2 and the fourth transistor N3 are the same, the first transistor P1 and the second transistor N1 each receive the first control sub-signal output by the first driving sub-circuit 221, and the third transistor N2 and the fourth transistor N3 each receive the second control sub-signal output by the second driving sub-circuit 222; the first control sub-signal and the second control sub-signal are complementary signals with 180 degrees of phase difference, so that the first capacitor Cfly can be charged and the second capacitor Cl can be discharged, and the voltage regulating sub-circuit 3 can convert the second voltage AVIN into the first voltage VCP.
With continued reference to fig. 1, a voltage regulator sub-circuit 3 (i.e., a charge pump negative voltage generating circuit) in an embodiment of the present disclosure will be specifically described.
Further, in order to make the voltage regulator sub-circuit 3 realize negative 1-time voltage conversion, the first transistor P1, the second transistor N1, the third transistor N2, and the fourth transistor N3 are specifically set. The first transistor P1 and the second transistor N1 are set to have opposite switching characteristics, and the second transistor N1, the third transistor N2, and the fourth transistor N3 are set to have the same switching characteristics will be described in detail. For example, the first transistor P1 is a P-type transistor, and the second transistor N1, the third transistor N2, and the fourth transistor N3 are all N-type transistors. In the embodiment of the disclosure, the first transistor P1 and the second transistor N1 both receive the first control sub-signal output by the first driving sub-circuit 221, and in order to realize simultaneous conduction at the same time, an inverter may be added before the first transistor P1 to realize simultaneous conduction of the first transistor P1 and the second transistor N1 at the same time.
It should be noted that, the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and the source and the drain of the transistors are symmetrical, so that there is no difference between the source and the drain. In order to distinguish between the source and drain of a transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. The transistors can be divided into N type and P type according to the characteristic distinction of the transistors, when the P type transistor is adopted, the first electrode is the source electrode of the P type transistor, the second electrode is the drain electrode of the P type transistor, and when the grid electrode inputs a low level signal, the source electrode and the drain electrode are conducted; when the N-type transistor is adopted, the first electrode is the drain electrode of the N-type transistor, the second electrode is the source electrode of the N-type transistor, and when the grid electrode inputs a high-level signal, the source electrode and the drain electrode are conducted.
Specifically, in one charge-discharge cycle, a charge phase and a discharge phase are included. In the charging stage, the first transistor P1 and the second transistor N1 in the voltage regulator sub-circuit 3 both receive the first control sub-signal output by the first driving sub-circuit 221, the first control sub-signal is at a high level, the first transistor P1 and the second transistor N1 are turned on, the second voltage AVIN is input to the first pole of the first capacitor Cfly to charge the first capacitor Cfly, the third transistor N2 and the fourth transistor N3 in the voltage regulator sub-circuit 3 both receive the second control sub-signal output by the second driving sub-circuit 222, the second control sub-signal is at a low level, and the third transistor N2 and the fourth transistor N3 are turned off.
It should be noted that the reference voltage terminal may be ground, or may be a terminal with a lower voltage than the other terminal (the input voltage terminal), which will not be described in detail later. The embodiment of the present disclosure will be described in detail with reference to the first reference voltage terminal. When the first transistor P1 and the second transistor N1 are both turned on, a first pole of the first capacitor Cfly is connected to the input voltage terminal, and a second pole of the first capacitor Cfly is connected to ground. Let the average charging current be I c The total charge amount is Q c The duty ratio is D, the period is T, and the average input current in each period is I IN 。
The method can obtain:
Q c ＝I c ×D×T＝I IN ×T；
V c ＝AVIN-I c ×(R P1 +R N1 )；
in the discharging stage, the third transistor N2 and the fourth transistor N3 in the voltage regulator sub-circuit 3 both receive the second control sub-signal output by the second driving sub-circuit 222, and at this time, the second control sub-signal is at a high level, the third transistor N2 and the fourth transistor N3 are turned on, and because the voltage difference between the two plates of the capacitor will not be abrupt, the first capacitor Cfly and the second capacitor Cl are in charge sharing, and after voltage stabilization, the voltage regulator sub-circuit 3 can convert the second voltage AVIN into the first voltage VCP, i.e. realize voltage conversion of minus 1 times. At this time, the first transistor P1 and the second transistor N1 in the voltage regulator sub-circuit 3 both receive the first control sub-signal output by the first driving sub-circuit 221, and at this time, the first control sub-signal is at a low level, and the first transistor P1 and the second transistor N1 are turned off. Let the discharge current be I D The total discharge charge of the first capacitor Cfly to the second capacitor Cl is Q D Average output current is I OUT 。
The method can obtain:
Q D ＝-I D ×(1-D)×T＝-I OUT ×T；
V D ＝-VCP-I D ×(R N2 +R N3 )；
because the total amount of charge to charge and discharge the capacitor in each period is equal, and the duty cycle D is 50%,
the method can obtain:
the total amount of charge transferred in one cycle is:
ΔQ＝C fly ×(V C -V D )
＝C fly ×(AVIN+VCP+2I Load ×(R P1 +R N1 +R N2 +R N3 ))
from q=it, the relationship between the first voltage VCP (output voltage of the voltage regulating sub-circuit 3) and the second voltage AVIN (input voltage of the voltage regulating sub-circuit 3) can be obtained:
the formula is (1-1),
wherein, VCP: a first voltage (output voltage of the voltage regulator sub-circuit 3); AVIN: a second voltage (input voltage of the voltage regulator sub-circuit 3); i Load : load current of the voltage regulator 5; f: the operating frequency of the voltage regulating sub-circuit 3; c (C) fly : a first capacitor; r is R P1 /R N1 /R N2 /R N3 : on-resistance of the first transistor P1/second transistor N1/third transistor N2/fourth transistor N3.
Since the equivalent series impedance (Equivalent Series Resistance, ESR) of the second capacitor Cl is small, the effect of the ESR on the first voltage VCP is ignored here.
The value of the first voltage VCP of the voltage regulator sub-circuit 3 is shown in the formula (1-1), and it can be seen from the formula that the value of the first voltage VCP is mainly determined by two parts, the first part is the switching frequency and the first capacitance Cfly, and the second part is the on-resistance of the first transistor P1, the second transistor N1, the third transistor N2 and the fourth transistor N3.
In the second part, the present disclosure mainly improves on the first part, since the load current Iload and the layout area determine that the on-resistances of the first transistor P1, the second transistor N1, the third transistor N2 and the fourth transistor N3 cannot be reduced all the time, but only to a reasonable value.
In some embodiments, the frequency modulation sub-circuit 1 modulates the frequency according to the feedback signal Isense fed back by the detection sub-circuit 4 and generates the clock signal CLK. The frequency modulation subcircuit 1 may be an oscillator, and the frequency modulation subcircuit 1 is taken as an oscillator in the embodiment of the disclosure for illustration. The following is a formula derivation of the fm sub-circuit 1.
IT＝CU
The above formula is (1-2),
wherein F: the operating frequency of the voltage regulating sub-circuit 3; i Load : load current of the voltage regulator 5; c: a charge capacitor in the frequency modulation sub-circuit 1; v (V) REF : a reference power supply in the frequency modulation sub-circuit 1; k (k) sense : scaling of the load current Iload.
In the formula (1-2), F1 is a constant value. For example, when the load current Iload is 0, the circuit needs to have a frequency so that the circuit can work normally, and F1 is a fixed value that ensures that the circuit can still work normally under the condition of no load.
As can be seen from the formula (1-2), the operating frequency F and the load current I of the voltage regulator sub-circuit 3 Load In a linear relationship, i.e. DeltaI Load /ΔF＝C×V REF ×k sense . Therefore, when the load current Iload changes, the difference between the first voltage VCP and the first portion in equation (1-1) can be regarded as a certain value. At this time, when the load current Iload is smaller, the operating frequency of the voltage regulator sub-circuit 3 is also lower, so that the switching loss of the transistor is reduced, and the efficiency of the power supply circuit in light load is improved.
In some embodiments, fig. 3 is a schematic structural diagram of a detection sub-circuit provided in an embodiment of the disclosure, and as shown in fig. 3, the detection sub-circuit 4 includes a first sampling unit 41, a voltage dividing unit 42, a current mirror circuit 43, and a second sampling unit 44; wherein the first sampling unit 41 is configured to reduce the electric signal output by the signal output terminal L1 of the voltage regulator 5 by K1 times, generate a first detection current, and output the first detection current to the voltage dividing unit 42; the voltage dividing unit 42 is configured to reduce the first detection current by K2 times, generating a second detection current; the current mirror circuit 43 is configured to mirror the second detected current, generate a feedback signal Isense, and output the feedback signal Isense to the second sampling unit 44; the second sampling unit 44 is configured to output the feedback signal Isense to the frequency modulation sub-circuit 1.
Specifically, in the embodiment of the present disclosure, the detection sub-circuit 4 detects the electrical signal (load current Iload here) output by the signal output terminal L1 of the voltage stabilizer 5, and processes the load current Iload, so that the differential pressure between the first voltage VCP and the second voltage AVIN can be kept at a small value even when the load current Iload is large.
In some embodiments, as shown in fig. 3, the first sampling unit 41 includes a first sampling transistor N4; the current mirror circuit 43 includes a first current source I1, a second current source I2, a fifth transistor N5, and a sixth transistor N6; the voltage dividing unit 42 includes a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a third voltage dividing resistor R3; the second sampling unit 44 includes a second sampling transistor N7; the control electrode of the first sampling transistor N4 is electrically connected to the voltage stabilizer 5, the first electrode of the first sampling transistor N4 is electrically connected to the signal output end L1 of the voltage stabilizer 5, and the second electrode of the first sampling transistor N4 is electrically connected to the first end of the second voltage dividing resistor R2; the first electrode of the fifth transistor N5 is electrically connected to the first current source I1 and the control electrode of the second sampling transistor N7, and the control electrode of the fifth transistor N5 is electrically connected to the control electrode of the sixth transistor N6 and the first electrode of the sixth transistor N6; the second pole of the fifth transistor N5 is electrically connected with the first end of the first divider resistor R1; the second end of the first voltage dividing resistor R1 is electrically connected with the first end of the second voltage dividing resistor R2, and the second end of the second voltage dividing resistor R2 is electrically connected with the voltage regulator sub-circuit 3; the first pole of the sixth transistor N6 is electrically connected with the second current source I2, the second pole of the sixth transistor N6 is electrically connected with the first end of the third voltage dividing resistor R3 and the second pole of the second sampling transistor N7, and the second end of the third voltage dividing resistor R3 is electrically connected with the voltage regulator sub-circuit 3; the first pole of the second sampling transistor N7 is electrically connected to the frequency modulation subcircuit 1.
Specifically, in the embodiment of the present disclosure, the control electrode of the first sampling transistor N4 is electrically connected to the voltage stabilizer 5, the first electrode of the first sampling transistor N4 is electrically connected to the signal output end L1 of the voltage stabilizer 5, and the second electrode of the first sampling transistor N4 is electrically connected to the first end of the second voltage dividing resistor R2, so as to sample the load current Iload.
The following is a formula derivation for the detection subcircuit 4 in an embodiment of the present disclosure:
the first current source I1 and the second current source I2 in the current mirror circuit 43 are the same constant current source, and it is possible to obtain:
V A ＝V B
I 1 ＝I 2
since the first sampling unit 41 includes the first sampling transistor N4, the first sampling unit 41 is configured to reduce the load current Iload output by the signal output terminal L1 of the voltage regulator 5 by K1 times, generate the first detection current, and output the first detection current to the voltage dividing unit 42, it is possible to:
wherein I is 3 Is the first sense current.
Since the voltage dividing unit 42 is configured to reduce the first detection current by K2 times, to generate the second detection current, the voltage dividing unit 42 includes the first voltage dividing resistor R1, the second voltage dividing resistor R2, and the third voltage dividing resistor R3, it is possible to:
R 1 ＝R 3 ＝K2×R 2
since the current mirror circuit 43 is configured to mirror the second detected current, generate the final feedback signal Isense and output the feedback signal Isense to the second sampling unit 44, the second sampling unit 44 is configured to output the feedback signal Isense to the frequency modulation sub-circuit 1, and the second sampling unit 44 comprises a second sampling transistor N7, the availability is that:
V A ＝(I 3 +I 1 )×R 2 +I 1 ×R 1
V B ＝(I 2 +I sense )×R 3
The above formula is (1-3),
as can be seen from the equation (1-3), the relation between the feedback signal Isense and the load current Iload obtained by the detection sub-circuit 4 is as follows:
the above formula is (1-4),
since the first current source I1 has a small value, in the formula (1-4)This term is negligible.
Continuing to combine the formulas (1-2) and (1-4) to obtain the following formula:
the above formula is (1-5),
in the embodiment of the disclosure, k1×k2 may be set, for example, K1 may be 2000, and K2 may be 4, so that after setting, the load current Iload is reduced by 8000 times after passing through the detection sub-circuit 4. When the load current Iload is larger, the first voltage VCP and the second voltage AVIN can still keep a smaller differential pressure value, so that the system is more stable.
In some embodiments, as shown in fig. 3, the detection sub-circuit 4 includes not only the above-described structure but also a seventh transistor N8 and an eighth transistor N9; the control electrode of the seventh transistor N8 is electrically connected to the fifth reference voltage terminal, the first electrode of the seventh transistor N8 is electrically connected to the frequency modulation subcircuit 1, the second electrode of the seventh transistor N8 is electrically connected to the second sampling unit 44 and the first electrode of the eighth transistor N9, and the second electrode of the eighth transistor N9 is electrically connected to the voltage regulation subcircuit 3.
Specifically, in the embodiment of the present disclosure, the first pole of the seventh transistor N8 is electrically connected to the frequency modulation subcircuit 1, the second pole of the seventh transistor N8 is electrically connected to the first pole of the second sampling transistor N7 and the first pole of the eighth transistor N9, and the second pole of the eighth transistor N9 is electrically connected to the voltage regulation subcircuit 3. The seventh transistor N8 and the eighth transistor N9 are added in the embodiment of the disclosure, so as to protect the detection sub-circuit 4. Preferably, the seventh transistor N8 is used under high voltage conditions to perform clamping, and the eighth transistor N9 may be a barrier diode to perform clamping as well.
In a second aspect, an embodiment of the present disclosure further provides a voltage stabilizing device, and fig. 4 is a schematic circuit structure diagram of the voltage stabilizing device provided in the embodiment of the present disclosure, as shown in fig. 4, including a power supply circuit and a voltage stabilizer 5 in any one of the foregoing embodiments, where the power supply circuit is configured to provide a first voltage VCP to the voltage stabilizer 5.
In some embodiments, as shown in fig. 4, the voltage regulator 5 includes a switching unit 51, a feedback network 52, and an operational amplifier EA; the feedback network 52 is configured to sample the electric signal output by the signal output terminal L1 of the voltage regulator 5 to generate a feedback voltage, and output the feedback voltage to the operational amplifier EA; the operational amplifier EA is configured to compare the feedback voltage with a reference voltage and generate a third control signal according to a comparison result; the switching unit 51 is configured to regulate the first voltage VCP according to the third control signal and output through the signal output terminal L1 of the voltage regulator 5.
In the embodiment of the present disclosure, the feedback network 52 in the voltage stabilizer 5 samples the electrical signal output by the signal output terminal L1 to generate a feedback voltage, where the electrical signal is a load voltage; the switching unit 51 in the voltage regulator 5 regulates the first voltage VCP according to the third control signal and outputs the regulated first voltage VCP through the signal output terminal L1, and the regulated first voltage VCP output through the signal output terminal L1 is referred to herein as a third voltage for convenience of description and understanding. The power supply circuit in the embodiment of the present disclosure converts the first voltage VCP into a third voltage that is stably output through the voltage regulator 5.
In some embodiments, as shown in fig. 4, feedback network 52 includes a fourth divider resistor R4 and a fifth divider resistor R5; the first end of the fourth voltage dividing resistor R4 is electrically connected to the signal output end L1 of the voltage stabilizer 5, the switching unit 51 and the detection sub-circuit 4, the second end of the fourth voltage dividing resistor R4 is electrically connected to the first end of the fifth voltage dividing resistor R5 and the operational amplifier EA, and the second end of the fifth voltage dividing resistor R5 is electrically connected to the fourth reference voltage end.
Specifically, in the embodiment of the present disclosure, by setting the fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5, after the circuit loop is established and operates normally, the third voltage set value may be made to satisfy the following formula:
Wherein Vs is a third voltage set value and Vr is a reference voltage.
Therefore, after the third voltage set point is fixed, if the feedback voltage is equal to the reference voltage, it is indicated that the third voltage reaches the set point. From this, it is understood that the relationship between the third voltage and the third voltage set value in the voltage regulator 5 can be confirmed by comparing the feedback voltage with the reference voltage.
In some embodiments, as shown in fig. 4, the noninverting input of the operational amplifier EA is electrically connected to the feedback network 52, the inverting input of the operational amplifier EA is electrically connected to the reference voltage terminal, and the output of the operational amplifier EA is electrically connected to the switching unit 51 and the detection subcircuit 4.
Specifically, in the embodiment of the present disclosure, the operational amplifier EA may be an error amplifier. The error amplifier outputs a third control signal by comparing the reference voltage with the feedback voltage and amplifying the difference between the reference voltage and the feedback voltage, so as to control the switching unit 51, thereby realizing voltage regulation of the third voltage.
In some embodiments, as shown in fig. 4, the switching unit 51 includes a ninth transistor N10; the first pole of the ninth transistor N10 is electrically connected to the feedback network 52, the second pole of the ninth transistor N10 is electrically connected to the voltage regulator sub-circuit 3, and the control pole of the ninth transistor N10 is electrically connected to the operational amplifier EA and the detection sub-circuit 4.
Specifically, in the embodiment of the present disclosure, the ninth transistor N10 may be a power transistor, which is mainly used as a current conduction channel between the input terminal and the output terminal of the voltage regulator 5, and the third control signal controls the voltage of the gate electrode of the ninth transistor N10, so as to stabilize the third voltage output by the signal output terminal L1.
In a third aspect, embodiments of the present disclosure further provide a power management chip including the voltage stabilizing device of any one of the above embodiments.
In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, which includes the power management chip in the foregoing embodiment. The electronic device provided by the embodiments of the present disclosure may be a wearable device, such as a watch. Of course, the display device can also be any product or component with display function such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display and the like. The electronic device mainly comprises a load and the power management chip provided by any embodiment, wherein the power management chip is connected with the load, converts the power voltage into the working voltage of the load and outputs the working voltage to the load.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims (14)

1. A power supply circuit configured to supply a first voltage to a voltage regulator, characterized in that the power supply circuit includes a frequency modulation sub-circuit, a logic control module, a voltage regulation sub-circuit, and a detection sub-circuit;
the detection subcircuit is configured to detect an electric signal output by a signal output end of the voltage stabilizer and generate a feedback signal;
the frequency modulation sub-circuit is configured to perform frequency modulation according to a feedback signal fed back by the detection sub-circuit and generate a clock signal;
the logic control module is configured to generate a first control signal according to the clock signal;
the voltage regulating sub-circuit is configured to convert a second voltage into the first voltage according to the first control signal.
2. The power supply circuit of claim 1, wherein the logic control module comprises a logic control sub-circuit and a drive sub-circuit;
the logic control sub-circuit is configured to generate a second control signal subjected to logic operation according to the clock signal;
the driving sub-circuit is configured to generate the first control signal according to the second control signal to drive the voltage regulating sub-circuit.
3. The power supply circuit of claim 2, wherein the drive sub-circuit comprises a first drive sub-circuit and a second drive sub-circuit, the first control signal comprising a first control sub-signal and a second control sub-signal that are 180 ° out of phase;
the first drive sub-circuit is configured to generate the first control sub-signal in dependence on the second control signal, and the second drive sub-circuit is configured to generate the second control sub-signal in dependence on the second control signal.
4. The power supply circuit of claim 3, wherein the voltage regulation subcircuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance, and a second capacitance; the switching characteristics of the first transistor, the second transistor, the third transistor and the fourth transistor are all the same;
the first pole of the first transistor is configured to receive the second voltage, the second pole of the first transistor is electrically connected to the second pole of the third transistor and the first pole of the first capacitor, the control pole of the first transistor is electrically connected to the first drive sub-circuit, the first pole of the third transistor is electrically connected to a first reference voltage terminal, the control pole of the third transistor is electrically connected to the second drive sub-circuit, the second pole of the second transistor is electrically connected to a second reference voltage terminal, the first pole of the second transistor is electrically connected to the second pole of the first capacitor and the first pole of the fourth transistor, the control pole of the second transistor is electrically connected to the first drive sub-circuit, the second pole of the fourth transistor is electrically connected to the first pole of the second capacitor and the voltage regulator, and the control pole of the fourth transistor is electrically connected to the second sub-circuit, the second pole of the second capacitor is electrically connected to a third reference voltage terminal.
5. The power supply circuit according to any one of claims 1 to 4, wherein the detection sub-circuit includes a first sampling unit, a voltage dividing unit, a current mirror circuit, and a second sampling unit;
the first sampling unit is configured to reduce the electric signal output by the signal output end of the voltage stabilizer by K1 times, generate a first detection current, and output the first detection current to the voltage dividing unit;
the voltage division unit is configured to reduce the first detection current by K2 times to generate a second detection current;
the current mirror circuit is configured to mirror the second detection current, generate the feedback signal, and output the feedback signal to the second sampling unit;
the second sampling unit is configured to output the feedback signal to the frequency modulation subcircuit.
6. The power supply circuit of claim 5, wherein the first sampling unit comprises a first sampling transistor; the current mirror circuit includes a first current source, a second current source, a fifth transistor, and a sixth transistor; the voltage dividing unit comprises a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor; the second sampling unit comprises a second sampling transistor;
The control electrode of the first sampling transistor is electrically connected with the voltage stabilizer, the first electrode of the first sampling transistor is electrically connected with the signal output end of the voltage stabilizer, and the second electrode of the first sampling transistor is electrically connected with the first end of the second voltage dividing resistor;
a first electrode of the fifth transistor is electrically connected to the first current source and the control electrode of the second sampling transistor, and a control electrode of the fifth transistor is electrically connected to the control electrode of the sixth transistor and the first electrode of the sixth transistor; a second electrode of the fifth transistor is electrically connected with a first end of the first voltage dividing resistor;
the second end of the first voltage dividing resistor is electrically connected with the first end of the second voltage dividing resistor, and the second end of the second voltage dividing resistor is electrically connected with the voltage regulating sub-circuit;
the first electrode of the sixth transistor is electrically connected with the second current source, the second electrode of the sixth transistor is electrically connected with the first end of the third voltage dividing resistor and the second electrode of the second sampling transistor, and the second end of the third voltage dividing resistor is electrically connected with the voltage regulating subcircuit; the first electrode of the second sampling transistor is electrically connected with the frequency modulation subcircuit.
7. The power supply circuit according to claim 5, wherein the detection sub-circuit further includes a seventh transistor and an eighth transistor; the control electrode of the seventh transistor is electrically connected with a fifth reference voltage end, the first electrode of the seventh transistor is electrically connected with the frequency modulation sub-circuit, the second electrode of the seventh transistor is electrically connected with the second sampling unit and the first electrode of the eighth transistor, and the second electrode of the eighth transistor is electrically connected with the voltage regulation sub-circuit.
8. A voltage regulator device comprising the power supply circuit of any one of claims 1-7 and a voltage regulator, the power supply circuit configured to provide a first voltage to the voltage regulator.
9. The voltage regulator of claim 8, wherein the voltage regulator comprises a switching unit, a feedback network, and an operational amplifier;
the feedback network is configured to sample an electric signal output by the signal output end of the voltage stabilizer to generate a feedback voltage, and output the feedback voltage to the operational amplifier;
the operational amplifier is configured to compare the feedback voltage with a reference voltage and generate a third control signal according to a comparison result;
The switching unit is configured to regulate the first voltage according to the third control signal and output the first voltage through a signal output end of the voltage stabilizer.
10. The voltage regulator of claim 9, wherein the feedback network comprises a fourth voltage divider resistor and a fifth voltage divider resistor; the first end of the fourth voltage dividing resistor is electrically connected with the signal output end of the voltage stabilizer, the switch unit and the detection sub-circuit, the second end of the fourth voltage dividing resistor is electrically connected with the first end of the fifth voltage dividing resistor and the operational amplifier, and the second end of the fifth voltage dividing resistor is electrically connected with the fourth reference voltage end.
11. The voltage regulator of claim 9, wherein the non-inverting input of the operational amplifier is electrically connected to the feedback network, the inverting input of the operational amplifier is electrically connected to a reference voltage terminal, and the output of the operational amplifier is electrically connected to the switching unit and the detection subcircuit.
12. The voltage stabilizing device according to claim 9, wherein the switching unit includes a ninth transistor; the first electrode of the ninth transistor is electrically connected with the feedback network, the second electrode of the ninth transistor is electrically connected with the voltage regulator sub-circuit, and the control electrode of the ninth transistor is electrically connected with the operational amplifier and the detection sub-circuit.
13. A power management chip comprising the voltage regulator device of any one of claims 8-12.
14. An electronic device comprising the power management chip of claim 13.
CN202310430126.1A 2023-04-20 2023-04-20 Power supply circuit, voltage stabilizing device, power management chip and electronic equipment Pending CN116470760A (en)

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