CN116469931A

CN116469931A - Semiconductor device and method of forming the same

Info

Publication number: CN116469931A
Application number: CN202210799654.XA
Authority: CN
Inventors: 林政颐; 李达元; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-03-04
Filing date: 2022-07-08
Publication date: 2023-07-21

Abstract

The present disclosure relates to semiconductor devices and methods of forming the same. One embodiment includes a device comprising: the semiconductor device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide interior extending downward from a top surface of the hybrid fin. The device further includes: a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending higher than a top surface of the first isolation region; a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin; a gate electrode on the high-k gate dielectric; and source/drain regions on the first semiconductor fin on opposite sides of the gate electrode.

Description

Semiconductor device and method of forming the same

Technical Field

The present disclosure relates to semiconductor devices and methods of forming the same.

Background

Semiconductor devices are used in a wide variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following processes: the deposition of insulating or dielectric layers, conductive layers, and semiconductor material layers is performed sequentially on a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems that should be solved arise.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a semiconductor device including: a first semiconductor fin extending from the substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, the hybrid fin having an oxide interior extending downward from a top surface of the hybrid fin; a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending higher than a top surface of the first isolation region; a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin; a gate electrode on the high-k gate dielectric; and source/drain regions on the first semiconductor fin on opposite sides of the gate electrode.

According to an aspect of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a first semiconductor fin and a second semiconductor fin extending from a substrate; forming an insulating material around the first semiconductor fin and the second semiconductor fin, a first portion of the insulating material being disposed between the first semiconductor fin and the second semiconductor fin; forming a hybrid fin on a first portion of the insulating material, the hybrid fin having a seam therein; recessing a first portion of the insulating material to form a first isolation region; forming a dummy gate structure over the first semiconductor fin, the hybrid fin, and the second semiconductor fin; forming source/drain regions on opposite sides of the dummy gate structure on the first semiconductor fin and the second semiconductor fin; removing the dummy gate structure to form a gate trench; a first gate dielectric layer formed in the gate trench over the first semiconductor fin, the hybrid fin, and the second semiconductor fin, the first gate dielectric layer filling a seam in the hybrid fin; a second gate dielectric layer formed on the first gate dielectric layer in the gate trench; and a gate electrode layer formed on the second gate dielectric layer in the gate trench.

According to an aspect of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a first semiconductor fin extending from a substrate; forming an insulating material around the first semiconductor fin; depositing a dielectric layer on the insulating material around the first semiconductor fin; and removing portions of the dielectric layer to form dielectric fins having seams therein; recessing the insulating material, wherein the dielectric fin extends above a top surface of the insulating material after recessing the insulating material; forming a dummy gate structure over the first semiconductor fin, the dielectric fin, and the recessed insulating material; forming source/drain regions on opposite sides of the dummy gate structure on the first semiconductor fin; removing the dummy gate structure to form a gate trench; performing a silicon precursor soaking process in the gate trench; and performing an oxidation process in the gate trench after performing the silicon precursor soaking process to form an interface layer on the first semiconductor fin and the dielectric fin in the gate trench, the interface layer filling a seam in the dielectric fin; a high-k gate dielectric layer formed on the interfacial layer in the gate trench; and a gate electrode layer formed on the high-k gate dielectric layer in the gate trench.

Drawings

Aspects of the disclosure will be best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale according to standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion.

Fig. 1 illustrates an example of a fin field effect transistor (FinFET), in accordance with some embodiments.

Fig. 2-19 are views of intermediate stages in FinFET fabrication according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "under," "beneath," "under," "over," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to various embodiments, hybrid fins are formed adjacent to and between the semiconductor fins. The hybrid fin includes seams that are filled by a silicon precursor soak process and an oxidation process. These processes simultaneously form the interfacial layer(s) under the replacement gate structure, thereby eliminating the need for additional processes to fill the seams of the hybrid fin. Filling the seam of the hybrid fin prevents conductive material from forming subsequently formed source/drain and/or gate contacts in the seam. Preventing conductive material from the source/drain and/or gate contacts from forming in the seams prevents the source/drain and gate from shorting to each other through the seams. Thus, the manufacturing yield of the device can be improved.

Fig. 1 illustrates an example of a fin field effect transistor (FinFET), in accordance with some embodiments. Fig. 1 is a three-dimensional view, in which some features of the FinFET are omitted for clarity. The FinFET includes a semiconductor fin 54 extending from a substrate 50 (e.g., a semiconductor substrate), wherein the semiconductor fin 54 serves as a channel region 58 of the FinFET. Isolation regions 68, such as Shallow Trench Isolation (STI) regions, are disposed between adjacent semiconductor fins 54, which may protrude higher than between adjacent isolation regions 68. Although isolation region 68 is depicted/described as being separate from substrate 50 (as used herein), the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. Further, although the bottom portion of the semiconductor fin 54 is shown as a single, continuous material with the substrate 50, the bottom portion of the semiconductor fin 54 and/or the substrate 50 may comprise a single material or multiple materials. In this context, the semiconductor fin 54 refers to a portion extending from between adjacent isolation regions 68.

Gate dielectric 112 is along the sidewalls of semiconductor fins 54 and over the top surfaces of these semiconductor fins. A gate electrode 114 is over the gate dielectric 112. Epitaxial source/drain regions 98 are disposed in opposite sides of semiconductor fin 54 with respect to gate dielectric 112 and gate electrode 114. Epitaxial source/drain regions 98 may be shared between the individual semiconductor fins 54. For example, adjacent epitaxial source/drain regions 98 may be electrically connected, such as by coalescing (by epitaxial growth) the epitaxial source/drain regions 98, or by coupling the epitaxial source/drain regions 98 with the same source/drain contacts.

Fig. 1 also illustrates a reference cross section used in the following figures. The cross section A-A' is along the longitudinal axis of the gate electrode 114. The cross-section B-B 'is perpendicular to the cross-section A-A' and along the longitudinal axis of the semiconductor fin 54 and in the direction of current flow between the epitaxial source/drain regions 98, e.g., finfets. The cross section C-C 'is parallel to the cross section A-A' and extends through the epitaxial source/drain regions 98 of the FinFET. For clarity, subsequent figures refer to these reference sections.

Some embodiments discussed herein are discussed in the context of finfets formed using a gate last process. In other embodiments, a gate-first process may be used. Further, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs).

Fig. 2-19 are views of intermediate stages in FinFET fabrication according to some embodiments. Fig. 2, 3, 4, 5, 6, 7, 8, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, and 19 are sectional views shown along sectional views similar to the reference section A-A' in fig. 1. Fig. 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, and 18B are sectional views shown along sectional views similar to the reference section B-B'. Fig. 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, and 18C are sectional views shown along a sectional view similar to the reference section C-C' in fig. 1.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., that may be doped (e.g., with p-type or n-type impurities) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate or the like. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; combinations thereof; etc.

The substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N may be used to form an N-type device, such as an NMOS transistor (e.g., an N-type FinFET), and the P-type region 50P may be used to form a P-type device, such as a PMOS transistor (e.g., a P-type FinFET). The N-type region 50N may be physically separated from the P-type region 50P (not separately illustrated), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are illustrated, any number of N-type regions 50N and P-type regions 50P may be provided.

In fig. 3, a fin structure 52 is formed in a substrate 50. Fin structure 52 includes semiconductor fin 54 as a semiconductor strip. Fin structure 52 may be formed in substrate 50 by etching trench 56 in substrate 50. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching process may be anisotropic.

Fin structure 52 may be patterned by any suitable method. For example, fin structure 52 may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, a double pattern or multiple pattern process combines lithography and self-aligned processes, allowing creation of patterns with smaller pitches, for example, than those obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used as a mask 60 to pattern fin structure 52. In some embodiments, mask 60 (or other layer) may remain on fin structure 52.

In the illustrated embodiment, fin structures 52 each have two semiconductor fins 54. However, the fin structures 52 may each have any number of semiconductor fins 54, such as one, two, three, or more semiconductor fins 54. Further, different fin structures 52 may have different numbers of semiconductor fins 54. For example, fin structures 52 in a first region (e.g., core logic region) of the die may have a first number of semiconductor fins 54, and fin structures 52 in a second region (e.g., input/output region) of the die may have a second number of semiconductor fins 54, where the second number is different than the first number.

The grooves 56 may have different widths. In some embodiments, the width of the first subset of grooves 56A is narrower than the width of the second subset of grooves 56B. Trenches 56A separate semiconductor fins 54 of respective fin structures 52, and trenches 56B separate fin structures 52 from each other. The semiconductor fins 54 of the respective fin structures 52 are spaced apart a distance less than the distance that the fin structures 52 are spaced apart from one another. In some embodiments, the semiconductor fins 54 of the respective fin structures 52 are spaced apart a distance D ₁ In the range of 5nm to 100nm, fin structures 52 are spaced apart from each other by a distance D ₂ In the range of 20nm to 200nm, and a distance D ₂ Greater than distance D ₁ . Trenches 56 having different widths may be formed by patterning through a mask 60 having the following pattern: the pattern has features that are spaced apart at different distances corresponding to different widths of the grooves 56. The width of trench 56 defines the width of semiconductor fin 54 (also referred to as the critical dimension of semiconductor fin 54). In some embodiments, the critical dimension of semiconductor fin 54 is in the range of 5nm to 30 nm.

In some embodiments, the grooves 56 have different depths. For example, the depth of trench 56A may be shallower than trench 56B. Trenches 56 having different depths may be formed as a result of pattern loading effects during etching of trenches 56, where the pattern loading effects are caused by patterns of mask 60 having features spaced apart at different distances. The depth of the trench 56 defines the height of the semiconductor fin 54. In some embodiments, the height of the semiconductor fin 54 is in the range of 10nm to 100 nm.

In fig. 4, one or more layers of insulating material 62 for isolation regions are formed over the substrate 50 and between adjacent semiconductor fins 54. The insulating material 62 may include an oxide, such as silicon oxide, nitride (e.g., silicon nitride), etc., or a combination thereof, and may be formed by Chemical Vapor Deposition (CVD), high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), atomic Layer Deposition (ALD), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, insulating material 62 includes liner 62A on the surface of substrate 50 and semiconductor fin 54 and fill material 62B on liner 62A. Liner 62A may be amorphous silicon, silicon oxide, silicon nitride, etc. conformally deposited using a conformal deposition process such as ALD, and filler material 62B may be silicon oxide grown using a conformal growth process such as FCVD. In another embodiment, a single layer of insulating material 62 is formed. Once the insulating material is formed, an annealing process may be performed. The annealing process can be performed in the presence of H ₂ Or O ₂ Is executed in the environment of (a). Liner 62A may be oxidized by an annealing process such that after annealing liner 62A is a material similar to filler material 62B. In an embodiment, insulating material 62 is formed such that an excess of insulating material 62 covers semiconductor fin 54.

The thickness of insulating material 62 is controlled such that insulating material 62 does not fill all trenches 56. In some embodiments, the thickness T of the deposited insulating material 62 ₁ In the range of 5nm to 30 nm. Distance D ₁ 、D ₂ (see FIG. 3) and thickness T ₁ Is controlled such that insulating material 62 fills trench 56A but not trench 56B. For example, the volume of insulating material 62 dispensed may be sufficient to completely fill (or overfill) trench 56A, but may not be sufficient to completely fill trench 56B. Thus, the insulating material 62 in the trench 56B does not completely fill the trench 56B, but rather forms a liner conformally on the surface of the substrate 50 and the sidewalls of the semiconductor fin 54 defining the trench 56B.

In the illustrated embodiment, the sidewalls of semiconductor fin 54 and insulating material 62 are illustrated as forming right angles with the top surfaces of substrate 50 and insulating material 62, respectively. In other embodiments, profiling (patterning) may occur during the patterning of the semiconductor fin 54 and the deposition of the insulating material 62. Accordingly, a rounded surface (rounded surface) may connect the sidewalls of semiconductor fin 54 to the top surface of substrate 50, and a rounded surface may connect the sidewalls of insulating material 62 to the top surface of insulating material 62.

In fig. 5, one or more dielectric layers 64 are formed over insulating material 62. Dielectric layer(s) 64 fill (and possibly overfill) the remaining portions of trench 56B that are not filled (e.g., not occupied) by insulating material 62. For example, in some embodiments, dielectric layer(s) 64 merge in trench 56B and form a seam or void 64A in trench 56B. Width W of seam 64A ₁ May be in the range of 1nm to 3 nm. Dielectric layer(s) 64 may be formed of one or more dielectric materials. Acceptable dielectric materials include nitrides (e.g., silicon nitride), oxides (e.g., tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, etc.), carbides (e.g., silicon carbonitride, silicon oxynitride, etc.), combinations thereof, and the like, which may be deposited by ALD, CVD, and the like. Other insulating materials formed by any acceptable process may be used. Further, dielectric layer(s) 64 may be formed of low-k dielectric materials (e.g., dielectric materials having a k value less than about 3.5), high-k dielectric materials (e.g., dielectric materials having a k value greater than about 7.0), or multilayers thereof. Dielectric layer(s) 64 are formed of material(s) having high etch selectivity (relative to etching of insulating material 62). In some embodiments, dielectric layer(s) 64 include silicon nitride formed by ALD.

In fig. 6, a removal process is applied to dielectric layer(s) 64 and insulating material 62 to remove excess portions of dielectric layer(s) 64 and insulating material 62 over semiconductor fin 54 (e.g., outside trench 56), thereby forming a hybrid fin 66 including seams or voids 66A on insulating material 62. In some embodiments, planarization processes such as Chemical Mechanical Polishing (CMP), etch-back processes, and others may be employedCombinations of (a) and the like. Dielectric layer(s) 64 have portions that remain in trench 56B (thereby forming hybrid fins 66) after the removal process. After the planarization process, the top surfaces of hybrid fin 66, insulating material 62, and semiconductor fin 54 are coplanar (within the scope of process variation) such that they are flush with one another. Hybrid fins 66 are disposed between and adjacent to fin structures 52. In some embodiments, after the planarization process, the depth D of the seam 66A of the fin 66 is blended ₄ In the range of 60nm to 70 nm. Hybrid fin 66 may also be referred to as a "dielectric fin".

In fig. 7, insulating material 62 is recessed to form STI regions 68. The insulating material 62 is recessed such that the upper portions of the semiconductor fin 54 and hybrid fin 66 protrude above the adjacent STI regions 68 from between these STI regions. Further, the top surface of STI region 68 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dished), or a combination thereof. The top surface of STI region 68 may be formed flat, convex, and/or concave by a suitable etch. The recessing of STI regions 68 may be performed using an acceptable etching process, such as one that is selective to the material(s) of insulating material 62. As will be described in greater detail later, the etching process selectively etches the material(s) of insulating material 62 at a faster rate (than the etching rate for the materials of semiconductor fin 54 and hybrid fin 66). Semiconductor fin 54 and hybrid fin 66 may thus be protected from damage during the formation of STI region 68. A timed etch process may be used to stop etching of insulating material 62 after STI regions 68 reach a desired height. In some embodiments, the height of STI regions 68 is in the range of 10nm to 100 nm. STI region 68 includes the remaining portion of insulating material 62 in trench 56.

As previously described, trench 56B is deeper than trench 56A. As a result, STI regions 68 have different heights. Specifically, the first subset of STI regions 68A has a height that is lower than the height of the second subset of STI regions 68B. STI regions 68A are in trenches 56A and between semiconductor fins 54 of respective fin structures 52, and may be referred to as "internal fin STI regions. STI region 68B is in trench 56B and is in phase around hybrid fin 66Between adjacent fin structures 52 (e.g., between semiconductor fin 54 and hybrid fin 66), and may be referred to as an "external STI region. Because trench 56B is deeper than trench 56A, the bottom surface of STI region 68B is disposed farther from the top surfaces of semiconductor fin 54 and hybrid fin 66 than the bottom surface of STI region 68A. In some embodiments, the bottom surface of STI region 68B is disposed a distance D farther from the top surfaces of semiconductor fin 54 and hybrid fin 66 (than the bottom surface of STI region 68A) ₃ (described previously).

The formation of STI regions 68 reforms (reforms) portions of trenches 56A, 56B. The reformed portion of trench 56A is between each pair of semiconductor fins 54, while the reformed portion of trench 56B is between each pair of semiconductor fins 54 and hybrid fin 66. Distance D ₁ 、D ₂ (see FIG. 3) and thickness T ₁ (see fig. 4) is controlled so that the reforming portion of the groove 56A is wider than the reforming portion of the groove 56B. In some embodiments, width W of reforming portion of trench 56A ₂ Width W of reforming portion of trench 56B in the range of 10nm to 30nm ₃ In the range of 5nm to 20nm, and a width W ₂ Greater than width W ₃ 。

The insulating material 62 may be recessed by different amounts as a result of pattern loading effects during recessing of the insulating material 62, where the pattern loading effects are caused by reformed portions of the trenches 56A, 56B having different widths. In some embodiments, etching of insulating material 62 is performed using etching parameters (e.g., temperature, pressure, and duration) that exacerbate the pattern loading effect. As a result of the pattern loading effect, the portion of insulating material 62 in trench 56A is recessed more (e.g., greater in depth) than the portion of insulating material 62 in trench 56B. Thus, the top surface of STI region 68B is disposed farther from substrate 50 than the top surface of STI region 68A. In other words, STI region 68B extends higher than STI region 68A relative to substrate 50. In some embodiments, the top surface of the STI region 68B is disposed a distance D farther from the substrate 50 (than the top surface of the STI region 68A) in the range of 2nm to 10nm ₅ 。

In some embodiments where insulating material 62 comprises silicon oxide, by using hydrogen fluorideAcid (HF) and ammonia (NH) ₃ ) Is used to recess insulative material 62. Each STI region 68B extends along three sides (e.g., sidewalls and bottom surface) of hybrid fin 66. Specifically, a first portion of STI region 68B is between hybrid fin 66 and first fin structure 52, a second portion of STI region 68B is between hybrid fin 66 and second fin structure 52, and a third portion of STI region 68B is below hybrid fin 66.

The process described with respect to fig. 2-7 is only one example of how semiconductor fin 54, hybrid fin 66, and STI region 68 may be formed. In some embodiments, a mask and epitaxial growth process may be used to form semiconductor fin 54 and/or hybrid fin 66. For example, a dielectric layer may be formed over the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in some trenches, an insulating structure may be deposited in other trenches, and the dielectric layer may be recessed (in a similar manner as described with respect to fig. 7) such that the epitaxial structure protrudes from the dielectric layer to form semiconductor fin 54 and the insulating structure protrudes from the dielectric layer to form hybrid fin 66. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and/or subsequent implants, although in situ and implant doping may be used together.

Furthermore, it may be advantageous for the epitaxially grown material in N-type region 50N to be different from the material in P-type region 50P. In various embodiments, the upper portion of semiconductor fin 54 may be formed of silicon-germanium (Si _x Ge _1-x Where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, and the like. For example, materials that may be used to form III-V compound semiconductors include, but are not limited to: indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum phosphide, gallium phosphide, and the like.

Furthermore, suitable wells (not separately shown) may be formed in the semiconductor fin 54 and/or the substrate 50. The conductivity type of the well may be opposite to that of source/drain regions to be subsequently formed in each of the N-type region 50N and the P-type region 50P. In some embodiments, a P-type well is formed in N-type region 50N and an N-type well is formed in P-type region 50P. In some embodiments, a P-type well or an N-type well is formed in both the N-type region 50N and the P-type region 50P.

In embodiments with different well types, the different implantation steps for the N-type region 50N and the P-type region 50P may be implemented using a mask (not separately shown) such as photoresist. For example, a photoresist may be formed over semiconductor fin 54, hybrid fin 66, and STI region 68 in N-type region 50N. The photoresist is patterned to expose the P-type region 50P. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, an N-type impurity implantation is performed in the P-type region 50P, and the photoresist may be used as a mask to substantially prevent the N-type impurity from being implanted into the N-type region 50N. The N-type impurity can be phosphorus, arsenic, antimony, etc. implanted in the region with a concentration range of 10 ¹³ cm ^-3 To 10 ¹⁴ cm ^-3 . After implantation, the photoresist is removed, for example by any acceptable ashing process.

After or before implantation of the P-type region 50P, a mask (not separately shown), such as photoresist, is formed over the semiconductor fin 54, hybrid fin 66, and STI region 68 in the P-type region 50P. The photoresist is patterned to expose the N-type region 50N. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, a P-type impurity implantation may be performed in the N-type region 50N, and the photoresist may act as a mask to substantially prevent the P-type impurity implantation into the P-type region 50P. The P-type impurity can be boron, boron fluoride, indium, etc. implanted in the region, and its concentration range is 10 ¹³ cm ^-3 To 10 ¹⁴ cm ^-3 . After implantation, the photoresist is removed, for example by any acceptable ashing process.

After implantation of the N-type region 50N and the P-type region 50P, an anneal may be performed to repair the implantation damage and activate the implanted P-type and/or N-type impurities. In some embodiments of epitaxially growing an epitaxial structure for semiconductor fin 54, the grown material may be doped in situ during growth, which may avoid implantation, although in situ and implant doping may be used together.

In fig. 8, a dummy dielectric layer 72 is formed on semiconductor fin 54, hybrid fin 66, and within seam 66A of hybrid fin 66. The dummy dielectric layer 72 may be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, and the like, which may be deposited or thermally grown according to acceptable techniques such as ALD, in situ vapor growth (ISSG), rapid Thermal Oxidation (RTO), and the like. The dummy dielectric layer 72 may fill or substantially fill the seam 66A of the hybrid fin 66. The dummy dielectric layer 72 may also include or be referred to as an interfacial layer or interfacial oxide layer. In some embodiments, the thickness of the dummy dielectric layer 72 is in the range of 1nm to 10 nm. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 may be deposited over the dummy dielectric layer 72 and then planarized, for example by CMP. The dummy gate layer 74 may be formed of an electrically conductive or non-conductive material, such as amorphous silicon, polysilicon (polysilicon), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, etc., which may be deposited by Physical Vapor Deposition (PVD), CVD, etc. The dummy gate layer 74 may be formed of material(s) having a high etch selectivity compared to etching of insulating material, such as STI regions 68 and/or dummy dielectric layer 72. A mask layer 76 may be deposited over the dummy gate layer 74. The mask layer 76 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the N-type region 50N and the P-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the semiconductor fin 54, the hybrid fin 66, and the STI region 68 such that the dummy dielectric layer 72 extends over the STI region 68 and between the dummy gate layer 74 and the STI region 68. In another embodiment, the dummy dielectric layer 72 covers only the semiconductor fin 54.

Fig. 9A-18C illustrate various additional steps in the fabrication of an embodiment device. Fig. 9A-18C illustrate features in either of the N-type region 50N and the P-type region 50P. For example, the illustrated structure may be applicable to both N-type region 50N and P-type region 50P. The structural differences, if any, between N-type region 50N and P-type region 50P are illustrated in the description of the figures.

In fig. 9A-9C, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 is then transferred to dummy gate layer 74 by any acceptable etching technique to form dummy gate 84. The pattern of mask 86 may optionally be further transferred to dummy dielectric layer 72 by any acceptable etching technique to form dummy dielectric 82. The dummy gate 84 overlies the corresponding channel region 58 of the semiconductor fin 54. The pattern of mask 86 may be used to physically separate adjacent dummy gates 84. The longitudinal direction of the dummy gate 84 may be substantially perpendicular (within process variations) to the longitudinal direction of the semiconductor fin 54. Mask 86 may be removed during patterning of dummy gate 84 or may be removed in a subsequent processing process.

Gate spacers 92 are formed over semiconductor fin 54 on exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. The gate spacers 92 may be formed by the steps of: one or more dielectric materials are conformally deposited and then etched. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like, which may be formed by conformal deposition processes such as Chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), plasma Enhanced Atomic Layer Deposition (PEALD), and the like. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process (e.g., dry etching, wet etching, etc., or combinations thereof) may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s) when etched has portions that remain on the sidewalls of the dummy gate 84 (thereby forming gate spacers 92). In some embodiments, the etch used to form gate spacers 92 is adjusted so that the dielectric material(s) also have portions that remain on the sidewalls of semiconductor fin 54 (thereby forming fin spacers 94) when etched. After etching, fin spacers 94 (if present) and gate spacers 92 may have straight sidewalls (as shown) or may have curved sidewalls (not separately shown).

Fin spacers 94 include inner fin spacers 94N (disposed between semiconductor fins 54 of the same fin structure 52, see fig. 8) and outer fin spacers 94O (disposed between semiconductor fins 54 and hybrid fins 66). In the illustrated embodiment, the internal fin spacers 94N are separated after patterning such that the STI regions 68A are exposed. In another embodiment, the inner fin spacers 94N are not completely separated, such that portions of the dielectric material(s) for the spacers remain over STI regions 68A. Further, because the height of STI region 68A is lower than the height of STI region 68B, inner fin spacer 94N has a higher height than outer fin spacer 94O.

In addition, implantation may be performed to form lightly doped source/drain (LDD) regions (not separately illustrated). In embodiments with different device types, a mask (not separately shown), such as photoresist, may be formed over the N-type region 50N, similar to the implantation for the well described previously, while exposing the P-type region 50P, and appropriate types of impurities (e.g., P-type) may be implanted into the semiconductor fin 54 exposed in the P-type region 50P. The mask may then be removed. Subsequently, a mask (not separately illustrated) such as a photoresist may be formed over the P-type region 50P while exposing the N-type region 50N, and an appropriate type of impurity (e.g., N-type) may be implanted into the semiconductor fin 54 exposed in the N-type region 50N. The mask may then be removed. The n-type impurity may be any of the aforementioned n-type impurities, and the p-type impurity may be any of the aforementioned p-type impurities. During the implantation, the channel region 58 remains covered by the dummy gate 84 such that the channel region 58 is substantially free of impurities implanted to form LDD regions. The impurity concentration of the LDD region may be 10 ¹⁵ cm ^-3 To 10 ¹⁹ cm ^-3 Within a range of (2). Annealing may be used to repair implant damage and activate implanted impurities.

Note that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be employed, steps in a different order may be employed, additional spacers may be formed and removed, and so forth. In addition, different structures and steps may be used to form n-type devices and p-type devices.

In fig. 10A-10C, source/drain recesses 96 are formed in the semiconductor fin 54. In the illustrated embodiment, the source/drain recesses 96 extend into the semiconductor fin 54. The source/drain recesses 96 may also extend to the substrate 50. In various embodiments, the source/drain recesses 96 may extend to the top surface of the substrate 50 without etching the substrate 50; the semiconductor fin 54 may be etched such that the bottom surface of the source/drain recess 96 is disposed lower than the top surface of the STI region 68; etc. The source/drain recesses 96 may be formed by etching the semiconductor fin 54 using an anisotropic etching process such as RIE, NBE, or the like. The etching process selectively etches the material(s) of the semiconductor fin 54 at a faster rate (than the etching rate for the material of the hybrid fin 66 and STI region 68). During the etching process for forming the source/drain recesses 96, the gate spacers 92 and the dummy gates 84 collectively mask portions of the semiconductor fin 54. A timed etch process may be used to stop the etching of the source/drain recesses 96 after the source/drain recesses 96 reach a desired depth. The fin spacers 94 (if present) may be etched during or after etching the source/drain recesses 96 such that the height of the fin spacers 94 is reduced. The size and dimensions of the source/drain regions to be subsequently formed in the source/drain recesses 96 may be controlled by adjusting the height of the fin spacers 94. When etching the source/drain recesses 96, the hybrid fin 66 is not recessed, but remains between the fin structures 52.

In fig. 11A-11C, epitaxial source/drain regions 98 are formed in source/drain recesses 96. The epitaxial source/drain regions 98 are thus disposed in the semiconductor fin 54 such that each dummy gate 84 (and corresponding channel region 58) is between a respective adjacent pair of epitaxial source/drain regions 98. Thus, the epitaxial source/drain regions 98 are contiguous with the channel region 58. In some embodiments, the gate spacers 92 are used to separate the epitaxial source/drain regions 98 from the dummy gate 84 by an appropriate lateral distance so that the epitaxial source/drain regions 98 do not short to the gates of the resulting FinFET that is subsequently formed. The material of the epitaxial source/drain regions 98 may be selected to impart stress in the respective channel regions 58 to enhance performance.

Epitaxial source/drain regions 98 in N-type region 50N may be formed by masking P-type region 50P. Source/drain regions 98 in N-type region 50N are then epitaxially grown in source/drain recesses 96 in N-type region 50N. Epitaxial source/drain regions 98 may comprise any acceptable material suitable for use in an n-type device. For example, if semiconductor fin 54 is silicon, epitaxial source/drain regions 98 in N-type region 50N may include a material that imparts a tensile strain on channel region 58, such as silicon, silicon carbide, phosphorus doped silicon carbide, silicon phosphide, and the like. The epitaxial source/drain regions 98 in the N-type region 50N may be referred to as "N-type source/drain regions". The epitaxial source/drain regions 98 in the N-type region 50N may have surfaces that are raised from the corresponding surfaces of the semiconductor fin 54 and may have facets.

Epitaxial source/drain regions 98 in P-type region 50P may be formed by masking N-type region 50N. Epitaxial source/drain regions 98 in P-type region 50P are then epitaxially grown in source/drain recesses 96 in P-type region 50P. Epitaxial source/drain regions 98 may comprise any acceptable material suitable for use in p-type devices. For example, if semiconductor fin 54 is silicon, epitaxial source/drain regions 98 in P-type region 50P may include a material that imparts a compressive strain on channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium tin, and the like. The epitaxial source/drain regions 98 in the P-type region 50P may be referred to as "P-type source/drain regions". The epitaxial source/drain regions 98 in the P-type region 50P may have surfaces that are raised from the corresponding surfaces of the semiconductor fin 54 and may have facets.

Can be implanted with impuritiesThe source/drain regions 98 and/or the semiconductor fin 54 are epitaxial to form source/drain regions, similar to the process described previously for forming LDD regions, and then annealed. The impurity concentration of the source/drain region may be 10 ¹⁹ cm ^-3 To 10 ²¹ cm ^-3 Within a range of (2). The n-type and/or p-type impurities for the source/drain regions may be any of the foregoing impurities. In some embodiments, the epitaxial source/drain regions 98 may be doped in-situ during growth.

The epitaxial source/drain regions 98 may include one or more layers of semiconductor material. For example, epitaxial source/drain regions 98 may each include a liner layer 98A, a main layer 98B, and a finish layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of layers of semiconductor material may be used for epitaxial source/drain regions 98. In embodiments where epitaxial source/drain regions 98 include three layers of semiconductor material, liner layer 98A may be grown in source/drain recesses 96, main layer 98B may be grown on liner layer 98A, and completion layer 98C may be grown on main layer 98B. The liner layer 98A, the main layer 98B, and the finish layer 98C may be formed of different semiconductor materials and may be doped with different impurity concentrations. In some embodiments, the main layer 98B has a higher impurity concentration than the finish layer 98C, and the finish layer 98C has a higher impurity concentration than the liner layer 98A. Forming the liner layer 98A with a lower impurity concentration than the main layer 98B may increase adhesion in the source/drain recess 96, and forming the finish layer 98C with a lower impurity concentration than the main layer 98B may reduce out-diffusion of dopants from the main layer 98B during subsequent processing.

As a result of the epitaxial process used to form epitaxial source/drain regions 98, the upper surfaces of the epitaxial source/drain regions have facets that extend laterally outward beyond the sidewalls of semiconductor fin 54. In some embodiments, these facets merge adjacent epitaxial source/drain regions 98, as shown in fig. 11C. However, hybrid fin 66 (if present) prevents lateral epitaxial growth to prevent coalescence of some of epitaxial source/drain regions 98. For example, hybrid fins 66 may be formed at cell boundaries to separate epitaxial source/drain regions 98 of adjacent cells. Thus, some of the epitaxial source/drain regions 98 are separated by the hybrid fin 66. Epitaxial source/drain regions 98 may contact sidewalls of hybrid fin 66. In the illustrated embodiment, fin spacers 94 are formed to cover the portion of the sidewalls of semiconductor fin 54 that extends higher than STI regions 68, thereby preventing epitaxial growth. In another embodiment, the spacer etch to be used to form gate spacers 92 is adjusted to not form fin spacers 94, allowing epitaxial source/drain regions 98 to extend to the surface of STI regions 68.

After fin spacers 94 are recessed (described with respect to fig. 10A-10C) and epitaxial source/drain regions 98 are grown (described with respect to fig. 11A-11C), fin spacers 94 may maintain their relative heights such that inner fin spacers 94N still have a greater height than outer fin spacers 94O. Thus, the outer fin spacer 94O over the STI region 68B (between the hybrid fin 66 and the semiconductor fin 54) has a first height, the inner fin spacer 94N over the STI region 68A (between the semiconductor fins 54) has a second height, and the second height is greater than the first height. In some embodiments, the heights of the inner fin spacers 94N and the outer fin spacers 94O are in the range of 5nm to 50 nm.

In fig. 12A-12C, a first interlayer dielectric (ILD) 104 is deposited over the epitaxial source/drain regions 98, the gate spacers 92, the mask 86 (if present) or the dummy gate 84, and the hybrid fin 66. The first ILD 104 may be formed of a dielectric material that may be deposited by any suitable method (e.g., CVD, plasma Enhanced CVD (PECVD), FCVD, etc.). Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used.

In some embodiments, a Contact Etch Stop Layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source/drain regions 98, the gate spacers 92, the mask 86 (if present) or the dummy gate 84, and the hybrid fin 66. In some embodiments, CESL 102 fills or substantially fills seam 66A of hybrid fin 66 adjacent source/drain regions 98 (see, e.g., fig. 12C). CESL 102 may be formed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with high etch selectivity (compared to the etch of first ILD 104). CESL 102 may be formed by any suitable method, such as CVD, ALD, and the like.

In fig. 13A-13C, a removal process is performed to bring the top surface of the first ILD 104 flush with the top surfaces of the gate spacers 92 and mask 86 (if present) or dummy gate 84. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), a deep etch process, combinations thereof, and the like may be employed. The planarization process may also remove the mask 86 over the dummy gate 84, as well as the portion of the gate spacer 92 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the first ILD 104, CESL 102, gate spacers 92, and mask 86 (if present) or dummy gate 84 are coplanar (within the process variation) so that they are flush with each other. Accordingly, the top surface of mask 86 (if present) or dummy gate 84 is exposed through first ILD 104. In the illustrated embodiment, the mask 86 remains and the planarization process leaves the top surface of the first ILD 104 flush with the top surface of the mask 86.

In fig. 14A-14C, the mask 86 (if present) and the dummy gate 84 and the dummy dielectric 82 are removed in an etching process to form the recess 106. The removal process removes the dummy dielectric 82 from the seam 66A of the hybrid fin 66, which was previously exposed with the removal of the dummy gate 84. In some embodiments, the dummy dielectric 82 is removed from the recess 106 in a first region of the die (e.g., the core logic region), but remains in the recess 106 in a second region of the die (e.g., the input/output region). In some embodiments, the dummy gate 84 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using reactive gas (es) that selectively etch the material of the dummy gate 84 at a faster rate (than the etch rate for the material of the first ILD 104 and gate spacer 92). During the removal, the dummy dielectric 82 may act as an etch stop layer when the dummy gate 84 is etched. The dummy dielectric 82 may then be removed after the dummy gate 84 is removed. In some embodiments, the dummy dielectric 82 is removed by an anisotropic etching process. Each recess 106 exposes and/or covers the channel region 58 of a respective semiconductor fin 54. The recess 106 also exposes the hybrid fin 66 and the seam 66A of the hybrid fin 66.

In fig. 15A-16C, a gate dielectric 112 and a gate electrode 114 are formed for the replacement gate. The gate dielectric 112 and gate electrode 114 of each respective pair may be collectively referred to as a "gate structure". Each gate structure extends along the sidewalls and top surface of the channel region 58 of the semiconductor fin 54. Some gate structures also extend along the sidewalls and top surfaces of hybrid fin 66.

The gate dielectric 112 includes two or more gate dielectric layers 112A and 112B disposed in the recess 106 (e.g., on the top surface and sidewalls of the semiconductor fin 54, on the top surface and sidewalls of the hybrid fin 66, and on the top surface and sidewalls of the gate spacer 92). The gate dielectric layer 112A may be referred to as an interfacial layer and may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a plurality of layers thereof, and the like. Gate dielectric layer 112A is formed to fill or substantially fill seam 66A in hybrid fin 66. The gate dielectric layer 112A is formed in the seam 66A by first immersing the structure in a silicon precursor followed by an oxidation process. In some embodiments, the silicon precursor comprises SiH ₄ 、Si ₂ H ₆ 、LTO520(C ₆ H ₁₇ NSi)、SAM24(C ₈ H ₂₂ N ₂ Si), or the like, or combinations thereof. In some embodiments, the silicon precursor soak process is performed under the following conditions: the temperature range is 350 ℃ to 490 ℃, the duration period is in the range of 10 minutes to 30 minutes, and the ratio of silicon precursor to carrier gas is in the range of 5:1 to 10:1, wherein the carrier gas comprises N ₂ 、H ₂ Etc. Performing a silicon precursor soak under process conditions in these ranges followed by an oxidation process provides a thin enough film (e.g., less than 10 angstroms) and a bulk wafer structure of semiconductor fins 54 mixed withThe length, width, and height of the trench design between fins 66 are not affected.

In some embodiments, the oxidation process is O ₃ And (5) an oxidation process. The gate dielectric layer 112A within the seam 66A of the hybrid fin 66 may have a different material composition than the gate dielectric layer 112A on the semiconductor fin 54. In some embodiments, the gate dielectric layer 112A within the seam 66A is more silicon-rich than the gate dielectric layer 112A outside of the seam 66A. For example, the silicon to oxygen ratio (Si: O) of gate dielectric layer 112A within seam 66A of hybrid fin 66 may be in the range of 1:1 to 1:1.5, and the Si to O ratio of gate dielectric layer 112A on semiconductor fin 54 may be in the range of 1:1.5 to 1:2.

Fig. 19 illustrates a structure at a similar processing stage as fig. 15A, in accordance with some embodiments. The steps and processes for forming the structure are similar to those described in other embodiments, and are not repeated here. In fig. 19, gate dielectric layer 112A is within seam 66A and over channel region 58 of semiconductor fin 54. In some embodiments, gate dielectric layer 112A is not formed on the outer sidewalls of hybrid fin 66, as shown in fig. 19.

By filling the seam 66A of the hybrid fin 66 with the interfacial layer 112A, conductive material from subsequently formed source/drain and/or gate contacts is prevented from forming in the seam 66A. Preventing conductive material from the source/drain and/or gate contacts from forming in the seam 66A prevents the source/drain and gate from shorting to each other through the seam 66A. Thus, the manufacturing yield of the device can be improved. Furthermore, by doing the following two simultaneously, no additional process is required to fill the seam of the hybrid fin: the formation of the interfacial layer(s) under the replacement gate structure, and the filling of the seam 66A.

After forming the gate dielectric layer 112A, the gate dielectric layer 112B is formed. The gate dielectric layer 112B may comprise a high-k dielectric material such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material(s) of gate dielectric layer 112B may be formed by Molecular Beam Deposition (MBD), ALD, PECVD, or the like. Gate dielectric layer 112B is not formed within seam 66A because seam 66A is already filled with gate dielectric layer 112A. In embodiments in which a portion of the dummy dielectric 82 remains in the recess 106, the gate dielectric layer 112 includes a material (e.g., silicon oxide) of the dummy dielectric 82. Although a dual-layer gate dielectric layer 112 is illustrated, the gate dielectric layer 112 may include any number of interface layers and any number of main layers.

In fig. 16A-16C, a gate electrode 114 comprising one or more gate electrode layers is disposed over the gate dielectric 112, filling the remainder of the recess 106. The gate electrode 114 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, and the like. Although a single layer gate electrode 114 is shown, the gate electrode 114 may include any number of work function modifying layers, any number of barrier layers, any number of adhesion layers, and filler materials.

As an example of forming the gate structure, one or more gate dielectric layers may be deposited in the recess 106. Gate dielectric layer(s) may also be deposited on top surfaces of first ILD 104, CESL 102, and gate spacers 92. Subsequently, one or more gate electrode layers may be deposited on the gate dielectric layer(s) 112. A removal process may then be performed to remove the excess portions of the gate dielectric layer(s) and gate electrode layer(s) over the top surfaces of the first ILD 104, CESL 102 and gate spacers 92. The gate dielectric layer(s) have portions left in the recess 106 (thereby forming the gate dielectric 112) after the removal process. The gate electrode layer(s) have portions that remain in the recess 106 (thereby forming the gate electrode 114) after the removal process. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), a deep etch process, combinations thereof, and the like may be employed. After the planarization process, the top surfaces of gate spacer 92, CESL 102, first ILD 104, gate dielectrics 112A and 112B, and gate electrode 114 are coplanar (within the scope of process variation) such that they are flush with each other.

The formation of gate dielectrics 112A and 112B in N-type region 50N and P-type region 50P may occur simultaneously such that gate dielectrics 112A and 112B in each region are formed of the same material(s), and the formation of gate electrode 114 may occur simultaneously such that gate electrode 114 in each region is formed of the same material(s). In some embodiments, the gate dielectrics 112A and 112B in each region may be formed by different processes such that the gate dielectrics 112A and 112B may comprise different materials and/or have different numbers of layers, and/or the gate electrode 114 in each region may be formed by different processes such that the gate electrode 114 may comprise different materials and/or have different numbers of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

In fig. 17A-17C, a second ILD 124 is deposited over gate spacer 92, CESL 102, first ILD 104, gate dielectrics 112A and 112B, and gate electrode 114. In some embodiments, the second ILD 124 is a flowable film formed by a flowable CVD process.

In some embodiments, the second ILD 124 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, that may be deposited by any suitable method, such as CVD, PECVD.

Optionally, a gate mask 116 is formed over the gate structure (including gate dielectric 112 and gate electrode 114) prior to forming the second ILD 124. As an example of forming the gate mask 116, the gate structure and optional gate spacer 92 may be recessed using any acceptable etching process. One or more dielectric materials may then be formed in the recess and on top surfaces of the CESL 102 and the first ILD 104. Acceptable dielectric materials include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and the like, which may be formed by conformal deposition processes such as Chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), plasma Enhanced Atomic Layer Deposition (PEALD), and the like. Other insulating materials formed by any acceptable process may be used. A removal process is performed to remove excess portions of the dielectric material(s) that are over the top surfaces of the CESL 102 and the first ILD 104, thereby forming the gate mask 116. The dielectric material(s) have portions left in the recesses (thereby forming the gate mask 116) after the removal process. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), a deep etch process, combinations thereof, and the like may be employed. After the planarization process, the top surfaces of CESL 102, first ILD 104, and gate mask 116 are coplanar (within the process variation) such that they are flush with each other. A gate contact will then be formed to penetrate gate mask 116 to contact the top surface of gate electrode 114.

In some embodiments, an Etch Stop Layer (ESL) 122 is formed between the second ILD 124 and the gate spacer 92, CESL 102, first ILD 104 and gate mask 116 (if present) or gate dielectrics 112A and 112B and gate electrode 114. The ESL 122 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etch selectivity (compared to the etch of the second ILD 124).

In fig. 18A-18C, gate contacts 132 and source/drain contacts 134 are formed to contact gate electrode 114 and epitaxial source/drain regions 98, respectively. The gate contact 132 is physically and electrically coupled to the gate electrode 114. Source/drain contacts 134 are physically and electrically coupled to epitaxial source/drain regions 98.

As an example of forming the gate contacts 132 and the source/drain contacts 134, openings for the gate contacts 132 are formed through the second ILD 124, ESL 122, and gate mask 116, and openings for the source/drain contacts 134 are formed through the second ILD 124, ESL 122, first ILD 104, and CESL 102. These openings may be formed using acceptable photolithography and etching techniques. Liners (not separately shown) such as diffusion barriers, adhesion layers, and conductive materials are formed in these openings. The liner may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 124. The remaining liner and conductive material form gate contacts 132 and source/drain contacts 134 in the openings. The gate contact 132 and the source/drain contact 134 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 132 and the source/drain contact 134 may be formed in different cross-sections, which may avoid shorting of the contacts.

Optionally, metal-semiconductor alloy regions 136 are formed at the interface between the epitaxial source/drain regions 98 and the source/drain contacts 134. The metal-semiconductor alloy region 136 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a germanide region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 136 may be formed by depositing metal in the opening of the source/drain contact 134 and then performing a thermal annealing process prior to the material(s) of the source/drain contact 134. The metal may be any metal capable of reacting with the semiconductor material (e.g., silicon-germanium, etc.) of the epitaxial source/drain regions 98 to form a low resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD. After the thermal annealing process, a cleaning process (e.g., a wet clean) may be performed to remove any residual metal from the openings for the source/drain contacts 134 (e.g., from the surface of the metal-semiconductor alloy regions 136). The material(s) of the source/drain contacts 134 may then be formed on the metal-semiconductor alloy region 136.

Various advantages may be realized by various embodiments. Filling seam 66A of hybrid fin 66 with interfacial layer 112A prevents conductive material from subsequently forming source/drain and/or gate contacts from forming in seam 66A. Preventing conductive material from the source/drain and/or gate contacts from forming in the seam 66A prevents the source/drain and gate from shorting to each other through the seam 66A. Thus, the manufacturing yield of the device can be improved. In some embodiments, the seam 66A is filled by a silicon precursor soak process and an oxidation process. These processes simultaneously form the interfacial layer(s) under the replacement gate structure, thereby eliminating the need for additional processes to fill the seams of the hybrid fin.

The disclosed FinFET embodiments may also be applied to nanostructure devices, such as nanostructured (e.g., nanoplatelets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced with nanostructures formed by patterning stacks of alternating layers of channel layers and sacrificial layers. The dummy gate structure and source/drain regions are formed in a manner similar to the embodiments described above. After the dummy gate structure is removed, the sacrificial layer in the channel region may be partially or completely removed. The replacement gate structure may be formed in a manner similar to the embodiments described above, the replacement gate structure may partially or completely fill the opening left by the removal of the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. ILD and contacts to the replacement gate structures and source/drain regions may be formed in a similar manner to the embodiments described above.

Furthermore, finFET/NSFET devices may be interconnected by metallization layers in overlying interconnect structures to form integrated circuits. The overlying interconnect structure may be formed in a back-end-of-line (BEOL) process in which a metallization layer is connected to the gate contacts 132 and the source/drain contacts 134. Such as passive devices, memory (e.g., magnetoresistive Random Access Memory (MRAM), resistive Random Access Memory (RRAM), phase Change Random Access Memory (PCRAM), etc., may be integrated with the interconnect structure during BEOL processing.

One embodiment includes a device comprising: the semiconductor device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide interior extending downward from a top surface of the hybrid fin. The device further includes: a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending higher than a top surface of the first isolation region; a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin; a gate electrode on the high-k gate dielectric; and source/drain regions on the first semiconductor fin on opposite sides of the gate electrode.

Embodiments may include one or more of the following features. The top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin of the device are flush with one another. The first semiconductor fin includes: an interfacial oxide layer between the sidewalls of the first semiconductor fin and the high-k gate dielectric. The oxide interior of the hybrid fin is more silicon-rich than the interfacial oxide layer. The hybrid fin includes silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. The device further includes: a third semiconductor fin adjacent to the second semiconductor fin, a second isolation region between the second semiconductor fin and the third semiconductor fin, a top surface of the first isolation region being disposed farther from the substrate than a top surface of the second isolation region. The bottom surface of the first isolation region is disposed farther from the top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin than the bottom surface of the second isolation region.

One embodiment includes a method comprising: forming a first semiconductor fin and a second semiconductor fin extending from a substrate; an insulating material is formed around the first semiconductor fin and the second semiconductor fin, with a first portion of the insulating material disposed between the first semiconductor fin and the second semiconductor fin. The method further comprises the steps of: a hybrid fin is formed on the first portion of the insulating material, the hybrid fin having a seam therein. The method further comprises the steps of: a first portion of the insulating material is recessed to form a first isolation region. The method further comprises the steps of: a dummy gate structure is formed over the first semiconductor fin, the hybrid fin, and the second semiconductor fin. The method further comprises the steps of: source/drain regions are formed on opposite sides of the dummy gate structure on the first semiconductor fin and the second semiconductor fin. The method further comprises the steps of: the dummy gate structure is removed to form a gate trench. The method further comprises the steps of: in the gate trench, a first gate dielectric layer is formed over the first semiconductor fin, the hybrid fin, and the second semiconductor fin, the first gate dielectric layer filling the seams in the hybrid fin. The method further comprises the steps of: in the gate trench, a second gate dielectric layer is formed on the first gate dielectric layer. The method further comprises the steps of: a gate electrode layer is formed on the second gate dielectric layer in the gate trench.

Embodiments may include one or more of the following features. The method for forming the hybrid fin comprises the following steps: depositing a dielectric layer on the insulating material between the first semiconductor fin and the second semiconductor fin not occupied by the insulating material; portions of the dielectric layer are removed. Removing the portion of the dielectric layer includes: the dielectric layer, the insulating material, the first semiconductor fin, and the second semiconductor fin are planarized, wherein top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are flush with each other. Forming the first gate dielectric layer includes: performing a silicon precursor soaking process in the gate trench; an oxidation process is performed in the gate trench after performing the silicon precursor soak process, wherein after the oxidation process a first gate dielectric layer is formed in the seam of the gate trench and the hybrid fin. The first gate dielectric layer comprises silicon oxide and wherein the second gate dielectric layer comprises a high-k layer. The first gate dielectric layer in the seam of the hybrid fin is more silicon-rich than the first gate dielectric layer on the first semiconductor fin. The hybrid fin includes silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. The method further comprises the steps of: forming an etch stop layer over the source/drain regions and the hybrid fin, the etch stop layer filling a portion of the seam in the hybrid fin outside the gate trench; an interlayer dielectric is formed over the etch stop layer. The method further comprises the steps of: conductive contacts are formed through the interlayer dielectric and the etch stop layer to the source/drain regions, the conductive contacts being electrically connected to the source/drain regions.

One embodiment includes a method comprising: a first semiconductor fin is formed extending from the substrate. The method further comprises the steps of: an insulating material is formed around the first semiconductor fin. The method further comprises the steps of: a dielectric layer is deposited over the insulating material around the first semiconductor fin. The method further comprises the steps of: portions of the dielectric layer are removed to form dielectric fins having seams therein. The method further comprises the steps of: the insulating material is recessed, wherein after recessing the insulating material, the dielectric fin extends above a top surface of the insulating material. The method further comprises the steps of: a dummy gate structure is formed over the first semiconductor fin, the dielectric fin, and the recessed insulating material. The method further comprises the steps of: source/drain regions are formed on the first semiconductor fin on opposite sides of the dummy gate structure. The method further comprises the steps of: the dummy gate structure is removed to form a gate trench. The method further comprises the steps of: a silicon precursor soak process is performed in the gate trench. The method further comprises the steps of: after performing the silicon precursor soak process, an oxidation process is performed in the gate trench to form an interfacial layer on the first semiconductor fin and the dielectric fin in the gate trench, the interfacial layer filling the seams in the dielectric fin. The method further comprises the steps of: in the gate trench, a high-k gate dielectric layer is formed on the interfacial layer. The method further comprises the steps of: in the gate trench, a gate electrode layer is formed on the high-k gate dielectric layer.

Embodiments may include one or more of the following features. The interfacial layer in the seams of the dielectric fin in this method is more silicon-rich than the interfacial layer on the first semiconductor fin. The high-k gate dielectric layer is not in the seams of the dielectric fin. Removing portions of the dielectric layer includes: the method includes planarizing the dielectric layer, the insulating material, and the first semiconductor fin, wherein top surfaces of the dielectric fin and the first semiconductor fin are flush with each other.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1. A semiconductor device includes:

a first semiconductor fin extending from the substrate;

a second semiconductor fin extending from the substrate;

A hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, the hybrid fin having an oxide interior extending downward from a top surface of the hybrid fin;

a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending higher than a top surface of the first isolation region;

a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin;

a gate electrode on the high-k gate dielectric; and

source/drain regions on the first semiconductor fin on opposite sides of the gate electrode.

Example 2 the device of example 1, wherein top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are flush with one another.

Example 3 the device of example 1, wherein the first semiconductor fin includes an interfacial oxide layer between a sidewall of the first semiconductor fin and the high-k gate dielectric.

Example 4 the device of example 3, wherein an oxide interior of the hybrid fin is more silicon-rich than the interfacial oxide layer.

Example 5 the device of example 1, wherein the hybrid fin comprises silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof.

Example 6 the device of example 1, further comprising:

a third semiconductor fin adjacent to the second semiconductor fin; and

a second isolation region between the second semiconductor fin and the third semiconductor fin, a top surface of the first isolation region being disposed farther from the substrate than a top surface of the second isolation region.

Example 7 the device of example 6, wherein a bottom surface of the first isolation region is disposed farther from a top surface of the hybrid fin, the first semiconductor fin, and the second semiconductor fin than a bottom surface of the second isolation region.

Example 8. A method of forming a semiconductor device, comprising:

forming a first semiconductor fin and a second semiconductor fin extending from a substrate;

forming an insulating material around the first semiconductor fin and the second semiconductor fin, a first portion of the insulating material being disposed between the first semiconductor fin and the second semiconductor fin;

Forming a hybrid fin on a first portion of the insulating material, the hybrid fin having a seam therein;

recessing a first portion of the insulating material to form a first isolation region;

forming a dummy gate structure over the first semiconductor fin, the hybrid fin, and the second semiconductor fin;

forming source/drain regions on opposite sides of the dummy gate structure on the first semiconductor fin and the second semiconductor fin;

removing the dummy gate structure to form a gate trench;

a first gate dielectric layer formed in the gate trench over the first semiconductor fin, the hybrid fin, and the second semiconductor fin, the first gate dielectric layer filling a seam in the hybrid fin;

a second gate dielectric layer formed on the first gate dielectric layer in the gate trench; and is also provided with

And a gate electrode layer formed on the second gate dielectric layer in the gate trench.

Example 9. The method of example 8, wherein forming the hybrid fin comprises:

depositing a dielectric layer on the insulating material between the first semiconductor fin and the second semiconductor fin not occupied by the insulating material; and is also provided with

And removing a part of the dielectric layer.

Example 10 the method of example 9, wherein removing the portion of the dielectric layer comprises:

the dielectric layer, the insulating material, the first semiconductor fin, and the second semiconductor fin are planarized, wherein top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are flush with each other.

Example 11 the method of example 8, wherein forming the first gate dielectric layer comprises:

performing a silicon precursor soaking process in the gate trench; and is also provided with

An oxidation process is performed in the gate trench after performing the silicon precursor soak process, wherein after the oxidation process the first gate dielectric layer is formed in the gate trench and in the seams of the hybrid fin.

Example 12 the method of example 8, wherein the first gate dielectric layer comprises silicon oxide, and wherein the second gate dielectric layer comprises a high-k layer.

Example 13 the method of example 12, wherein the first gate dielectric layer in the seam of the hybrid fin is more silicon-rich than the first gate dielectric layer on the first semiconductor fin.

Example 14. The method of example 8, wherein the hybrid fin comprises silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof.

Example 15. The method of example 8, further comprising:

forming an etch stop layer over the source/drain regions and the hybrid fin, the etch stop layer filling a portion of a seam in the hybrid fin outside the gate trench; and is also provided with

An interlayer dielectric is formed over the etch stop layer.

Example 16 the method of example 15, further comprising:

conductive contacts are formed through the interlayer dielectric and the etch stop layer to the source/drain regions, the conductive contacts electrically connected to the source/drain regions.

Example 17 a method of forming a semiconductor device, comprising:

forming a first semiconductor fin extending from a substrate;

forming an insulating material around the first semiconductor fin;

depositing a dielectric layer on the insulating material around the first semiconductor fin; and is also provided with

Removing portions of the dielectric layer to form dielectric fins having seams therein;

Recessing the insulating material, wherein the dielectric fin extends above a top surface of the insulating material after recessing the insulating material;

forming a dummy gate structure over the first semiconductor fin, the dielectric fin, and the recessed insulating material;

forming source/drain regions on opposite sides of the dummy gate structure on the first semiconductor fin;

removing the dummy gate structure to form a gate trench;

Performing an oxidation process in the gate trench after performing the silicon precursor soaking process to form an interface layer on the first semiconductor fin and the dielectric fin in the gate trench, the interface layer filling a seam in the dielectric fin;

a high-k gate dielectric layer formed on the interfacial layer in the gate trench; and is also provided with

A gate electrode layer formed on the high-k gate dielectric layer in the gate trench.

Example 18 the method of example 17, wherein the interfacial layer in the seam of the dielectric fin is more silicon-rich than the interfacial layer on the first semiconductor fin.

Example 19 the method of example 17, wherein the high-k gate dielectric layer is not in a seam of the dielectric fin.

Example 20 the method of example 17, wherein removing the portion of the dielectric layer comprises:

the dielectric layer, the insulating material, and the first semiconductor fin are planarized, wherein top surfaces of the dielectric fin and the first semiconductor fin are flush with each other.

Claims

1. A semiconductor device, comprising:

a first semiconductor fin extending from the substrate;

a second semiconductor fin extending from the substrate;

a gate electrode on the high-k gate dielectric; and

2. The device of claim 1, wherein top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are flush with one another.

3. The device of claim 1, wherein the first semiconductor fin comprises an interfacial oxide layer between sidewalls of the first semiconductor fin and the high-k gate dielectric.

4. The device of claim 3, wherein an oxide interior of the hybrid fin is more silicon-rich than the interfacial oxide layer.

5. The device of claim 1, wherein the hybrid fin comprises silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof.

6. The device of claim 1, further comprising:

a third semiconductor fin adjacent to the second semiconductor fin; and

7. The device of claim 6, wherein a bottom surface of the first isolation region is disposed farther from top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin than a bottom surface of the second isolation region.

8. A method of forming a semiconductor device, comprising:

removing the dummy gate structure to form a gate trench;

9. The method of claim 8, wherein forming the hybrid fin comprises:

And removing a part of the dielectric layer.

10. A method of forming a semiconductor device, comprising:

forming a first semiconductor fin extending from a substrate;

forming an insulating material around the first semiconductor fin;

Removing the dummy gate structure to form a gate trench;