CN116469428A

CN116469428A - Nonvolatile memory device and cache reading method thereof

Info

Publication number: CN116469428A
Application number: CN202310076591.XA
Authority: CN
Inventors: 曺溶成; 金珉辉; 赵虎相
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-01-18
Filing date: 2023-01-16
Publication date: 2023-07-21

Abstract

A nonvolatile memory device including a plurality of page buffer units each having a sensing latch and a sensing node line and a cache latch, and a cache read method thereof are provided. The method comprises the following steps: performing a first on-chip valley search (OVS) read on the selected memory cell using a first sense node line and a first sense latch of a first page buffer cell of the plurality of page buffer cells; storing first data sensed from the selected memory cell in a first sense latch, the first data based on a result of the first OVS read; dumping the first data to a sensing node line of at least one page buffer unit other than the first page buffer unit among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sense latch.

Description

Nonvolatile memory device and cache reading method thereof

The present application claims korean patent application No. 10-2022-0007354 filed on 1 month 18 of 2022 and korean patent application No. 10-2022-0054806 filed on 5 month 3 of 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

Example embodiments of the inventive concepts relate to a semiconductor memory device, and more particularly, to a nonvolatile memory device having a combined sensing node and a cache read method thereof.

Background

Recently, with the multifunctionality of information and communication devices, there is a demand for increasing the capacity and high integration of semiconductor memory devices. The semiconductor memory device includes a write driver for writing data and a sense amplifier for reading data. In particular, a nonvolatile memory device that stores data even after power is removed may include a page buffer having functions of a write driver and a sense amplifier.

The page buffer includes a plurality of latches for temporarily storing data to be written to and/or sensed from the memory cells. The number of such latches may be increased in order to improve the reliability or performance of the page buffer. However, as the number of latches increases, the chip area increases and the cost increases. Accordingly, there is a need for techniques that can improve the performance and/or reliability of page buffers without increasing the chip area and/or the number of latches.

Disclosure of Invention

Some embodiments of the present disclosure provide a nonvolatile memory device capable of providing high data reliability or performance without adding latches by utilizing the capacity of a sensing node and a method of reading a cache thereof.

According to an embodiment of the inventive concept, a cache read method of a nonvolatile memory device including a memory cell array, a plurality of page buffer units each having a sensing latch and a sensing node line, and a cache latch, the method includes: performing a first on-chip valley search (OVS) read on the selected memory cell using a first sense node line and a first sense latch of a first page buffer cell of the plurality of page buffer cells; storing first data sensed from the selected memory cell in a first sense latch, the first data based on a result of the first OVS read; dumping the first data to a sensing node line of at least one page buffer unit other than the first page buffer unit among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sense latch.

According to an embodiment of the inventive concept, a nonvolatile memory device includes: a cell array including a plurality of memory cells connected in series to a bit line; a page buffer circuit comprising a plurality of page buffer units configured to: programming or sensing at least one of the plurality of memory cells through a bit line and electrically connecting or blocking an adjacent sense node line in response to a transmission control signal; and a control circuit configured to: during a cache read operation, moving first data corresponding to a first state, which is sensed through a first sensing node line, in a first sensing latch of a first page buffer unit to a second sensing node line of a second page buffer unit; and controlling the page buffer circuit such that the first sensing latch performs an on-chip valley search (OVS) for reading the second state of the first sensing node line.

According to an embodiment of the inventive concept, a method of a cache read method of a nonvolatile memory device includes: storing first data in a sense latch of a first page buffer unit, the first data being sensed from a selected memory unit; a sense node line for dumping the first data to the second page buffer unit; and performing an on-chip valley search (OVS) on the selected memory cells using the sense latches.

Drawings

The above and other objects and features of the present disclosure will become apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a non-volatile memory device in accordance with at least one embodiment of the present invention.

Fig. 2 schematically illustrates a structure of the non-volatile memory device of fig. 1 in accordance with at least one embodiment of the present disclosure.

Fig. 3 is a circuit diagram showing an example structure of a memory block constituting the cell array of fig. 2.

Fig. 4 is a diagram showing a connection between the cell array and the page buffer circuit.

Fig. 5 is a circuit diagram showing a page buffer unit and a cache unit constituting a page buffer.

Fig. 6 is a diagram showing an arrangement of a page buffer circuit according to an embodiment of the present invention.

Fig. 7 is a circuit diagram schematically illustrating some configurations of the upper page buffer and page buffer decoder of fig. 6.

Fig. 8 is a diagram schematically illustrating a page buffer unit performing an on-chip valley search OVS and sensing nodes of the remaining page buffer units among the upper page buffer of fig. 7.

Fig. 9 is a flowchart illustrating an operation method using the combined sensing node c_so performed in the control circuit of fig. 1.

Fig. 10 is a diagram illustrating a read method for a specific page of memory cells in accordance with at least one embodiment of the present invention.

Fig. 11 is a timing chart showing a read operation accompanying on-chip valley search OVS in a program suspension period.

Fig. 12 is a timing diagram showing a cache read operation accompanying an on-chip valley search OVS in a program suspension period.

Fig. 13 is a waveform diagram illustrating a method of configuring the combined sensing node c_so in the second sensing part of fig. 12.

Fig. 14A and 14B are waveform diagrams showing a data movement process of the page buffer unit PBU3a according to at least one embodiment of the present invention.

Fig. 15 is a cross-sectional view schematically showing a COP structure of a nonvolatile memory device according to at least one embodiment of the present invention.

Detailed Description

It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide additional description of the invention claimed. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Reference numerals are indicated in the exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used throughout the description and the drawings to refer to the same or like parts. Unless indicated otherwise, the functional elements in the following description and corresponding blocks shown in the figures may be implemented in processing circuitry (such as hardware, software, or a combination thereof) configured to perform specific functions. For example, the processing circuitry may more particularly include electronic components such as at least one of transistors, resistors, capacitors, etc., AND/OR may include electronic components such as logic gates including at least one of AND (AND) gates, OR (OR) gates, NOR (NOR) gates, NAND (NAND) gates, NOT (NOT) gates, exclusive OR (XOR) gates, etc.

Spatially relative terms, such as "horizontal," "vertical," "above … …," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or elements or feature or features as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, the device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1 is a block diagram illustrating a non-volatile memory device in accordance with at least one embodiment of the present invention. Referring to fig. 1, the nonvolatile memory device 100 may include a cell array 110, a row decoder 120, a page buffer circuit 130, a control circuit 140, and a voltage generator 150.

The cell array 110 is connected to the row decoder 120 through word lines WL and through select lines SSL and GSL. The cell array 110 is connected to the page buffer circuit 130 through a bit line BL. In at least one embodiment, the cell array 110 may include a plurality of NAND cell strings. The channel of each cell string may be formed in a vertical direction or a horizontal direction. The cell array 110 of the present invention may include a plurality of memory cells forming a cell string. Multiple memory cells may be programmed, erased and/or sensed by voltages applied to the bit lines BL or word lines WL. The program operation may be performed in units of pages, and the erase operation may be performed in units of blocks BLK0 to BLKi (e.g., i is a positive integer) shown.

In at least one embodiment of the present invention, the cell array 110 may be provided as a three-dimensional memory array. For example, a three-dimensional memory array may be integrally formed on one or more physical levels (physical levels) of an array of memory cells having active areas disposed over a silicon substrate and circuitry associated with operation of the memory cells. The circuitry involved in the operation of the memory cell may be located in or on the substrate. The term "integral" refers to the layers of each level of the three-dimensional array being deposited directly on the layers of the lower level of the three-dimensional array.

In at least one embodiment of the invention, the 3D memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on another memory cell. At least one memory cell includes a charge trapping layer. Each vertical NAND string can include at least one select transistor located above a memory cell. The at least one selection transistor may have the same structure as the memory cell, and may be integrally formed with the memory cell.

Such a construction is disclosed in the following patents incorporated herein by reference, in which a three-dimensional memory array may be composed of multiple levels, with word lines or bit lines shared between the levels, and is applicable to three-dimensional memory arrays: us patent No. 7,679,133, us patent No. 8,553,466, us patent No. 8,654,587, us patent No. 8,559,235 and us patent publication No. 2011/023648.

The row decoder 120 may select one of the memory blocks of the cell array 110 in response to the address ADDR. The row decoder 120 may select one of the word lines of the selected memory block in response to the address ADDR. The row decoder 120 transfers the voltage VWL corresponding to the operation mode to the word line of the selected memory block. During a program operation, the row decoder 120 transfers the program voltage Vpgm and the verify voltage Vfy to the selected word line, and transfers the pass voltage Vpass to the unselected word lines. During a read operation, the row decoder 120 transfers a read voltage (or referred to as a select read voltage) Vrd to a selected word line and a read pass voltage (or referred to as a non-select read voltage) Vread to unselected word lines.

The page buffer circuit 130 operates as a write driver or a sense amplifier. For example, during a program operation, the page buffer circuit 130 transfers a bit line voltage corresponding to data to be programmed to the bit line BL of the cell array 110; and during a read operation or a verify read operation, the page buffer circuit 130 senses data stored in the selected memory cell through the bit line BL.

Each of the plurality of page buffers PB0 to PBn-1 (e.g., n may be an integer greater than 1) may perform sensing and data latching functions for performing an on-chip valley search (hereinafter, OVS) (or referred to as on-chip valley search read or on-chip valley search sense) operation. That is, each of the plurality of page buffers PB0 through PBn-1 may perform an OVS read operation using a different read voltage (and/or bit line development time) under the control of the on-chip valley search OVS circuit 145 to identify an optimal read level. Further, the plurality of page buffers PB0 to PBn-1 may perform fine sensing (fine sensing) for the corresponding memory cells based on an optimal read voltage (and/or bit line development time) determined according to a result of the OVS read operation.

Each of the plurality of page buffers PB0 to PBn-1 includes a page buffer unit PBU and a cache unit CU. The page buffer units (e.g., PBU0 to PBUn-1 in fig. 4) and the cache units (e.g., CU0 to CUn-1 in fig. 4) included in the plurality of page buffers PB0 to PBn-1 may have separate structures (e.g., may be spaced apart from each other). The sensing node SO of each of the plurality of page buffers PB0 to PBn-1 may be commonly connected to the common sensing node SOC. Furthermore, the cache units CU0 through CUn-1 may be commonly connected to a common sense node SOC. Accordingly, the plurality of page buffer units PBU0 to PBUn-1 may be connected to the cache units CU0 to CUn-1 through the common sense node SOC. Based on this structure, the degree of freedom of wiring provided on the page buffer units PBU0 to PBUn-1 can be increased, and the complexity of layout can be reduced. Further, the cache units CU0 to CUn-1 are disposed adjacent to the data input/output line, so that a distance between a cache latch (hereinafter, CL) and the data input/output line is reduced, thereby improving the data input/output speed. The sensing operation, the latching operation, and the selecting operation of the plurality of page buffers PB0 to PBn-1 will be described in example embodiments with reference to drawings to be described later.

Each of the page buffer units PBU0 to PBUn-1 included in the plurality of page buffers PB0 to PBn-1 may include a pair of transfer transistors (e.g., pt_u and pt_d in fig. 5) and a sensing node SO line for connecting the pair of transfer transistors to each other. In this case, the sensing node line may be implemented as one track (track) of the lower metal layer, and may correspond to the sensing node SO. During the data sensing period, the transfer transistors pt_u and pt_d respectively included in the plurality of page buffer units may be electrically disconnected from each other. Accordingly, the sensing node lines of each of the plurality of page buffer units may be electrically cut off from each other. On the other hand, during the data transfer period, the transfer transistors pt_u and pt_d included in the plurality of page buffer units may be turned on. Accordingly, the sensing node lines included in each of the plurality of page buffer units are electrically connected to each other, and thus may be used as data lines. Hereinafter, the structure of such a sensing node line will be referred to as a combined sensing node (c_so).

Further, even during a cache read operation performed in a program suspension period, the page buffer circuit 130 of the present invention may perform a Full on-chip valley search (Full OVS) on stored data. Program suspension is performed, for example, by a program suspension command for suspending a program operation to one memory block and accessing another memory block. During a program pause, the data latches of page buffers PB0 through PBn-1 are occupied by the write data of the previous program operation. Further, when a cache read command is provided during a program suspension period, the cache read data occupies a cache latch (C-latch, hereinafter, CL) of each of the page buffers PB0 to PBn-1. Thus, performing a Full on-chip valley search (Full OVS) for two or more program states with only one sense latch (S-latch, hereinafter SL) is generally not feasible.

In contrast, in at least one embodiment of the present invention, the sense node SO lines of the page buffer units that are not being subjected to the on-chip valley search are combined to form a combined sense node C_SO. The combined sense node c_so may be used as a storage device for a data dump (dump). Thus, the page buffer circuit 130 of the present invention may support Full on-chip valley searches (Full OVS) in cache read operations performed during a program suspension period without additional latches.

The control circuit 140 controls the page buffer circuit 130, the row decoder 120, and the voltage generator 150 in response to, for example, a command CMD transmitted from the outside. The control circuit 140 may control the voltage generator 150, the page buffer circuit 130, and/or the row decoder 120 to perform a program operation, a read operation, and/or an erase operation on the selected memory cells according to the command CMD. The control circuit 140 may send the address ADDR to the row decoder 120 and/or may provide the voltage control signal vtg_c to the voltage generator 150. In at least one example, the control circuit 140 may include an OVS circuit 145 for performing on-chip valley search OVS operations. The control circuit 140 may control the pass transistors pt_u and pt_d of each of the plurality of page buffer units to perform a Full on-chip valley search (Full OVS) in a cache read operation performed in the program suspension period. For example, the control circuit 140 may generate a transmission control signal (so_pass < i >, i being an integer) or a common transmission control signal (soc_pass < j >, j being an integer) for forming the combined sensing node c_so.

The voltage generator 150 generates various types of word line voltages VWL to be supplied to the corresponding word lines and voltages to be supplied to a bulk (e.g., well region) where memory cells are formed under the control of the control circuit 140. The word line voltages to be supplied to the corresponding word lines include a program voltage Vpgm, a pass voltage Vpass, a select read voltage Vrd, and a non-select read voltage Vread.

Although not shown, the nonvolatile memory device 100 may further include components such as an input/output buffer (I/O buffer) and a Mass Bit Counter (MBC) below. The nonvolatile memory device 100 according to the present invention forms a combined sensing node c_so using the sensing nodes of the page buffer units on which the on-chip valley search OVS is not performed. The non-volatile memory device 100 may then store the data to the combined sense node c_so. Thus, the page buffer circuit 130 of the present invention may perform a Full on-chip valley search (Full OVS) without additional latches, even during a cache read operation, where the use of cache latches is not generally possible during a program pause period. Thus, according to the present invention, it is possible to realize the nonvolatile memory device 100 having high data reliability regardless of the operation mode.

Fig. 2 schematically illustrates a structure of the non-volatile memory device of fig. 1 in accordance with at least one embodiment of the present disclosure. Referring to fig. 2, the nonvolatile memory device 100 may include a first semiconductor layer L1 and a second semiconductor layer L2, wherein the first semiconductor layer L1 may be stacked in a Vertical Direction (VD) perpendicular to the second semiconductor layer L2. Specifically, the second semiconductor layer L2 may be disposed below with respect to the first semiconductor layer L1 in the vertical direction VD, and thus, the second semiconductor layer L2 may be disposed close to the substrate.

In one embodiment, the cell array 110 of fig. 1 may be formed on the first semiconductor layer L1, and peripheral circuits corresponding to the row decoder 120, the page buffer circuit 130, the control circuit 140, and the voltage generator 150 of fig. 1 may be formed in the second semiconductor layer L2. Accordingly, the nonvolatile memory device 100 may have a structure in which the cell array 110 is disposed on the peripheral circuits 120, 130, 140, and 150. This structure may be referred to as a COP (on-peripheral-unit) structure. The COP structure can effectively reduce the horizontal area and improve the integration of the nonvolatile memory device 100.

In at least one embodiment, the second semiconductor layer L2 may include a substrate, and the peripheral circuits 120, 130, 140, and 150 may be formed in the second semiconductor layer L2 by forming transistors and metal patterns for wiring the transistors on the substrate. After the peripheral circuits 120, 130, 140, and 150 are formed on the second semiconductor layer L2, the first semiconductor layer L1 including the cell array 110 may be formed, and a metal pattern for electrically connecting the word line WL and the bit line BL to the peripheral circuits 120, 130, 140, and 150 formed in the second semiconductor layer L2 may be formed. For example, the bit line BL may extend in the first horizontal direction HD1, and the word line WL may extend in the second horizontal direction HD 2.

As the semiconductor process progresses, since the number of levels of memory cells disposed in the cell array 110 increases (for example, since the number of stacked word lines WL increases), the area of the cell array 110 decreases, and thus the areas of the peripheral circuits 120, 130, 140, and 150 are also reduced. Specifically, the nonvolatile memory device 100 stores data of the page buffer unit on which the on-chip valley search OVS is not performed using the combined sensing node c_so. Thus, the non-volatile memory device 100 of the present invention may perform a Full OVS (Full OVS) in the program suspension period without additional latches or area increase.

Fig. 3 is a circuit diagram showing an example structure of a memory block constituting the cell array of fig. 2. Referring to fig. 3, a cell string (or referred to as a NAND cell string or NAND string) NS is formed between bit lines BL0, BL1, BL2, and BL3 and a common source line CSL to form a memory block BLK. For example, the cell string NS may be formed in a vertical direction perpendicular to the substrate SUB. For example, one of the cell strings (e.g., NS0, NS1, NS2, … … of fig. 4) may be formed between one of the bit lines (e.g., BL0, BL1, BL2, … …) and the common source line.

For example, a cell string may be formed between the bit line BL0 and the common source line CSL. For uniformity, the cell strings formed between the bit line BL0 and the common source line CSL may be referred to as cell strings NS10, NS20, … …, but are not so shown in the drawings for clarity of illustration. The plurality of cell strings NS11, NS21, NS12, NS22, NS13, and NS23 are also formed between the bit lines BL1, BL2, and BL3 and the common source line CSL in the same manner. Each cell string may also be connected to a respective string selection line SSL0, SSL1, SSL2, SLL3, etc. by at least one respective string selection transistor SST. The string selection transistor SST of the cell string NS may be connected to a corresponding bit line BL. The ground selection transistor GST of the cell string NS may be connected to the common source line CSL. The memory cell MC is disposed between the string selection transistor SST and the ground selection transistor GST of the cell string NS.

Each cell string NS includes a ground selection transistor GST. The ground selection transistor included in the cell string NS may be controlled by a ground selection line GSL. Alternatively, although not shown, the cell strings corresponding to each row may be controlled by different ground selection lines (e.g., GSL0, GSL1, GSL2, GSL3, etc.).

The circuit configuration of the memory cells included in one memory block BLK has been briefly described above. However, for convenience of description, the circuit structure of the illustrated memory block is only a simplified structure, and the actual memory block is not limited to the illustrated example. That is, it will be well understood that more semiconductor layers, bit lines BL, and string select lines SSL may be included in one physical block.

Fig. 4 is a diagram showing a connection between the cell array and the page buffer circuit. Referring to fig. 4, the cell array 110 may include a plurality of NAND cell strings NS0 to NSn-1. Further, the page buffer circuit 130 may include a plurality of page buffer units PBU0 to PBUn-1 and a plurality of cache units CU0 to CUn-1.

Each of the plurality of NAND cell strings NS0 to NSn-1 may include a ground selection transistor GST connected to a ground selection line GSL, a plurality of memory cells MC connected to word lines WL <0> to WL < m-1>, and a string selection transistor SST connected to a string selection line SSL. The ground selection transistor GST, the plurality of memory cells MC, and the string selection transistor SST may be connected in series with each other. Here, "m" is a positive integer.

The page buffer circuit 130 may include a plurality of page buffer units PBU0 to PBUn-1. The first page buffer unit PBU0 is connected to the first NAND string NS0 through a first bit line BL0, and the nth page buffer unit PBUn-1 is connected to the nth NAND string NSn-1 through an nth bit line BLn-1. Here, "n" is a positive integer. For example, "n" may be 8, and the page buffer circuit 130 may have a structure in which a plurality of page buffer units (e.g., PBU0 to PBU 7) are arranged on one line. Alternatively, in the page buffer circuit 130, the page buffer units PBU0 to PBU3 and the page buffer units PBU4 to PBU7 arranged in a row are symmetrically arranged with respect to the page buffer decoder.

For example, the plurality of page buffer units PBU0 to PBUn-1 may be arranged on one line along the extending direction of the first to nth bit lines BL0 to BLn-1. The page buffer circuit 130 may further include a plurality of cache units CU0 to CUn-1 corresponding to the plurality of page buffer units PBU0 to PBUn-1, respectively. For example, when "n" is 8, the page buffer circuit 130 may have a structure in which eight cache units CL0 to CL7 are arranged in a row. For example, the plurality of cache units CU0 to CUn-1 may be arranged on one line along the extending direction of the first to nth bit lines BL0 to BLn-1. The sensing node SO of each of the plurality of page buffer units PBU0 to PBUn-1 may be commonly connected to the common sensing node SOC. Further, the plurality of cache units CU0 through CUn-1 may be commonly connected to a common sense node SOC. Accordingly, the plurality of page buffer units PBU0 to PBUn-1 may be connected to the plurality of cache units CU0 to CUn-1 through the common sense node SOC.

In the page buffer circuit 130 having the above structure, each of the plurality of page buffer units PBU0 to PBUn-1 may include transfer transistors pt_u and pt_d (see fig. 5) that may connect the sensing node SO to an adjacent sensing node. Further, the pass transistors pt_u and pt_d may be connected in series with each other, and thus, the sensing nodes included in each of the plurality of page buffer units PBU0 to PBUn-1 may be electrically connected to each other, thereby having a capacity for storing data. As mentioned above, the sense node to which one or more sense nodes of the plurality of page buffer units PBU0 to PBUn-1 are connected is referred to as a combined sense node c_so.

Further, when a cache read operation is being performed in any one of the plurality of page buffer units PBU0 to PBUn-1, data for the cache read operation is stored in a cache latch included in the corresponding cache unit. At this time, by connecting the sensing nodes SO of the unused page buffer units among the plurality of page buffer units PBU0 to PBUn-1, a combined sensing node c_so having an appropriate capacity may be formed. The combined sensing node c_so may be used as a storage medium for a Full on-chip valley search (Full OVS). The connection of the sensing nodes and the formation of the combined sensing node c_so may be achieved by control of pass transistors pt_u and pt_d. These features will be described in detail with reference to the following drawings.

Fig. 5 is a circuit diagram showing a page buffer unit and a cache unit constituting a page buffer. Referring to fig. 5, the page buffer PB may include a page buffer unit PBU and a cache unit CU. The cache unit CU comprises a cache latch CL. Since the cache latch CL is connected to the data input/output line, the cache unit CU may be disposed adjacent to the data input/output line. Accordingly, the page buffer unit PBU and the cache unit CU may be disposed to be spaced apart from each other, and the page buffer PB may have separate structures of the page buffer unit PBU and the cache unit CU.

The page buffer unit PBU may include a bit line selection transistor tr_hv connected to the bit line BL and driven by a bit line selection signal BLSLT. The bit line selection transistor tr_hv may be implemented as a high voltage transistor, and thus, the bit line selection transistor tr_hv may be disposed in a high voltage region.

The page buffer unit PBU includes a sense latch (hereinafter, SL), a force latch (hereinafter, FL), a Most Significant Bit (MSB) latch (hereinafter, ML), and a Least Significant Bit (LSB) latch (hereinafter, LL). During a programming operation, data to be programmed is stored in the MSB latch ML, the LSB latch LL, and the cache latch CL. On the other hand, in the program suspension period, data to be programmed is stored in the MSB latch ML, the LSB latch LL, and the forced latch FL.

The sense latch SL may store the data stored in the memory cell and/or the sensing result of the threshold voltage of the memory cell during a read or program verify operation. Further, the sense latch SL may be used to apply a program bit line voltage and/or a program inhibit voltage to the bit line BL during a program operation. In one example, the sense latch SL may receive a SET signal s_set and a reset signal s_rst. The forced latch FL may be used as a bit line biasing device for improving threshold voltage distribution during a programming operation. MSB latch ML, LSB latch LL, and cache latch CL may be used to store data input from the outside during a program operation.

The page buffer unit PBU may further include a Precharge (PRCH) circuit PC capable of controlling a precharge operation on the bit line BL or the sense node SO based on the bit line clamp control signal (bit line clamping control signal) BLCLAMP. The page buffer unit PBU may further include a transistor PM1 driven by a bit line set signal BLSETUP.

The page buffer unit PBU may include first to fourth transistors NM1 to NM4. The first transistor NM1 may connect the sensing latch SL and the sensing node SO in response to the ground control signal SOGND. The second transistor NM2 may connect the forced latch FL and the sensing node SO in response to the forced monitoring signal mon_f. The third transistor NM3 may connect the MSB latch ML and the sensing node SO in response to the high-order monitor signal mon_m. The fourth transistor NM4 may connect the LSB latch LL and the sense node SO in response to the low monitoring signal mon_l.

The page buffer unit PBU may further include a fifth transistor NM5 and a sixth transistor NM6 connected in series between the bit line selection transistor tv_hv and the sensing node SO. The fifth transistor NM5 may be driven by a bit line off signal BLSHF, and the sixth transistor NM6 may be driven by a bit line connection control signal CLBLK. In addition, the page buffer unit PBU may further include a precharge transistor PM2. The precharge transistor PM2 is connected to the sensing node SO and may be driven by a LOAD signal LOAD.

For example, the page buffer unit PBU may further include a pair of transmission transistors pt_u and pt_d connected to the sensing node SO. The PASS transistors pt_u and pt_d may be driven according to the PASS control signal so_pass. The first pass transistor pt_u may be connected between the first terminal soc_u and the sensing node SO, and the second pass transistor pt_d may be connected between the sensing node SO and the second terminal soc_d. The PASS transistors pt_u and pt_d may connect or disconnect the sensing node SO with the sensing node SO 'of the other page buffer unit PBU' in response to the PASS control signal so_pass. The sense nodes SO ', SO "that the pass transistors pt_u and pt_d are arranged in pairs to be connected to the adjacent page buffer units PBU' and PBU", respectively, have been described. However, it will be appreciated that a single pass transistor PT may be configured to connect the sense node SO to the sense node SO 'of the adjacent page buffer unit PBU'.

Here, the page buffer unit PBU may connect one or more sensing nodes SO to form a combined sensing node c_so, and store data based on the capacity provided by the combined sensing node c_so. For example, when any one of the plurality of page buffer units PBU performs the on-chip valley search OVS, the remaining unused page buffer units PBU may be connected by the transmission control signal so_pass to form the combined sensing node c_so. Further, the data of the sensing latch SL sensed for the on-chip valley search OVS may be temporarily stored in the combined sensing node c_so. And when the on-chip valley search OVS is terminated, the data of the combined sense node c_so may be restored to the sense latch SL again. This operation may be particularly useful in the page buffer circuit 130, where the page buffer circuit 130 performs a cache read operation accompanied by an on-chip valley search OVS during a program suspension period. If a technique using such a combined sense node (c_so) is used, an on-chip valley search OVS of all data states may be performed even during a cache read operation in a program suspension period. In one example, the cache unit CU may further include a seventh transistor NM7, and the seventh transistor NM7 may connect the cache latch CL and the common sensing node SOC in response to the signal mon_c.

Fig. 6 is a diagram illustrating an arrangement of a page buffer circuit according to at least one embodiment of the present invention. Referring to fig. 6, the page buffer circuit 130 includes a plurality of page buffer columns including a first page buffer column 130a and a second page buffer column 130b disposed along the second horizontal direction HD 2. Each of the plurality of page buffer columns 130a and 130b may include a plurality of page buffers arranged in a multi-stage structure.

The first page buffer column 130a may include page buffer units PBU0a to PBU7a, cache units CU0a to CU7a, and a Page Buffer Decoder (PBDEC) 132. Specifically, the first page buffer column 130a includes page buffer units PBU0a to PBU7a and cache units CU0a to CU7a symmetrically arranged with respect to the page buffer decoder 132. That is, the first to fourth page buffer units PBU0a to PBU3a and the fifth to eighth page buffer units PBU4a to PBU7a may be symmetrically arranged with respect to the page buffer decoder 132. Further, the first to fourth cache units CU0a to CU3a may be symmetrically arranged with respect to the fifth to eighth cache units CU4a to CU7a with respect to the page buffer decoder 132.

The second page buffer column 130b may include page buffer units PBU0b to PBU7b, cache units CU0b to CU7b, and a page buffer decoder 132. For example, the second page buffer column 130b further includes page buffer units PBU0b to PBU7b and cache units CU0b to CU7b symmetrically arranged with respect to the page buffer decoder 132.

Each of the first page buffer column 130a and the second page buffer column 130b may be symmetrically disposed with respect to the page buffer decoder 132. For example, each of the first page buffer column 130a and the second page buffer column 130b may be divided into an upper page buffer 131 and a lower page buffer 133 based on the page buffer decoder 132. The configuration or function of each of the upper page buffer 131 and the lower page buffer 133 is substantially the same. That is, the description of the operation of the upper page buffer 131 is the same as and/or substantially equally applied to the operation of the lower page buffer 133.

Each of the page buffer units PBU0a to PBU7a and PBU0b to PBU7b may be implemented to be identical and/or substantially similar to the page buffer unit PBU of fig. 5, and each of the cache units CU0a to CU7a and CU0b to CU7b may be implemented to be substantially similar to the cache unit CU of fig. 5.

Here, an example in which each of the first page buffer column 130a and the second page buffer column 130b is symmetrically arranged with respect to the page buffer decoder 132 has been described, but the present invention is not limited thereto. For example, the page buffer decoder 132 may be disposed below in the first horizontal direction HD1, and the cache units CU0a to CU7a and CU0b to CU7b may be sequentially disposed above the page buffer decoder 132, and the page buffer units PBU0a to PBU7a and PBU0b to PBU7b may be disposed above the cache units CU0a to CU7a and CU0b to CU7 b.

Hereinafter, the configuration of the upper page buffer 131 and the page buffer decoder 132 will be described. For example, these descriptions may be equally applied to the lower page buffer 133.

Fig. 7 is a circuit diagram schematically illustrating some configurations of the upper page buffer and page buffer decoder of fig. 6. Referring to fig. 7, the page buffer circuit 130 may include an upper page buffer 131 and a page buffer decoder 132.

The upper page buffer 131 includes a plurality of page buffer cells (e.g., PBU0a, PBU1a, PBU2a, and PBU3 a) included in the first page buffer column PGBUFa and a plurality of page buffer cells (e.g., PBU0b, PBU1b, PBU2b, and PBU3 b) included in the second page buffer column PGBUFb. In the page buffer units arranged in the same row, the sensing nodes SO may be connected to or blocked from the sensing nodes SO of the adjacent page buffer units by the same transmission control signal so_pass < i >, where "i" is an integer.

The page buffer unit PBU0a may include transfer transistors pt0a_u and pt0a_d connected in series, and the page buffer unit PBU0b may include transfer transistors pt0b_u and pt0b_d connected in series. The PASS control signal so_pass <0> may be applied to the gates of PASS transistors pt0a_ U, PT a_ D, PT b_u and pt0b_d. When the transmission control signal so_pass <0> is activated, the sensing node SO0a of the page buffer unit PBU0a and the sensing node SO0b of the page buffer unit PBU0b may be connected to adjacent sensing nodes in the same column. Similarly, the transfer control signal so_pass <1> is supplied to the gates of the transfer transistors pt1a_ U, PT a_ D, PT b_u and pt1b_d of the page buffer units PBU1a and PBU1 b. The transfer control signal so_pass <2> is supplied to the gates of the transfer transistors pt2a_ U, PT2a_ D, PT2b_u and pt2b_d of the page buffer units PBU2a and PBU2 b.

The transfer control signal so_pass <3> is supplied to the gates of the upper transfer transistors pt3a_u and pt3b_u of the page buffer units PBU3a and PBU3 b. On the other hand, the common transfer control signal soc_pass <0> is supplied to the gates of the lower transfer transistors pt3a_d and pt3b_d of the page buffer units PBU3a and PBU3 b.

If the PASS control signals SO_PASS <0> to SO_PASS <3> are activated, PASS transistors PT0a_ U, PT0a_ D, PT1a_ U, PT1a_ D, PT2a_ U, PT2a_ D, PT3a_ U, PT0b_ U, PT0 35 b_ D, PT1b_ U, PT1b_ D, PT2b_ U, PT2b_ D, PT3b_U are turned on. Then, the sensing nodes SO0a, SO1a, SO2a, and SO3a of the page buffer units PBU0a, PBU1a, PBU2a, and PBU3a of the same column are electrically connected. The combined sense node c_ SOa is formed according to the connection of the sense nodes SO0a, SO1a, SO2a, and SO3 a. And when the transmission control signals so_pass <0> to so_pass <3> are activated, the sensing nodes SO0b, SO1b, SO2b, SO3b of the page buffer units PBU0b, PBU1b, PBU2b, and PBU3b arranged in the same column are also electrically connected. Thus, the combined sensing node c_sob is also formed.

When the transmission control signals so_pass <0> to so_pass <3> are deactivated, the sensing nodes SO0a, SO1a, SO2a, SO3a and the sensing nodes SO0b, SO1b, SO2b, SO3b are electrically disconnected from each other. Accordingly, the combined sensing node c_ SOa is divided into the sensing nodes SO0a, SO1a, SO2a, SO3a of the page buffer units PBU0a, PBU1a, PBU2a, and PBU3a, respectively, and the combined sensing node c_sob is also divided into the sensing nodes SO0b, SO1b, SO2b, and SO3b of the page buffer units PBU0b, PBU1b, PBU2b, and PBU 3b.

In addition, when the transfer control signals so_pass <0> to so_pass <3> and the common transfer control signal soc_pass <0> are activated, the lower transfer transistors pt3a_d and pt3b_d of the page buffer units PBU3a and PBU3b are turned on. In addition, the combined sensing nodes c_ SOa and c_sob are electrically connected to the common sensing nodes SOCa and SOCb, respectively. On the other hand, when the common transmission control signal soc_pass <0> is deactivated, the lower transmission transistors pt3a_d and pt3b_d of the page buffer units PBU3a and PBU3b are turned off, and the combined sensing nodes c_ SOa and c_sob are electrically isolated from the common sensing nodes SOCa and SOCb, respectively.

The page buffer units PBU0a to PBU3a may further include precharge transistors PM0a to PM3a. In the page buffer unit PBU0a, the precharge transistor PM0a may be connected between the first sensing node SO0a and a voltage terminal to which a precharge voltage is applied, and may have a gate to which a LOAD signal LOAD is applied. The precharge transistor PM0a may precharge the first sensing node SO0a with a precharge voltage in response to the LOAD signal LOAD. In addition, the page buffer units PBU0b to PBU3b may further include precharge transistors PM0b to PM3b.

The first cache unit CU0a may include a monitor transistor nm7a_0, e.g., the monitor transistor nm7a_0 may correspond to the transistor NM7 of fig. 5. The source S of the monitor transistor nm7a_0 may be connected to the first common sense node SOCa, and the cache monitor signal mon_c <0> may be applied to the gate of the monitor transistor nm7a_0. The monitoring transistors nm7a_0 to nm7a_3 included in the first to fourth cache units CU0a to CU3a may be commonly connected in parallel to the first common sensing node SOCa. For example, the source of each of the monitoring transistors nm7a_0 to nm7a_3 may be commonly connected to the first common sensing node SOCa. In addition, the cache monitor signals mon_c <0> to mon_c <3> may be applied to the gates of the monitor transistors nm7b_0 to nm7b_3 included in the cache units CU0b to CU3 b.

The precharge circuits soc_prea and soc_prep may be included between the page buffer units PBU3a and PUB3b of the upper page buffer 131 and the first cache units CU0a and CU0 b. The precharge circuit soc_prea may include a precharge transistor PMa and a shield transistor NMa for precharging the first common sensing node SOCa. The precharge transistor PMa may be driven by a common sense node LOAD signal load_soc. The shield transistor NMa can be driven by a common sense node shield signal shld_soc. Similarly, the precharge circuit soc_preb may include a precharge transistor PMb and a masking transistor NMb for precharging the second common sensing node SOCb. The precharge transistor PMb may be driven by a common sense node LOAD signal load_soc. The mask transistor NMb may be driven by a common sense node mask signal shld_soc.

The page buffer decoder 132 may be disposed adjacent to the upper page buffer 131 in the first horizontal direction HD1, and the page buffer decoders PBDECa and PBDECb may be disposed along the second horizontal direction HD 2. The page buffer decoders PBDECa and PBDECb may be connected to the first page buffer column PGBUFa and the second page buffer column PGBUFb, respectively. For example, the first page buffer decoder PBDECa may generate a decoder output signal according to a sensing result stored in the sensing latch SL of the first page buffer unit PBU0a included in the first page buffer column PGBUFa.

The first page buffer decoder PBDECa may include an inverter INVa and transistors NOa, NOa 'and noa″ connected in series, and the second page buffer decoder PBDECb includes an inverter INVb and transistors NOb, NOb' and NOb ″ connected in series. The inverter ina receives the first page buffer signal PBSa from the first page buffer column PGBUFa, and the reference current signal ref_curr is applied to the gate of the transistor NOa ". The inverter INVb receives the second page buffer signal PBSb from the second page buffer column PGBUFb and the reference current signal ref_curr is applied to the gate of the transistor NOb ".

For example, the first and second page buffer decoders PBDECa and PBDECb may receive the first and second page buffer signals PBSa and PBSb from the page buffer units PBU0a and PBU0b, respectively. For example, when logic "0" is stored in the sensing latch SL of the page buffer unit PBU0a, the voltage levels of the first sensing node SO0a and the first common sensing node SOCa may be referred to as logic low, and the first page buffer signal PBSa may correspond to a logic low voltage level of the first sensing node SO0 a. In this case, the inverter ina outputs a logic high signal, and thus the transistor NOa is turned on, and the first page buffer decoder PBDECa may operate as a current sink (current sink).

The transistor noa″ may output a first signal (e.g., a reference current) to a wired OR (OR) terminal wor_out based on the reference current signal ref_curr. Here, the reference current is a current flowing in the transistor noa″ when the transistor noa″ is turned on according to the reference current signal ref_curr. Similarly, the transistor NOb "can output a second signal (i.e., a reference current) to the wired OR terminal wor_out based on the reference current signal ref_curr. The wired OR terminal wor_out may be commonly connected to the first and second page buffer decoders PBDECa and PBDECb, and thus, the first and second signals output from the first and second page buffer decoders PBDECa and PBDECb may be accumulated in the wired OR terminal wor_out to be generated as an output signal. For example, the output signal may correspond to a current signal flowing through the wired OR terminal wor_out.

Fig. 8 is a diagram schematically illustrating sensing nodes of page buffer units performing on-chip valley search OVS sensing and nodes of remaining page buffer units among the upper page buffer of fig. 7.

Referring to fig. 8, when the page buffer unit 137 performs the on-chip valley search OVS, the combined sensing nodes c_ SOa and c_sob of the unselected page buffer units 135 may be used to store data of the sensing latches SLa, SLb. Here, a plurality of page buffer cells included in each of the first and second page buffer columns PGBUFa and PGBUFb are shown. For convenience of description, features of the present invention will be described by configurations and functions of the page buffer units PBU0a to PBU3a included in the first page buffer column PGBUFa forming the combined sensing node c_ SOa. Of course, it will be well understood that the description is equally applicable to the page buffer units PBU0b to PBU3b included in the second page buffer column PGBUFb forming the combined sense node c_sob.

Further, for convenience of description, the features of the present invention will be described by performing on-chip valley search OVS on the memory cells through the bit lines BL based on the page buffer unit PBU3 a; then, the remaining three unselected page buffer units PBU0a, PBU1a, and PBU2a do not perform a separate sensing operation or writing operation. Thus, the sensing nodes SO0a, SO1a, and SO2a of the remaining three unselected page buffer units PBU0a, PBU1a, and PBU2a may constitute a combined sensing node c_ SOa. Further, the combined sense node c_ SOa can be used as a storage device for performing a Full on-chip valley search (Full OVS) for multiple program states in the sense latch SLa of the page buffer unit PBU3 a. An example in which the data stored in the sensing latch SLa is dumped to the sensing nodes SO0a, SO1a, and SO2a of the three unselected page buffer units PBU0a, PBU1a, and PBU2a is shown in fig. 8, but the example is not limited thereto, and the data stored in the sensing latch may be dumped to the sensing node of one unselected page buffer unit or the sensing nodes of at least two unselected page buffer units.

For example, the page buffer unit PBU3a may perform on-chip valley search OVS reading on LSB page data of the selected memory cell. The fine sensing operation for the corresponding memory cell may be performed with reference to the result of the previously performed on-chip valley search OVS for the first program state. Further, the data in the sense latch SLa stored as a result of the fine sensing may be dumped to the combined sense node c_ SOa for on-chip valley search OVS for the second program state. For this, the pass transistor pt3a_u of the page buffer unit PBU3a is turned on, and the data stored in the sensing latch SLa may be transferred to the combined sensing node c_ SOa. At this time, to construct the combined sensing node C_ SOa, the PASS control signal SO_PASS <3:0> is activated and the PASS transistors Pt0a_ U, PT0a_ D, PT1a_ U, PT a_ D, PT a_ U, PT a_D and Pt3a_U are turned on. In addition, the common PASS control signal soc_pass <0> is deactivated, and the PASS transistor pt3a_d maintains a blocking state. After the data is moved to the combined sense node C_ SOa, the PASS control signals SO_PASS <3:0> are deactivated, and then the PASS transistors PT0a_ U, PT a_ D, PT1a_ U, PT a_ D, PT a_ U, PT a_D and PT3a_U are turned off.

Thereafter, when the all on-chip valley search OVS of the page buffer unit PBU3a is terminated, the data temporarily stored in the combined sense node c_ SOa may be returned to the sense latch SLa of the page buffer unit PBU3 a. The data exchange between the sensing latch SLa and the combined sensing node C SOa will be described in more detail through a timing chart to be described later.

The structure for configuring the combined sensing nodes c_ SOa and c_sob in the page buffer units 135 and 137 is as follows. To configure the combined sense node c_ SOa, the sense node SO0a between the pass transistors pt0a_u and pt0a_d may be formed using a first metal layer (or referred to as a lower metal wire or lower metal line) LM 0. Similarly, the sensing node SO1a between the transfer transistors pt1a_u and pt1a_d, the sensing node SO2a between the transfer transistors pt2a_u and pt2a_d, and the sensing node SO3a between the transfer transistors pt3a_u and pt3a_d may be formed by using the first metal layer LM 0. In addition, the wirings of the high voltage regions HV <0>, HV <1>, HV <2> and HV <3> may be formed using a third metal layer (or referred to as an upper metal wiring or an upper metal line) LM 2. In addition, bit line pass-through holes BLTHV <0> disposed between high voltage regions HV <0> and HV <1>, and bit line pass-through holes BLTHV <1> disposed between high voltage regions HV <2> and HV <3>, may be formed using a second metal layer (otherwise referred to as an intermediate metal wire or intermediate metal line) LM1 and vias to provide electrical connection between the sense nodes SO0a, SO1a, SO2a, and SO3 a. As a result, the combined sensing node c_ SOa includes a plurality of metal layers LM0, LM1, and LM2, and provides a capacitance capable of exchanging data with the sensing latch SLa of the page buffer unit PBU3 a.

Fig. 9 is a flowchart illustrating an operation method using the combined sensing node c_so performed in the control circuit of fig. 1. Referring to fig. 1 and 9, the nonvolatile memory device 100 may perform a cache read operation in a program suspension period in a Full on-chip valley search (Full OVS) mode.

In step S110, the control circuit 140 detects a Program (PGM) suspension Command (CMD) PGM suspension CMD. The program suspension command PGM suspension CMD is a command for suspending a program operation for a specific memory block and performing an access (such as a cache read) to another memory block.

In step S120, the control circuit 140 determines whether the command CMD provided after the program suspension command PGM suspension CMD is a cache read command or an on-chip valley search OVS command. If the command CMD provided after the program pause command PGM Suspend CMD corresponds to the cache read, the process moves to step S130. On the other hand, when the command CMD provided after the program pause command PGM Suspend CMD is a normal on-chip valley search OVS command, the process moves to step S150.

In step S130, the control circuit 140 determines whether the cache read operation is accompanied by an on-chip valley search OVS. If the cache read operation is accompanied by an on-chip valley search OVS, the process moves to step S140. On the other hand, when the cache read operation is a normal cache read operation that does not accompany the on-chip valley search OVS, the process moves to step S160.

In step S140, the control circuit 140 activates the combined sensing node c_so of the page buffer during the cache read operation to perform the on-chip valley search OVS. For example, the control circuit 140 controls the page buffer circuit 130 to temporarily store the data stored in the sense latch SL in the combined sense node c_so (instead of the cache latch CL occupied by the cache read data). The activation of the combined sense node c_so eventually occurs in a cache read mode with an on-chip valley search OVS occurring in the program pause period.

In step S150, the control circuit 140 may perform a full on-chip valley search OVS using the combined sensing node c_so of the page buffer even during a cache read operation. For example, the fine sensing operation is performed based on the result of the on-chip valley search OVS performed on the first program state. The fine sensing data obtained according to the result of the fine sensing operation is stored in the sensing latch SL. Then, the control circuit 140 moves the fine sensing data from the sensing latch SL to the combined sensing node c_so. Then, on-chip valley search OVS for the second program state may be performed using empty sense latches SL according to the movement of the fine sense data. When the on-chip valley search OVS for the second program state is completed, the control circuit 140 may return the data stored in the combined sense node c_so to the sense latch SL.

In step S160, the control circuit 140 may combine the data returned from the combined sense node c_so to the sense latch SL and the fine sense data reflecting the on-chip valley search OVS for the second program state. Thereafter, when the data stored in the cache latch CL is output, the combined data may be transferred to the cache latch CL.

In the above, an example of the operation using the combined sensing node c_so performed in the control circuit 140 has been briefly described. However, it will be well understood that the mode of operation utilizing the combined sense node c_so may be used in various situations where the utilization of the cache latch CL is limited.

Fig. 10 is a diagram illustrating a read method for a specific page of memory cells according to an embodiment of the present invention. Referring to fig. 10, a method of reading a Least Significant Bit (LSB) page of a triple-layered cell (hereinafter, TLC) capable of storing 3-bit data per cell is shown. Further, for convenience of description, features of the present invention will be described based on the nonvolatile memory device 100 performing a cache read operation accompanied by an on-chip valley search OVS in a program suspension period. In fig. 10, E0 represents an erased state, P1 to P7 represent a programmed state, and the horizontal axis represents a threshold voltage Vth.

To read the least significant bit LSB page of the selected memory cell, a read voltage RD5 may be applied to the word line of the selected memory cell. Then, on-chip valley search OVS reading of the read voltage RD5 is performed. The on-chip valley search OVS may be performed by only one or some of the page buffers. The data latched according to the result of the on-chip valley search OVS is transferred to the wired OR terminal wor_out and used for the bit counting operation. The fine sensing is performed according to the read voltage RD5 of a level adjusted based on the result of the on-chip valley search OVS and the bit count. The fine sensing result is stored in the sensing latch SL of the page buffer unit PBU. The data sensed according to the adjusted read voltage RD5 will be referred to as first data.

Subsequently, the combined sensing node c_so of the unused page buffer units among the page buffer units PBU is activated by the control circuit 140. For example, the control circuit 140 moves the first data of the sensing latch SL sensed by the fine sensing to the combined sensing node c_so instead of the cache latch CL occupied by the cache read data. In addition, on-chip valley search OVS using read voltage RD1 and bit count may be performed using empty sense latches SL according to data movement. Thereafter, the first data stored in the combined sensing node c_so may be returned to the sensing latch SL again. The first data returned to the sensing latch SL and the second data sensed according to the adjusted read voltage RD1 are decoded and stored in the sensing latch SL.

In the above, the cache read operation of the on-chip valley search OVS accompanying the LSB page of the triple cell TLC has been described. However, the operation of performing the full on-chip valley search OVS using the combined sensing node c_so as a temporary storage may be equally applied to the center significant bit CSB page or the most significant bit MSB page.

Fig. 11 is a timing chart showing a read operation accompanying on-chip valley search OVS during a program suspension period. Referring to fig. 11, when the cache latch CL is empty, a Full on-chip valley search (Full OVS) may be performed using the cache latch CL.

At time T0, a page buffer for the on-chip valley search OVS is initialized. That is, the cache latch CL of the page buffer is reset (CL RST).

At time T1, a first Sensing 1st Sensing operation is started. For example, a read voltage RD5 is applied to the word line of the memory cell for sensing, and a precharge (BL PRCH) is performed on the bit line BL. The setting of the sense latch SL will also take place.

At time T2, the page buffer unit performs an on-chip valley search OVS using the read voltage RD 5. For on-chip valley search OVS, different levels of read voltages may be provided to the word lines of the selected memory cells. Alternatively, the data of the memory cell may be sensed by the sensing latch SL of the page buffer cell at different bit line development times for the same level of the read voltage RD 5.

At time T3, an on-chip valley search OVS check (OVS CHK) with a quality bit counter is performed using the result of the on-chip valley search OVS read. For example, the voltage corresponding to the valley may be determined by comparing data at different levels of the read voltage RD5, or the development time with the minimum error may be determined for the same level of the read voltage RD 5.

At time T4, a data read is performed that applies the result of the on-chip valley search OVS. First, the sense latch SL is reset (SL RST), and fine sensing is performed according to the read voltage RD5 adjusted based on the on-chip valley search OVS result or the adjusted development time. As a result of the fine sensing, first data (RD 5 data) is stored in the sense latch SL.

At time T5, the first data stored in the sense latch SL moves to the cache latch CL. To this end, the sense node SO is precharged, and at time T6, data corresponding to the first data stored in the sense latch SL is moved to the cache latch CL via the sense node SO.

At time T7, on-chip valley search OVS is performed with read voltage RD1 using the sense latch SL of the page buffer unit. The on-chip valley search OVS may be provided with different levels of the read voltage RD1. Alternatively, the data of the memory cell may be sensed according to different bit line development times under the same level of the read voltage RD1. Then, on-chip valley search OVS check is performed using the result of on-chip valley search OVS reading.

At time T8, a data read is performed that applies the result of the on-chip valley search OVS read. For example, first, the sense latch SL is reset, and fine sensing is performed according to the read voltage RD1 adjusted based on the on-chip valley search OVS result and/or the adjusted development time. As a result of the fine sensing, second data (RD 1 data) is stored in the sensing latch SL.

At time T9, the second data latched in the sense latch SL may be transferred to the cache latch CL for output.

According to the above timing diagram, since the cache latch CL is empty during a normal read operation, it is possible to move the data of the sense latch SL to the cache latch CL. Therefore, it is possible to perform a full on-chip valley search OVS even during the read target state using the sense latch SL. In fig. 11, symbol EOS may represent even odd sensing (even odd sensing), which is a sensing function of sensing precharged bit lines in the upper page buffer 131 (see fig. 6) and the lower page buffer 133 (see fig. 6), respectively. For example, even odd sensing may occur on both sides of the page buffer decoder 132 (see fig. 6), e.g., even odd sensing may occur on both the upper page buffer 131 and the lower page buffer 133.

Fig. 12 is a timing diagram showing a cache read operation accompanied by an on-chip valley search OVS during a program suspension period. Referring to fig. 12, it is possible to perform a Full on-chip valley search (Full OVS) by using the combined sensing node c_so of the present invention when the cache latch CL is occupied by cache read data. In the cache latch CL, data sensed by a previous cache read command is waiting for output.

At time T0, a page buffer for the on-chip valley search OVS is initialized.

At time T1, a first sensing operation is started. For example, the read voltage RD5 is applied to the word line of the memory cell for sensing, and precharging is performed on the bit line BL. And the setting of the sense latch SL will take place.

At time T2, the page buffer unit performs an on-chip valley search OVS using the read voltage RD5. The on-chip valley search OVS may be provided with different levels of read voltage RD5. Alternatively, the data of the memory cell may be sensed according to different bit line development times in the sensing latch SL of the page buffer unit for the same level of the read voltage RD5.

At time T3, an on-chip valley search OVS check using a quality bit counter (MBC) is performed using the result of the on-chip valley search OVS read. For example, the voltage corresponding to the valley bottom may be determined by comparing data at different read voltage levels for on-chip valley search OVS inspection. Alternatively, the on-chip valley search OVS check may be performed in such a manner that the development time with the minimum error is determined under the condition of the read voltage RD5 of the same level.

At time T4, a data read is performed that applies the result of the on-chip valley search OVS read. For example, first, the sense latch SL is reset, and fine sensing is performed according to the adjusted read voltage RD5 and/or the adjusted development time based on the on-chip valley search OVS result. As a result of the fine sensing, the first data is stored in the sensing latch SL.

At time T5, the second sensing operation is started. For example, the read voltage RD1 is applied to the word line of the memory cell for sensing, and precharging is performed on the bit line BL. To this end, the first data of the sensing latch SL is dumped to the combined sensing node c_so. In at least one embodiment, to dump the first data to the combined sense node c_so, the sense node SO is precharged. And at time T6, the first data stored in the sensing latch SL moves to the combined sensing node c_so via the sensing node SO. For example, based on the first data, at least one of a read voltage applied to the precharged sensing node SO or a development time may be set.

At time T7, an on-chip valley search OVS corresponding to the read voltage RD1 is performed using the sense latch SL of the page buffer unit. The on-chip valley search OVS may be provided with different levels of read voltage RD1 and/or data of the memory cell may be sensed according to different bit line development times under the same level of read voltage RD 1. Then, on-chip valley search OVS check is performed using the result of the on-chip valley search OVS.

At time T8, the first data (1 st data) moved to the combined sensing node c_so returns to the sensing latch SL. For this, the sensing node SO is precharged, and a level corresponding to the first data maintained in the combined sensing node c_so is moved to the sensing latch SL via the sensing node SO.

At time T9, a data read applying the result of the on-chip valley search OVS read is performed. For example, first, the sense latch SL is reset, and fine sensing is performed according to the read voltage RD1 adjusted based on the on-chip valley search OVS read result and/or the adjusted development time. The result of the fine sensing and the first data are decoded, and cache read data (N RD data) as a result of the decoding are stored in the sense latch SL. The cache read data (N RD data) is data to be output after the cache read data N-1RD data of the current cache latch CL is output.

According to the timing diagram described above, in the program suspension period of the nonvolatile memory device 100, the cache latch is occupied with data to be output during the cache read operation. Thus, for on-chip valley search OVS for multiple states, additional latches are required. However, according to embodiments of the present invention, a Full on-chip valley search (Full OVS) may be performed using the combined sense node c_so without additional latch configuration.

Fig. 13 is a waveform diagram illustrating a method of configuring the combined sensing node c_so in the second sensing period of fig. 12. Referring to fig. 8, 12 and 13, the first data stored in the sensing latch SL for the second sensing may be stored using the capacity provided by the combined sensing node c_so and may be restored later. For convenience of description, the operations of the page buffer units PBU0a, PBU1a, PBU2a, and PBU3a belonging to the first page buffer column PGBUFa will be mainly described. However, the described operation can be equally applied to the page buffer units PBU0b, PBU1b, PBU2b, and PBU3b belonging to the second page buffer column PGBUFb.

At time T5, dumping of the first data stored in the sense latch SLa to the combined sense node c_ SOa begins. For this purpose, the control circuit 140 (refer to fig. 1) transitions the transmission control signals so_pass <3:0> to a high level. For example, to increase the charge capacity of the combined sense node c_ SOa, the transmission control signal so_pass <3:0> (e.g., representing so_pass <0> through so_pass <3 >) may be provided in an amount equal to or greater than the sum (e.g., 3V) of the threshold voltages (e.g., 1V) of the transmission transistors pt0a_ U, PT0a_ D, PT1a_ U, PT1a_ D, PT2a_ U, PT a_d and pt3a_u and the internal power supply voltage (e.g., 2V). Then, the sense nodes SOa <3:0> (e.g., representing SO0a through SO3 a) of the page buffer units PBU0a, PBU1a, PBU2a, and PBU3a have turn-off voltage levels (e.g., it will rise to 2V) corresponding to the magnitudes of the transmission control signals SO_PASS <3:0 >. At this time, the first data stored in the sense latch SLa is dumped to the combined sense node c_ SOa connected to the sense node SOa <3:0 >. The processing will be described with reference to a waveform chart to be described later. When dumping the first data to the combined sense node c_ SOa is completed, the transmission control signals so_pass <3:0> are deactivated. That is, the transmission control signals SO_PASS <3:0> will fall to ground.

At time T7, an on-chip valley search OVS is performed. To this end, the sense node SOa <3> (e.g., representing SO3 a) of the page buffer unit PBU3a sends the development result sent from the bit line BL to the sense latch SLa. The sense latch SLa transfers latched data at different development times as a value of a bit count through the first page buffer decoder PBDECa.

At time T7', the result of the on-chip valley search OVS read stored in the sense latch SLa is transferred to the page buffer decoder PBDECa for counting. The common transmission control signal soc_pass <0> is activated to a high level to transfer the result of the on-chip valley search OVS read stored in the sensing latch SLa to the page buffer decoder PBDECa. The PASS transistor pt3a_d of the page buffer unit PBU3a is turned on by the common PASS control signal soc_pass <0>, and the on-chip valley search OVS read result stored in the sense latch SLa is transmitted to the page buffer decoder PBDECa via the sense node SO3 a. In one example, the page buffer decoder PBDECa may provide data sensed by the sense latch SLa (e.g., on-chip valley search OVS read results) to the wired OR terminal wor_out.

At time T8, the common transfer control signal soc_pass <0> is again shifted to the low level, and the transfer transistor pt3a_d of the page buffer unit PBU3a is again turned off. And the first data stored in the combined sense node c_ SOa is returned to the sense latch SLa again. For this purpose, the control circuit 140 transitions the transmission control signals SO_PASS <3:0> to a high level. Then, the data of the sensing latch SLa of the page buffer unit PBU3a may be set according to the voltage of the combined sensing node c_ SOa. The illustrated voltage level may be set when the first data stored in the combined sensing node c_ SOa is at a high level. In at least one embodiment, the high level voltage of the combined sense node C SOa has a higher value than the Trip level (Trip level) SL Trip level of the sense latch SLa.

At time T8', when the data dump from the combined sense node c_ SOa to the sense latch SLa of the page buffer unit PBU3a is completed, the transfer control signal so_pass <3:0> transitions to a low level. Then, the sense nodes SOa <3:0> are then precharged (SO PRCH) for fine sensing using the result of the on-chip valley search OVS.

Fig. 14A and 14B are waveform diagrams showing data movement processing of the page buffer unit PBU3a according to the embodiment of the present invention. Fig. 14A shows control signals for a data dump from the sense latch SLa to the combined sense node C SOa. Fig. 14B shows waveforms of control signals for data recovery from the combined sense node c_ SOa to the sense latch SLa. Referring to fig. 5, 8 and 14A, data movement from the sensing latch SLa to the combined sensing node C SOa may be performed in a manner of discharging the precharge voltage or maintaining the precharge voltage according to the data of the sensing latch SLa.

At time t0, when the LOAD signal LOAD is activated to the low level L, the precharge transistors PM0a, PM1a, PM2a, and PM3a are turned on. Then, each of the sensing nodes SO0a, SO1a, SO2a, and SO3a of the page buffer units PBU0a, PBU1a, PBU2a, and PBU3a of the same page buffer column will be charged with a precharge voltage.

At time t1, the transmission control signals SO_PASS <3:0> are activated to a high level. Then, the page buffer units PBU0a, PBU1a, PBU2a, and the sense nodes SO0a, SO1a, SO2a, and SO3a of the same page buffer column including the page buffer unit PBU3a are connected. The combined sense node c_ SOa is configured according to the connection of the sense nodes SO0a, SO1a, SO2a, and SO3 a.

At time t2, when the LOAD signal LOAD is deactivated to the high level H, the precharge transistors PM0a, PM1a, PM2a, and PM3a are turned off.

At time t3, the ground control signal SOGND <3> transitions to a high level. Then, the charge precharged to the combined sensing node c_ SOa can be discharged or maintained according to the logic value of the first data stored in the sensing latch SLa.

At time t4, the ground control signal SOGND <3> transitions to a low level. Then, the data dump combining the sense node c_ SOa and the sense latch SLa is terminated.

At time t5, the transmission control signal SO_PASS <3:0> transitions to a low level. Then, the sensing nodes SO0a, SO1a, SO2a, and SO3a of the page buffer units PBU0a, PBU1a, PBU2a, and PBU3a constituting the combined sensing node c_ SOa are electrically isolated. However, the logic value of the precharge in each of the sensing nodes SO0a, SO1a, SO2a, and SO3a may be maintained.

Referring to fig. 5, 8 and 14B, data movement from the combined sensing node c_ SOa to the sensing latch SLa of the page buffer unit PBU3a may be performed in a charge-sharing manner. Here, the LOAD signal LOAD may maintain the inactive state at the high level H.

At time t1', the transmission control signals SO_PASS <3:0> are activated to a high level. Then, the sensing nodes SO0a, SO1a, SO2a, and SO3a of the page buffer units PBU0a, PBU1a, PBU2a, and PBU3a of the same page buffer column are electrically connected. Then, charges corresponding to the first data temporarily stored in the sensing nodes SO0a, SO1a, and SO2a are distributed to the sensing nodes SO0a, SO1a, SO2a, and SO3a. If the level of the first data temporarily stored in the sensing nodes SO0a, SO1a, and SO2a is logic low, the voltages of the sensing nodes SO0a, SO1a, SO2a, and SO3a will remain at the ground level even after the sensing nodes SO0a, SO1a, SO2a, and SO3a are connected.

In the previous step, the sensing node SO3a is used to transmit the on-chip valley search OVS read result of the page buffer unit PBU3a to the page buffer decoder PBDECa. Thus, the charged charges may not exist in the sensing node SO3a. When the level of the first data is logic high (e.g., when the transmission control signal so_pass <3:0> is activated to a high level), the voltages of the nodes SO0a, SO1a, SO2a, and SO3a constituting the combined sensing node c_ SOa may be slightly reduced by charge sharing. An example of which is shown in fig. 13.

At time t2', the ground control signal SOGND <3> for connecting the sensing latch SLa of the page buffer unit PBU3a and the sensing node SO3a transitions to the high level. Then, the charges charged into the sensing nodes SO0a, SO1a, SO2a, and SO3a constituting the combined sensing node c_ SOa may be transferred to the sensing latch SLa.

At time t3', after the data stored in the combined sense node c_ SOa moves to the sense latch SLa, the ground control signal SOGND <3> transitions to a low level. Then, the first data moved to the sensing latch SLa is fixed to the sensing latch SLa of the page buffer unit PBU3 a. At time t4', when the transmission control signal SO_PASS <3:0> transitions to a low level again, the data movement between the combined sense node C_ SOa and the sense latch SLa is terminated.

In the above, the data moving process from the combined sense node c_ SOa to the sense latch SLa has been briefly described.

Fig. 15 is a cross-sectional view schematically showing the COP structure of a nonvolatile memory device according to an embodiment of the present invention. Referring to fig. 15, the nonvolatile memory device 200 may have a on-periphery unit COP structure in which a unit region 210 is stacked on a peripheral region 270. At least a portion of the peripheral region 270 and at least a portion of the unit region 210 may be vertically stacked. For convenience, an example in which the entire unit region 210 and the entire peripheral region 270 are stacked on each other will be described herein, but the present invention is not intended to be limited thereto.

The peripheral region 270 includes one or more peripheral transistors 274 disposed on the lower substrate 271, peripheral circuit wiring 272 electrically connected to the peripheral transistors 274, and a lower insulating layer 273 covering the peripheral circuit wiring 272 and the peripheral transistors 274.

The cell region 210 may include an upper substrate 211, a cell array 214 disposed on the upper substrate 211, and an upper insulating layer 213 covering the cell array 214. The cell region 210 may further include connection circuit wirings 212 electrically connecting the cell array 214 and the peripheral circuit wirings 272. The cell array 214 may include metal contacts 215 that electrically connect the cell array 214 to the connection circuit wiring 212.

In the peripheral region 270, the lower substrate 271 may include a semiconductor substrate (such as a silicon wafer). The peripheral circuit wiring 272 may include, for example, a lower metal wiring LM0, an intermediate metal wiring LM1, and an upper metal wiring LM2 sequentially stacked on the lower substrate 271. The peripheral circuit wiring 272 includes a lower metal contact LMC1 electrically connecting the peripheral transistor 274 to the lower metal wiring LM0, an intermediate metal contact LMC2 electrically connecting the lower metal wiring LM0 to the intermediate metal wiring LM1, and an upper metal contact LMC3 electrically connecting the intermediate metal wiring LM1 to the upper metal wiring LM2.

In the cell region 210, the cell array 214 may have a three-dimensional structure in which a plurality of cells are vertically stacked on the upper substrate 211 having a well structure. The metal contacts 215 may electrically connect the plurality of cells of the cell array 214 and the upper substrate 211 to the connection circuit wiring 212.

The connection circuit wiring 212 may be electrically connected to the peripheral circuit wiring 272. The connection circuit wiring 212 may include a lower metal wiring M0, an intermediate metal wiring M1, and an upper metal wiring M2 sequentially stacked on the cell array 214. The connection circuit wiring 212 further includes a connection metal contact MC0 electrically connecting the peripheral circuit wiring 272 to the connection circuit wiring 212, a lower metal contact MC1 electrically connecting the connection metal contact MC0 and the lower metal wiring M0, an intermediate metal contact MC2 for electrically connecting the lower metal wiring M0 to the intermediate metal wiring M1, and a via VA as an upper metal contact electrically connecting the intermediate metal wiring M1 to the upper metal wiring M2. The lower metal contact MC1 may connect the cell array 214 to the lower metal line M0. The intermediate metal wiring M1 may include a bit line BL electrically connected to the vertical channel 216 of the cell array 214.

The nonvolatile memory device 200 having the COP structure described above can perform the full on-chip valley search OVS by controlling the combined sense node without adding the latch of the page buffer circuit even in a state where the cache latch is occupied. Therefore, it is possible to reduce data errors in the cache read operation performed in the program suspension period, thereby providing high reliability.

Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A cache read method of a nonvolatile memory device comprising a memory cell array, a plurality of page buffer units, each of the plurality of page buffer units having a sense latch and a sense node line, and a cache latch, the cache read method comprising:

performing a first off-chip valley search OVS read on the selected memory cell using a first sense node line and a first sense latch of a first page buffer cell of the plurality of page buffer cells;

storing first data sensed from the selected memory cell in a first sense latch, the first data based on a result of the first OVS read;

dumping the first data to a sensing node line of at least one page buffer unit other than the first page buffer unit among the plurality of page buffer units; and

a second OVS read is performed on the selected memory cell using the first sense latch.

2. The cache read method of claim 1, further comprising:

connecting a first sensing node line of a first page buffer unit to a sensing node line of each of the plurality of page buffer units according to a transmission control signal; and

in response to the common transmission control signal, the result of the second OVS read is sent to the page buffer decoder,

wherein the sensing node lines of the plurality of page buffer units are connected to each other through a transfer transistor configured to be turned on or off according to a transfer control signal.

3. The cache read method of claim 2, wherein dumping the first data comprises:

turning on a transfer transistor of the at least one of the plurality of page buffer units to electrically connect a sensing node line and a first sensing node line of the at least one page buffer unit;

precharging a sensing node line of the at least one page buffer unit; and

at least one of a read voltage or a development time applied to the precharged sensing node line is set based on the first data.

4. The cache read method of claim 2, wherein the step of transmitting the result of the second OVS read to the page buffer decoder includes: the transmission control signal is deactivated and the common transmission control signal is activated.

5. The cache read method of claim 1, further comprising:

after the second OVS read is completed, the first data stored in the sensing node line of the at least one page buffer cell is returned to the first sensing latch.

6. The cache read method of claim 5, further comprising:

based on the result of the second OVS read, second data stored in the selected memory cell is sensed.

7. The cache read method according to any one of claims 1 to 6, wherein the cache read method of the nonvolatile memory device is performed in a program suspension period of the nonvolatile memory device.

8. A non-volatile memory device, comprising:

a cell array including a plurality of memory cells connected in series to a bit line;

a page buffer circuit comprising a plurality of page buffer units configured to: programming or sensing at least one of the plurality of memory cells through a bit line and electrically connecting or blocking an adjacent sense node line in response to a transmission control signal; and

control circuitry configured to: during a cache read operation, moving first data corresponding to a first state, which is sensed through a first sensing latch, in a first sensing latch of a first page buffer unit to a second sensing node line of a second page buffer unit; and controlling the page buffer circuit such that the first sense latch performs an on-chip valley search OVS for reading the second state.

9. The non-volatile memory device of claim 8, wherein each of the plurality of page buffer units comprises at least one pass transistor configured to: in response to the transmission control signal, adjacent sense node lines of adjacent page buffer units are electrically connected or blocked.

10. The non-volatile memory device of claim 9, wherein the first data is dumped to a sense node line of at least two page buffer units including the second page buffer unit.

11. The non-volatile memory device of claim 10, wherein the at least two page buffer units correspond to page buffer units that are unused during OVS for reading the second state.

12. The non-volatile memory device of claim 9, wherein a level of the transfer control signal is greater than or equal to a sum of a threshold voltage of the at least one transfer transistor and an internal supply voltage.

13. The non-volatile memory device of claim 8, wherein the first data corresponds to finely sensed data under bias conditions determined based on results of previous OVSs used to read the first state.

14. The non-volatile memory device of claim 8, wherein the control circuit is configured to: the page buffer circuit is controlled to return the first data from the second sensing node line to the first sensing latch when the first sensing latch completes an on-chip valley search for reading the second state.

15. The non-volatile memory device of claim 8, wherein the page buffer circuit comprises:

a plurality of cache units configured to: transmitting sensed data sensed during OVS of each of the plurality of page buffer units to an output terminal; and

a page buffer decoder configured to: the data sensed by the first sense latch is provided to a wired or terminal.

16. The non-volatile memory device of claim 15, wherein the first page buffer unit comprises:

a first pass transistor configured to: connecting the first sensing node line to the second sensing node line in response to the transmission control signal; and

a second pass transistor configured to: the first sense node line is connected to a wire or terminal in response to a common transmission control signal.

17. A cache read method of a non-volatile memory device, comprising:

Storing first data in a sense latch of a first page buffer unit, the first data being sensed from a selected memory unit;

a sense node line for dumping the first data to the second page buffer unit; and

an on-chip valley search OVS is performed on the selected memory cells using the sense latches.

18. The cache read method of claim 17, wherein the first data is data sensed under bias conditions set according to a result of a previous OVS for the selected memory cell.

19. The cache read method of claim 17, wherein the second page buffer unit includes at least two page buffer units, and the sensing node line corresponds to a combined sensing node of the sensing node lines electrically connecting the at least two page buffer units.

20. The cache read method of claim 17, further comprising:

after the OVS is completed, the first data dumped to the sensing node line is transferred to the sensing latch of the first page buffer unit.