CN116467983A

CN116467983A - Center grain acquisition method and system, and readable storage medium

Info

Publication number: CN116467983A
Application number: CN202310445317.5A
Authority: CN
Inventors: 周朱琴
Original assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Current assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority date: 2023-04-19
Filing date: 2023-04-19
Publication date: 2023-07-21

Abstract

The invention provides a method and a system for acquiring a central crystal grain, and a readable storage medium, which can automatically acquire the central crystal grain based on Mapping data, reduce a great deal of labor cost required and improve the efficiency; and can be based on the similarity and meet the two kinds of judgement conditions of total number of test devices of the design requirement, can improve the accuracy of obtaining the central crystal grain. Furthermore, the total number of the test devices of the corresponding crystal grains can be updated by adjusting the error critical value, so that the flexibility is high.

Description

Center grain acquisition method and system, and readable storage medium

Technical Field

The present invention relates to the field of integrated circuit design and manufacturing technologies, and in particular, to a method and system for obtaining a central grain, and a readable storage medium.

Background

The semiconductor device model is a bridge between a connection foundry and an Integrated Circuit (IC) design company, and only the accurate device model can ensure accurate circuit simulation results. To model semiconductor devices, engineers typically need to design test devices for specific individual devices (e.g., MOS devices, etc.), go through the wafer, and test to obtain enough test data that contains enough dimensions to reflect the average and boundary levels of process conditions. Therefore, a parameter list can be obtained according to the test data fitting curve and stored, and a model file for SPICE simulation can be obtained.

For example, when building a Spice model of MOS devices, a series of MOS devices with different sizes need to be designed in each Die (Die) of a whole Wafer (Wafer), each MOS device with different sizes is used as a test device (testkey), and the Wafer is removed, then, a test related to Wafer map (Mapping) data is performed, a central Die (Golden Die) is determined according to the Mapping data, and then, a test related to Curve (Curve) data is performed on the central Die. Wherein Mapping data generally refers to test values of typical test parameters (such as threshold voltage VTLIN of a linear region, threshold voltage VTSAT of a saturation region, on-current IDLIN of a linear region, on-current IDSAT of a saturation region, off-current Idoff, etc.) of each test device on a whole Wafer (Wafer), and Curve (Curve) data refers to current I-voltage V Curve data and capacitance C-voltage V Curve data for each test device in a central Die (Golden Die). In this scheme, golden Die is determined before the test related to the Curve data, so as to ensure that the Curve data reflects typical characteristics of the process and the MOS device as much as possible, i.e. the Curve data is as close to the Median (Median) of the Mapping data as possible.

Therefore, how to accurately and rapidly acquire the center die based on Mapping data is one of the keys for accurately and rapidly establishing a semiconductor device model.

Disclosure of Invention

The invention aims to provide a method and a system for acquiring a central grain and a readable storage medium, which can accurately and quickly acquire the central grain.

In order to achieve the above object, the present invention provides a method for obtaining a center crystal grain, comprising the steps of:

s1, calculating the median of corresponding test parameters of each test device relative to all grains based on Mapping data of a plurality of different test devices on a wafer;

s2, taking the test values of the test parameters of all the test devices at each die on the wafer as a test array, taking the median of the test parameters of all the test devices of each die as a median array, and calculating the similarity between the test array and the median array of the test parameters of each die to obtain the similarity of each die;

s3, calculating the error between the test parameter and the corresponding median of each tested device at each die on the wafer, and counting the total number of tested devices meeting the requirements in each die based on an error critical value set for the test parameter;

and S4, comparing the calculation results of the similarity of all the grains with the statistical results of the total number of the tested devices, and determining the grain as a central grain when the grain with the highest similarity is consistent with the grain with the maximum total number of the tested devices.

Optionally, in step S1, a median of a plurality of test parameters is calculated for each test device; and in the step S2, calculating the similarity between the test array of each test parameter of each grain and the corresponding median array, and synthesizing the similarity calculation results of all the test parameters of each grain to obtain the similarity of each grain.

Optionally, in step S1, a median of a plurality of test parameters is calculated for each test device; in step S3, different error thresholds are set for different test parameters, and whether the respective test devices at each die meet the requirements is comprehensively evaluated based on the set different error thresholds.

Optionally, when it is determined in the step S4 that the die with the highest similarity is inconsistent with the die with the largest total number of test devices, returning to the step S3, and setting an error threshold value corresponding to at least one test parameter, so as to update the total number of test devices of the corresponding die, until the die with the highest similarity is consistent with the die with the largest total number of test devices.

Optionally, updating the total number of the test devices of the corresponding dies by tightening the critical error threshold corresponding to the test parameter.

Optionally, in step S2, arranging all the grains in order of high-to-low similarity to obtain a first ranking table; in step S3, arranging all the dies in the order from the large to the small according to the total number of the test devices to obtain a second ranking table; in step S4, it is compared whether the first names in the first ranking table and the second ranking table are identical.

Optionally, in step S2, when the difference between the similarities of the two grains is within a first preset range, the ranks of the two grains in the first ranking table are considered to be the same; and/or, in step S3, when the difference between the total number of the test devices of the two dies is within a second preset range, the ranks of the two dies in the second ranking table are considered to be the same.

Based on the same inventive concept, the present invention also provides a center grain acquisition system, including:

the median calculating module is configured to calculate the median of each test parameter of each test device relative to all dies based on Mapping data of a plurality of different test devices on the wafer;

the similarity calculation module is configured to take the test values of the test parameters of all the test devices at each die on the wafer as a test array, take the median of the test parameters of all the test devices of each die as a median array, and calculate the similarity between the test array of the test parameters of each die and the median array;

the error judging module is configured to calculate the error between the test parameter of each tested device at each die on the wafer and the corresponding median, and count the total number of tested devices meeting the requirement in each die based on an error critical value set for the test parameter;

and the central grain determining module is configured to compare the calculation results of the similarity of all grains with the statistical results of the total number of the tested devices, and determine the grain as a central grain when the grain with the highest similarity is consistent with the grain with the largest total number of the tested devices.

Optionally, the error determining module is further configured to adjust an error critical value corresponding to at least one test parameter when the central die determining module determines that the die with the highest similarity is inconsistent with the die with the largest total number of test devices, so as to update the total number of test devices of the corresponding die counted by the error determining module.

Optionally, the central grain acquisition system further includes a visual interface, and the similarity calculation module is further configured to arrange all grains in order of high-to-low similarity, so as to obtain a first ranking table and display the first ranking table on the visual interface; and/or the error judging module is further used for arranging all the crystal grains according to the sequence from the total number of the test devices to the small so as to obtain a second ranking table and display the second ranking table on the visual interface, and displaying the error critical value of each test parameter on the visual interface.

Based on the same inventive concept, the present invention provides a readable storage medium having a program stored thereon, which when executed by a processor, is configured to implement the center grain acquisition method of the present invention.

Compared with the prior art, the technical scheme of the invention has one of the following beneficial effects:

1. the center crystal grains can be automatically obtained, so that a large amount of labor cost is reduced, and the efficiency is improved;

2. based on the similarity and the total number of test devices meeting design requirements, the accuracy of obtaining the center crystal grains can be improved.

3. The total number of the test devices of the corresponding crystal grains can be updated by adjusting the error critical value, and the flexibility is high.

Drawings

Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

fig. 1 is a flow chart of a conventional method for obtaining a central die.

Fig. 2 is a flow chart of a method for obtaining a center grain according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of the first 3 grains in the first ranking table obtained in step S2 of the center grain acquisition method shown in fig. 2.

Fig. 4 is a distribution diagram of each test device satisfying design requirements on a wafer obtained in step S3 of the center die acquisition method shown in fig. 2.

Fig. 5 is a schematic diagram of the first 3 grains in the second ranking table obtained in step S3 of the center grain acquisition method shown in fig. 2.

Fig. 6 is a schematic view of a visual interface when a corresponding error threshold is set in step S3 of the center grain acquisition method shown in fig. 2.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Referring to fig. 1, a conventional method for obtaining a central Die (Golden Die) includes the following steps:

step 1, calculating the median value of each measurement parameter of each test device according to Mapping test data;

step 2, calculating error data between all Mapping test data and corresponding median values;

step 3, calculating the statistical distribution value of error data of each measurement parameter of each test device;

step 4, determining a standard value for selecting the central crystal grain according to the statistical distribution value;

step 5, counting the total number of devices meeting the standard value and the measurement parameters in each Die;

and 6, selecting the devices meeting the standard value and taking the Die with the largest total number of measured parameters as Golden Die.

The above scheme has the following defects:

1. in the step 6, the total number of the measured parameters is at most used as one of the basis for determining Golden Die, but the measured parameters have different importance, so that the result is possibly wrong;

2. in the step 6, the total number of the measured parameters is at most used as one of the basis for determining Golden Die, but the total number of the satisfied conditions is not proportional to the similarity, so that the result is possibly wrong;

3. in the above scheme, the user cannot manually relax and tighten the error threshold (i.e. the corresponding SPEC threshold) of the measurement parameter, so the flexibility is not enough;

4. an empirical SPEC threshold combination cannot be formed to extend the basis for determining Golden Die, thereby affecting the efficiency and accuracy of determining Golden Die.

Based on the method and the system, the automatic acquisition of the center crystal grains can be realized based on Mapping test data, double condition judgment and automatic parameter critical value fine adjustment logic, a large amount of labor cost is reduced, the efficiency is improved, and a user can adjust the error value range according to the severe condition of the test parameters with higher weight, so that the accuracy and the efficiency of the acquired center crystal grains are ensured.

Specifically, referring to fig. 2, an embodiment of the present invention provides a method for obtaining a center die, which includes the following steps:

s2, taking the test values of the test parameters of all the test devices at each die on the wafer as a test array, taking the median of the test parameters of all the test devices of each die as a median array, and calculating the similarity between the test array and the median array of the test parameters of each die;

It should be understood that a small Wafer body on a Wafer (Wafer) is generally called a Die (Die), and a Wafer is divided into a plurality of dies by dicing channels (or scribe lines), and after Wafer packaging and dicing, each Die is packaged as a chip (chip). In order to monitor the manufacturing process of the corresponding devices in the wafer to ensure the yield of the devices in the finally manufactured chips, a plurality of test devices (called test structures and test patterns) specially used for testing are usually arranged in the scribing grooves, and whether the processes are normal and stable or not is monitored by testing the test devices.

When the same chip design is adopted for each die on a corresponding wafer, a plurality of different test devices required by the chip design are usually arranged at each die, the types and the distributions of the test devices corresponding to the different dies are the same, and for one die, the plurality of different test devices arranged for the die can be components of the same type and different sizes (for example, MOS transistors with different width-to-length ratios), can be components of different types (for example, a combination of at least two types of MOS transistors, triodes, BJT transistors and the like), can also be application-specific integrated circuits of different types (for example, inverters, logic gates and the like), and can also be a combination of at least two of the above components and application-specific integrated circuits.

In order to better understand the technical solution of the present embodiment, a plurality of MOS transistors with different width-to-length ratios (for example, 50 width-to-length ratios, corresponding to 50 MOS transistors) are taken as examples of a plurality of test devices disposed at each die on the wafer in this case, and all MOS transistors appearing hereinafter refer to MOS transistors as the test devices.

After testing the MOS transistors with different width-to-length ratios at each crystal grain of the wafer by using a testing machine, mapping data corresponding to the MOS transistors with each width-to-length ratio can be obtained. The Mapping data of the MOS transistor at each width-to-length ratio generally refers to a test value of a typical test parameter of the MOS transistor at that width-to-length ratio on a whole Wafer (Wafer) (e.g., at least one of a threshold voltage VTLIN of a linear region, a threshold voltage VTSAT of a saturation region, an on-current IDLIN of the linear region, an on-current IDSAT of the saturation region, etc.).

Therefore, in step S1, the median of each test parameter of the MOS transistor under each aspect ratio with respect to all dies can be calculated based on Mapping data of the MOS transistor under each aspect ratio on the wafer, so as to obtain a median array of all aspect ratios on the wafer corresponding to each test parameter. Taking typical test parameters VTLIN, VTSAT, IDLIN, IDSAT of MOS transistors as an example, in this step, by taking the average value of VTLIN of all MOS transistors in each aspect ratio, the median of VTLIN in each aspect ratio can be obtained, and similarly, the median of VTSAT in each aspect ratio, the median of IDLIN in each aspect ratio, and the median of IDSAT in each aspect ratio can be obtained.

In step S2, further regarding all the MOS transistors with the aspect ratio as one sample group, based on the median of each test parameter under each aspect ratio obtained in step S1, a VTLIN median array composed of VTLIN median under all the aspect ratios, a VTSAT median array composed of VTSAT median under all the aspect ratios, an ITSAT median array composed of ITSAT median under all the aspect ratios, and an ITSAT median array composed of ITSAT median under all the aspect ratios may be obtained. Taking the VTLIN test value of the MOS transistor under all the width-to-length ratios at each grain as a VTLIN test array, taking the VTSAT test value of the MOS transistor under all the width-to-length ratios at each grain as a VTSAT test array, taking the ITSAT test value of the MOS transistor under all the width-to-length ratios at each grain as an ITSAT test array, and taking the ITLIN test value of the MOS transistor under all the width-to-length ratios at each grain as an ITLIN test array. Therefore, through similarity calculation methods such as T test or Z test, the similarity of the VTLIN test array and the VTLIN bit array, the similarity of the VTSAT test array and the VTSAT bit array, the similarity of the ITLIN test array and the ITLIN bit array, the similarity of the ITSAT test array and the ITSAT bit array at each grain are calculated, and the similarity calculation results of the four parameters are synthesized VTLIN, VTSAT, ITLIN, ITSAT, so that the similarity of each grain is obtained. Further alternatively, the grains may be ranked in order of their similarity from top to bottom, resulting in a first ranking table, as shown in fig. 3.

It should be appreciated that any suitable method in the art may be used to integrate the similarity calculations for the four parameters VTLIN, VTSAT, ITLIN, ITSAT to obtain the similarity of the individual grains. For example, a similarity threshold may be set for each of the four parameters VTLIN, VTSAT, ITLIN, ITSAT, the similarity of more test parameters in a die satisfying a range specified by the corresponding similarity threshold, the higher the similarity of the die. For another example, different weights may be set for the four test parameters VTLIN, VTSAT, ITLIN, ITSAT, and a weighted calculation of the similarity may be performed based on the weights, so as to calculate a similarity integrated value of all the test parameters of each grain, where the higher the similarity integrated value, the higher the similarity of the grain.

In order to increase the acquisition effect of the central crystal grain as much as possible, the difference rate between the degrees of similarity of the crystal grains may be compared, and when the difference rate between the degrees of similarity of the two crystal grains is within 1%, the ranks of the two crystal grains in the first ranking table are juxtaposed.

In step S3, different error thresholds are set in advance for VTLIN, VTSAT, ITLIN, ITSAT, and the size of the range defined by the error threshold is set according to the importance level of VTLIN, VTSAT, ITLIN, ITSAT, and the more important test parameters, the more stringent the requirements are for the test parameters, the smaller the range defined by the error threshold can be set. After calculating the errors of the VTLIN, VTSAT, ITLIN, ITSAT test values of each MOS transistor at each die relative to the corresponding VTLIN median, VTSAT median, ittlin median, ITSAT median, respectively, it can be further determined whether the errors of VTLIN, VTSAT, ITLIN, ITSAT of each MOS transistor respectively satisfy the ranges specified by the error threshold values corresponding to VTLIN, VTSAT, ITLIN, ITSAT. Thus, whether each MOS transistor at each grain meets the requirement is comprehensively evaluated, wherein when errors of VTLIN, VTSAT, ITLIN, ITSAT four test parameters in one MOS transistor meet the range specified by the corresponding error critical value, the MOS transistor meets the requirement (namely meets the chip design requirement).

As an example, in the table shown in fig. 4, it is shown in which the MOS transistors Testkey1 to Testkey19 having different width-to-length ratios respectively satisfy the requirements in which dies, and it can be seen from the table that Testkey16 in die (1, 0) does not satisfy the requirements. The total number of MOS transistors meeting the requirements in each die can thus be counted based on the table.

Further alternatively, the die may be ranked in order of top to bottom of the total number of MOS transistors in the die that meet the requirements, resulting in a second ranking table, as shown in fig. 5.

Wherein, in order to enhance the acquisition effect of the center die as much as possible, when the difference rate between the total number of MOS transistors satisfying the requirement in the two dies is within 1%, the ranks of the two dies in the second ranking table are juxtaposed.

In step S4, whether the die with the highest similarity obtained in step S2 (i.e., the first name in the first ranking table shown in fig. 3) and the die with the largest total number of MOS transistors obtained in step S3 (i.e., the first name in the second ranking table shown in fig. 5) are identical (i.e., identical) is compared. If they are identical (i.e., if they are identical), the die is the center die; if not (i.e. if not, the process returns to step S3 again, and sets an error threshold corresponding to at least one test parameter to update the total number of MOS transistors meeting the requirement counted for the corresponding die, until the die with the highest similarity obtained in step S2 is consistent with the die with the largest total number of MOS transistors obtained in step S3.

In order to increase the obtaining effect of the central grain as much as possible, the operation times for adjusting the test parameters are reduced, after step S4 determines that the grain with the highest similarity obtained in step S2 is inconsistent with the grain with the largest total number of MOS transistors obtained in step S3, the total number of MOS transistors meeting the requirements counted for the corresponding grain is updated by tightening the error threshold corresponding to the important test parameters.

In addition, the operation of adjusting the test parameters can be automatically realized through a program, for example, the error critical value of the corresponding important test parameters is automatically fine-tuned by +/-0.1 percent through the program; or manually adjusted by the user through a visual interface, as shown in fig. 6.

In addition, in the visual interface, proper test parameters can be selected and proper error critical value settings can be set through historical data or user experience, or default test parameter combination conditions and error critical value settings can be automatically formed on the visual interface through the historical data, so that empirical test parameter combination conditions and error critical value settings can be formed, the basis for determining the center crystal grains can be further expanded, and the efficiency and accuracy for acquiring the center crystal grains are improved.

It should be understood that, in the above embodiment, only four typical electrical parameters VTLIN, VTSAT, ITLIN, ITSAT of the MOS transistor are taken as an example for illustration, but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the test parameters such as the off-state current IOFF, the transconductance Gm, gds, and various typical capacitance test parameters of the MOS transistor may be obtained based on Mapping data, as shown in fig. 6.

Based on the same inventive concept, an embodiment of the present invention further provides a center grain acquisition system, including:

the median calculating module is configured to calculate the median of each test parameter of each test device relative to all dies based on Mapping data of a plurality of different test devices on a wafer, so as to obtain a median array corresponding to all the test devices on the wafer.

The similarity calculation module is configured to regard the data of all the test parameters of each die on the wafer as a test array respectively, and calculate the similarity between each test array and the median array;

the error judging module is configured to implement step S3 in the method for obtaining a central die of the present embodiment, and is specifically configured to calculate an error between each test parameter of each tested device on the wafer and a corresponding median, and calculate the total number of tested devices meeting the requirement in each die based on an error critical value set for each test parameter;

Optionally, the center grain acquisition system of the present embodiment further includes a visual interface, and the similarity calculation module is further configured to arrange all grains in a sequence from high to low in similarity, so as to obtain a first ranking table and display the first ranking table on the visual interface; and/or the error judging module is further used for arranging all the crystal grains according to the sequence from the total number of the test devices to the small so as to obtain a second ranking table and display the second ranking table on the visual interface, and displaying the error critical value of each test parameter on the visual interface.

It should be understood that, the central grain acquisition system provided in this embodiment is used to implement the central grain acquisition method of this embodiment, where the bit number calculation module is used to implement step S1 of the central grain acquisition method of this embodiment, the similarity calculation module is used to implement step S2 of the central grain acquisition method of this embodiment, the error determination module is used to implement step S3 of the central grain acquisition method of this embodiment, and when the central grain determination module determines that the grains with the highest similarity are inconsistent with the grains with the largest total number of test devices, the error threshold corresponding to at least one of the test parameters is adjusted to update the total number of test devices counted by the error determination module. The center grain determining module is configured to implement step S4 of the center grain acquiring method of the present embodiment.

It is to be understood that all or some of the steps in the central grain acquisition method of the present invention, as well as the functional modules in the central grain system, may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules mentioned in the above description does not necessarily correspond to the division of physical components. For example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a readable storage medium.

Based on the same inventive concept, an embodiment of the present invention provides a readable storage medium having a program stored thereon, which when executed by a processor, is configured to implement the method for acquiring a center grain according to the present invention.

The readable storage Media of the present invention is any suitable medium for storing the desired information and which can be accessed by a computer and may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk CDVD or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, smart Media Card (SMC), secure digital (SecureDigital, SD) Card, flash memory Card (Flash Card), and the like. Furthermore, the program on the readable storage medium may be any suitable information stored in the readable storage medium, and may include, but is not limited to, computer readable instructions or algorithms, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and the like.

In summary, the technical scheme of the invention can automatically acquire the central crystal grain, reduce a great deal of labor cost required, improve the efficiency, and improve the accuracy of acquiring the central crystal grain based on two judging conditions of similarity and total number of test devices meeting the design requirement. Furthermore, the total number of test devices of the corresponding crystal grains can be updated by adjusting the error critical value, the flexibility is high, and the empirical test parameter combination conditions and error critical value setting can be formed, so that the basis for determining the center crystal grains can be expanded, and the efficiency and accuracy for acquiring the center crystal grains are improved.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.

Claims

1. A method of center grain acquisition comprising the steps of:

s3, calculating the error between the test parameter and the corresponding median of each tested device at each die on the wafer, and counting the total number of tested devices meeting the requirements in each die;

2. The center grain acquisition method according to claim 1, wherein a median of a plurality of test parameters is calculated for each test device in step S1; and in the step S2, calculating the similarity between the test array of each test parameter of each grain and the corresponding median array, and synthesizing the similarity calculation results of all the test parameters of each grain to obtain the similarity of each grain.

3. The center grain acquisition method according to claim 1, wherein a median of a plurality of test parameters is calculated for each test device in step S1; in step S3, different error thresholds are set for different test parameters, and whether the respective test devices at each die meet the requirements is comprehensively evaluated based on the set different error thresholds.

4. The method of claim 3, wherein when it is determined in the step S4 that the die having the highest similarity is inconsistent with the die having the largest total number of test devices, returning to the step S3, and setting an error threshold corresponding to at least one of the test parameters to update the total number of test devices corresponding to the die until the die having the highest similarity is consistent with the die having the largest total number of test devices.

5. The method of claim 4, wherein the total number of test devices for the corresponding die is updated by tightening an error threshold corresponding to the test parameter of interest.

6. The center grain acquisition method according to any one of claims 1 to 5, wherein in step S2, all the grains are arranged in order of high-to-low similarity to obtain a first ranking table; in step S3, arranging all the dies in the order from the large to the small according to the total number of the test devices to obtain a second ranking table; in step S4, it is compared whether the first names in the first ranking table and the second ranking table are identical.

7. The method of obtaining a center crystal grain according to claim 6, wherein in step S2, when a difference in similarity of two crystal grains is within a first preset range, the two crystal grains are regarded as being ranked the same in the first ranking table; and/or, in step S3, when the difference between the total number of the test devices of the two dies is within a second preset range, the ranks of the two dies in the second ranking table are considered to be the same.

8. A center die acquisition system, comprising:

the similarity calculation module is configured to take the test values of the test parameters of all the test devices at each die on the wafer as a test array, take the median of the test parameters of all the test devices of each die as a median array, and calculate the similarity between the test array of the test parameters of each die and the median array so as to obtain the similarity of each die;

the error judging module is configured to calculate the error between the test parameter of each tested device at each crystal grain on the wafer and the corresponding median, and count the total number of the tested devices meeting the requirement in each crystal grain;

9. The system of claim 8, wherein the error determination module is further configured to adjust an error threshold corresponding to at least one of the test parameters to update the total number of test devices for the corresponding die counted by the error determination module when the central die determination module determines that the die with the highest similarity is inconsistent with the die with the maximum total number of test devices.

10. The central grain acquisition system of claim 9 further comprising a visual interface, the similarity calculation module further configured to rank all of the grains in a high-to-low order of similarity to obtain a first ranking table and display on the visual interface; and/or the error judging module is further used for arranging all the crystal grains according to the sequence from the total number of the test devices to the small so as to obtain a second ranking table and display the second ranking table on the visual interface, and displaying the error critical value of each test parameter on the visual interface.

11. A readable storage medium having stored thereon a program for implementing the center grain acquisition method according to any one of claims 1-7 when executed by a processor.