CN116466882A - SSD performance improving method, device, equipment and medium based on HMB - Google Patents
SSD performance improving method, device, equipment and medium based on HMB Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005192 partition Methods 0.000 claims abstract description 56
- 238000013461 design Methods 0.000 claims abstract description 9
- 238000004590 computer program Methods 0.000 claims description 15
- 238000012937 correction Methods 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 9
- 238000012795 verification Methods 0.000 claims description 7
- 230000006872 improvement Effects 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000002708 enhancing effect Effects 0.000 description 5
- 238000013507 mapping Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
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- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention discloses an SSD performance improving method, device, equipment and medium based on HMB, wherein an HMB address space adopts partition design, and the method comprises the following steps: classifying data to be stored in the SSD; and different protection strategies and access modes are adopted for the classified data by utilizing the partitions of the HMB. By adopting different protection strategies and access modes for each classified data through partition design of the HMB address space, the access delay is reduced, the reliability of the protected data is improved, and the SSD performance is further integrally improved.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to an SSD performance improving method, device, equipment and medium based on HMB.
Background
Consumer grade SSD products take into account the balance of cost and performance, the current mainstream adopts hmb+dram, where dram is removed from the SSD disk side, and HMB (host memory buffer) where part of the data that must be temporarily stored is stored on the host side after dram is removed from the disk side.
At present, the whole HMB adopts a unified data protection scheme and access mode, namely 512B performs ECC error correction, the data interaction of the HMB needs to be performed in an integral multiple of 512B, under the random RD condition, 512B data needs to be read every time 4B mapping information is acquired, unnecessary 508B data is additionally acquired, a large amount of time delay is caused, the side of the SSD needs to wait for the end after the HMB access is initiated, then the next work is performed, the software and the hardware cannot be asynchronous, and a large amount of performance loss is caused.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an SSD performance improving method, device, equipment and medium based on HMB, aiming at improving SSD performance while guaranteeing data reliability.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
in a first aspect, the present invention provides an SSD performance improvement method based on HMB, an HMB address space employing a partition design, the method comprising:
classifying data to be stored in the SSD;
and different protection strategies and access modes are adopted for the classified data by utilizing the partitions of the HMB.
The further technical scheme is as follows: the partitions of the HMB address space include a first partition, a second partition, and a third partition.
The further technical scheme is as follows: the first partition is located at a low address of the HMB address space, the second partition is located at an intermediate address of the HMB address space, and the third partition is located at a high address of the HMB address space.
The further technical scheme is as follows: the first partition adopts a first type data protection strategy and a first type data access mode, the second partition adopts a second type data protection strategy and a second type data access mode, and the third partition adopts a third type data protection strategy and a third type data access mode.
The further technical scheme is as follows: the first type data protection strategy is a parity check strategy, and the first type data access mode comprises Double Word and DMA burst.
The further technical scheme is as follows: the second type data protection strategy is a single-Byte error correction verification strategy, and the second type data access mode comprises Byte, word, double Word and DMA burst.
The further technical scheme is as follows: the third type data protection policy is a block error correction checking policy, and the third type data access mode includes DMA burst.
In a second aspect, the present invention provides an SSD performance enhancing apparatus based on HMB, the HMB address space being designed in a partition, the apparatus comprising a classification module and a processing module;
the separation module is used for classifying data to be stored in the SSD;
the processing module is used for adopting different protection strategies and access modes for the classified data by utilizing the partitions of the HMB.
In a third aspect, the present invention provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the HMB-based SSD performance enhancement method as described above when executing the computer program.
In a fourth aspect, the present invention provides a computer readable storage medium storing a computer program comprising program instructions which, when executed by a processor, cause the processor to perform an HMB-based SSD performance enhancement method as described above.
Compared with the prior art, the invention has the beneficial effects that: the data to be stored in the SSD are classified, different protection strategies and access modes are adopted for each classified data by utilizing the partition design of the HMB address space, so that the access delay is reduced, the reliability of the protection data is improved, and the SSD performance is integrally improved.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the present invention so that the same may be more clearly understood, as well as to provide a better understanding of the present invention with reference to the following detailed description of the preferred embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of an SSD performance enhancing method based on HMB according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of an SSD performance enhancing device based on HMB provided in an embodiment of the present invention;
fig. 3 is a schematic block diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
The invention provides an SSD performance improving method based on HMB, wherein an HMB address space adopts a partition design. As shown in fig. 1, the method comprises the steps of: S10-S20.
S10, classifying data required to be stored in the SSD.
The data to be stored is specifically the data to be cached in the memory of the host side in the SSD. The host side and the SSD interact through the HMB controller, and the SSD can directly access the host memory by utilizing HMB (Host Memory Buffer), so that multiple copies and transfers of data are avoided. In accessing this process, the conversion of physical addresses into logical address space is accomplished by the HMB controller. When a host sends a read-write request to an SSD, the HMB controller maps the requested logical address space to the corresponding physical address space and transfers data from the host memory to the SSD.
S20, different protection strategies and access modes are adopted for the classified data by utilizing the partitions of the HMB.
The data protection strategies and access modes of all partitions of the HMB are different, so that different protection strategies and access modes can be adopted for different classified data, the access delay is reduced, the reliability of the protected data is improved, and the SSD performance is further integrally improved.
In one embodiment, the partitions of the HMB address space include a first partition, a second partition, and a third partition.
The first partition, namely the mapping data area, is located at a low address of the HMB address space, and adopts a first type data protection strategy and a first type data access mode. Specifically, the first type of data protection policy is a parity check policy, and the first type of data access manner includes Double Word and DMAburst.
In this embodiment, the Parity check policy is Bit31 Parity, only Bit0-Bit30 can be actually used, and 2TB SSD can be supported at maximum under the 4KB mapping condition; the mapping data area must be accessed in Double Word or DMAburst mode; the parity check can detect the error of 1bit, and after the error occurs, the HMB controller reports the error to the SSD, and the SSD performs exception handling.
The second partition, namely the Sys data area, is positioned at the middle address of the HMB address space and adopts a second type data protection strategy and a second type data access mode. Specifically, the second type data protection policy is a single Byte error correction verification policy, and the second type data access mode includes Byte, word, double Word and DMAburst.
In this embodiment, the single Byte error correction verification strategy is 1Byte ECC, which is capable of detecting and correcting single Byte errors. In the memory, each byte is accompanied by one bit of ECC check code for recording the check information of the byte. When the data is read out, the ECC check code is recalculated, if the calculation result is inconsistent with the check code in the memory, the Byte is indicated to have errors, and at the moment, the 1Byte ECC automatically performs error correction to replace the error data with correct data.
And the third partition, namely a User data area, is positioned at a high address of the HMB address space, and adopts a third type data protection strategy and a third type data access mode. Specifically, the third type of data protection policy is a block error correction verification policy, and the third type of data access mode includes DMAburst.
In this embodiment, the block error correction checking strategy is 512Bytes ECC, which is capable of detecting and correcting 512Bytes (or referred to as a sector) of error in memory. In the memory, each sector is accompanied by an ECC check code for recording the check information of the sector. When the data is read out, the ECC check code is recalculated, if the calculation result is inconsistent with the check code in the memory, the sector is indicated to have errors, and the ECC technology automatically performs error correction to replace the error data with correct data.
In addition, interaction between the HMB controller and the SSD software is performed in a Desc mode, the information in the Desc comprises an HMB address, a local SSD memory address, an HMB area and an accessed size, the HMB controller performs data access on the HMB according to the information, and the software can submit a plurality of Descs at the same time, so that asynchronous work of the SSD software and the HMB controller can be achieved, and performance is improved.
A schematic block diagram of an HMB-based SSD performance lifting device 100 provided for an embodiment of the invention; corresponding to the above-mentioned SSD performance enhancing method based on HMB, the embodiment of the invention further provides an SSD performance enhancing device 100 based on HMB.
As shown in fig. 2, the HMB-based SSD performance enhancement device 100, in which the HMB address space is designed in a partition, includes a classification module 110 and a processing module 120; a separation module 110, configured to classify data that needs to be stored in the SSD; the processing module 120 is configured to use each partition of the HMB to apply different protection policies and access manners to each classified data.
The HMB-based SSD performance enhancement method described above may be implemented in the form of a computer program that can be run on a computer device as shown in fig. 3.
Referring to fig. 3, fig. 3 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 700 may be a server, where the server may be a stand-alone server or may be a server cluster formed by a plurality of servers.
As shown in fig. 3, the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the HMB-based SSD performance enhancement method described above when executing the computer program.
The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720, a memory, and a network interface 750, which are connected through a system bus 710, wherein the memory may include a non-volatile storage medium 730 and an internal memory 740.
The non-volatile storage medium 730 may store an operating system 731 and computer programs 732. The computer program 732, when executed, may cause the processor 720 to perform any one of the HMB-based SSD performance enhancement methods.
The processor 720 is used to provide computing and control capabilities to support the operation of the overall computer device 700.
The internal memory 740 provides an environment for the execution of a computer program 732 in the non-volatile storage medium 730, which computer program 732, when executed by the processor 720, causes the processor 720 to perform any of the HMB-based SSD performance enhancement methods.
The network interface 750 is used for network communications such as sending assigned tasks and the like. Those skilled in the art will appreciate that the structures shown in FIG. 3 are block diagrams only and do not constitute a limitation of the computer device 700 to which the present teachings apply, and that a particular computer device 700 may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components. Wherein the processor 720 is configured to execute the program code stored in the memory to implement the following steps:
the invention provides an SSD performance improving method based on HMB, wherein an HMB address space adopts partition design, and the method comprises the following steps:
classifying data to be stored in the SSD;
and different protection strategies and access modes are adopted for the classified data by utilizing the partitions of the HMB.
In one embodiment, the partitions of the HMB address space include a first partition, a second partition, and a third partition.
In one embodiment, the first partition is located at a low address of the HMB address space, the second partition is located at an intermediate address of the HMB address space, and the third partition is located at a high address of the HMB address space.
In an embodiment, the first partition adopts a first type data protection policy and a first type data access mode, the second partition adopts a second type data protection policy and a second type data access mode, and the third partition adopts a third type data protection policy and a third type data access mode.
In an embodiment, the first type data protection policy is a parity policy, and the first type data access manner includes Double Word and DMAburst.
In an embodiment, the second type data protection policy is a single Byte error correction verification policy, and the second type data access manner includes Byte, word, double Word and DMAburst.
In an embodiment, the third type of data protection policy is a block error correction checking policy, and the third type of data access mode includes DMAburst.
It should be appreciated that in embodiments of the present application, the processor 720 may be a central processing unit (Central Processing Unit, CPU), the processor 720 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf Programmable gate arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that the computer device 700 structure shown in FIG. 3 is not limiting of the computer device 700 and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
In another embodiment of the present invention, a computer-readable storage medium is provided. The computer readable storage medium may be a non-volatile computer readable storage medium. The computer readable storage medium stores a computer program, wherein the computer program when executed by a processor implements the HMB-based SSD performance improvement method disclosed in the embodiments of the invention.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus, device and unit described above may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein. Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus, device and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units is merely a logical function division, there may be another division manner in actual implementation, or units having the same function may be integrated into one unit, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units may be stored in a storage medium if implemented in the form of software functional units and sold or used as stand-alone products. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. The SSD performance improving method based on the HMB is characterized in that an HMB address space adopts a partition design, and the method comprises the following steps:
classifying data to be stored in the SSD;
and different protection strategies and access modes are adopted for the classified data by utilizing the partitions of the HMB.
2. The HMB-based SSD performance enhancement method of claim 1, wherein the partitions of the HMB address space include a first partition, a second partition, and a third partition.
3. The HMB-based SSD performance enhancement method of claim 2, wherein the first partition is located at a low address of the HMB address space, the second partition is located at an intermediate address of the HMB address space, and the third partition is located at a high address of the HMB address space.
4. The HMB-based SSD performance enhancement method of claim 2, wherein the first partition employs a first type data protection policy and a first type data access manner, the second partition employs a second type data protection policy and a second type data access manner, and the third partition employs a third type data protection policy and a third type data access manner.
5. The HMB-based SSD performance enhancement method of claim 4, wherein the first type of data protection policy is a parity policy, and the first type of data access includes DoubleWord and DMAburst.
6. The HMB-based SSD performance enhancement method of claim 4, wherein the second type data protection policy is a single byte error correction verification policy, the second type data access means including Byte, word, doubleWord and DMAburst.
7. The HMB-based SSD performance enhancement method of claim 4, wherein the third type of data protection policy is a block error correction verification policy, the third type of data access means including DMAburst.
8. The SSD performance improving device based on the HMB is characterized in that an HMB address space adopts a partition design, and the device comprises a classification module and a processing module;
the separation module is used for classifying data to be stored in the SSD;
the processing module is used for adopting different protection strategies and access modes for the classified data by utilizing the partitions of the HMB.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the HMB-based SSD performance enhancement method of any one of claims 1-7 when the computer program is executed.
10. A computer readable storage medium, characterized in that the storage medium stores a computer program comprising program instructions that, when executed by a processor, cause the processor to perform the HMB-based SSD performance improvement method of any one of claims 1-7.
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| CN202310388359.XA CN116466882A (en) | 2023-04-12 | 2023-04-12 | SSD performance improving method, device, equipment and medium based on HMB |
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