CN116466795A - Component clock synchronization method, device, computer equipment and storage medium - Google Patents
Component clock synchronization method, device, computer equipment and storage medium Download PDFInfo
- Publication number
- CN116466795A CN116466795A CN202310380655.5A CN202310380655A CN116466795A CN 116466795 A CN116466795 A CN 116466795A CN 202310380655 A CN202310380655 A CN 202310380655A CN 116466795 A CN116466795 A CN 116466795A
- Authority
- CN
- China
- Prior art keywords
- time
- clock synchronization
- request
- target
- target time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 230000004044 response Effects 0.000 claims abstract description 82
- 238000004422 calculation algorithm Methods 0.000 claims description 36
- 238000004590 computer program Methods 0.000 claims description 21
- 230000001360 synchronised effect Effects 0.000 claims description 17
- 238000004364 calculation method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000012545 processing Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The application relates to a component clock synchronization method, a device, a computer device and a storage medium, wherein the method comprises the following steps: responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end; acquiring a first target moment when the component end sends out a clock synchronization request; receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request; acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller; calculating a standard target time based on the first target time, the second target time and the third target time; and carrying out clock synchronization on the component end according to the standard target moment. The method and the device can effectively reduce the difference of physical clocks caused by time drift of different components, avoid the logic problem caused by time asynchronization and enable the server to be in the best working performance.
Description
Technical Field
The present disclosure relates to the field of clock synchronization technologies, and in particular, to a component clock synchronization method, device, computer device, and storage medium.
Background
The BMC (Baseboard Management Controller ) is an independent small card on a server main board, and is provided with an independent processor and a control system, communicates with the main board through various hardware interfaces, and provides functions of inquiry, control and the like through a network, a serial port and the like. OpenBMC (open source based baseboard management controller) is a Linux release of BMC, an open source and re-architecture system, intended to manage across heterogeneous systems.
Because the main board adopts two Intel high-performance CPU (Central Processing Unit ) processing chips, the processing capacity is strong, a plurality of high-performance components such as an intelligent network card, a JBOD (Just a Bunch Of Disks, a cluster of disks, a serial bundling array) card and the like are externally connected through a hardware interface, and the external high-performance components have own systems to independently perform various responses and logic processing, and simultaneously perform information interaction with the OpenBMC through communication modes such as a network, a serial port or an IPMB (Intelligent Platform Management Bus, an intelligent platform management bus) and the like. In a natural state, the components use their own physical clocks to represent time stamps, however, when the system has strict requirements on the time of an event (such as state synchronization), the physical clocks have the following problems: because of the structural difference between the components, different time drift is generated after the components run for a period of time, so that a certain difference exists between the physical clocks of different components, the sequence of the events A may be later than that of the events B, the sent time stamp is smaller than that of the events B, if the state synchronization is involved, the data of the B can cover the data of the A, and the problem is more remarkable when the multiple components are synchronized.
Therefore, there is a need to propose a component clock synchronization method, apparatus, computer device and storage medium for solving the logic problem caused by time-out-of-sync due to time drift of different components.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a component clock synchronization method, apparatus, computer device, and storage medium.
In one aspect, a component clock synchronization method is provided, the method comprising:
responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end;
acquiring a first target moment when the component end sends out a clock synchronization request;
receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request;
acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller;
calculating a standard target time based on the first target time, the second target time and the third target time;
and carrying out clock synchronization on the component end according to the standard target moment.
In one embodiment, the method further comprises: the method for generating the second target time comprises the following steps:
the baseboard management controller responds to the clock synchronization request sent by the component end;
and acquiring the time when the baseboard management controller responds to the clock synchronization request, and defining the time as the second target time.
In one embodiment, the method further comprises: before said calculating a standard target time based on said first target time, said second target time and said third target time, said method further comprises:
acquiring a sending request time and a response request time;
and determining a preset algorithm for calculating a standard target moment according to the sending request time and the response request time.
In one embodiment, the method further comprises: the preset algorithm for determining the calculation standard target time according to the sending request time and the response request time comprises the following steps:
in response to detecting that the sending request time and the response request time are symmetrical, calculating the standard target moment by adopting a first preset algorithm;
and in response to detecting that the sending request time and the response request time are asymmetric, calculating the standard target moment by adopting a second preset algorithm.
In one embodiment, the method further comprises: the first preset algorithm comprises the following steps:
T＝T3+(T1-T0)/2
wherein T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, and T3 represents the second target time.
In one embodiment, the method further comprises: the second preset algorithm comprises the following steps:
wherein, T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, T3 represents the second target time, tresponse-min represents the minimum response time, and Trequest-min represents the shortest request time.
In one embodiment, the method further comprises: the method for acquiring the sending request time and the response request time comprises the following steps:
acquiring the starting sending time of the clock synchronization request and the successful sending time of the clock synchronization request, and calculating the difference value of the starting sending time and the successful sending time of the clock synchronization request to obtain the sending request time;
and obtaining the starting time of responding to the clock synchronization request and the ending time of responding to the clock synchronization request, and calculating the difference value of the starting time and the ending time of the clock synchronization request to obtain the response request time.
In another aspect, there is provided a component clock synchronizing device, the device comprising:
the response module is used for responding to the component clock synchronization instruction and sending a clock synchronization request to the baseboard management controller by the component end;
the first target time acquisition module is used for acquiring the first target time of the clock synchronization request sent by the component end;
the second target time acquisition module is used for receiving a second target time returned by the baseboard management controller in response to the clock synchronization request;
a third target time acquisition module, configured to acquire a third target time when the component end receives the second target time returned by the baseboard management controller;
a standard target time calculation module, configured to calculate a standard target time based on the first target time, the second target time, and the third target time;
and the clock synchronization module is used for carrying out clock synchronization on the component end according to the standard target moment.
In yet another aspect, a computer device is provided comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of:
responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end;
acquiring a first target moment when the component end sends out a clock synchronization request;
receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request;
acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller;
calculating a standard target time based on the first target time, the second target time and the third target time;
and carrying out clock synchronization on the component end according to the standard target moment.
In yet another aspect, a computer readable storage medium is provided, having stored thereon a computer program which when executed by a processor performs the steps of:
responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end;
acquiring a first target moment when the component end sends out a clock synchronization request;
receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request;
acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller;
calculating a standard target time based on the first target time, the second target time and the third target time;
and carrying out clock synchronization on the component end according to the standard target moment.
The component clock synchronization method, the device, the computer equipment and the storage medium, wherein the method comprises the following steps: responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end; acquiring a first target moment when the component end sends out a clock synchronization request; receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request; acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller; calculating a standard target time based on the first target time, the second target time and the third target time; according to the method and the device, clock synchronization is carried out on the component ends according to the standard target time, the difference of physical clocks caused by time drift of different components can be effectively reduced, the logic problem caused by time desynchronization is avoided, and the server is enabled to be in the best working performance.
Drawings
FIG. 1 is an application environment diagram of a component clock synchronization method in one embodiment;
FIG. 2 is a flow diagram of a component clock synchronization method in one embodiment;
FIG. 3 is another flow diagram of a component clock synchronization method in one embodiment;
FIG. 4 is a block diagram of the components clock synchronization device in one embodiment;
fig. 5 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It should be understood that throughout this description, unless the context clearly requires otherwise, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
It should also be appreciated that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
It should be noted that the terms "S1", "S2", and the like are used for the purpose of describing steps only, and are not intended to be limited to the order or sequence of steps or to limit the present application, but are merely used for convenience in describing the method of the present application and are not to be construed as indicating the sequence of steps. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.
According to the background technology, the prior art has the technical problems that due to the structural difference between the components, different time drift occurs after the components run for a period of time, so that a certain difference exists between the physical clocks of different components, the sequence of events A may be later than that of events B, the sent time stamp is smaller than that of events B, if the state synchronization is involved, the data of B can cover the data of A, and the problem is more remarkable when the components are synchronized.
In order to solve the technical problems, the application provides a component clock synchronization method, a device, computer equipment and a storage medium, so that the difference of physical clocks of different components caused by time drift is effectively reduced, the logic problem caused by time asynchronization is avoided, and the server is enabled to be in the best working performance.
The component clock synchronization method provided by the application can be applied to an application environment shown in fig. 1. The terminal 102 communicates with a data processing platform disposed on the server 104 through a network, where the terminal 102 may be, but is not limited to, various personal computers, notebook computers, smartphones, tablet computers, and portable wearable devices, and the server 104 may be implemented by a stand-alone server or a server cluster composed of a plurality of servers.
Example 1: in one embodiment, as shown in fig. 2-3, a component clock synchronization method is provided, and the method is applied to the terminal in fig. 1 for illustration, and includes the following steps:
s1: responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end;
s2: acquiring a first target moment when the component end sends out a clock synchronization request;
s3: receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request;
s4: acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller;
s5: calculating a standard target time based on the first target time, the second target time and the third target time;
s6: and carrying out clock synchronization on the component end according to the standard target moment.
It should be noted that, in some embodiments, the component clock synchronization instruction may be triggered periodically according to the actual requirement and according to the first time length, where the first time length may be set according to the actual requirement, for example, 20 minutes, so as to perform the clock synchronization operation in a circulating manner; component clock synchronization may also be performed in a single pass.
In some embodiments, in response to the component clock synchronization instruction, acquiring a first target time when a component end sends a clock synchronization request, and a second target time and a third target time corresponding to the first target time, including:
as shown in fig. 3, the component end is a Client end (end initiating a request) where each component is located, each component refers to an external high-performance component such as an intelligent network card, a JBOD card and the like, and the external high-performance component has its own system to perform various responses and logic processes independently, and performs information interaction with a baseboard management controller through communication modes such as a network, a serial port or an IPMB, where the baseboard management controller refers to an OpenBMC (open source-based baseboard management controller), and the OpenBMC is used as a Server end (service end) to provide a standard synchronization time for clock synchronization of other components.
Further, the method for acquiring the second target time corresponding to the first target time includes:
the baseboard management controller responds to the clock synchronization request sent by the component end;
and acquiring the time when the baseboard management controller responds to the clock synchronization request, and defining the time as the second target time.
The method for acquiring the third target time corresponding to the first target time comprises the following steps:
the component end receives a response result of the baseboard management controller;
and acquiring the receiving time of the response result, and defining the receiving time as a third target time.
Specifically, when a component clock synchronization instruction is detected, each component of the Client initiates a clock synchronization request to the OpenBMC, the time of the request sending is recorded as a first target time T0, the OpenBMC responds to the clock synchronization request sent by the Client, an OpenBMC response time, namely a second target time T3, is added to a request packet, and the request packet is returned to the Client, and the Client defines the time of receiving the OpenBMC response request packet as a third target time T1.
In some embodiments, calculating a standard target time using a preset algorithm based on the first target time, the second target time, and a third target time includes:
it should be noted that, the preset algorithm in the present application may be Cristian algorithm (kriging An Suanfa), and before calculating the standard target time by using the preset algorithm, the method further includes:
acquiring a sending request time and a response request time;
in response to detecting that the sending request time and the response request time are symmetrical, calculating the standard target moment by adopting a first preset algorithm;
and in response to detecting that the sending request time and the response request time are asymmetric, calculating the standard target moment by adopting a second preset algorithm.
The method for acquiring the sending request time and the response request time comprises the following steps:
acquiring the starting sending time of the clock synchronization request and the sending success time of the clock synchronization request, and calculating the difference value of the starting sending time and the sending success time of the clock synchronization request to obtain the sending request time Trequest, wherein the Client terminal prints a time stamp after starting sending the request instruction and printing the time stamp again after the sending request instruction is successful, and the difference value of the two time stamps is the sending request time Trequest;
obtaining the starting time of responding to the clock synchronization request and the ending time of responding to the clock synchronization request, and calculating the difference value of the starting time and the ending time of responding to the clock synchronization request to obtain the response request time Tresponse, wherein the Server end prints a time stamp when responding to the request instruction, and the time stamp is printed again after responding to the request instruction success, and the difference value of the two time stamps is the response request time Tresponse.
Further, the method for judging whether the sending request time and the responding request time are symmetrical is as follows:
ideally, the sending request time Trequest is basically the same as the response request time Tresponse, but if the OpenBMC is performing other communication or data processing when sending the request, the system time is occupied, the sending request time Trequest is prolonged, and when the sending request time Trequest is not equal to the response request time Tresponse, the sending request time and the response request time are judged to be asymmetric; when the transmission request time Trequest and the response request time Tresponse are equal, judging that the transmission request time and the response request time are symmetrical.
Still further, the first preset algorithm includes:
T＝T3+(T1-T0)/2
wherein T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, and T3 represents the second target time.
The second preset algorithm comprises the following steps:
wherein, T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, T3 represents the second target time, tresponse-min represents the minimum response time, and Trequest-min represents the shortest request time.
The minimum response time and the shortest request time can be obtained through actual iterative test, and the specific method comprises the following steps:
and other operations are not carried out among the components, namely the Client end and the Server end do not carry out other processes, only basic instructions are sent and received, and the minimum value is obtained through testing in a pressure testing mode.
In some embodiments, clock synchronizing the component ends according to the standard target time comprises:
according to the calculated standard target time, synchronizing physical clocks of all components of the Client end, so that the time of each component is identical to the OpenBMC time, and the processing logic problem caused by the fact that the clock time of each component is not synchronous is avoided.
In the above component clock synchronization method, the method includes: periodically triggering a component clock synchronization instruction according to the first time length; responding to the component clock synchronization instruction, and acquiring a first target time when a component end sends out a clock synchronization request, and a second target time and a third target time corresponding to the first target time; calculating a standard target time by using a preset algorithm based on the first target time, the second target time and the third target time; and responding to the standard target moment, and performing clock synchronization operation on the component end to complete single clock synchronization on the component end.
It should be understood that, although the steps in the flowchart of fig. 2 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 2 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
Example 2: in one embodiment, as shown in fig. 4, there is provided a component clock synchronization apparatus, comprising: the system comprises a response module, a first target time acquisition module, a second target time acquisition module, a third target time acquisition module, a standard target time calculation module and a clock synchronization module, wherein:
the response module is used for responding to the component clock synchronization instruction and sending a clock synchronization request to the baseboard management controller by the component end;
the first target time acquisition module is used for acquiring the first target time of the clock synchronization request sent by the component end;
the second target time acquisition module is used for receiving a second target time returned by the baseboard management controller in response to the clock synchronization request;
a third target time acquisition module, configured to acquire a third target time when the component end receives the second target time returned by the baseboard management controller;
a standard target time calculation module, configured to calculate a standard target time based on the first target time, the second target time, and the third target time;
and the clock synchronization module is used for carrying out clock synchronization on the component end according to the standard target moment.
In a preferred embodiment of the present invention, the second target time acquisition module is specifically further configured to:
the baseboard management controller responds to the clock synchronization request sent by the component end;
and acquiring the time when the baseboard management controller responds to the clock synchronization request, and defining the time as the second target time.
As a preferred implementation manner, in the embodiment of the present invention, the apparatus further includes a judging module, where the judging module is specifically configured to:
acquiring a sending request time and a response request time;
and determining a preset algorithm for calculating a standard target moment according to the sending request time and the response request time.
As a preferred implementation manner, in the embodiment of the present invention, the apparatus further includes a judging module, where the judging module is specifically further configured to:
in response to detecting that the sending request time and the response request time are symmetrical, calculating the standard target moment by adopting a first preset algorithm;
in response to detecting that the sending request time and the response request time are asymmetric, calculating the standard target moment by adopting a second preset algorithm;
the first preset algorithm comprises the following steps:
T＝T3+(T1-T0)/2
wherein T represents a synchronous clock time, T1 represents a third target time, T0 represents a first target time, and T3 represents a second target time;
the second preset algorithm comprises the following steps:
wherein, T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, T3 represents the second target time, tresponse-min represents the minimum response time, and Trequest-min represents the shortest request time.
As a preferred implementation manner, in the embodiment of the present invention, the apparatus further includes a judging module, where the judging module is specifically further configured to:
acquiring the starting sending time of the clock synchronization request and the successful sending time of the clock synchronization request, and calculating the difference value of the starting sending time and the successful sending time of the clock synchronization request to obtain the sending request time;
and obtaining the starting time of responding to the clock synchronization request and the ending time of responding to the clock synchronization request, and calculating the difference value of the starting time and the ending time of the clock synchronization request to obtain the response request time.
For specific limitations of the component clock synchronization apparatus, reference may be made to the above limitation of the component clock synchronization method, and no further description is given here. The various modules in the component clock synchronization apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
Example 3: in one embodiment, a computer device is provided, which may be a terminal, and the internal structure of which may be as shown in fig. 5. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a component clock synchronization method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the structure shown in fig. 5 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of when executing the computer program:
s1: responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end;
s2: acquiring a first target moment when the component end sends out a clock synchronization request;
s3: receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request;
s4: acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller;
s5: calculating a standard target time based on the first target time, the second target time and the third target time;
s6: and carrying out clock synchronization on the component end according to the standard target moment.
In one embodiment, the processor when executing the computer program further performs the steps of:
the baseboard management controller responds to the clock synchronization request sent by the component end;
and acquiring the time when the baseboard management controller responds to the clock synchronization request, and defining the time as the second target time.
In one embodiment, the processor when executing the computer program further performs the steps of:
acquiring a sending request time and a response request time;
and determining a preset algorithm for calculating a standard target moment according to the sending request time and the response request time.
In one embodiment, the processor when executing the computer program further performs the steps of:
in response to detecting that the sending request time and the response request time are symmetrical, calculating the standard target moment by adopting a first preset algorithm;
in response to detecting that the sending request time and the response request time are asymmetric, calculating the standard target moment by adopting a second preset algorithm;
wherein, the first preset algorithm comprises:
T＝T3+(T1-T0)/2
wherein T represents a synchronous clock time, T1 represents a third target time, T0 represents a first target time, and T3 represents a second target time;
the second preset algorithm comprises the following steps:
wherein, T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, T3 represents the second target time, tresponse-min represents the minimum response time, and Trequest-min represents the shortest request time.
In one embodiment, the processor when executing the computer program further performs the steps of:
acquiring the starting sending time of the clock synchronization request and the successful sending time of the clock synchronization request, and calculating the difference value of the starting sending time and the successful sending time of the clock synchronization request to obtain the sending request time;
and obtaining the starting time of responding to the clock synchronization request and the ending time of responding to the clock synchronization request, and calculating the difference value of the starting time and the ending time of the clock synchronization request to obtain the response request time.
Example 4: in one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
s1: responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end;
s2: acquiring a first target moment when the component end sends out a clock synchronization request;
s3: receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request;
s4: acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller;
s5: calculating a standard target time based on the first target time, the second target time and the third target time;
s6: and carrying out clock synchronization on the component end according to the standard target moment.
In one embodiment, the computer program when executed by the processor further performs the steps of:
the baseboard management controller responds to the clock synchronization request sent by the component end;
and acquiring the time when the baseboard management controller responds to the clock synchronization request, and defining the time as the second target time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring a sending request time and a response request time;
and determining a preset algorithm for calculating a standard target moment according to the sending request time and the response request time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
in response to detecting that the sending request time and the response request time are symmetrical, calculating the standard target moment by adopting a first preset algorithm;
in response to detecting that the sending request time and the response request time are asymmetric, calculating the standard target moment by adopting a second preset algorithm;
wherein, the first preset algorithm comprises:
T＝T3+(T1-T0)/2
wherein T represents a synchronous clock time, T1 represents a third target time, T0 represents a first target time, and T3 represents a second target time;
the second preset algorithm comprises the following steps:
wherein, T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, T3 represents the second target time, tresponse-min represents the minimum response time, and Trequest-min represents the shortest request time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring the starting sending time of the clock synchronization request and the successful sending time of the clock synchronization request, and calculating the difference value of the starting sending time and the successful sending time of the clock synchronization request to obtain the sending request time;
and obtaining the starting time of responding to the clock synchronization request and the ending time of responding to the clock synchronization request, and calculating the difference value of the starting time and the ending time of the clock synchronization request to obtain the response request time.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application.
Claims (10)
1. A method of component clock synchronization, the method comprising:
responding to a component clock synchronization instruction, and sending a clock synchronization request to a baseboard management controller by a component end;
acquiring a first target moment when the component end sends out a clock synchronization request;
receiving a second target moment returned by the baseboard management controller in response to the clock synchronization request;
acquiring a third target moment when the component end receives the second target moment returned by the baseboard management controller;
calculating a standard target time based on the first target time, the second target time and the third target time;
and carrying out clock synchronization on the component end according to the standard target moment.
2. The component clock synchronization method according to claim 1, wherein the second target time generation method includes:
the baseboard management controller responds to the clock synchronization request sent by the component end;
and acquiring the time when the baseboard management controller responds to the clock synchronization request, and defining the time as the second target time.
3. The component clock synchronization method according to claim 1 or 2, characterized in that before the calculating of a standard target time based on the first target time, the second target time and the third target time, the method further comprises:
acquiring a sending request time and a response request time;
and determining a preset algorithm for calculating a standard target moment according to the sending request time and the response request time.
4. A component clock synchronization method according to claim 3, wherein the predetermined algorithm for determining a calculation standard target time according to the transmission request time and the response request time comprises:
in response to detecting that the sending request time and the response request time are symmetrical, calculating the standard target moment by adopting a first preset algorithm;
and in response to detecting that the sending request time and the response request time are asymmetric, calculating the standard target moment by adopting a second preset algorithm.
5. The component clock synchronization method of claim 4, wherein the first preset algorithm comprises:
T＝T3+(T1-T0)/2
wherein T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, and T3 represents the second target time.
6. The component clock synchronization method of claim 4, wherein the second preset algorithm comprises:
wherein, T represents the synchronous clock time, T1 represents the third target time, T0 represents the first target time, T3 represents the second target time, tresponse-min represents the minimum response time, and Trequest-min represents the shortest request time.
7. The component clock synchronization method of claim 3, wherein the method of acquiring the transmission request time and the response request time comprises:
acquiring the starting sending time of the clock synchronization request and the successful sending time of the clock synchronization request, and calculating the difference value of the starting sending time and the successful sending time of the clock synchronization request to obtain the sending request time;
and obtaining the starting time of responding to the clock synchronization request and the ending time of responding to the clock synchronization request, and calculating the difference value of the starting time and the ending time of the clock synchronization request to obtain the response request time.
8. A component clock synchronization apparatus, the apparatus comprising:
the response module is used for responding to the component clock synchronization instruction and sending a clock synchronization request to the baseboard management controller by the component end;
the first target time acquisition module is used for acquiring the first target time of the clock synchronization request sent by the component end;
the second target time acquisition module is used for receiving a second target time returned by the baseboard management controller in response to the clock synchronization request;
a third target time acquisition module, configured to acquire a third target time when the component end receives the second target time returned by the baseboard management controller;
a standard target time calculation module, configured to calculate a standard target time based on the first target time, the second target time, and the third target time;
and the clock synchronization module is used for carrying out clock synchronization on the component end according to the standard target moment.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 7 when the computer program is executed by the processor.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310380655.5A CN116466795A (en) | 2023-04-11 | 2023-04-11 | Component clock synchronization method, device, computer equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310380655.5A CN116466795A (en) | 2023-04-11 | 2023-04-11 | Component clock synchronization method, device, computer equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116466795A true CN116466795A (en) | 2023-07-21 |
Family
ID=87183703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310380655.5A Pending CN116466795A (en) | 2023-04-11 | 2023-04-11 | Component clock synchronization method, device, computer equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116466795A (en) |
-
2023
- 2023-04-11 CN CN202310380655.5A patent/CN116466795A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107733708B (en) | Equipment parameter configuration method and device, computer equipment and storage medium | |
| CN109753418B (en) | Performance test method and device, computer equipment and storage medium | |
| CN108446172B (en) | Data calling method and device, computer equipment and storage medium | |
| EP3605422A1 (en) | Transaction control device, transaction control method | |
| WO2021042733A1 (en) | Blockchain transaction processing method and apparatus, computer device, and storage medium | |
| CN110267060B (en) | Video file storage injection method and device, computer equipment and storage medium | |
| CN111290919A (en) | Log file generation method and device, computer equipment and storage medium | |
| CN110866011B (en) | Data table synchronization method and device, computer equipment and storage medium | |
| CN113886496A (en) | Data synchronization method and device of block chain, computer equipment and storage medium | |
| CN108241616B (en) | Message pushing method and device | |
| CN116466795A (en) | Component clock synchronization method, device, computer equipment and storage medium | |
| CN112698987A (en) | On-line backup method, device, equipment and storage medium for snapshot-free operating system | |
| CN111966530A (en) | Disaster recovery switching method and device for application system, computer equipment and storage medium | |
| CN110519789B (en) | Performance detection method, device, computer equipment and storage medium | |
| CN112818021B (en) | Data request processing method, device, computer equipment and storage medium | |
| CN113556200A (en) | Clock calibration method, and network security protection method and device based on clock synchronization | |
| CN115509861A (en) | Process monitoring method, system, computer device and storage medium | |
| US9686206B2 (en) | Temporal based collaborative mutual exclusion control of a shared resource | |
| CN112800123A (en) | Data processing method, data processing device, computer equipment and storage medium | |
| CN114328711A (en) | Data processing method and device, computer equipment and storage medium | |
| US10528432B2 (en) | Off-site backup network disk | |
| RU2750642C2 (en) | System and method for registering a unique mobile device identifier | |
| US20120136837A1 (en) | Information processing method and information processing apparatus | |
| CN111158609B (en) | Data storage method and device, computer equipment and storage medium | |
| CN110704218B (en) | Data processing method, data processing device, computer equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |