CN116456807A - SOT-MRAM memory cell and preparation method thereof - Google Patents
SOT-MRAM memory cell and preparation method thereof Download PDFInfo
- Publication number
- CN116456807A CN116456807A CN202310450021.2A CN202310450021A CN116456807A CN 116456807 A CN116456807 A CN 116456807A CN 202310450021 A CN202310450021 A CN 202310450021A CN 116456807 A CN116456807 A CN 116456807A
- Authority
- CN
- China
- Prior art keywords
- layer
- memory cell
- hard mask
- heavy metal
- tunnel junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 214
- 230000005291 magnetic effect Effects 0.000 claims abstract description 64
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 150000002500 ions Chemical class 0.000 claims abstract description 28
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 230000007547 defect Effects 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000002885 antiferromagnetic material Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052748 manganese Inorganic materials 0.000 claims description 8
- 239000011572 manganese Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- OQCGPOBCYAOYSD-UHFFFAOYSA-N cobalt palladium Chemical compound [Co].[Co].[Co].[Pd].[Pd] OQCGPOBCYAOYSD-UHFFFAOYSA-N 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 239000000395 magnesium oxide Substances 0.000 claims description 5
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 5
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- -1 silicon carbide nitride Chemical class 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- ZDZZPLGHBXACDA-UHFFFAOYSA-N [B].[Fe].[Co] Chemical compound [B].[Fe].[Co] ZDZZPLGHBXACDA-UHFFFAOYSA-N 0.000 claims description 3
- QAAXRTPGRLVPFH-UHFFFAOYSA-N [Bi].[Cu] Chemical compound [Bi].[Cu] QAAXRTPGRLVPFH-UHFFFAOYSA-N 0.000 claims description 3
- FHKNFXAIEAYRKQ-UHFFFAOYSA-N [Cu].[Ir] Chemical compound [Cu].[Ir] FHKNFXAIEAYRKQ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 229910052790 beryllium Inorganic materials 0.000 claims description 3
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 3
- JWVAUCBYEDDGAD-UHFFFAOYSA-N bismuth tin Chemical compound [Sn].[Bi] JWVAUCBYEDDGAD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- RYTYSMSQNNBZDP-UHFFFAOYSA-N cobalt copper Chemical compound [Co].[Cu] RYTYSMSQNNBZDP-UHFFFAOYSA-N 0.000 claims description 3
- VLWBWEUXNYUQKJ-UHFFFAOYSA-N cobalt ruthenium Chemical compound [Co].[Ru] VLWBWEUXNYUQKJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- WVBBLATZSOLERT-UHFFFAOYSA-N gold tungsten Chemical compound [W].[Au] WVBBLATZSOLERT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 3
- SHMWNGFNWYELHA-UHFFFAOYSA-N iridium manganese Chemical compound [Mn].[Ir] SHMWNGFNWYELHA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- DALUDRGQOYMVLD-UHFFFAOYSA-N iron manganese Chemical compound [Mn].[Fe] DALUDRGQOYMVLD-UHFFFAOYSA-N 0.000 claims description 3
- SORXVYYPMXPIFD-UHFFFAOYSA-N iron palladium Chemical compound [Fe].[Pd] SORXVYYPMXPIFD-UHFFFAOYSA-N 0.000 claims description 3
- OBACEDMBGYVZMP-UHFFFAOYSA-N iron platinum Chemical compound [Fe].[Fe].[Pt] OBACEDMBGYVZMP-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- QEBDLIWRLCPLCY-UHFFFAOYSA-N selanylidenebismuth Chemical compound [Bi]=[Se] QEBDLIWRLCPLCY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052714 tellurium Inorganic materials 0.000 claims description 3
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000005415 magnetization Effects 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000010354 integration Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/20—Spin-polarised current-controlled devices
Abstract
The application belongs to the technical field of memory devices, and particularly relates to an SOT-MRAM memory cell and a preparation method thereof. The memory cell in this application contains the substrate, locates the heavy metal layer of substrate surface, and the magnetic tunnel junction that forms on heavy metal layer to and be located the hard mask of magnetic tunnel junction top, this magnetic tunnel junction contains free layer, barrier layer, reference layer and the pinning reference layer of range upon range of, and wherein, reference layer, pinning reference layer and hard mask constitute the cylinder, still are formed with the protective layer at the cylinder periphery. The memory cell is provided with a large-area free layer which is not covered by a hard mask, doped ions are conveniently implanted, and magnetization inversion of the free layer can be effectively driven on the premise that circuit complexity is not required to be additionally increased and short circuit of a device is not easy to cause.
Description
Technical Field
The application belongs to the technical field of memory devices, and particularly relates to an SOT-MRAM memory cell and a preparation method thereof.
Background
With the rapid development of spintronics, spin-Orbit Coupling (SOC) is receiving more and more attention, and mainly includes Spin hall effect, interface Edelstein effect and inverse effect thereof, and can realize the interconversion of voltage-controllable current and Spin flow. And Spin-Orbit Torque (SOT) is based on the SOC effect, and Spin transfer Torque is generated by utilizing Spin current induced by charge current, so that the purpose of regulating and controlling the magnetic memory unit is achieved. The read-write path is separated, so that the magnetic head has the advantages of low energy consumption, high write-in speed, strong magnetic moment reversibility, high efficiency, high stability and the like, and has great prospect in the fields of magnetic memory devices and the like.
Spin-orbit rectangular magnetic random access memory (SOT-MRAM) is an information writing mode by utilizing SOT generated by self-rotational flow, so that excellent characteristics of high speed, low power consumption and the like of the MRAM are maintained, separation of read-write paths is realized, and the performances of breakdown resistance, long service life and the like of the device are improved.
At present, for SOT-MRAM (solid state memory) taking a magnetic tunnel junction with excellent performance and perpendicular magnetic anisotropy as a basic memory cell, deterministic directional magnetization inversion cannot be realized by using independent spin orbit moment, and deterministic magnetic moment inversion and information writing of a perpendicular free layer in the magnetic tunnel junction can be realized with the help of an external magnetic field in a specific direction. However, the introduction of the externally applied magnetic field increases the complexity and reliability risk of the circuit, which is disadvantageous for the integration of the device.
Disclosure of Invention
The technical purpose of the application is to at least solve the problem that the SOT-MRAM device can not realize magnetization inversion of the driving free layer under the condition of effective integration without an external magnetic field.
The aim is achieved by the following technical scheme:
in a first aspect, the present application provides an SOT-MRAM memory cell comprising:
a substrate;
the heavy metal layer is arranged on the surface of the substrate;
a hard mask positioned above the heavy metal layer;
the magnetic tunnel junction is arranged between the heavy metal layer and the hard mask;
the magnetic tunnel junction includes a stacked free layer, barrier layer, reference layer, and pinned reference layer;
the reference layer, the pinning reference layer and the hard mask form a column body, and a protective layer is formed on the periphery of the column body.
The memory cell is provided with a large-area free layer which is not covered by a hard mask, so that doping ions are conveniently injected, and magnetization inversion of the free layer is easier to drive.
In some embodiments of the present application, the cylinder is at least one of a cylinder, an elliptical cylinder, or a polygonal prism;
preferably a cylinder.
In some embodiments of the present application, there are defects in the magnetic tunnel junction that are more abundant on one side of the magnetic tunnel junction than on the other side in the direction of current flow in the heavy metal layer.
In some embodiments of the present application, the defect is generated by implanting dopant ions.
In some embodiments of the present application, the dopant ions comprise at least one of nitrogen, arsenic, argon, phosphorus, boron, or beryllium.
In some embodiments of the present application, the memory cell further includes a channel disposed on the substrate for receiving an external circuit.
In some embodiments of the present application, the free layer and the reference layer are magnetic layers, and the magnetic layer material comprises one or more of cobalt, iron, cobalt palladium, iron palladium, manganese gallium, cobalt iron boron, iron platinum;
the barrier layer is an oxide layer, and the oxide layer material comprises magnesium oxide;
the pinning reference layer is made of a manganese-based antiferromagnetic material or a multilayer film artificial antiferromagnetic material, wherein the manganese-based antiferromagnetic material comprises iridium manganese and/or iron manganese, and the multilayer film artificial antiferromagnetic material comprises one or more than two of cobalt, palladium, copper, ruthenium, cobalt palladium, cobalt copper or cobalt ruthenium.
In some embodiments of the present application, the heavy metal layer is a metal layer or a topological insulator layer;
the metal layer material comprises one or more than two of tantalum, platinum, tungsten, hafnium, iridium, copper bismuth, copper iridium or gold tungsten;
the topological insulator layer material comprises one or more than two of bismuth tin, tin tellurium or bismuth selenium;
the hard mask material comprises tantalum and/or ruthenium;
the protective layer material comprises one or more than two of silicon nitride, silicon carbide, silicon oxynitride and silicon carbide nitride.
In a second aspect, the present application provides a method for fabricating an SOT-MRAM memory cell, comprising:
providing a substrate;
forming a heavy metal layer on the substrate;
forming a free layer, a barrier layer, a reference layer and a pinning reference layer on the heavy metal layer;
forming a hard mask on the surface of the pinning reference layer;
patterning from the hard mask surface toward the free layer until the barrier layer surface stops to form a magnetic tunnel junction;
implanting doping ions along one side of the magnetic tunnel junction;
and forming a protective layer on the peripheries of the reference layer, the pinning reference layer and the hard mask.
According to the preparation method, the patterning treatment is stopped on the surface of the barrier layer, the probability that the barrier layer is attached with metal and then the device is easy to cause short circuit is effectively relieved, the device integration is facilitated, meanwhile, the free layer is provided with a large-area free layer which is not covered by a hard mask, doping ions are conveniently injected into the free layer, one side defect of a magnetic tunnel junction can be redundant to the other side defect after ion injection, and therefore a transverse asymmetric magnetic tunnel junction structure is formed in the direction perpendicular to a current source, and when current is introduced into a heavy metal layer, magnetization overturning of the free layer is easy to realize.
In some embodiments of the present application, the implantation direction of the dopant ions has an angle α with respect to the vertical direction of the substrate, preferably 0 ° < α < 90 °.
In some embodiments of the present application, the vertical direction of the substrate is the coordinate axis z direction.
In some embodiments of the present application, the patterning comprises a photolithography process that includes forming a photoresist on the hard mask surface, the photolithography stopping until the barrier layer surface.
In some embodiments of the present application, the forming modes of the free layer, the barrier layer, the reference layer and the pinned reference layer include any one of a sputtering method and a deposition method; the deposition method includes atomic layer deposition or physical vapor deposition.
In some embodiments of the present application, the method further comprises etching from the surface of the protective layer toward the heavy metal layer for forming a channel for accommodating an external circuit.
The beneficial effects of the technical scheme disclosed by the application are mainly shown as follows:
1. the memory cell provided by the application is provided with the free layer which is large in area and is not covered by the hard mask, doped ions are conveniently injected, and magnetization inversion of the driving free layer is easier to realize.
2. According to the preparation method of the memory cell, the patterning treatment is stopped on the surface of the barrier layer, so that the probability of short circuit of a device caused by metal adhesion of the barrier layer is effectively relieved, and the integration of the device is facilitated.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 schematically illustrates a schematic structure of a prior art SOT-MRAM device; wherein, a magnetic field is applied in the y direction of the coordinate axis;
FIG. 2 schematically illustrates a schematic structure of a prior art SOT-MRAM device; wherein the etching process is stopped on the heavy metal layer;
FIG. 3 schematically illustrates a schematic structure of an SOT-MRAM memory cell in accordance with an embodiment of the present application;
FIG. 4 schematically illustrates a schematic structure of an SOT-MRAM memory cell in accordance with an embodiment of the present application;
fig. 5 schematically shows a top view of fig. 4;
FIG. 6 schematically illustrates a schematic structure of an SOT-MRAM memory cell in accordance with an embodiment of the present application;
fig. 7 schematically illustrates a process flow diagram for fabricating an SOT-MRAM memory cell according to an embodiment of the present application.
The reference numerals in the drawings are as follows:
100. a substrate;
200. a heavy metal layer;
300. a magnetic tunnel junction; 310. a free layer; 320. a barrier layer; 330. a reference layer; 340. pinning a reference layer;
400. a hard mask;
500. a protective layer;
600. a channel;
A. a column; a', the area of the column body; B. an ion implantation region; C. ion regions are not implanted.
Coordinate axis x direction: the length or width direction of the memory cell;
coordinate axis y direction: the width or length direction of the memory cell;
coordinate axis z direction: the thickness or height direction of the memory cell.
Shorthand and term interpretation:
SOT-MRAM: a spin-orbit torque based magnetic random access memory;
MTJ: a magnetic tunnel junction;
sub: a substrate; heavy metal: heavy metals; BARC: a bottom antireflective coating; PR: and (3) photoresist patterns.
Detailed Description
In the prior art, to achieve the directional magnetization inversion of the spin-orbit torque, an external magnetic field is generally applied in a specific direction, as shown in fig. 1, and a magnetic field is applied in the x-axis direction to break the symmetry of the structure, and the current flowing through the heavy metal layer induces a moment to drive the magnetization inversion of the free layer, however, this way increases the complexity of the circuit, reduces the thermal stability of the ferromagnetic layer, and is not beneficial to integration.
In order to solve the above-mentioned problem, fig. 2 discloses that in the prior art, defects are caused by ion implantation into the magnetic tunnel junction, and because the magnetic tunnel junction itself is shielded, one side defect of the magnetic tunnel junction can be redundant to the other side defect after ion implantation, thereby forming a laterally asymmetric magnetic tunnel junction structure in a direction perpendicular to the current source, and realizing magnetization inversion of the driving free layer when current is introduced into the heavy metal layer.
The ion implantation method drives magnetization inversion of the free layer, but in the specific preparation, the etching process is mainly stopped on the heavy metal layer, metal is easily attached to the magnesium oxide barrier layer in the etching process, the device is easily short-circuited, the free layer in the magnetic tunnel junction is covered by the hard mask, and very effective ion implantation cannot be realized, so that the magnetization inversion of the free layer is limited.
In order to solve the technical problems, the application provides an SOT-MRAM memory cell, which comprises a substrate, a heavy metal layer, a magnetic tunnel junction and a hard mask, wherein the hard mask and a reference layer in the magnetic tunnel junction and a pinning reference layer form a column body, so that a free layer is not covered by the hard mask, and doping ions are conveniently and effectively injected. The free layer has vertical magnetization with fixed direction, the magnetic moment of the free layer is provided by a heavy metal layer positioned below the free layer, the heavy metal layer can generate spin orbit moment after current is introduced, when the defect content formed in the magnetic tunnel junction by ion implantation is inconsistent and the magnetic tunnel junction structure is asymmetric, the spin orbit moment drives the free layer to turn over directionally, and the direction of magnetization of the free layer or the reference layer is the same or opposite, and the storage data of 0 or 1 is written into the storage device for realizing effective storage of the data. Because the memory cell is provided with the large-area free layer which is not covered by the hard mask, doping ions can be effectively injected, and the directional magnetization inversion of the driving free layer is easier to realize.
The electronic device comprising the SOT-MRAM memory cell described above may be any of a cell phone, a computer, a media player, a personal digital assistant, an industrial Internet of things, a robot, a medical device, an artificial intelligence, an automotive and portable design, and a wearable electronic device.
In order to achieve the above technical effects, as can be seen from fig. 3, 4 and 5, the memory cell includes a substrate 100, a heavy metal layer 200 disposed on the surface of the substrate 100, a magnetic tunnel junction 300 formed on the heavy metal layer 200, and a hard mask 400 disposed above the magnetic tunnel junction 300, wherein the magnetic tunnel junction 300 includes a free layer 310, a barrier layer 320, a reference layer 330 and a pinned reference layer 340, the reference layer 330, the pinned reference layer 340 and the hard mask 400 form a pillar a, and a protective layer 500 is further formed on the periphery of the pillar a. As is apparent from fig. 5, only a partial region of the magnetic tunnel junction 300, i.e., region C, is not ion doped, and other regions of the free layer are ion doped, so the memory cell of the present application has a free layer with a large area that is not masked by a hard mask.
In some embodiments, defects are present in the magnetic tunnel junction and the content of defects on one side of the magnetic tunnel junction is greater than on the other side along the direction of current flow in the heavy metal layer.
The defects are generated by implanting doping ions, wherein conventional doping ions comprise at least one of nitrogen, arsenic, argon, phosphorus, boron or beryllium, and the direction of the implanting doping ions is controlled to realize that the defect content of one side of a magnetic tunnel junction along the current direction in a heavy metal layer is more than that of the other side, so that the spatial symmetry of a free layer is broken to realize that spin orbit moment drives the free layer to directionally flip. Because the memory cell designed by the application has the free layer which is large in area and is not covered by the hard mask, doping ions are conveniently injected, and the directional magnetization inversion of the free layer is easier to realize.
In some embodiments, the column a may be at least one of a cylinder, an elliptic cylinder or a polygonal prism, which is preferred in the present application, and the shape of the column a is affected by the manufacturing process and the device integration, which is not described in detail in the present application.
In some embodiments, the memory cell further includes a channel disposed on the substrate for receiving an external circuit. As can be seen from fig. 4 and 6, the preferred channel 600 is a trench formed between the protective layer 500 and the heavy metal layer 200, the trench is formed by etching, and is beneficial to photoetching after subsequent deposition of Tetraethylorthosilicate (TEOS), and metal electrodes are filled in the via holes for connection with an external circuit.
In some embodiments, the free layer and the reference layer are magnetic layers, and the magnetic layer material includes, but is not limited to, any one of cobalt, iron, cobalt palladium, iron palladium, manganese gallium, cobalt iron boron, iron platinum.
In some embodiments, the barrier layer is an oxide layer, the oxide layer material including, but not limited to, magnesium oxide, preferably magnesium oxide.
In some embodiments, the pinned reference layer employs a manganese-based antiferromagnetic material including but not limited to iridium manganese or iron manganese or a multilayer film artificial antiferromagnetic material including but not limited to any of cobalt, palladium, copper, ruthenium, cobalt palladium, cobalt copper or cobalt ruthenium.
In some embodiments, the heavy metal layer is a metal layer or a topological insulator layer, wherein the metal layer material includes, but is not limited to, any of tantalum, platinum, tungsten, hafnium, iridium, copper bismuth, copper iridium, or gold tungsten, and the topological insulator layer material includes, but is not limited to, any of bismuth tin, tin tellurium, or bismuth selenium.
In some embodiments, the hard mask material includes, but is not limited to, any of tantalum, ruthenium, and the hard mask may be a single layer structure or a multi-layer composite structure.
In some embodiments, the protective layer material includes, but is not limited to, any of silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride.
In some embodiments, the substrate material is a material conventional in the art, preferably silicon dioxide.
In a second aspect, the present application provides a method for preparing the SOT-MRAM memory cell, which includes the following steps:
s01, providing a substrate;
s02, forming a heavy metal layer on the substrate;
s03, forming a free layer, a barrier layer, a reference layer and a pinning reference layer on the heavy metal layer;
s04, forming a hard mask on the surface of the pinning reference layer;
s05, patterning from the surface of the hard mask towards the direction of the free layer until the surface of the barrier layer is stopped, so as to form a magnetic tunnel junction;
s06, implanting doping ions along one side of the magnetic tunnel junction;
s07, forming a protective layer on the peripheries of the reference layer, the pinning reference layer and the hard mask.
According to the preparation method, the patterning treatment is stopped on the surface of the barrier layer, the probability that the barrier layer is attached with metal and then the device is easy to cause short circuit is effectively relieved, the device integration is facilitated, meanwhile, the free layer is provided with a large-area free layer which is not covered by a hard mask, doping ions are conveniently injected into the free layer, one side defect of a magnetic tunnel junction can be redundant to the other side defect after ion injection, and therefore a transverse asymmetric magnetic tunnel junction structure is formed in the direction perpendicular to a current source, and when current is introduced into a heavy metal layer, magnetization overturning of the free layer is easy to realize.
In some embodiments, the implantation direction of the doped ions and the vertical direction of the substrate have an included angle α, where the vertical direction of the substrate is preferably the direction of the coordinate axis z, and the included angle α is preferably 0 ° < α < 90 °, such as 40 °, 45 °, 50 °, 60 °, or any value satisfying a range value, as shown in fig. 4.
In some embodiments, the patterning comprises a photolithography process that includes forming a photoresist on the hard mask surface, the photolithography stopping until the barrier layer surface.
In some embodiments, the formation of the free layer, the barrier layer, the reference layer, and the pinned reference layer includes any one of sputtering and deposition; wherein the deposition method comprises atomic layer deposition or physical vapor deposition.
In some embodiments, the heavy metal layer is formed by a method including, but not limited to, sputtering, physical vapor deposition, or molecular beam epitaxy, preferably, the heavy metal layer is formed on a silicon dioxide substrate using the above method.
Sputtering, deposition, and molecular beam epitaxy include any of the forms conventional in the art.
In some embodiments, the method further includes etching a surface of the self-protective layer toward the heavy metal layer to form a channel for accommodating an external circuit.
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example 1
The preparation method of the SOT-MRAM memory cell is provided, and as can be seen from FIG. 7, the preparation method comprises the following steps:
(a) Providing a silicon dioxide substrate;
(b) Depositing and growing a heavy metal layer on one side of the silicon dioxide substrate, wherein the thickness of the heavy metal layer can meet the range value;
(c) Forming a free layer, a barrier layer, a reference layer and a pinning reference layer on the heavy metal layer,
(d) Forming a hard mask on the surface of the pinning reference layer;
(e) Coating a bottom reflecting coating on the surface of the hard mask, and coating photoresist on the surface of the bottom reflecting coating;
(f) Photoetching from the surface of the hard mask towards the direction of the free layer until the surface of the barrier layer is stopped, so as to form a magnetic tunnel junction; the reference layer, the pinning reference layer and the hard mask form a column A, and the free layer is provided with a large-area which is not shielded by the hard mask;
(g) Doping ions are injected along one side of the magnetic tunnel junction, an included angle alpha is formed between the injection direction of the doping ions and the vertical direction of the substrate, the included angle alpha meets the conditions that alpha is smaller than 90 degrees and 0 degrees, and any angle can be selected in the embodiment;
(h) Forming a silicon nitride protective layer on the periphery of the reference layer, the pinning reference layer and the hard mask, wherein the forming mode of the silicon nitride protective layer comprises any mode conventional in the art;
(i) Etching channels for accommodating external circuits on two sides of the silicon nitride protective layer, the barrier layer, the free layer and the heavy metal layer along the direction of the silicon nitride protective layer towards the heavy metal layer; wherein the etching process comprises any form conventional in the art.
Further comprising forming a thin film over the surface of the memory cell by subsequent deposition of tetraethyl orthosilicate (TEOS), and continuing photolithography to form vias for filling metal electrodes for connection to external circuitry, thereby completing the interconnection of the device, including any conventional form in the art. Therefore, the preparation method of the memory cell stops patterning treatment on the surface of the barrier layer, effectively relieves the probability of easily causing short circuit of the device due to the adhesion of metal on the barrier layer, and is more convenient for device integration.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.
The foregoing is merely a preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An SOT-MRAM memory cell, comprising:
a substrate;
the heavy metal layer is arranged on the surface of the substrate;
a hard mask positioned above the heavy metal layer;
the magnetic tunnel junction is arranged between the heavy metal layer and the hard mask;
the magnetic tunnel junction includes a stacked free layer, barrier layer, reference layer, and pinned reference layer;
the reference layer, the pinning reference layer and the hard mask form a column body, and a protective layer is formed on the periphery of the column body.
2. The memory cell of claim 1, wherein the pillar is at least one of a cylinder, an elliptical pillar, or a polygonal prism;
preferably a cylinder.
3. The memory cell of claim 1 wherein a defect is present in the magnetic tunnel junction, the defect being present in the heavy metal layer more on one side of the magnetic tunnel junction than on the other side in the direction of current flow in the heavy metal layer;
the defects are created by implanting dopant ions.
4. The memory cell of claim 3, wherein the dopant ions comprise at least one of nitrogen, arsenic, argon, phosphorus, boron, or beryllium.
5. The memory cell of any of claims 1-4, further comprising a channel provided in the substrate for receiving an external circuit.
6. The memory cell of any one of claims 1-4, wherein the free layer and the reference layer are magnetic layers, the magnetic layer material comprising one or a combination of more than two of cobalt, iron, cobalt palladium, iron palladium, manganese gallium, cobalt iron boron, iron platinum;
the barrier layer is an oxide layer, and the oxide layer material comprises magnesium oxide;
the pinning reference layer is made of a manganese-based antiferromagnetic material or a multilayer film artificial antiferromagnetic material, wherein the manganese-based antiferromagnetic material comprises iridium manganese and/or iron manganese, and the multilayer film artificial antiferromagnetic material comprises one or more than two of cobalt, palladium, copper, ruthenium, cobalt palladium, cobalt copper or cobalt ruthenium.
7. The memory cell of any one of claims 1-4, wherein the heavy metal layer is a metal layer or a topological insulator layer;
the metal layer material comprises one or more than two of tantalum, platinum, tungsten, hafnium, iridium, copper bismuth, copper iridium or gold tungsten;
the topological insulator layer material comprises one or more than two of bismuth tin, tin tellurium or bismuth selenium;
the hard mask material comprises any one of tantalum and/or ruthenium;
the protective layer material comprises one or more than two of silicon nitride, silicon carbide, silicon oxynitride and silicon carbide nitride.
8. A method for fabricating an SOT-MRAM memory cell, comprising:
providing a substrate;
forming a heavy metal layer on the substrate;
forming a free layer, a barrier layer, a reference layer and a pinning reference layer on the heavy metal layer;
forming a hard mask on the surface of the pinning reference layer;
patterning from the hard mask surface toward the free layer until the barrier layer surface stops to form a magnetic tunnel junction;
implanting doping ions along one side of the magnetic tunnel junction;
and forming a protective layer on the peripheries of the reference layer, the pinning reference layer and the hard mask.
9. A method of manufacturing a memory cell according to claim 8, characterized in that the direction of implantation of the dopant ions is at an angle α, preferably 0 ° < α < 90 °, to the vertical direction of the substrate.
10. The method for manufacturing a memory cell according to any one of claims 8 to 9, wherein,
the patterning comprises a photoetching process, wherein the photoetching process comprises the steps of forming photoresist on the surface of a hard mask, and photoetching until the surface of a barrier layer is stopped;
the formation modes of the free layer, the barrier layer, the reference layer and the pinning reference layer comprise any one of a sputtering method and a deposition method; the deposition method comprises atomic layer deposition or physical vapor deposition;
the preparation method further comprises the step of etching the surface of the protective layer towards the heavy metal layer to form a channel for accommodating an external circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310450021.2A CN116456807A (en) | 2023-04-24 | 2023-04-24 | SOT-MRAM memory cell and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310450021.2A CN116456807A (en) | 2023-04-24 | 2023-04-24 | SOT-MRAM memory cell and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116456807A true CN116456807A (en) | 2023-07-18 |
Family
ID=87123610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310450021.2A Pending CN116456807A (en) | 2023-04-24 | 2023-04-24 | SOT-MRAM memory cell and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116456807A (en) |
-
2023
- 2023-04-24 CN CN202310450021.2A patent/CN116456807A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8368133B2 (en) | Memory constructions comprising magnetic materials | |
| US8125040B2 (en) | Two mask MTJ integration for STT MRAM | |
| US20140015080A1 (en) | Stt mram magnetic tunnel junction architecture and integration | |
| US20140175581A1 (en) | Magnetoresistive element having a novel cap multilayer | |
| CN108713261A (en) | For the method and obtained structure that Hall MTJ device is embedded in logic processor that will spin | |
| KR102338319B1 (en) | Magnetic memory device and method for manufacturing the same | |
| US8592928B2 (en) | Magnetic random access memory and method of manufacturing the same | |
| US9583698B2 (en) | Magnetoresistive element having a novel recording multilayer | |
| JP2012019163A (en) | Magnetic random access memory and method for manufacturing the same | |
| US11386951B2 (en) | Multi-level magnetic tunnel junction (MTJ) devices including mobile magnetic skyrmions or ferromagnetic domains | |
| US7374952B2 (en) | Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof | |
| US10943950B2 (en) | Magnetic memory devices with enhanced tunnel magnetoresistance ratio (TMR) and methods of fabrication | |
| JP6985220B2 (en) | Manufacturing method of magnetic tunnel junction element, magnetic memory using it, and magnetic tunnel junction element | |
| TW202013367A (en) | Compound free layer for memory device | |
| JP2005515625A (en) | Resistive memory device having reduced roughness | |
| JP2009064826A (en) | Spin transistor and its manufacturing method | |
| US9997565B2 (en) | Magnetic memory element and magnetic memory | |
| US20090052237A1 (en) | Magnetic memory device and magnetic memory apparatus | |
| US20200313074A1 (en) | Magnetic memory devices and methods of fabrication | |
| CN116456807A (en) | SOT-MRAM memory cell and preparation method thereof | |
| US20220044718A1 (en) | Stt-sot hybrid magnetoresistive element and manufacture thereof | |
| US11682514B2 (en) | Memory cell having a free ferromagnetic material layer with a curved, non-planar surface and methods of making such memory cells | |
| US10937958B2 (en) | Magnetoresistive element having a novel cap multilayer | |
| CN110660906A (en) | Magnetic memory device | |
| KR20030073371A (en) | A magnetic random access memory to use diode fabricated by MILC ( metal-induced lateral crystallization ) and a method for the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |