CN116455557A

CN116455557A - Device and reset method for hash operation

Info

Publication number: CN116455557A
Application number: CN202310403067.9A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Biren Intelligent Technology Co Ltd
Priority date: 2023-04-14
Filing date: 2023-04-14
Publication date: 2023-07-18

Abstract

The present disclosure provides an apparatus and a reset method for hash operations. Wherein the device comprises: an arithmetic unit electrically connected to the configuration unit and the reset unit, respectively, the arithmetic unit configured to perform a hash operation according to configuration information from the configuration unit and reset in response to an enabled arithmetic unit reset signal of the reset unit; a configuration unit configured to generate configuration information; and a reset unit configured to cause the operation unit reset signal to be enabled according to the alarm signal from the operation unit. In the device, after the operation unit is reset, hash operation can be directly carried out according to the configuration information of the configuration unit, and the process of reconfiguring the configuration information of the configuration unit can be omitted, so that the speed of carrying out hash operation again by the operation unit is obviously increased, and the execution efficiency of the hash operation is improved.

Description

Device and reset method for hash operation

Technical Field

Embodiments of the present disclosure relate generally to the field of hash operation technology, and more particularly, to an apparatus and a reset method for hash operation.

Background

Based on a Hash (i.e., hashing) algorithm, input data having an arbitrary length (i.e., ha Xiyuan data) can be converted into output data having a fixed length (i.e., a Hash value). In a conventional hash operation system, the hash operation system performs hash operation in a pre-configured pattern. When resetting the hash system, the preconfigured mode is also reset due to the reset operation. Therefore, after the reset of the hash operation system is completed, the hash operation system needs to be reconfigured so that the hash operation system performs hash operation according to the configured mode. The time consumed by the above reconfiguration process may reduce the execution efficiency of the hash operation.

Disclosure of Invention

In view of the foregoing, the present disclosure provides an apparatus and a reset method for hash operation, which can save configuration time after reset, so as to improve execution efficiency of hash operation.

According to a first aspect of the present disclosure, an apparatus for hash operations is provided. The device comprises: an arithmetic unit electrically connected to the configuration unit and the reset unit, respectively, the arithmetic unit configured to perform a hash operation according to configuration information from the configuration unit and reset in response to an enabled arithmetic unit reset signal of the reset unit; a configuration unit configured to generate configuration information; and a reset unit configured to cause the operation unit reset signal to be enabled according to the alarm signal from the operation unit.

In some embodiments, the arithmetic unit comprises: a host device module electrically connected to the hash operation module and the reset unit, respectively, the host device module configured to send a hash data request to the reply module, and to suspend sending the hash data request in response to the enabled operation unit reset signal, the reply module configured to reply according to the hash data request; and a hash operation module electrically connected to the configuration unit, the main device module, and the reset unit, respectively, configured to perform a hash operation according to the configuration information and Ha Xiyuan data from the main device module, and reset in response to an enabled operation unit reset signal.

In some embodiments, the arithmetic unit further comprises: the response monitoring module is respectively and electrically connected with the reset unit and the main equipment module, and is configured to determine whether the response module completes response to the hash data request and generate a response completion signal in response to determining that the response module completes response to the hash data request; the reset unit is further configured to cause the main device module to be reset in accordance with the enabled arithmetic unit reset signal and the reply completion signal.

In some embodiments, the answer monitoring module comprises: a request reply counter configured to cause the count value to change in a first direction after each transmission of the hash data request by the host device module, and to cause the count value to change in a second direction after each reply by the reply module, the first direction being opposite to the second direction; and a response completion signal generation module configured to generate a response completion signal when the count value of the request response counter meets a predetermined condition.

In some embodiments, the answer monitoring module further comprises: a request suspension module configured to cause a request suspension signal to be enabled when a count value of the request reply counter is equal to a predetermined count threshold, such that the master device module suspends sending the hash data request in response to the enabled request suspension signal.

In some embodiments, the apparatus further comprises: a first bus electrically connected to the configuration unit, the first bus being for accessing the configuration unit according to a predetermined access pattern; and an alarm unit configured to determine whether the access to the configuration unit via the first bus meets a predetermined access pattern, and to generate alarm information in response to determining that the access to the configuration unit via the first bus does not meet the predetermined access pattern.

In some embodiments, the apparatus further comprises: the second bus is electrically connected with the main equipment module and the response module respectively; and the master device module is further configured to send the hash data request to the reply module via a second bus having a transmission rate greater than the transmission rate of the first bus.

In some embodiments, the reset unit includes: a register write operation module configured to write a predetermined value to the reset register according to the alarm signal from the operation unit; a flip module configured to cause a value stored in the reset register to be flipped when the reset register is written with a predetermined value; and a reset enable module configured to enable the arithmetic unit reset signal in response to the value stored by the reset register being flipped.

In some embodiments, the reset enable module is further configured to generate a pulse signal in response to the value stored by the reset register being toggled, and to cause the arithmetic unit reset signal to be enabled according to the pulse signal.

In some embodiments, the host device module is further configured to send a hash data read request or a hash data write request to the reply module according to a predetermined state machine.

In some embodiments, the reset unit is further configured to cause the arithmetic unit reset signal to be enabled in accordance with configuration information from the configuration unit.

According to a second aspect of the present disclosure, there is provided a reset method implemented with an apparatus according to the first aspect of the present disclosure. The method comprises the following steps: generating configuration information at a configuration unit; performing hash operation at the operation unit according to the configuration information from the configuration unit; at the reset unit, enabling an arithmetic unit reset signal in accordance with the alert signal from the arithmetic unit; and at the arithmetic unit, being reset in response to an enabled arithmetic unit reset signal of the reset unit.

In some embodiments, the arithmetic unit includes a master device module and a hash operation module; at the operation unit, performing hash operation according to the configuration information from the configuration unit, including: at the host device module, sending a hash data request to the reply module to obtain Ha Xiyuan data; and performing, at the hash operation module, a hash operation according to the configuration information and Ha Xiyuan data from the master device module; at an arithmetic unit, reset in response to an enabled arithmetic unit reset signal of a reset unit, comprising: suspending, at the master device module, sending the hash data request in response to the enabled arithmetic unit reset signal; and at the hash operation module, being reset in response to the enabled operation unit reset signal.

In some embodiments, the arithmetic unit further comprises a response monitor module; the method further comprises the steps of: at the reply monitoring module, determining whether the reply to the hash data request is completed by the reply module, and generating a reply completion signal in response to determining that the reply to the hash data request is completed by the reply module; at the reset unit, causing the arithmetic unit reset signal to be enabled in accordance with the alert signal from the arithmetic unit, comprising: at the reset unit, the main device module is reset according to the enabled arithmetic unit reset signal and the answer completion signal.

In some embodiments, the reply monitoring module includes a request reply counter and a reply completion signal generation module; at the reply monitoring module, determining whether the reply to the hash data request is completed by the reply module, and generating a reply completion signal in response to determining that the reply to the hash data request is completed by the reply module, comprising: at the request reply counter, changing the counter value in a first direction after each transmission of the hash data request by the master device module, and in a second direction after each reply by the reply module, the first direction being opposite to the second direction; and generating, at the answer completion signal generation module, an answer completion signal when the count value of the request answer counter meets a predetermined condition.

In some embodiments, the reply monitoring module further includes a request pause module; the method further comprises the steps of: at the request suspension module, a request suspension signal is enabled when the count value of the request reply counter is equal to a predetermined count threshold, such that the master module suspends sending the hash data request in response to the enabled request suspension signal.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements.

Fig. 1 shows a block schematic diagram of an apparatus for hash operations of an embodiment of the present disclosure.

Fig. 2 shows a block schematic diagram of an apparatus for hash operations of an embodiment of the present disclosure.

Fig. 3 shows a block schematic diagram of a reset unit of an embodiment of the present disclosure.

Fig. 4 shows a flowchart of a reset method of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, in the conventional hash operation system, when an error (including, for example, but not limited to, a bus error, a padding information error, etc.) occurs in the hash operation system, it is necessary to reset the hash operation system. During the reset process, the preconfigured mode may also be reset due to the reset operation, for example, the configuration registers in the configuration hash system are reset. Therefore, after the hash operation system is reset, the hash operation system needs to be reconfigured, for example, configuration information is written into a configuration register, so that the hash operation system is configured into a desired mode by using the configuration register, and thus hash operation is performed. The above reconfiguration process requires a long time, which significantly reduces the execution efficiency of the hash operation.

To at least partially address one or more of the above problems, as well as other potential problems, example embodiments of the present disclosure propose an apparatus for hash operations. In an aspect of the disclosure, the apparatus for hash operation includes an operation unit, a configuration unit, and a reset unit, where the operation unit is configured to perform hash operation, the configuration unit is configured to generate configuration information to configure the operation unit, the reset unit is configured to enable an operation unit reset signal according to an alarm signal from the operation unit, and the enabled operation unit reset signal is configured to enable the operation unit to be reset. Therefore, after the operation unit is reset, the hash operation can be directly carried out according to the configuration information of the configuration unit, and the process of reconfiguring the configuration information of the configuration unit can be omitted, so that the speed of the operation unit for carrying out the hash operation again is obviously increased, and the execution efficiency of the hash operation is improved.

The apparatus for hash operation according to the embodiment of the present disclosure is described in detail below.

Fig. 1 shows a block schematic diagram of an apparatus 100 for hash operations according to an embodiment of the disclosure. The apparatus 100 comprises an arithmetic unit 102, a configuration unit 104 and a reset unit 106. The arithmetic unit 102 is electrically connected to the configuration unit 104 and the reset unit 106, respectively, the arithmetic unit 102 being configured to perform a hash operation according to configuration information from the configuration unit 104 and to be reset in response to an enabled arithmetic unit reset signal of the reset unit 106. The configuration unit 104 is configured to generate configuration information. The reset unit 106 is configured to enable the arithmetic unit reset signal in accordance with the alert signal from the arithmetic unit 102.

Regarding the configuration unit 104, it includes, for example, a configuration register for storing configuration information. The configuration unit 104 is for example connected to a bus through which the target device can access the configuration unit 104. The access to the configuration unit 104 may be, for example, a read operation or a write operation. Writing to the configuration unit 104 may enable configuration of the configuration unit 104 such that the configuration unit 104 stores desired configuration information to cause the operation unit 102 to perform hash operations in a desired pattern. The configuration information may include, for example, hash length information and the like.

Regarding the operation unit 102, it may acquire Ha Xiyuan data from a target device, for example, and hash Ha Xiyuan the data according to configuration information from the configuration unit 104 to generate a hash value. The arithmetic unit 102 may also output a hash value, for example. The arithmetic unit 102 may also generate, for example, an alarm signal. For example, the arithmetic unit 102 may acquire Ha Xiyuan data from the target device via the bus, and in the process of the arithmetic unit 102 acquiring Ha Xiyuan data, if a bus error or the like occurs, the arithmetic unit 102 generates an alarm signal. For example, in the course of hash operation by the operation unit 102, if a padding error or the like occurs, the operation unit 102 generates an alarm signal. For example, the arithmetic unit 102 may output the hash value to the target device through the bus, and in the process of the arithmetic unit 102 outputting the hash value, if a bus error or the like occurs, the arithmetic unit 102 generates an alarm signal. The alarm signal can be a level signal or a pulse signal, and can be reasonably selected according to application scenes.

Regarding the reset unit 106, it enables an arithmetic unit reset signal, for example, in accordance with an alarm signal from the arithmetic unit 102. The reset unit 106 may be implemented by, for example, a combinational logic circuit (combinational logic circuit) or a sequential logic circuit (sequential logic circuit). In some embodiments, the reset unit 106 is implemented as a preferred option using sequential logic circuitry. The reset unit 106, for example, causes the arithmetic unit reset signal to be disabled in a default state, and the reset unit 106 causes the arithmetic unit reset signal to be enabled in response to the alarm signal from the arithmetic unit 102. The enabled arithmetic unit reset signal may be a level signal, for example, the enabled arithmetic unit reset signal is a high level signal and the disabled arithmetic unit reset signal is a low level signal. The enabled arithmetic unit reset signal may also be a pulse signal. For example, the reset unit 106 causes the arithmetic unit reset signal to remain low to be in an unset state, and the reset unit 106 causes the arithmetic unit reset signal to form a positive pulse signal such that the positive pulse signal corresponds to the enabled arithmetic unit reset signal. The pulse width of the positive pulse signal may satisfy a predetermined duration, such as one or more clock cycles, where the clock cycle may be the clock cycle corresponding to the clock signal employed by the reset unit 106.

The arithmetic unit 102 is reset in response to the enabled arithmetic unit reset signal.

In some embodiments, the arithmetic unit 102 includes, for example, a master device module and a hash operation module. The host device module is respectively and electrically connected with the hash operation module and the reset unit, the host device module is configured to send a hash data request to the response module, and the response module is configured to respond according to the hash data request by suspending sending the hash data request in response to the enabled operation unit reset signal; the hash operation module is electrically connected to the configuration unit, the master device module, and the reset unit 106, respectively, and is configured to perform a hash operation according to the configuration information and Ha Xiyuan data from the master device module, and to be reset in response to an enabled operation unit reset signal.

In some embodiments, the computing unit 102 further includes, for example, a reply monitor module electrically coupled to the reset unit 106 and the host device module, respectively, the reply monitor module configured to determine whether the reply to the hash data request is completed by the reply module, and to generate a reply completion signal in response to determining that the reply to the hash data request is completed by the reply module. The reset unit 106 is further configured to cause the main device module to be reset in accordance with the enabled arithmetic unit reset signal and the reply completion signal.

In some embodiments, the apparatus 100 further comprises, for example, a first bus and an alarm unit. The first bus is electrically connected with the configuration unit 104, and the first bus is used for accessing the configuration unit 104 according to a predetermined access mode; the alarm unit is configured to determine whether the access to the configuration unit 104 via the first bus meets a predetermined access pattern and to generate alarm information in response to determining that the access to the configuration unit 104 via the first bus does not meet the predetermined access pattern.

In some embodiments, the apparatus 100 further comprises, for example, a second bus electrically connected to the master device module and the answering module, respectively; the host device module is further configured to send a hash data request to the reply module via the second bus, the transmission rate of the second bus is greater than the transmission rate of the first bus.

In the above-described scheme, the configuration unit may not be reset when the operation unit is reset, and therefore, the configuration information stored by the configuration unit is not necessarily reset because the operation unit is reset. Therefore, in this case, the operation unit can be configured into a desired mode according to the configuration information of the configuration unit immediately after completion, and the process of requiring reconfiguration of the configuration unit because the configuration unit is reset can be omitted, thereby significantly accelerating the speed of the operation unit to perform the hash operation again, so as to improve the execution efficiency of the hash operation.

Fig. 2 shows a block schematic diagram of an apparatus 200 for hash operations according to an embodiment of the disclosure. The computing unit 102 includes, for example, a master device module 122 and a hash operation module 124. The master device module 122 is electrically connected to the hash operation module 124 and the reset unit 106, respectively, and the master device module 122 is configured to send a hash data request to the reply module 302 and to suspend sending the hash data request in response to an enabled operation unit reset signal. The hash operation module 124 is electrically connected to the configuration unit 104, the master module 124, and the reset unit 106, respectively, and is configured to perform a hash operation according to the configuration information and Ha Xiyuan data from the master module 122, and to be reset in response to an enabled operation unit reset signal.

The apparatus 200 also includes, for example, a second bus 202, the second bus 202 being electrically connected to the master device module 122 and the reply module 302, respectively. The master module 122 is further configured to send a hash data request to the reply module 302 via the second bus 202.

Regarding the main device module 122, it may be implemented using, for example, an MCU (Micro Controller Unit, micro control unit), a CPU (Central Processing Unit ), a GPU (Graphics Processing Unit, graphics processor), a GPGPU (General-purpose Computing on Graphics Processing Units, general-purpose graphics processor), an FPGA (Field Programmable Gate Array ), and an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), or the like.

The master module 122 may send a hash data request to the reply module 302 via the second bus 202. The response module 302 stores Ha Xiyuan data. The master device module 122 sends a hash read request to the answering module 302 to read Ha Xiyuan data from the answering module 302; after receiving the hash read request, the reply module 302 transmits Ha Xiyuan the data to the master module 122 via the second bus 202.

In some embodiments, ha Xiyuan is longer in length, and the host module 122 sends a hash read request to the reply module 302 multiple times according to a predetermined state machine, each time a portion of Ha Xiyuan data is read, and complete Ha Xiyuan data is obtained through multiple read operations.

The hash operation module 124 performs a hash operation according to the configuration information from the configuration unit 104 and the Ha Xiyuan data from the master device module 122, and generates a hash value. The hash operation module 124 may notify the master device module 122, for example, in the form of an interrupt signal after the hash operation is completed. After receiving the interrupt signal, the master device module 122 sends a hash data write request to the reply module 302 via the second bus 202 to write the hash value to the reply module 302. In some embodiments, the configuration registers of the configuration unit 104 include a status register corresponding to the status of the hash operation module 124, for storing status information of the hash operation module 124. After the hash operation module 124 completes the hash operation to obtain the hash value, the hash operation module 124 may, for example, write a corresponding value into the status register of the configuration unit 104 in the form of an interrupt, so that the status information stored in the status register of the hash operation module 124 characterizes the hash operation module 124 to complete the hash operation. In some embodiments, configuration unit 104 may be accessed via first bus 204 (e.g., configuration unit 104 may be read via first bus 204), and thus, an associated device or module coupled to first bus 204 may access configuration unit 104 via first bus 204 to obtain the state information of hash operation module 124. In some embodiments, the master device module 122 sends the hash data write request to the answering module 302 multiple times according to a predetermined state machine, transmitting a portion of the hash value to the answering module 302 at a time, and transmitting the complete hash value to the answering module 302 through multiple write operations.

The hash operation module 124 is, for example, a hardware accelerator that exclusively performs hash operations. The hash operation module 124 generates and outputs a hash value through operations such as padding, message expansion, iterative compression, output, and the like. For example, in the stuffing operation, if a stuffing information error occurs, the hash operation module 124 generates an alarm signal. For example, in the message expansion operation, if an expansion error occurs, the hash operation module 124 generates an alarm signal. For example, in an iterative compression operation, if a compression error occurs, the hash module 124 generates an alert signal.

In the above scheme, after the operation unit 102 generates the alarm signal, the hash operation module 124 is reset in response to the enabled operation unit reset signal. In order to achieve the stability of the overall operation of the apparatus 200, the master device module 122 may not be reset according to the enabled arithmetic unit reset signal, but may cause the master device module 122 to suspend sending the hash data request in response to the enabled arithmetic unit reset signal. For example, when the computing unit 102 generates the alert signal, the master device module 122 has issued some of the plurality of hash data read requests for acquiring Ha Xiyuan data, such that the master device module 122 suspending sending the hash data requests (e.g., not continuing to send the remaining hash data read requests of the plurality of hash data read requests for acquiring Ha Xiyuan data) may reduce the time required for the computing unit 102 as a whole to complete the reset. Similarly, when the computing unit 102 generates the alert signal, the master device module 122 has issued some of the plurality of hash data write requests for outputting the hash value, such that the master device module 122 suspending sending the hash data requests (e.g., not continuing to send the remaining hash data write requests of the plurality of hash data write requests for outputting the hash value) may reduce the time required for the computing unit 102 as a whole to complete the reset.

The arithmetic unit 102 also comprises, for example, a response monitor module 126. The reply monitoring module 126 is electrically connected to the reset unit 106 and the master device module 122, respectively, and the reply monitoring module 126 is configured to determine whether the reply module 302 has completed replying to the hash data request, and to generate a reply completion signal in response to determining that the reply module 302 has completed replying to the hash data request. The reset unit 106 is further configured to cause the main device module 122 to be reset in accordance with the enabled arithmetic unit reset signal and the reply completion signal.

The reply monitoring module 126 includes, for example, a request reply counter 162 and a reply completion signal generation module 164. The request reply counter 162 is configured to cause the count value to change in a first direction after each transmission of a hash data request by the master device module 122 and to cause the count value to change in a second direction after each reply by the reply module 302, the first direction being opposite the second direction. The answer completion signal generation module 164 is configured to generate an answer completion signal when the count value of the request answer counter 162 meets a predetermined condition. In some embodiments, the request reply counter 162 includes, for example, a read request reply counter corresponding to a hash data read request, and a write request reply counter corresponding to a hash data write request.

For example, in retrieving Ha Xiyuan data, the master module 122 sends a hash data read request to the reply module 302 in multiple passes according to a predetermined state machine. For each hash data request sent by the master module 122, the request reply counter 162 increments its count value by 1. For example, for each hash data read request sent by the master module 122, the read request reply counter increments its count value by 1.

For each hash data request sent by the master device module 122, the reply module 302 responds with a reply operation. For example, for each hash data read request sent by the host module 122, the reply module 302 responds to the hash data read request and transmits to the host module 122 via the second bus 202 the data (e.g., ha Xiyuan data, or a portion of Ha Xiyuan data) that the host module 122 desires to read, and the reply module 302 also transmits to the host module 122 via the second bus 202 a reply signal that may indicate that the reply module 302 responded to the present hash data request. Request reply counter 162 may, for example, have its count value decremented by 1 in response to a reply signal from reply module 302. For example, in response to the reply signal of the reply module 302 to the hash data read request, the read request reply counter decrements its count value by 1.

It should be noted that, after each sending the hash data read request, the master device module 122 may wait for the response module 302 to send the hash data read request again after feeding back the response signal for the hash data read request. The master device module 122 may send out the hash data read request again after sending out the hash data read request each time without waiting for the response module 302 to feed back the response signal for the hash data read request.

When the count value of the request reply counter 162 is zero, indicating that all hash data requests issued by the master device module 122 have been replied to, the reply completion signal generation module 164 generates a reply completion signal. For example, when the count value of the read request reply counter is zero, indicating that all hash data read requests issued by the master device module 122 have been replied, the reply completion signal generation module 164 generates a reply completion signal.

For example, in transmitting the hash value, the master device module 122 sends a hash data write request to the reply module 302 in multiple times according to a predetermined state machine. For each hash data request sent by the master module 122, the request response counter 162 increases its count value by 1. For example, for each hash data write request sent by the master module 122, the write request reply counter increments its count value by 1.

For each hash data request sent by the master device module 122, the reply module 302 responds with a reply operation. For example, for each hash data write request sent by the host module 122, after the reply module 302 receives the data (e.g., is a hash value, or a portion of a hash value) written by the host module 122 via the second bus 202, the reply module 302 also transmits a reply signal to the host module 122 via the second bus 202, which may indicate that the reply module 302 responded to the current hash data request. Request reply counter 162 may, for example, have its count value decremented by 1 in response to a reply signal from reply module 302. For example, in response to the reply signal of the reply module 302 to the hash data write request, the write request reply counter decrements its count value by 1.

It should be noted that, after each time a hash data write request is issued, the master device module 122 may wait for the response module 302 to feedback a response signal for the hash data write request, and issue the hash data write request again. The master device module 122 may send out the hash data write request again after sending out the hash data write request each time without waiting for the response module 302 to feed back the response signal for the hash data write request.

It should be noted that, the computing unit 102 generates the alarm signal with randomness. After the arithmetic unit 102 generates the alarm signal, the hash operation module 124 needs to be reset, and thus, the hash operation module 124 is reset in response to the enabled arithmetic unit reset signal. Considering that the host device module 122 may have issued one or more requests for hash data when the alert signal occurs, and that the reply module 302 has not yet completely replied to completion, the reply module 302 will reply at a later time, i.e., there is still a "data residual" between the host device module 122 and the reply module 302. If the host module 122 is also reset at this time, it may cause the host module 122 to reset to complete the re-operation, and receive the response of the response module 302 to the one or more hash data requests that have been sent by the host module 122 before the reset, which will affect the normal operation of the host module 122. Accordingly, in the above scheme, after the operation unit 102 generates the alarm signal, the hash operation module 124 is reset in response to the enabled operation unit reset signal. For the stability of the overall operation of the apparatus 200, the master device module 122 does not have to be reset according to the enabled arithmetic unit reset signal, but rather causes the master device module 122 to suspend sending hash data requests in response to the enabled arithmetic unit reset signal to avoid "backlog" of subsequent invalid hash data requests at the reply module 302. And, the reply monitoring module 126 determines whether the reply module completed replying to the hash data request and generates a reply completion signal in response to determining that the reply module 302 completed replying to the hash data request. The reset unit 106 causes the main device module 122 to be reset according to the enabled arithmetic unit reset signal and the answer completion signal. That is, after the hash data requests sent by the master device module 122 are all acknowledged by the acknowledgement module 302, the master device module 122 is reset, so that the condition of "data residue" is effectively avoided from affecting the normal operation of the master device module 122.

In some embodiments, the reply monitoring module 126 further includes a request suspension module 166, the request suspension module 166 being configured to cause a request suspension signal to be enabled when the count value of the request reply counter 162 is equal to a predetermined count threshold, such that the master device module 122 suspends sending hash data requests in response to the enabled request suspension signal. When the count value of the request reply counter 162 is equal to the predetermined count threshold, it is indicated that, among the hash data requests issued by the master device module 122, the number of hash data requests for which the reply module 302 has not yet made a reply has reached the predetermined count threshold. In this case, the request suspension signal is enabled so that the master device module 122 suspends sending the hash data request in response to the enabled request suspension signal, so that it is possible to avoid further increase in the hash data request that has not yet been responded at the response module 302, thereby effectively controlling the time taken for waiting for the response module 302 to complete the response to increase the rate at which the operation unit 102 completes the reset when the alarm signal occurs and the operation unit 102 needs to be reset, so as to increase the execution efficiency of the hash operation performed by the operation unit 102.

In implementation, a read count threshold may be set for the read request response counter as a predetermined count threshold corresponding to the read request response counter. The request pause module 166 causes the request pause signal to be enabled when the count value of the read request reply counter is equal to a predetermined count threshold. Similarly, a write count threshold is set for the write request reply counter as a predetermined count threshold corresponding to the write request reply counter. The request pause module 166 causes the request pause signal to be enabled when the count value of the write request reply counter is equal to a predetermined count threshold.

The apparatus 200 further comprises, for example, a first bus 204, an alarm unit 206. The first bus 204 is electrically connected to the configuration unit 104, the first bus 204 being adapted to access the configuration unit according to a predetermined access pattern; the alarm unit 206 is configured to determine whether the access to the configuration unit 104 via the first bus 204 meets a predetermined access pattern and to generate alarm information in response to determining that the access to the configuration unit 104 via the first bus 204 does not meet the predetermined access pattern.

The first bus 204 may be electrically connected to an external device that may access the configuration unit 104, e.g., the external device may write to the configuration unit 104 via the first bus 204 to configure the configuration unit 104 such that the configuration unit 104 stores configuration information. The first bus 204 may be, for example, an APB (Advanced Peripheral Bus, peripheral bus) bus. The first bus 204 is configured in a secure mode, i.e. the external device should access the configuration unit 104 via the first bus 204 according to the protocol to which the secure mode corresponds. If the access of the external device does not conform to the protocol corresponding to the security mode, the alarm unit 206 determines that the access to the configuration unit 104 via the first bus 204 does not conform to the predetermined access mode, and generates alarm information. For example, when the configuration unit 104 is read in a manner not conforming to the security mode, the read data is alarm information "DEADBEEF" generated by the alarm unit 206, and each bit in the alarm information is a 16-ary number. For the setting of alarm information, on one hand, related users (such as research and development engineers) can conveniently search, locate and find fault defects; on the other hand, the operation of non-secure access cannot obtain the configuration information stored in the configuration unit 104, and the configuration information stored in the configuration unit 104 cannot be modified, so that the security of the operation unit 102 is effectively ensured.

In some embodiments, the transmission rate of the second bus 202 is greater than the transmission rate of the first bus 204. For example, the first bus 204 is an APB bus and the second bus 202 is an AXI (Advanced eXtensible Interface, a bus protocol) bus. The hash data request generally involves a larger data transmission amount, and thus the second bus 202 having a higher transmission rate is employed in order to improve transmission efficiency. The amount of data is smaller for accesses to the configuration unit 104, and the frequency of accesses is generally lower, thus employing the first bus 204 with a lower transmission rate. In the scheme, reasonable utilization of resources can be realized.

Fig. 3 shows a block schematic diagram of the reset unit 106 of an embodiment of the present disclosure. The reset unit 106 includes a register write operation module 172, a flip module 174, and a reset enable module 176. Wherein the register write operation module 172 is configured to write a predetermined value to the reset register according to the alarm signal from the operation unit 102. The flip module 174 is configured to cause the value stored by the reset register to be flipped when the reset register is written to a predetermined value. The reset enable module 176 is configured to enable the arithmetic unit reset signal in response to the value stored by the reset register being toggled.

In some embodiments, the apparatus 200 includes a reset register, and when the alarm signal of the operation unit 102 is received, the register write operation module 172 writes a predetermined value, for example, 1 (high level signal), to the reset register in response to the alarm signal, and then the flip module 174 causes the value stored in the reset register to flip (for example, the value 1 stored originally is flipped to 0 or the value 0 stored originally is flipped to 1). That is, the reset register is set to a W1T (write 1 flip) register.

It is worth noting that in some embodiments, the configuration unit 104 includes, for example, a reset configuration register. When a device or module connected to the first bus 204 configures the reset configuration register in the configuration unit 104 via the first bus 204 such that the state of the reset configuration register corresponds to the state in which the arithmetic unit reset signal is enabled, the reset unit 106 enables the arithmetic unit reset signal in response to configuration information of the self-configuration unit (e.g., the state in which the reset configuration register corresponds to the state in which the arithmetic unit reset signal is enabled). In some embodiments, the reset configuration register is set to a W1T (write 1 flip) register. A device or module connected to the first bus 204 writes a predetermined value, for example 1 (high signal), to a reset configuration register in the configuration unit 104, for example via the first bus 204, and the value stored in the reset configuration register toggles. The reset unit 106 is flipped in response to resetting the value stored by the configuration register such that the arithmetic unit reset signal is enabled.

In some embodiments, the reset enable module 176 is further configured to generate a pulse signal in response to the value stored by the reset register being toggled, and to cause the arithmetic unit reset signal to be enabled according to the pulse signal. For example, each time the value stored by the reset register toggles, the reset enable module 176 generates a corresponding pulse signal and enables the arithmetic unit reset signal according to the pulse signal, e.g., as an enabled arithmetic unit reset signal. Using the pulse signal as an enabled arithmetic unit reset signal may cause the arithmetic unit 102 to automatically release from the reset state after the end of the pulse, so as to quickly enter the operating state.

Fig. 4 shows a flowchart of a reset method 400 of an embodiment of the present disclosure. Method 400 may be implemented by apparatus 100 or by apparatus 200. It should be understood that method 400 may also include additional steps not shown and/or that the illustrated steps may be omitted, the scope of the present disclosure being not limited in this respect.

In step 402, at a configuration unit, configuration information is generated.

For example, writing to the configuration unit 104 may enable configuration of the configuration unit 104 such that the configuration unit 104 stores desired configuration information to cause the operation unit 102 to perform hash operations in a desired pattern. The configuration information may include, for example, hash length information and the like.

In step 404, at the arithmetic unit, a hash operation is performed according to the configuration information from the configuration unit.

The arithmetic unit 102 acquires Ha Xiyuan data from the target device and performs hash operation on Ha Xiyuan data according to the configuration information from the configuration unit 104 to generate a hash value. The arithmetic unit 102 may also output a hash value, for example. The arithmetic unit 102 may also generate, for example, an alarm signal. For example, the arithmetic unit 102 may acquire Ha Xiyuan data from the target device via the bus, and in the process of the arithmetic unit 102 acquiring Ha Xiyuan data, if a bus error or the like occurs, the arithmetic unit 102 generates an alarm signal. For example, in the course of hash operation by the operation unit 102, if a padding error or the like occurs, the operation unit 102 generates an alarm signal. For example, the arithmetic unit 102 may output the hash value to the target device through the bus, and in the process of the arithmetic unit 102 outputting the hash value, if a bus error or the like occurs, the arithmetic unit 102 generates an alarm signal.

In step 406, at the reset unit, the arithmetic unit reset signal is enabled in accordance with the alert signal from the arithmetic unit.

The reset unit 106, for example, causes the arithmetic unit reset signal to be disabled in a default state, and the reset unit 106 causes the arithmetic unit reset signal to be enabled in response to the alarm signal from the arithmetic unit 102.

In step 408, at the arithmetic unit, the reset is performed in response to the enabled arithmetic unit reset signal of the reset unit.

In some embodiments, the arithmetic unit 102 includes a master device module 122 and a hash operation module 124.

Step 404 includes, for example: at the host device module, sending a hash data request to the reply module to obtain Ha Xiyuan data; and performing, at the hash operation module, a hash operation based on the configuration information and Ha Xiyuan data from the master device module.

For example, the master module 122 may send a hash data request to the reply module 302 via the second bus 202. The response module 302 stores Ha Xiyuan data. The master device module 122 sends a hash read request to the answering module 302 to read Ha Xiyuan data from the answering module 302; after receiving the hash read request, the reply module 302 transmits Ha Xiyuan the data to the master module 122 via the second bus 202.

Step 408 includes, for example: suspending, at the master device module, sending the hash data request in response to the enabled arithmetic unit reset signal; and at the hash operation module, being reset in response to the enabled operation unit reset signal.

The hash operation module 124 performs a hash operation according to the configuration information from the configuration unit 104 and the Ha Xiyuan data from the master device module 122, and generates a hash value. The hash operation module 124 may notify the master device module 122, for example, in the form of an interrupt signal after the hash operation is completed. After receiving the interrupt signal, the master device module 122 sends a hash data write request to the reply module 302 via the second bus 202 to write the hash value to the reply module 302.

In some embodiments, the arithmetic unit 102 further includes a reply monitor module 126. The method 400 further comprises: at the reply monitor module, determining whether the reply module completed replying to the hash data request, and generating a reply completion signal in response to determining that the reply module completed replying to the hash data request. Accordingly, step 406 includes, for example: at the reset unit, the main device module is reset according to the enabled arithmetic unit reset signal and the answer completion signal.

In some embodiments, the reply monitoring module 126 includes a request reply counter 162 and a reply completion signal generation module 164.

At the reply monitoring module, determining whether the reply to the hash data request is completed by the reply module, and generating a reply completion signal in response to determining that the reply to the hash data request is completed by the reply module, for example, includes: at the request reply counter, changing the counter value in a first direction after each transmission of the hash data request by the master device module, and in a second direction after each reply by the reply module, the first direction being opposite to the second direction; and generating, at the answer completion signal generation module, an answer completion signal when the count value of the request answer counter meets a predetermined condition.

For example, in transmitting the hash value, the master device module 122 sends a hash data write request to the reply module 302 in multiple times according to a predetermined state machine. For each hash data request sent by the master module 122, the request reply counter 162 increments its count value by 1. For example, for each hash data write request sent by the master module 122, the write request reply counter increments its count value by 1.

In some embodiments, the answer monitoring module 126 also includes a request pause module 166. The method 400 further includes, for example: at the request suspension module, a request suspension signal is enabled when the count value of the request reply counter is equal to a predetermined count threshold, such that the master module suspends sending the hash data request in response to the enabled request suspension signal.

When the count value of the request reply counter 162 is equal to the predetermined count threshold, it is indicated that, among the hash data requests issued by the master device module 122, the number of hash data requests for which the reply module 302 has not yet made a reply has reached the predetermined count threshold. In this case, the request suspension signal is enabled so that the master device module 122 suspends sending the hash data request in response to the enabled request suspension signal, so that it is possible to avoid further increase in the hash data request that has not yet been responded at the response module 302, thereby effectively controlling the time taken for waiting for the response module 302 to complete the response to increase the rate at which the operation unit 102 completes the reset when the alarm signal occurs and the operation unit 102 needs to be reset, so as to increase the execution efficiency of the hash operation performed by the operation unit 102.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

The foregoing is merely an alternative embodiment of the present disclosure, and is not intended to limit the present disclosure, and various modifications and variations may be made to the present disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. An apparatus for hash operations, comprising:

an arithmetic unit electrically connected to the configuration unit and the reset unit, respectively, the arithmetic unit configured to perform a hash operation according to configuration information from the configuration unit and reset in response to an enabled arithmetic unit reset signal of the reset unit;

a configuration unit configured to generate configuration information; and

and a reset unit configured to enable the operation unit reset signal according to the alarm signal from the operation unit.

2. The apparatus according to claim 1, wherein the operation unit includes:

a host device module electrically connected to the hash operation module and the reset unit, respectively, the host device module configured to send a hash data request to the response module to obtain Ha Xiyuan data, and to suspend sending the hash data request in response to an enabled operation unit reset signal, the response module configured to respond according to the hash data request; and

And the hash operation module is respectively and electrically connected with the configuration unit, the main equipment module and the reset unit, and is configured to perform hash operation according to the configuration information and Ha Xiyuan data from the main equipment module and reset in response to an enabled operation unit reset signal.

3. The apparatus according to claim 2, wherein the operation unit further comprises:

the response monitoring module is respectively and electrically connected with the reset unit and the main equipment module, and is configured to determine whether the response module completes response to the hash data request and generate a response completion signal in response to determining that the response module completes response to the hash data request;

the reset unit is further configured to cause the main device module to be reset in accordance with the enabled arithmetic unit reset signal and the reply completion signal.

4. The apparatus of claim 3, wherein the response monitor module comprises:

a request reply counter configured to cause the count value to change in a first direction after each transmission of a hash data request by the host device module, and to cause the count value to change in a second direction after each reply by the reply module, the first direction being opposite to the second direction; and

And a response completion signal generation module configured to generate a response completion signal when the count value of the request response counter meets a predetermined condition.

5. The apparatus of claim 4, wherein the response monitor module further comprises:

a request suspension module configured to enable a request suspension signal when a count value of the request reply counter is equal to a predetermined count threshold, so that the master device module suspends transmitting the hash data request in response to the enabled request suspension signal.

6. The apparatus as recited in claim 2, further comprising:

a first bus electrically connected to the configuration unit, the first bus being for accessing the configuration unit according to a predetermined access pattern; and

an alarm unit configured to determine whether access to the configuration unit via the first bus meets a predetermined access pattern, and to generate alarm information in response to determining that access to the configuration unit via the first bus does not meet the predetermined access pattern.

7. The apparatus as recited in claim 6, further comprising:

the second bus is electrically connected with the main equipment module and the response module respectively; and

the host device module is further configured to send the hash data request to the reply module via a second bus having a transmission rate greater than the transmission rate of the first bus.

8. The apparatus of claim 1, wherein the reset unit comprises:

a register write operation module configured to write a predetermined value to the reset register according to the alarm signal from the operation unit;

a flip module configured to cause a value stored in the reset register to be flipped when the reset register is written with a predetermined value; and

a reset enable module configured to enable the arithmetic unit reset signal in response to the value stored by the reset register being flipped.

9. The apparatus of claim 8, wherein the reset enable module is further configured to generate a pulse signal in response to the value stored by the reset register being flipped, and to cause the arithmetic unit reset signal to be enabled in accordance with the pulse signal.

10. The apparatus of claim 2, wherein the master device module is further configured to send a hash data read request or a hash data write request to the reply module according to a predetermined state machine.

11. The apparatus of claim 1, wherein the reset unit is further configured to cause the arithmetic unit reset signal to be enabled based on configuration information from the configuration unit.

12. A reset method, characterized in that it is implemented with an apparatus according to any one of claims 1-11, said method comprising:

Generating configuration information at a configuration unit;

performing hash operation at the operation unit according to the configuration information from the configuration unit;

at the reset unit, enabling an arithmetic unit reset signal in accordance with the alert signal from the arithmetic unit; and

at the arithmetic unit, reset is performed in response to an enabled arithmetic unit reset signal of the reset unit.

13. The method of claim 12, wherein the arithmetic unit comprises a master device module and a hash operation module;

at the operation unit, performing hash operation according to the configuration information from the configuration unit, including:

at the host device module, sending a hash data request to the reply module to obtain Ha Xiyuan data; and

performing hash operation at a hash operation module according to the configuration information and Ha Xiyuan data from the main equipment module;

at an arithmetic unit, reset in response to an enabled arithmetic unit reset signal of a reset unit, comprising:

suspending, at the master device module, sending the hash data request in response to the enabled arithmetic unit reset signal; and

at the hash operation module, it is reset in response to the enabled operation unit reset signal.

14. The method of claim 13, wherein the arithmetic unit further comprises a response monitor module;

the method further comprises the steps of:

at the response monitor module, determining whether the response module completes the response to the hash data request, and generating a response complete signal in response to determining that the response module completes the response to the hash data request;

at the reset unit, causing the arithmetic unit reset signal to be enabled in accordance with the alert signal from the arithmetic unit, comprising:

at the reset unit, the main device module is reset according to the enabled arithmetic unit reset signal and the answer completion signal.

15. The method of claim 14, wherein the reply monitoring module comprises a request reply counter and a reply completion signal generation module;

at the response monitor module, determining whether the response module completes the response to the hash data request, and generating a response completion signal in response to determining that the response module completes the response to the hash data request, comprising:

at the request reply counter, changing the counter value in a first direction after each transmission of the hash data request by the master device module, and in a second direction after each reply by the reply module, the first direction being opposite to the second direction; and

At the answer completion signal generation module, configured to generate an answer completion signal when the count value of the request answer counter meets a predetermined condition.

16. The method of claim 15, wherein the answer monitoring module further comprises a request pause module;

the method further comprises the steps of:

at the request suspension module, a request suspension signal is enabled when the count value of the request reply counter is equal to a predetermined count threshold, such that the master module suspends sending the hash data request in response to the enabled request suspension signal.