CN116455212A

CN116455212A - DC-DC converter

Info

Publication number: CN116455212A
Application number: CN202310501160.3A
Authority: CN
Inventors: 阳云霄
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2023-05-05
Filing date: 2023-05-05
Publication date: 2023-07-18

Abstract

Embodiments of the present disclosure provide a DC-DC converter including: the circuit comprises a voltage conversion circuit, a switching circuit, a voltage holding circuit, a first voltage comparator, a second voltage comparator, a zero crossing detection circuit, a logic and driving circuit, a power tube, a follow-up tube and an inductor. The voltage conversion circuit converts the first reference voltage into the second reference voltage in the non-dormant period, otherwise, the operation is stopped. The switching circuit connects the voltage conversion circuit to the first input terminal of the first voltage comparator during the non-sleep period, and disconnects the voltage conversion circuit otherwise. A voltage holding circuit holds a voltage at the first input terminal. The second input of the first voltage comparator is provided with an output voltage. The logic and driving circuit controls the power tube to be turned on and the freewheel tube to be turned off when the pulse width modulation signal output by the first voltage comparator is in an effective level, controls the power tube to be turned off and the freewheel tube to be turned on when the inductance current peak value indication signal is in the effective level, and controls the power tube and the freewheel tube to be turned off when the zero crossing indication signal is in the effective level.

Description

DC-DC converter

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to DC-DC converters.

Background

DC-DC (direct current-direct current) converters are often used in various electronic devices for converting direct voltage. In order to realize different output voltages, the conventional DC-DC converter needs to provide a voltage dividing resistor between an output voltage terminal and a feedback voltage terminal. The feedback voltage end is connected to the input end of the error amplifier in the loop, and different output voltages are realized by adjusting the voltage dividing resistor. After the conventional DC-DC converter enters the light load operation mode, the DC-DC converter is expected to switch to the low power consumption mode, but the voltage dividing resistor also needs to consume quiescent current, so that the quiescent current of the whole chip is large, and the light load efficiency is low. In low power applications, the quiescent current across the divider resistor will prevent further reduction of the quiescent current of the DC-DC converter, affecting efficiency.

Disclosure of Invention

Embodiments described herein provide a DC-DC converter.

According to a first aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter includes: the switching device comprises a voltage conversion circuit, a switching circuit, a voltage holding circuit, a first voltage comparator, a second voltage comparator, a zero crossing detection circuit, a logic and driving circuit, a power tube, a follow-up tube and an inductor. Wherein the voltage conversion circuit is configured to: converting the first reference voltage to a second reference voltage during a non-sleep period of the DC-DC converter; and stopping the operation during the period in which the DC-DC converter is in the sleep period. The switching circuit is configured to: during a non-sleep period of the DC-DC converter, causing an output terminal of the voltage conversion circuit to be connected to a first input terminal of the first voltage comparator via the first node, thereby providing a second reference voltage to the first input terminal of the first voltage comparator; and disconnecting the voltage conversion circuit from the first input of the first voltage comparator during a sleep period of the DC-DC converter. The voltage holding circuit is configured to: the voltage at the first input of the first voltage comparator is maintained. The second input end of the first voltage comparator is coupled with the output end of the DC-DC converter. The pulse width modulation signal is output from the output terminal of the first voltage comparator. The second voltage comparator is configured to output an inductor current peak indication signal at an active level in the event that the inductor current flowing through the inductor reaches a peak current threshold. The zero-crossing detection circuit is configured to: and outputting a zero crossing indication signal at an active level under the condition that the inductance current is zero. The logic and drive circuitry is configured to: the power tube is controlled to be turned on and the freewheel tube is controlled to be turned off when the pulse width modulation signal is in an effective level, the inductance current peak value indication signal is in an effective level, the power tube is controlled to be turned off and the freewheel tube is controlled to be turned on, and the zero crossing indication signal is in an effective level, and the power tube and the freewheel tube are controlled to be turned off.

In some embodiments of the present disclosure, a voltage conversion circuit includes: a reference voltage circuit, a first voltage controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, and a second feedback resistor. Wherein the reference voltage circuit is configured to generate a first reference voltage. The first end of the first voltage-controlled switch is coupled with the output end of the reference voltage circuit. The second end of the first voltage-controlled switch is coupled with the first input end of the error amplifier. The first voltage controlled switch is configured to be closed during a non-sleep period of the DC-DC converter and to be opened during a sleep period of the DC-DC converter. The second input terminal of the error amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor. The output end of the error amplifier is coupled with the control electrode of the first transistor. The error amplifier stops operating during the period when the DC-DC converter is in the sleep period. The first end of the first capacitor is coupled to the first input end of the error amplifier. The second terminal of the first capacitor is coupled to the second voltage terminal. A first pole of the first transistor is coupled to the second end of the first feedback resistor and the first node. The second pole of the first transistor is coupled to the first voltage terminal. The second end of the second feedback resistor is coupled to the second voltage end.

In some embodiments of the present disclosure, the switching circuit includes: and a second voltage-controlled switch. The first end of the second voltage-controlled switch is coupled to the first node. The second end of the second voltage-controlled switch is coupled to the first input end of the first voltage comparator. The second voltage controlled switch is configured to be closed during a non-sleep period of the DC-DC converter and to be opened during a sleep period of the DC-DC converter.

In some embodiments of the present disclosure, the voltage holding circuit includes: and a second capacitor. The first end of the second capacitor is coupled to the first input end of the first voltage comparator. The second terminal of the second capacitor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, the first voltage comparator switches to the low current mode during a period in which the DC-DC converter is in sleep.

In some embodiments of the present disclosure, the DC-DC converter further includes: sleep control circuitry. The sleep control circuit is configured to: a sleep indication signal is generated from the zero crossing indication signal. Wherein, in the case that the zero crossing indication signal is at an inactive level, the sleep indication signal is at an inactive level. The sleep indication signal toggles to an active level when the zero crossing indication signal toggles to an active level. The sleep indication signal toggles to the inactive level after a first period of time from when the sleep indication signal toggles to the active level and remains at the inactive level for a second period of time.

In some embodiments of the present disclosure, the sleep control circuit includes: a ramp signal generating circuit, a timing clear circuit, and a sleep signal output circuit. The ramp signal generating circuit is configured to: a ramp signal is generated and provided to the sleep signal output circuit via the second node. Wherein the ramp signal is raised to an active level when a rise time of the ramp signal reaches a first period. The timing clear circuit is configured to: the ramp signal is reset when the time at which the sleep indication signal toggles to the inactive level reaches the second period. The sleep signal output circuit is configured to: in the case that the zero crossing indication signal is at an inactive level or the ramp signal is at an active level, the sleep indication signal is at an inactive level; otherwise the sleep indication signal is at an active level.

In some embodiments of the present disclosure, a ramp signal generating circuit includes: a bias current source, and a third capacitor. Wherein the bias current source is configured to: a bias current is provided to the first terminal of the third capacitor. The first end of the third capacitor is coupled to the second node. The second terminal of the third capacitor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, the timing clear circuit includes: a first unidirectional delay circuit, and a second transistor. Wherein the first unidirectional delay circuit is configured to: and controlling the second transistor to be conducted when the time for the sleep indication signal to flip to the inactive level reaches the second time period. The first electrode of the second transistor is coupled to the second voltage terminal. The second diode of the second transistor is coupled to the second node.

In some embodiments of the present disclosure, the sleep signal output circuit includes: the second unidirectional delay circuit, the first inverter, and the or gate. Wherein the second unidirectional delay circuit is configured to: and outputting the delayed zero crossing indication signal when the time when the zero crossing indication signal is turned to the active level reaches a third time period. The input end of the first inverter is coupled with the output end of the second unidirectional delay circuit. The output end of the first inverter is coupled with the second input end of the OR gate. The first input terminal of the OR gate is coupled to the second node. The sleep indication signal is output from the output of the or gate.

In some embodiments of the present disclosure, the sleep control circuit includes: a bias current source, a third capacitor, a first inverter, a second inverter, a third inverter, a first unidirectional delay circuit, a second transistor, a third transistor, and an or gate. Wherein the bias current source is configured to: a bias current is provided to the first terminal of the third capacitor. The first end of the third capacitor is coupled to the input end of the second inverter, the second pole of the second transistor and the second pole of the third transistor. The second terminal of the third capacitor is coupled to the second voltage terminal. The control electrode of the third transistor is coupled to the output end of the second inverter and the input end of the third inverter. The first electrode of the third transistor is coupled to the first voltage terminal. The output end of the third inverter is coupled to the first input end of the OR gate. The first unidirectional delay circuit is configured to: and controlling the second transistor to be conducted when the time for the sleep indication signal to flip to the inactive level reaches the second time period. The first electrode of the second transistor is coupled to the second voltage terminal. The second unidirectional delay circuit is configured to: and outputting the delayed zero crossing indication signal when the time when the zero crossing indication signal is turned to the active level reaches a third time period. The input end of the first inverter is coupled with the output end of the second unidirectional delay circuit. The output end of the first inverter is coupled with the second input end of the OR gate. The sleep indication signal is output from the output of the or gate.

In some embodiments of the present disclosure, the bias current source includes: fourth to eighth transistors and a start-up circuit. Wherein the start-up circuit is configured to: the fourth transistor is supplied with a start-up current when the DC-DC converter is powered up and stops operating when the bias current source is able to generate a bias current. The control electrode and the second electrode of the fourth transistor are coupled to the output terminal of the start-up circuit, the second electrode of the fifth transistor, the control electrode of the seventh transistor and the control electrode of the eighth transistor. The first electrode of the fourth transistor is coupled to the first voltage terminal. The control electrode of the fifth transistor is coupled to the control electrode of the sixth transistor and the second electrode of the seventh transistor. The first pole of the fifth transistor is coupled to the first end of the first resistor. The second end of the first resistor is coupled to the first end of the second resistor and the first pole of the sixth transistor. The second end of the second resistor is coupled to the second voltage end. The first pole of the seventh transistor is coupled to the first voltage terminal. The first electrode of the eighth transistor is coupled to the first voltage terminal. The second pole of the eighth transistor is coupled to the first end of the third capacitor.

According to a second aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter includes: the circuit comprises a reference voltage circuit, a first voltage-controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, a second voltage-controlled switch, a second capacitor, a first voltage comparator, a second voltage comparator, a zero-crossing detection circuit, a logic and driving circuit, a power tube, a shunt tube and an inductor. Wherein the reference voltage circuit is configured to generate a first reference voltage. The controlled end of the first voltage-controlled switch is provided with a sleep indication signal. The first end of the first voltage-controlled switch is coupled with the output end of the reference voltage circuit. The second end of the first voltage-controlled switch is coupled with the first input end of the error amplifier. Wherein the sleep indication signal is at an inactive level during a period in which the DC-DC converter is not in sleep and at an active level during a period in which the DC-DC converter is in sleep. The second input terminal of the error amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor. The output end of the error amplifier is coupled with the control electrode of the first transistor. The error amplifier stops operating during the period when the DC-DC converter is in the sleep period. The first end of the first capacitor is coupled to the first input end of the error amplifier. The second terminal of the first capacitor is coupled to the second voltage terminal. A first pole of the first transistor is coupled to the second end of the first feedback resistor and the first end of the second voltage-controlled switch. The second pole of the first transistor is coupled to the first voltage terminal. The second end of the second feedback resistor is coupled to the second voltage end. The controlled end of the second voltage-controlled switch is provided with a sleep indication signal. The second end of the second voltage-controlled switch is coupled to the first input end of the first voltage comparator. The first end of the second capacitor is coupled to the first input end of the first voltage comparator. The second terminal of the second capacitor is coupled to the second voltage terminal. The second input end of the first voltage comparator is coupled with the output end of the DC-DC converter. The pulse width modulation signal is output from the output terminal of the first voltage comparator. The second voltage comparator is configured to output an inductor current peak indication signal at an active level in the event that the inductor current flowing through the inductor reaches a peak current threshold. The zero-crossing detection circuit is configured to: and outputting a zero crossing indication signal at an active level under the condition that the inductance current is zero. The logic and drive circuitry is configured to: the power tube is controlled to be turned on and the freewheel tube is controlled to be turned off when the pulse width modulation signal is in an effective level, the inductance current peak value indication signal is in an effective level, the power tube is controlled to be turned off and the freewheel tube is controlled to be turned on, and the zero crossing indication signal is in an effective level, and the power tube and the freewheel tube are controlled to be turned off.

According to a third aspect of the present disclosure, a chip is provided. The chip comprises a DC-DC converter according to the first or second aspect of the present disclosure.

According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a chip according to the third aspect of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 is an exemplary topology of a DC-DC converter;

FIG. 2 is a schematic block diagram of a DC-DC converter according to an embodiment of the disclosure;

FIG. 3 is an exemplary circuit diagram of a DC-DC converter according to an embodiment of the present disclosure;

FIG. 4 is a further exemplary circuit diagram of a DC-DC converter according to an embodiment of the present disclosure;

FIG. 5 is a schematic block diagram of the sleep control circuit of FIG. 4;

FIG. 6 is an exemplary circuit diagram of the sleep control circuit of FIG. 4;

FIG. 7 is another exemplary circuit diagram of the sleep control circuit of FIG. 4;

FIG. 8 is an exemplary circuit diagram of the bias current source of FIGS. 6 and 7; and

Fig. 9 is a timing diagram of some signals for a DC-DC converter according to an embodiment of the present disclosure.

In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

In all embodiments of the present disclosure, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control pole and the remaining two terminals of the MOS transistor are referred to as the first pole and the second pole, respectively. The transistors employed in the embodiments of the present disclosure are primarily switching transistors. In addition, for convenience of unified expression, in the context, the base of a bipolar transistor (BJT) is referred to as a control electrode, the emitter of the BJT is referred to as a first electrode, and the collector of the BJT is referred to as a second electrode. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

Fig. 1 shows an exemplary topology of a DC-DC converter 100. The DC-DC converter 100 converts an input voltage VIN to an output voltage VOUT. In the DC-DC converter 100 of fig. 1, an upper tube Q1, a lower tube Q2, a current sampling circuit sense, an inductor L, an output capacitor Cout, a first feedback resistor Rf1, a second feedback resistor Rf2, a reference voltage circuit BG, an error amplifier EA, a compensation capacitor C, PWM voltage comparator COMP, a logic and drive circuit, and a zero-crossing detection circuit are shown.

The non-inverting input of the error amplifier EA is coupled to the reference voltage circuit BG, and is thus supplied with the reference voltage Vref. The inverting input of the error amplifier EA is coupled to the feedback voltage terminal FB between the first feedback resistor Rf1 and the second feedback resistor Rf 2. The first feedback resistor Rf1 and the second feedback resistor Rf2 divide the output voltage VOUT of the DC-DC converter. The error signal Vea output from the output terminal of the error amplifier EA is supplied to the non-inverting input terminal of the PWM voltage comparator COMP. The current sampling circuit sense collects a current signal flowing through the upper tube Q1. The current signal is supplied to the inverting input terminal of the PWM voltage comparator COMP after being superimposed with the ramp signal Slop. The PWM voltage comparator COMP outputs a pulse width modulation signal PWM to the logic and driving circuit. The logic and driving circuit generates an upper tube driving signal dr_q1 and a lower tube driving signal dr_q2 according to the pulse width modulation signal PWM, the clock signal CLK, and the zero crossing detection signal ZCD output from the zero crossing detection circuit. The upper tube driving signal dr_q1 is used to control on and off of the upper tube Q1. The down tube driving signal dr_q2 is used to control on and off of the down tube Q2.

In the example of fig. 1, different output voltages VOUT may be achieved by controlling the ratio of the resistance values of the first feedback resistor Rf1 and the second feedback resistor Rf 2. In order to realize the voltage regulating function, the first feedback resistor Rf1 and the second feedback resistor Rf2 are indispensable. They generate additional quiescent current and reduce light load efficiency.

Embodiments of the present disclosure propose a DC-DC converter capable of eliminating a quiescent current on a first feedback resistor Rf1 and a second feedback resistor Rf2 in a sleep period. Fig. 2 shows a schematic block diagram of a DC-DC converter 200 according to an embodiment of the disclosure. The DC-DC converter 200 includes: the voltage conversion circuit 210, the switching circuit 220, the voltage holding circuit 230, the first voltage comparator CMP1, the second voltage comparator CMP2, the zero-crossing detection circuit 250, the logic and driving circuit 240, the power transistor, the shunt tube, and the inductor L.

Fig. 2 illustrates a BUCK converter (BUCK) as an example. In the example of fig. 2, the upper tube Q1 is a power tube and the lower tube Q2 is a continuous tube. The control electrode of the upper pipe Q1 is supplied with an upper pipe driving signal dr_q1 outputted from the logic and driving circuit 240. The first pole of the upper tube Q1 is coupled to the input voltage terminal VIN. The second pole of the upper tube Q1 is coupled to the second pole of the lower tube Q2 and the first end of the inductor L (node SW). The gate of the down tube Q2 is provided with a down tube drive signal dr_q2 output by the logic and drive circuit 240. The first pole of the down tube Q2 is coupled to the second voltage terminal V2. The second terminal of the inductor L is coupled to the output voltage terminal VOUT and the first terminal of the output capacitor Cout. The second terminal of the output capacitor Cout is coupled to the second voltage terminal V2.

The DC-DC converter according to embodiments of the present disclosure may also be a BOOST converter (BOOST). In the boost converter, the upper tube Q1 is a freewheel tube, and the lower tube Q2 is a power tube.

The input terminal of the voltage conversion circuit 210 is coupled to the first reference voltage terminal Vref1 and the sleep indication signal terminal SLP. The output terminal of the voltage converting circuit 210 is coupled to the switch circuit 220 via the first node N1. The voltage conversion circuit 210 is configured to: converting the first reference voltage Vref1 into the second reference voltage Vref2 during the non-sleep period of the DC-DC converter 200; and stopping the operation during the sleep period of the DC-DC converter 200. In some embodiments of the present disclosure, the DC-DC converter 200 may be controlled to enter the sleep period by the sleep indication signal SLP from the sleep indication signal terminal SLP. The DC-DC converter 200 is in the sleep period when the sleep indication signal SLP is at an active level. The DC-DC converter 200 is in the non-sleep period when the sleep indication signal SLP is at the inactive level. In some embodiments of the present disclosure, the second reference voltage Vref2 is equal to zero volts when the voltage conversion circuit 210 stops operating. When the voltage conversion circuit 210 operates normally, the second reference voltage Vref2 is greater than the first reference voltage Vref1.

The switch circuit 220 is coupled to the sleep indication signal terminal SLP. The switch circuit 220 is coupled to the output terminal of the voltage converting circuit 210 via the first node N1. The switching circuit 220 is further coupled to a first input of the first voltage comparator CMP1 and the voltage holding circuit 230. The switching circuit 220 is configured to: in the case where the DC-DC converter 200 is in the non-sleep period (the sleep indication signal SLP is at the inactive level), the output terminal of the voltage conversion circuit 210 is caused to be connected to the first input terminal of the first voltage comparator CMP1 via the first node N1, thereby supplying the second reference voltage Vref2 to the first input terminal of the first voltage comparator CMP 1; and in the case where the DC-DC converter 200 is in the sleep period (the sleep indication signal SLP is at an active level), the connection between the voltage conversion circuit 210 and the first input terminal of the first voltage comparator CMP1 is disconnected.

The voltage holding circuit 230 is coupled to the first input terminal of the first voltage comparator CMP 1. The voltage holding circuit 230 is configured to: the voltage Vea at the first input of the first voltage comparator CMP1 is maintained.

A second input terminal of the first voltage comparator CMP1 is coupled to an output terminal of the DC-DC converter 200, thereby being provided with the output voltage VOUT. The pulse width modulation signal PWM is output from the output terminal of the first voltage comparator CMP 1. In some embodiments of the present disclosure, the first voltage comparator CMP1 is a hysteresis comparator. In some embodiments of the present disclosure, during the period in which the DC-DC converter 200 is in the sleep period, the first voltage comparator CMP1 switches to the low current mode, i.e., the bias current in the first voltage comparator CMP1 becomes small to reduce power consumption.

The first input terminal of the second voltage comparator CMP2 is coupled to the peak reference voltage terminal vref_peak. A second input terminal of the second voltage comparator CMP2 is coupled to the node SW. The inductor current peak indication signal PeakOut is output from the output terminal of the second voltage comparator CMP 2. When the inductor current IL is zero, the voltage at node SW is higher than the peak reference voltage vref_peak from the peak reference voltage terminal vref_peak, and the inductor current peak indication signal PeakOut is at an inactive level. As inductor current IL increases, the voltage at node SW decreases. When the voltage at the node SW drops to the peak reference voltage vref_peak, the inductor current peak indication signal PeakOut output by the second voltage comparator CMP2 is inverted to an active level. That is, the second voltage comparator CMP2 is configured to output an inductor current peak indication signal PeakOut at an inactive level in the case that the inductor current IL flowing through the inductor L does not reach the peak current threshold value; and outputting an inductor current peak indication signal PeakOut at an active level in a case where the inductor current IL flowing through the inductor L reaches a peak current threshold. In some embodiments of the present disclosure, the second voltage comparator CMP2 is a hysteresis voltage comparator.

The zero crossing detection circuit 250 is coupled to the node SW and the logic and driving circuit 240. The zero-crossing detection circuit 250 is configured to: the zero crossing indication signal ZCD at an active level is output in case the inductor current IL is zero. The zero-crossing indication signal ZCD output from the zero-crossing detection circuit 250 is at an inactive level in the case where the inductor current IL is not zero. In some embodiments of the present disclosure, the active level of the zero crossing indication signal ZCD is a high level. The inactive level of the zero crossing indication signal ZCD is a low level.

The logic and drive circuit 240 is configured to: the power tube is controlled to be turned on and the freewheel tube is controlled to be turned off when the pulse width modulation signal PWM is in an effective level, the inductance current peak value indication signal PeakOut is controlled to be turned off and the freewheel tube is controlled to be turned on when the inductance current peak value indication signal PeakOut is in an effective level, and the zero crossing indication signal ZCD is controlled to be turned off when the zero crossing indication signal ZCD is in an effective level. In some embodiments of the present disclosure, when the zero crossing indication signal ZCD is at an active level, the sleep indication signal SLP is at an active level, and the DC-DC converter 200 is in a sleep period. When the zero crossing indication signal ZCD is at an inactive level, the sleep indication signal SLP is at an inactive level, and the DC-DC converter 200 is in a non-sleep period.

In some embodiments of the present disclosure, the active level of the sleep indication signal SLP is a low level. The inactive level of the sleep indication signal SLP is a high level.

In the example of fig. 2, the second voltage terminal V2 is grounded. The upper transistor Q1 is a PMOS transistor. The lower transistor Q2 is an NMOS transistor. The first input of the first voltage comparator CMP1 is a non-inverting input. The second input of the first voltage comparator CMP1 is an inverting input. The active level of the pulse width modulated signal PWM is high. The inactive level of the pulse width modulated signal PWM is a low level. The first input of the second voltage comparator CMP2 is a non-inverting input. The second input of the second voltage comparator CMP2 is an inverting input. The active level of the inductor current peak indication signal PeakOut is high. The inactive level of the inductor current peak indication signal PeakOut is a low level. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 2 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the example shown in fig. 2.

In the case where the DC-DC converter 200 is in the non-sleep period (normal operation), the second reference voltage Vref2 is supplied to the first input terminal of the first voltage comparator CMP 1. The voltage Vea at the first input of the first voltage comparator CMP1 is equal to the second reference voltage Vref2. When the output voltage VOUT < Vea, the pulse width modulation signal PWM output by the first voltage comparator CMP1 is at an active level (high level), the upper tube Q1 is turned on and the lower tube Q2 is turned off, and the inductor current IL rises. When the current flowing through the upper tube Q1 reaches the peak current, the voltage of the node SW drops to the peak reference voltage vref_peak. Accordingly, the inductor current peak indication signal PeakOut output from the second voltage comparator CMP2 is inverted to an active level (high level). At this time, the upper tube Q1 is turned off and the lower tube Q2 is turned on, and the inductor current IL decreases. When the inductor current IL falls to 0A, the zero crossing indication signal ZCD is inverted to an active level (high level), and both the upper tube Q1 and the lower tube Q2 are turned off. In some embodiments of the present disclosure, the second voltage comparator CMP2 stops operating when the zero crossing indication signal ZCD is at an active level.

In the case where both the upper pipe Q1 and the lower pipe Q2 are turned off, if the output voltage VOUT > Vea, the DC-DC converter 200 enters the sleep period. When the load pulls down the output voltage VOUT to be less than Vea, the PWM signal PWM is turned to an active level (high level), and the upper tube Q1 is turned on again. The above process is then repeated. Therefore, the average value of the output voltage VOUT is about Vea, and Vea is equal to the second reference voltage Vref2. The second reference voltage Vref2 is generated from the first reference voltage Vref1, and thus the voltage conversion circuit 210 can regulate the output voltage VOUT according to the first reference voltage Vref 1.

During the sleep period of the DC-DC converter 200, the switching circuit 220 disconnects the voltage converting circuit 210 from the first input terminal of the first voltage comparator CMP 1. The voltage conversion circuit 210 stops operating to reduce the quiescent current during the sleep period. The voltage holding circuit 230 may cause the voltage Vea at the first input terminal of the first voltage comparator CMP1 to be held as the second reference voltage Vref2. This enables a loop to be quickly established when the DC-DC converter 200 returns to a non-sleep period.

Fig. 3 shows an exemplary circuit diagram of a DC-DC converter 300 according to an embodiment of the present disclosure. The voltage conversion circuit 310 includes: the reference voltage circuit BG, the first voltage-controlled switch S1, the first capacitor C1, the error amplifier EA, the first transistor M1, the first feedback resistor Rf1, and the second feedback resistor Rf2.

The reference voltage circuit BG is configured to generate a first reference voltage Vref1. The first end of the first voltage-controlled switch S1 is coupled to the output end of the reference voltage circuit BG. A second terminal of the first voltage-controlled switch S1 is coupled to a first input terminal of the error amplifier EA. The controlled terminal of the first voltage-controlled switch S1 is coupled to the sleep indication signal terminal SLP. The first voltage controlled switch S1 is configured to be closed during a non-sleep period of the DC-DC converter 300 and to be opened during a sleep period of the DC-DC converter 300.

The second input of the error amplifier EA is coupled to the first end of the first feedback resistor Rf1 and the first end of the second feedback resistor Rf 2. The output terminal of the error amplifier EA is coupled to the control electrode of the first transistor M1. The error amplifier EA stops operating in the case where the DC-DC converter 300 is in the sleep period (the sleep indication signal SLP is at the active level). In some embodiments of the present disclosure, sleep indication signal SLP may control the supply voltage of error amplifier EA, which may be disabled by setting the supply voltage of error amplifier EA to zero volts. In other embodiments of the present disclosure, sleep indication signal SLP may control the bias current of error amplifier EA, and error amplifier EA may be disabled by setting the bias current of error amplifier EA to zero.

A first terminal of the first capacitor C1 is coupled to a first input terminal of the error amplifier EA. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2. A first pole of the first transistor M1 is coupled to the second end of the first feedback resistor Rf1 and the first node N1. The second pole of the first transistor M1 is coupled to the first voltage terminal V1. The second terminal of the second feedback resistor Rf2 is coupled to the second voltage terminal V2.

The switching circuit 320 includes: and a second voltage-controlled switch S2. The first end of the second voltage-controlled switch S2 is coupled to the first node N1. The second terminal of the second voltage-controlled switch S2 is coupled to the first input terminal of the first voltage comparator CMP 1. The controlled terminal of the second voltage controlled switch S2 is coupled to the sleep indication signal terminal SLP, thereby being provided with the sleep indication signal SLP. The second voltage controlled switch S2 is configured to be closed during a non-sleep period of the DC-DC converter 300 and to be opened during a sleep period of the DC-DC converter 300.

The voltage holding circuit 330 includes: and a second capacitor C2. The first end of the second capacitor C2 is coupled to the first input end of the first voltage comparator CMP 1. The second terminal of the second capacitor C2 is coupled to the second voltage terminal V2.

In the example of fig. 3, a high voltage signal is input from a first voltage terminal V1, and a second voltage terminal V2 is grounded. The first transistor M1 is an NMOS transistor. The first input of the error amplifier EA is a non-inverting input. The second input of the error amplifier EA is an inverting input. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 3 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the example shown in fig. 3.

In the case where the DC-DC converter 300 is in the non-sleep period (normal operation), the voltage at the first end of the first feedback resistor Rf1 is equal to the first reference voltage Vref1 according to the characteristics of the weak short and weak broken of the error amplifier EA. The method can obtain the following steps:

Vref2＝Vref1×(Rf1+Rf2)/Rf2 (1)

wherein Vref2 represents the voltage value of the second reference voltage Vref2, vref1 represents the voltage value of the first reference voltage Vref1, rf1 represents the resistance value of the first feedback resistor Rf1, and Rf2 represents the resistance value of the second feedback resistor Rf 2. The second voltage-controlled switch S2 is closed, and the second reference voltage Vref2 is supplied to the first input terminal of the first voltage comparator CMP1, so that the output voltage VOUT of the DC-DC converter 300 is set to the second reference voltage Vref2 by loop regulation. According to equation (1), the voltage conversion circuit 310 may regulate the output voltage VOUT by adjusting the resistance value of the first feedback resistor Rf1 or the resistance value of the second feedback resistor Rf 2.

During the sleep period of the DC-DC converter 300, the second voltage controlled switch S2 is turned off and the second reference voltage Vref2 is no longer supplied to the first input terminal of the first voltage comparator CMP 1. The second capacitor C2 may cause the voltage Vea at the first input terminal of the first voltage comparator CMP1 to be maintained as the second reference voltage Vref2. This enables a loop to be quickly established when the DC-DC converter 300 returns to a non-sleep period. At this time the error amplifier EA stops operating. Accordingly, the current flowing through the first feedback resistor Rf1 and the second feedback resistor Rf2 is zero, thereby reducing the quiescent current of the DC-DC converter 300 in the sleep period.

The inventors of the present disclosure found that there may be a problem of leakage of components in the DC-DC converter 300, and thus it is necessary to regularly refresh the voltage Vref1 at the first input terminal of the error amplifier EA and the voltage Vea at the first input terminal of the first voltage comparator CMP1 in the sleep period. The embodiment of fig. 4 proposes to further provide a sleep control circuit 460 in the DC-DC converter 400. Sleep control circuit 460 is configured to: the sleep indication signal SLP is generated according to the zero-crossing indication signal ZCD. In the case where the zero crossing indication signal ZCD is at the inactive level, the sleep indication signal SLP is at the inactive level. The sleep indication signal SLP is flipped to an active level when the zero crossing indication signal ZCD is flipped to an active level. After a first period of time from when the sleep indication signal SLP is turned to the active level, the sleep indication signal SLP is turned to the inactive level and remains at the inactive level for a second period of time, and then turned to the active level. The length of the first and second time periods may be set according to a specific application.

Thus, the DC-DC converter 400 is periodically awakened during the sleep period to refresh Vref1 and Vea, thereby avoiding unstable output voltage VOUT caused by component leakage.

Fig. 5 is a schematic block diagram of sleep control circuit 460 in fig. 4. Sleep control circuit 560 includes: a ramp signal generating circuit 561, a timing clear circuit 562, and a sleep signal output circuit 563.

An output terminal of the ramp signal generating circuit 561 is coupled to an output terminal of the timing clear circuit 562 and an input terminal of the sleep signal output circuit 563 via a second node N2. The ramp signal generating circuit 561 is configured to: generates a ramp signal and supplies the ramp signal to the sleep signal output circuit 563 via the second node N2. Wherein the ramp signal is raised to an active level when a rise time of the ramp signal reaches a first period.

The timing clearing circuit 562 is coupled to the output terminal of the ramp signal generating circuit 561 and the input terminal of the sleep signal output circuit 563 via a second node N2. The timing clear circuit 562 is configured to: resetting the ramp signal (i.e., clearing the voltage at the second node N2) when the time when the sleep indication signal SLP toggles to the inactive level reaches the second period; otherwise the voltage at the second node N2 is not affected.

An input terminal of the sleep signal output circuit 563 is coupled to an output terminal of the ramp signal generating circuit 561 and an output terminal of the timing clearing circuit 562 via a second node N2. Sleep signal output circuit 563 is also coupled to the output of zero-crossing detection circuit 250. The sleep signal output circuit 563 is configured to: in the case where the zero crossing indication signal ZCD is at an inactive level or the ramp signal is at an active level, the sleep indication signal SLP is at an inactive level; otherwise the sleep indication signal SLP is at an active level.

When the zero crossing indication signal ZCD is at an inactive level, the sleep indication signal SLP is at an inactive level. The ramp signal is reset when the time when the sleep indication signal SLP is flipped to the inactive level reaches the second period. When the zero crossing indication signal ZCD is inverted to an active level, the sleep indication signal SLP is inverted to an active level, the timing clear circuit 562 does not affect the voltage at the second node N2, and the ramp signal starts to rise. When the rising time of the ramp signal reaches the first period, the ramp signal rises to an active level, thereby causing the sleep indication signal SLP to flip to an inactive level. The ramp signal is reset when the time when the sleep indication signal SLP is flipped to the inactive level reaches the second period, so that the sleep indication signal SLP is flipped to the active level.

In this way, the DC-DC converter 400 is awakened to refresh Vref1 and Vea over a first period of time under the sleep period, and enters the sleep period again when the wake-up time reaches a second period of time.

As described above, in some embodiments of the present disclosure, the first voltage comparator CMP1 switches to the low current mode during the period in which the DC-DC converter is in the sleep period. In other embodiments of the present disclosure, the first voltage comparator CMP1 switches to the low current mode in case the zero crossing indication signal ZCD is at an active level. In this way, in the above-described second period of time that is awakened, the first voltage comparator CMP1 is also in the small current mode, enabling further reduction in power consumption.

Fig. 6 is an exemplary circuit diagram of sleep control circuit 460 in fig. 4. In the sleep control circuit 660 of fig. 6, the ramp signal generating circuit 661 includes: a bias current source IS, and a third capacitor C3. Wherein the bias current source IS configured to: the bias current Ibias is supplied to the first terminal of the third capacitor C3. The first end of the third capacitor C3 is coupled to the second node N2. The second terminal of the third capacitor C3 is coupled to the second voltage terminal V2.

The timing clear circuit 662 includes: a first unidirectional delay circuit DL1, and a second transistor M2. Wherein the first unidirectional delay circuit DL1 is configured to: the second transistor M2 is controlled to be turned on when the time when the sleep indication signal SLP is flipped to the inactive level reaches the second period. The first unidirectional delay circuit DL1 is further configured to: the second transistor M2 is directly controlled to be turned off when the sleep indication signal SLP is flipped to an active level.

The first pole of the second transistor M2 is coupled to the second voltage terminal V2. The second diode of the second transistor M2 is coupled to the second node N2.

The sleep signal output circuit 663 includes: a second unidirectional delay circuit DL2, a first inverter NG1, and an OR gate OR. Wherein the second unidirectional delay circuit DL2 is configured to: and outputting the delayed zero crossing indication signal when the time when the zero crossing indication signal ZCD is turned to the active level reaches a third time period. In other words, the second unidirectional delay circuit DL2 causes the transition edge of the zero crossing indication signal ZCD, which is inverted from the inactive level to the active level, to be delayed for the third period. The second unidirectional delay circuit DL2 is further configured to: and outputting the zero crossing indication signal at the invalid level when the time when the zero crossing indication signal ZCD is inverted to the valid level does not reach the third time period or the zero crossing indication signal ZCD is at the invalid level. The input terminal of the first inverter NG1 is coupled to the output terminal of the second unidirectional delay circuit DL 2. The output of the first inverter NG1 is coupled to the second input of the OR gate OR. The first input terminal of the OR gate is coupled to the second node N2. The sleep indication signal SLP is output from the output terminal of the OR gate OR. Noise on the zero-crossing indication signal ZCD can be avoided by setting the second unidirectional delay circuit DL2 so that the sleep indication signal SLP is erroneously flipped to an active level. In addition, by setting the second unidirectional delay circuit DL2, it is also possible to avoid that the zero crossing indication signal ZCD is in an active level for too short a time so that the DC-DC converter rapidly exits from the sleep period after entering the sleep period. The length of the third time period may be set according to a specific application.

When the zero crossing indication signal ZCD is at an inactive level (low level), the sleep indication signal SLP output from the OR gate OR is at an inactive level (high level). When the time when the sleep indication signal SLP turns to the inactive level reaches the second period, the second transistor M2 is turned on, and the ramp signal is reset to zero volt. When the time when the zero crossing indication signal ZCD is inverted to the active level (high level) reaches the third period, the sleep indication signal SLP output from the OR gate OR is inverted to the active level (low level), and the second transistor M2 is turned off. At this time, the bias current Ibias starts to charge the third capacitor C3, and the ramp signal starts to rise. When the rising time of the ramp signal reaches the first period, the ramp signal rises to an active level, and the first input terminal of the OR gate OR receives the high level signal, so that the sleep indication signal SLP is inverted to an inactive level (high level). The second transistor M2 is turned on at a time when the sleep indication signal SLP is turned to the inactive level reaches the second period, and the ramp signal is reset to zero volt, so that the sleep indication signal SLP is turned to the active level (low level).

Fig. 7 is another exemplary circuit diagram of sleep control circuit 760 in fig. 4. On the basis of the sleep control circuit 660 shown in fig. 6, the sleep control circuit 760 further includes: a second inverter NG2, a third inverter NG3, and a third transistor M3. In the example of fig. 7, the bias current source IS configured to: the bias current Ibias is supplied to the first terminal of the third capacitor C3. The first terminal of the third capacitor C3 is coupled to the input terminal of the second inverter NG2, the second pole of the second transistor M2, and the second pole of the third transistor M3. The second terminal of the third capacitor C3 is coupled to the second voltage terminal V2. The control electrode of the third transistor M3 is coupled to the output terminal of the second inverter NG2 and the input terminal of the third inverter NG 3. The first pole of the third transistor M3 is coupled to the first voltage terminal V1. The output of the third inverter NG3 is coupled to the first input of the OR gate OR. The first one-way delay circuit DL1 is configured to: the second transistor M2 is controlled to be turned on when the time when the sleep indication signal SLP is flipped to the inactive level reaches the second period. The first pole of the second transistor M2 is coupled to the second voltage terminal V2. The second unidirectional delay circuit DL2 is configured to: and outputting the delayed zero crossing indication signal when the time when the zero crossing indication signal ZCD is turned to the active level reaches a third time period. In other words, the second unidirectional delay circuit DL2 causes the transition edge of the zero crossing indication signal ZCD, which is inverted from the inactive level to the active level, to be delayed for the third period. The second unidirectional delay circuit DL2 is further configured to: and outputting the zero crossing indication signal at the invalid level when the time when the zero crossing indication signal ZCD is inverted to the valid level does not reach the third time period or the zero crossing indication signal ZCD is at the invalid level. The input terminal of the first inverter NG1 is coupled to the output terminal of the second unidirectional delay circuit DL 2. The output of the first inverter NG1 is coupled to the second input of the OR gate OR. The sleep indication signal SLP is output from the output terminal of the OR gate OR.

When the zero crossing indication signal ZCD is at an inactive level (low level), the sleep indication signal SLP output from the OR gate OR is at an inactive level (high level). When the time when the sleep indication signal SLP turns to the inactive level reaches the second period, the second transistor M2 is turned on, and the ramp signal is reset to zero volt. At this time, the second inverter NG2 outputs a high level signal, and the third transistor M3 is turned off. When the time when the zero crossing indication signal ZCD is inverted to the active level (high level) reaches the third period, the sleep indication signal SLP output from the OR gate OR is inverted to the active level (low level), and the second transistor M2 is turned off. At this time, the bias current Ibias starts to charge the third capacitor C3, and the ramp signal starts to rise. Through the inversion of the second inverter NG2, the third transistor M3 starts to be turned on, thereby accelerating the rising speed of the ramp signal. When the rise time of the ramp signal reaches the first period, the ramp signal rises to an active level (high level). The third inverter NG3 supplies a high level signal to the first input terminal of the OR gate OR, thereby causing the sleep indication signal SLP to flip to an inactive level (high level). The second transistor M2 is turned on at a time when the sleep indication signal SLP is turned to the inactive level reaches the second period, and the ramp signal is reset to zero volt, so that the sleep indication signal SLP is turned to the active level (low level).

In the example of fig. 7, the rising speed of the ramp signal is increased by the third transistor M3, so the bias current Ibias may be set smaller than Ibias in fig. 6 to further save static power consumption.

Fig. 8 shows an exemplary circuit diagram of the bias current source IS in fig. 6 and 7. The bias current source IS includes: fourth to eighth transistors M4 to M8 and a start circuit ST. Wherein the start-up circuit ST is configured to: the fourth transistor M4 IS supplied with a start-up current when the DC-DC converter IS powered up and stops operating when the bias current source IS capable of generating the bias current Ibias. The control electrode and the second electrode of the fourth transistor M4 are coupled to the output terminal of the start-up circuit ST, the second electrode of the fifth transistor M5, the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8. The first pole of the fourth transistor M4 is coupled to the first voltage terminal V1. The control electrode of the fifth transistor M5 is coupled to the control electrode and the second electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7. A first pole of the fifth transistor M5 is coupled to a first end of the first resistor Ra. The second terminal of the first resistor Ra is coupled to the first terminal of the second resistor Rb and the first pole of the sixth transistor M6. A second terminal of the second resistor Rb is coupled to the second voltage terminal V2. The first pole of the seventh transistor M7 is coupled to the first voltage terminal V1. The first pole of the eighth transistor M8 is coupled to the first voltage terminal V1. The second pole of the eighth transistor M8 is coupled to the first end of the third capacitor C3. The current flowing through the fourth transistor M4 is mirrored to the eighth transistor M8, resulting in the bias current Ibias.

Fig. 9 shows a timing diagram of some signals for a DC-DC converter according to an embodiment of the disclosure. At the first time T1, the output voltage VOUT drops to Vea, and thus the pulse width modulation signal PWM is inverted to a high level. The logic and driving circuit 240 controls the upper tube driving signal dr_q1 to flip to a low level, the upper tube Q1 is turned on, and the inductor current IL increases. The zero crossing indication signal ZCD is inverted to a low level, and thus the sleep indication signal SLP is inverted to a high level.

Since the first voltage comparator CMP1 is a hysteresis comparator, the pulse width modulation signal PWM is inverted to a low level when the output voltage VOUT is higher than Vea by a preset value at the second time T2.

At the third time T3, the inductor current IL rises to the peak current, and the logic and driving circuit 240 controls the upper tube driving signal dr_q1 and the lower tube driving signal dr_q2 to flip to the high level, the upper tube Q1 is turned off and the lower tube Q2 is turned on, and the inductor current IL starts to fall.

At the fourth time T4, the inductor current IL falls to zero, the zero-crossing indication signal ZCD is inverted to a high level, and thus the sleep indication signal SLP is inverted to a low level. The logic and drive circuit 240 controls the down tube drive signal dr_q2 to flip low, both the up tube Q1 and the down tube Q2 are turned off, and the inductor current IL remains zero.

From the fourth time T4 to the fifth time T5, the ramp signal rises to a high level. The sleep indication signal SLP is flipped to a high level. The second transistor M2 is turned on at a time when the sleep indication signal SLP is turned to the high level for a second period (from the fifth time T5 to the sixth time T6), and the ramp signal is reset to zero volt, so that the sleep indication signal SLP is turned to the low level.

Thus, the DC-DC converter is awakened to refresh Vref1 and Vea over a first period of time during the sleep period, and enters the sleep period again when the wake-up time reaches a second period of time. Turning off the voltage conversion circuit during the sleep period of the DC-DC converter can reduce the quiescent current of the DC-DC converter. Furthermore, the DC-DC converter is awakened at fixed time, so that unstable output voltage VOUT caused by electric leakage of components can be avoided.

The embodiment of the disclosure also provides a chip. The chip includes a DC-DC converter according to an embodiment of the present disclosure. The chip is, for example, a power management type chip.

The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is for example a smart terminal device such as a tablet computer, a smart phone or the like.

In summary, the DC-DC converter according to the embodiments of the present disclosure can reduce the quiescent current, thereby reducing power consumption. The DC-DC converter according to the embodiment of the disclosure can be awakened at fixed time to avoid unstable output voltage VOUT caused by electric leakage of components.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A DC-DC converter, comprising: a voltage conversion circuit, a switching circuit, a voltage holding circuit, a first voltage comparator, a second voltage comparator, a zero-crossing detection circuit, a logic and driving circuit, a power tube, a shunt tube, and an inductor,

wherein the voltage conversion circuit is configured to: converting a first reference voltage to a second reference voltage during a non-sleep period of the DC-DC converter; and stopping the operation during a sleep period of the DC-DC converter;

the switching circuit is configured to: during the non-sleep period of the DC-DC converter, causing an output of the voltage conversion circuit to be connected to a first input of the first voltage comparator via a first node, thereby providing the second reference voltage to the first input of the first voltage comparator; and disconnecting the voltage conversion circuit from the first input of the first voltage comparator during the sleep period of the DC-DC converter;

The voltage holding circuit is configured to: maintaining a voltage at the first input of the first voltage comparator;

the second input end of the first voltage comparator is coupled with the output end of the DC-DC converter, and pulse width modulation signals are output from the output end of the first voltage comparator;

the second voltage comparator is configured to output an inductor current peak indication signal at an active level in a case where an inductor current flowing through the inductor reaches a peak current threshold;

the zero-crossing detection circuit is configured to: outputting a zero crossing indication signal at an effective level under the condition that the inductance current is zero;

the logic and drive circuitry is configured to: and when the pulse width modulation signal is in an effective level, the power tube is controlled to be turned on and the freewheel tube is controlled to be turned off, when the inductive current peak value indication signal is in an effective level, the power tube is controlled to be turned on and the freewheel tube is controlled to be turned off, and when the zero crossing indication signal is in an effective level, the power tube and the freewheel tube are controlled to be turned off.

2. A DC-DC converter according to claim 1, wherein the voltage conversion circuit comprises: a reference voltage circuit, a first voltage controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, and a second feedback resistor,

Wherein the reference voltage circuit is configured to generate the first reference voltage;

a first end of the first voltage controlled switch is coupled to the output end of the reference voltage circuit, a second end of the first voltage controlled switch is coupled to the first input end of the error amplifier, and the first voltage controlled switch is configured to be closed during the non-sleep period of the DC-DC converter and to be opened during the sleep period of the DC-DC converter;

a second input end of the error amplifier is coupled with a first end of the first feedback resistor and a first end of the second feedback resistor, an output end of the error amplifier is coupled with a control electrode of the first transistor, and the error amplifier stops working during the period that the DC-DC converter is in the dormancy state;

a first end of the first capacitor is coupled with the first input end of the error amplifier, and a second end of the first capacitor is coupled with a second voltage end;

a first pole of the first transistor is coupled to the second end of the first feedback resistor and the first node, and a second pole of the first transistor is coupled to a first voltage end;

the second end of the second feedback resistor is coupled to the second voltage end.

3. A DC-DC converter according to claim 1 wherein the switching circuit comprises: a second voltage-controlled switch is provided for controlling the voltage of the first voltage-controlled switch,

wherein a first end of the second voltage controlled switch is coupled to the first node, a second end of the second voltage controlled switch is coupled to the first input of the first voltage comparator, the second voltage controlled switch is configured to be closed during the non-sleep period of the DC-DC converter and to be opened during the sleep period of the DC-DC converter.

4. A DC-DC converter according to claim 1, wherein the voltage holding circuit comprises: the second capacitor is used to form a second capacitor,

the first end of the second capacitor is coupled to the first input end of the first voltage comparator, and the second end of the second capacitor is coupled to the second voltage end.

5. A DC-DC converter according to any one of claims 1 to 4, wherein the DC-DC converter further comprises: the sleep control circuit is configured to control the sleep mode of the device,

the sleep control circuit is configured to: generating a sleep indication signal according to the zero crossing indication signal; wherein, the sleep indication signal is at an inactive level in case the zero crossing indication signal is at an inactive level; the sleep indication signal is flipped to an active level when the zero crossing indication signal is flipped to an active level; the sleep indication signal toggles to an inactive level after a first period of time from when the sleep indication signal toggles to an active level and remains at an inactive level for a second period of time.

6. A DC-DC converter according to claim 5 wherein the sleep control circuit comprises: a ramp signal generating circuit, a timing clear circuit, and a sleep signal outputting circuit,

the ramp signal generating circuit is configured to: generating a ramp signal and providing the ramp signal to the sleep signal output circuit via a second node, wherein the ramp signal rises to an active level when a rise time of the ramp signal reaches the first period of time;

the timing clear circuit is configured to: resetting the ramp signal when the time for which the sleep indication signal is flipped to an inactive level reaches the second period;

the sleep signal output circuit is configured to: the sleep indication signal is at an inactive level if the zero crossing indication signal is at an inactive level or the ramp signal is at an active level; otherwise, the sleep indication signal is at an active level.

7. The DC-DC converter according to claim 6, wherein the ramp signal generating circuit includes: a bias current source, and a third capacitor,

wherein the bias current source is configured to: providing a bias current to a first terminal of the third capacitor;

The first end of the third capacitor is coupled to the second node, and the second end of the third capacitor is coupled to the second voltage end.

8. The DC-DC converter of claim 6 wherein the timing clearing circuit comprises: a first unidirectional delay circuit, and a second transistor,

wherein the first unidirectional delay circuit is configured to: controlling the second transistor to be conducted when the time for the sleep indication signal to flip to the inactive level reaches the second time period;

the first pole of the second transistor is coupled to the second voltage terminal, and the second pole of the second transistor is coupled to the second node.

9. A DC-DC converter according to claim 5 wherein the sleep control circuit comprises: a bias current source, a third capacitor, a first inverter, a second inverter, a third inverter, a first unidirectional delay circuit, a second transistor, a third transistor, and an or gate,

the first end of the third capacitor is coupled with the input end of the second inverter, the second pole of the second transistor and the second pole of the third transistor, and the second end of the third capacitor is coupled with a second voltage end;

A control electrode of the third transistor is coupled with the output end of the second inverter and the input end of the third inverter, and a first electrode of the third transistor is coupled with a first voltage end;

the output end of the third inverter is coupled with the first input end of the OR gate;

the first unidirectional delay circuit is configured to: controlling the second transistor to be conducted when the time for the sleep indication signal to flip to the invalid level reaches a second time period;

a first pole of the second transistor is coupled to the second voltage terminal;

the second unidirectional delay circuit is configured to: outputting a delayed zero crossing indication signal when the time of turning over the zero crossing indication signal to the effective level reaches a third time period;

the input end of the first inverter is coupled with the output end of the second unidirectional delay circuit, and the output end of the first inverter is coupled with the second input end of the OR gate;

and outputting the sleep indication signal from the output end of the OR gate.

10. A DC-DC converter, comprising: a reference voltage circuit, a first voltage-controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, a second voltage-controlled switch, a second capacitor, a first voltage comparator, a second voltage comparator, a zero-crossing detection circuit, a logic and driving circuit, a power transistor, a shunt tube, and an inductor,

Wherein the reference voltage circuit is configured to generate a first reference voltage;

a controlled end of the first voltage-controlled switch is provided with a sleep indication signal, a first end of the first voltage-controlled switch is coupled with an output end of the reference voltage circuit, a second end of the first voltage-controlled switch is coupled with a first input end of the error amplifier, wherein the sleep indication signal is at an inactive level during a non-sleep period of the DC-DC converter and at an active level during a sleep period of the DC-DC converter;

a first pole of the first transistor is coupled to the second end of the first feedback resistor and the first end of the second voltage-controlled switch, and a second pole of the first transistor is coupled to a first voltage end;

A second end of the second feedback resistor is coupled to the second voltage end;

the controlled end of the second voltage-controlled switch is provided with the sleep indication signal, and the second end of the second voltage-controlled switch is coupled with the first input end of the first voltage comparator;

a first end of the second capacitor is coupled with the first input end of the first voltage comparator, and a second end of the second capacitor is coupled with the second voltage end;