CN116454123A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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Publication number
CN116454123A
CN116454123A CN202210984942.2A CN202210984942A CN116454123A CN 116454123 A CN116454123 A CN 116454123A CN 202210984942 A CN202210984942 A CN 202210984942A CN 116454123 A CN116454123 A CN 116454123A
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China
Prior art keywords
gate dielectric
dielectric layer
layer
fin structure
isolation insulating
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CN202210984942.2A
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Chinese (zh)
Inventor
唐浩明
陈书涵
简筠珊
李达元
徐志安
陈宗儒
丁一心
王涵圣
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/837,848 external-priority patent/US20230274938A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116454123A publication Critical patent/CN116454123A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an isolation insulating layer is formed such that an upper portion of the fin structure is isolated from the isolation insulating layerAnd forming a gate dielectric layer by a deposition process, performing a nitridation operation on the gate dielectric layer, and forming a gate electrode layer over the gate dielectric layer. The gate dielectric layer formed comprises silicon oxide and the nitridation operation comprises using N 2 Gas and NH 3 Plasma nitriding operation of the gas.

Description

Method for manufacturing semiconductor device and semiconductor device
Technical Field
The present disclosure relates generally to a method of manufacturing a semiconductor device and a semiconductor device.
Background
As the semiconductor industry moves into nanotechnology process nodes for higher device density, higher performance, and lower cost, challenges from both manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate Field Effect Transistors (FETs), including fin FETs (finfets) and Gate All Around (GAA) FETs. As transistor dimensions continue to scale down to technology nodes below 10-15nm, further improvements in finfets, such as precise Critical Dimension (CD) control and defect-free or damage-free fin formation processes, are needed.
Disclosure of Invention
According to an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, the method including: forming a fin structure by patterning the semiconductor layer; forming an isolation insulating layer such that an upper portion of the fin structure protrudes from the isolation insulating layer; forming a gate dielectric layer by a deposition process; introducing nitrogen into the gate dielectric layer after forming the gate dielectric layer; and forming a gate electrode layer over the gate dielectric layer, wherein the formed gate dielectric layer is silicon oxide.
According to another embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, the method including: forming a fin structure by patterning the semiconductor layer; forming an isolation insulating layerSuch that an upper portion of the fin structure protrudes from the isolation insulating layer; forming a gate dielectric layer over the fin structure by a deposition process; performing a nitridation operation on the gate dielectric layer; and forming a gate electrode layer over the gate dielectric layer, wherein: the gate dielectric layer formed comprises silicon oxide, and the nitridation operation comprises using N 2 Gas and NH 3 Plasma nitridation of one or more of the gases and flow ratio NH 3 /(N 2 +NH 3 ) In the range of 0.4 to 1.0.
According to another embodiment of the present disclosure, there is provided a semiconductor device including: a semiconductor fin structure disposed over the substrate and including a channel region; an isolation insulating layer from which the channel region protrudes; a gate dielectric layer disposed over the channel region; and a gate electrode disposed over the gate dielectric layer, wherein: the gate dielectric layer comprises silicon oxide that is only partially nitrided.
Drawings
The disclosure is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A, 1B, 1C, and 1D illustrate cross-sectional views of various stages of a sequential process for fabricating a FinFET device in accordance with an embodiment of the present disclosure.
Fig. 2A, 2B, 2C, and 2D illustrate cross-sectional views of various stages of a sequential process for fabricating a FinFET device in accordance with an embodiment of the present disclosure.
Fig. 3A, 3B, 3C, and 3D illustrate cross-sectional views of various stages of a sequential process for fabricating a FinFET device in accordance with an embodiment of the present disclosure.
Fig. 4A, 4B, 4C, 4D, 4E, and 4F illustrate cross-sectional views of various stages of a sequential process for fabricating a FinFET device in accordance with an embodiment of the present disclosure.
Fig. 5 shows a flowchart of sequential fabrication operations of a FinFET device in accordance with an embodiment of the present disclosure.
Fig. 6A is a perspective view after forming a gate electrode layer, and fig. 6B shows a cross-sectional view of a gate dielectric layer and a fin structure, according to an embodiment of the present disclosure.
Fig. 7A, 7B, and 7C illustrate cross-sectional views of a gate dielectric layer and a fin structure according to various embodiments of the present disclosure.
Fig. 8 illustrates nitrogen concentration along the vertical direction of a nitrided gate dielectric layer according to various embodiments of the present disclosure.
Fig. 9A illustrates a plasma processing apparatus according to an embodiment of the present disclosure, and fig. 9B illustrates a pulse bias plasma process according to an embodiment of the present disclosure.
Fig. 10A shows a schematic diagram of a directional plasma processing apparatus according to an embodiment of the disclosure. Fig. 10B, 10C, and 10D illustrate schematic diagrams of directional plasma processing according to embodiments of the present disclosure.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired characteristics of the device. Furthermore, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. For simplicity and clarity, the various features may have been arbitrarily drawn at different scales.
Furthermore, spatially relative terms (e.g., "below," "lower," "above," "upper," etc.) may be used herein to facilitate describing a relationship of one element or feature to another element(s) or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the term "consisting of" may mean "comprising" or "consisting of. In this disclosure, the phrase "one of A, B and C" refers to "A, B and/or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and unless otherwise indicated, does not refer to one element from a, one element from B, and one element from C. Throughout this disclosure, source and drain may be used interchangeably, and source/drain refers to one or both of source and drain. In the following embodiments, materials, configurations, dimensions, processes, and/or operations as described with respect to one embodiment (e.g., one or more of the figures) may be employed in other embodiments, and detailed descriptions thereof may be omitted.
The quality of the gate dielectric layer is one of the key issues in the fabrication operations of semiconductor devices including finfets. In particular, when silicon oxide is used as the gate dielectric layer, the gate dielectric layer is required to exhibit high reliability of electrical properties (e.g., high Time Dependent Dielectric Breakdown (TDDB) properties) and high physical properties (e.g., high etching durability). In the present disclosure, a novel process is provided for improving the quality of a silicon oxide gate dielectric layer by introducing nitrogen into the silicon oxide layer.
Fig. 1A-4F illustrate views of various stages of a sequential fabrication operation of a FinFET device according to an embodiment of the present disclosure, and fig. 5 illustrates a flowchart of a sequential fabrication operation of a FinFET device according to an embodiment of the present disclosure. It will be appreciated that for additional embodiments of the method, additional operations may be provided before, during, and after the processes shown in fig. 1A-4F and 5, and that some of the operations described below may be replaced or eliminated. The order of these operations/processes may be interchangeable.
In S101 of fig. 5, a hard mask pattern for forming a fin structure is formed. In some embodiments, as shown in FIG. 1A, a hard mask layer 15 is formed over the substrate 10. In one embodiment, the substrate 10 includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate 10 may comprise single crystal semiconductor materials such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP. In one embodiment, the substrate 10 is made of Si. The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., of p-type or n-type conductivity). The dopant is, for example, boron (BF 2 ) And phosphorus, arsenic for p-type finfets.
In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. In some embodiments, the first mask layer 15A comprises a silicon nitride layer and the second mask layer 15B comprises a silicon oxide layer. The first mask layer 15A and the second mask layer 15B are formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD) including sputtering, atomic Layer Deposition (ALD), or other suitable film formation process. In some embodiments, the pad oxide layer 12 is formed before the first mask layer 15A is formed, and the pad oxide layer 12 is made of silicon oxide that can be formed by thermal oxidation.
In some embodiments, the fin structure is formed using one or more photolithographic processes, including a double patterning process or a multiple patterning process. Typically, a double patterning process or a multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns, for example, having a pitch that is smaller than would otherwise be possible using a single direct lithographic process. For example, as shown in fig. 1B, a sacrificial layer is formed over a substrate and patterned using one or more photolithography and etching processes to form a mandrel pattern (sacrificial pattern) 16. Then, a blanket layer 18 is formed as shown in fig. 1C, and an anisotropic etch is performed to form sidewall spacers 18 beside the mandrel pattern using a self-aligned process, as shown in fig. 1D. Then, the mandrel patterns 16 are removed, and the remaining spacers 18 are used as mask patterns 18, as shown in fig. 2A. In some embodiments, one or more additional sidewall formation processes are performed to form a mask pattern having further reduced pitch.
As shown in fig. 2A, mask pattern 18 includes a plurality of line patterns corresponding to one or more fin structures in the p-type region and one or more fin structures in the n-type region. In some embodiments, the pitch of the mask patterns 18 in the p-type region is greater than the pitch of the mask patterns 18 in the n-type region.
Furthermore, in some embodiments, as shown in fig. 2B, a cap layer 19 is further formed over the mask pattern 18. In some embodiments, cap layer 19 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride (SiON), siOCN, siCN, fluorine doped silicate glass (FSG), or low-k dielectric materials. In some embodiments, cap layer 19 is formed by ALD. In some embodiments, the thickness of the cap layer 19 is in the range of about 0.5nm to about 5 nm.
Mask layer 15 and pad oxide layer 12 are then patterned using one or more etching operations, as shown in fig. 2C. In some embodiments, mask pattern 18 is cut into short segments using one or more photolithography and etching operations to form patterns corresponding to individual fin structures prior to patterning mask layer 15 and pad oxide layer 12. In some embodiments, one or more unnecessary patterns (e.g., dummy structures) are also removed by etching.
Further, at S102 of fig. 5, the substrate 10 is patterned by using the patterned mask layer as an etching mask, thereby forming fin structures 20N and 20P (collectively referred to as fin structures 20) extending in the Y direction. In some embodiments, fin structure 20N is for an N-type FET and fin structure 20P is for a P-type FET. In fig. 2D, two fin structures 20P are arranged in the X direction in the P-type region, and four fin structures 20N are arranged in the X direction in the N-type region. However, the number of fin structures is not limited to two or four, and may be as few as one, and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of fin structure 20 to improve pattern fidelity in patterning operations.
After forming fin structure 20, one or more cleaning operations are performed at S103 of fig. 5. In some embodiments, meniscus reconfiguration cleaning (menisci re-configuration cleaning) using heated isopropyl alcohol is used as the cleaning operation.
In some embodiments, after the wet cleaning operation, a first anneal operation is performed to remove damage to the sidewalls of the fin structure at S104 of fig. 5. In some embodiments, the annealing operation includes rapid thermal annealing at a temperature in the range of about 900 ℃ to about 1100 ℃ for about 1 second to 20 seconds. In other embodiments, the temperature is in the range of about 950 ℃ to 1050 ℃. In other embodiments, the duration is in the range of about 5 seconds to 15 seconds. In some embodiments, the annealing operation is performed in an inert gas (Ar, he, and/or N 2 ) Executing in the environment. In other embodiments, the annealing operation is at 1×10 -7 To 5X 10 -6 Performed under a pressure in the range of the torr. The annealing operation diffuses hydrogen and fluorine atoms out of the fin structure and recrystallizes the damaged region. When the temperature is below the above range, hydrogen and fluorine may not be effectively removed from the damaged area of the fin structure, and when the temperature is above the above range, the fin structure may be bent and damaged. When the process time is shorter than the above range, hydrogen and fluorine may not be effectively removed from the damaged region of the fin structure, and when the process time is longer than the above range, the previously formed diffusion region may be damaged.
Next, at S105 of fig. 5, one or more layers of insulating material 30L for isolating the insulating layer are formed over the fin structure, as shown in fig. 3A. In some embodiments, the insulating material layer 30L is formed over the substrate such that the fin structure 20 is fully embedded in the insulating layer 30L. The insulating material of the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), siOCN, siCN, fluorine doped silicate glass (FSG), or a low-k dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing operation may be performed after the insulating layer is formed.
Then, as shown in fig. 3B, a first planarization operation (e.g., a Chemical Mechanical Polishing (CMP) method and/or an etch back method) is performed such that an upper surface of the second mask layer 15B is exposed from the insulating material layer 30L. Then, a second planarization operation is further performed to remove the second mask layer 15B and the first mask layer 15A and expose the upper surface of the fin structure 20, as shown in fig. 3C. In some embodiments, the first and second planarization operations are combined.
Then, as shown in fig. 3D, the insulating material layer 30L is recessed to form an isolation insulating layer 30, thereby exposing an upper portion (channel region 22) of the fin structure 20. By this operation, the fin structures 20 are electrically separated from each other by the isolation insulating layer 30, which is also referred to as Shallow Trench Isolation (STI).
In some embodiments, one or more insulating liner layers are formed over fin structure 20 prior to forming isolation insulating layer 30. The insulating liner layer comprises silicon oxide, silicon nitride, silicon oxynitride (SiON), siOCN, siCN, or any other suitable material. When the isolation insulating layer 30 is recessed, the insulating liner layer formed on the channel region 22 of the fin structure is removed, and the lower portion of the fin structure is covered by the insulating liner layer located in the isolation insulating layer 30.
In some embodiments, one or more liner semiconductor layers are formed over the fin structure prior to forming the isolation insulating layer 30 and forming the liner layer. In some embodiments, the liner semiconductor layer comprises a first liner semiconductor layer comprising silicon, siGe, or Ge. In certain embodiments, silicon is used. A first liner semiconductor layer is formed over the fin structure to prevent fin bending. In some embodiments, the thickness of the first liner semiconductor layer is in the range of about 0.2nm to about 4nm and in the range of about 0.5nm to about 2nm, depending on device and/or process requirements. In some embodiments, the first liner semiconductor layer is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. The LPCVD process uses, for example, siH at a temperature of about 400 ℃ to 850 ℃ and a pressure of about 1 Torr to 200 Torr below the annealing temperature 4 、Si 2 H 6 Or Si (or) 3 H 8 And the like. If SiGe or Ge is formed, the source gas includes GeH 4 Or Ge (Ge) 2 H 6 One or more ofA plurality of them. In some embodiments, the first liner semiconductor layer is undoped, while in other embodiments, the first liner semiconductor layer is appropriately doped for the N-type fin structure 20N and the P-type fin structure 20P.
In some embodiments, one or more wet cleaning operations are performed after the first liner semiconductor layer is formed. In some embodiments, the wet cleaning solution includes ammonia (NH 3 ) And hydrogen peroxide (H) 2 O 2 ) And/or aqueous hydrochloric acid (HCl) and hydrogen peroxide (H) 2 O 2 ) Is a solution of (a) and (b). During the wet clean operation, the first liner semiconductor layer (and in some embodiments the fin structure 20) is lightly etched.
Then, in some embodiments, a second liner semiconductor layer is formed over the fin structure. In some embodiments, the second liner semiconductor layer comprises silicon, siGe, or Ge. In certain embodiments, silicon is used. A second liner semiconductor layer is formed over the fin structure to adjust the dimension (width) of the fin structure. In some embodiments, the thickness of the second liner semiconductor layer is in the range of about 0.2nm to about 4nm and in the range of about 0.5nm to about 2nm, depending on device and/or process requirements. In some embodiments, the second liner semiconductor layer is epitaxially grown similar to the first liner semiconductor layer. In some embodiments, the second liner semiconductor layer is undoped, while in other embodiments, the second liner semiconductor layer is appropriately doped for the N-type fin structure 20N and the P-type fin structure 20P.
Next, after forming the isolation insulating layer 30, a gate dielectric layer 120 is formed over the channel region 22 of the fin structure 20 and the upper surface of the isolation insulating layer 30, as shown in fig. 4A, at S106 of fig. 5. In some embodiments, gate dielectric layer 120 is silicon oxide formed by CVD including low pressure CVD and plasma enhanced CVD, ALD including plasma enhanced ALD, or other suitable film formation processes. In some embodiments, the thickness of the gate dielectric layer 120 is in the range of about 0.5nm to about 10nm and in other embodiments in the range of about 1nm to about 6nm, depending on design and/or process requirements.
Then, at S107 of fig. 5, as shown in fig. 4B, the nitridation operation 100 is performed on the gate dielectric layer 120 to nitrided a surface portion of the gate dielectric layer 120.
In some embodiments, by using a gas N with an active 2 And NH 3 Is used to perform the nitridation process. In some embodiments, NH 3 /(N 2 +NH 3 ) Is in the range of about 0.4 to 1.0. In some embodiments, NH 3 Is greater than N 2 Is a flow rate of (a). In some embodiments, the flow ratio is in the range of about 0.4 to 0.6. In other embodiments, the flow ratio is in the range of about 0.8 to 0.95. In certain embodiments, the flow ratio is in the range of about 0.6 to 0.8. When NH 3 As the amount of (c) increases, the uniformity of nitriding increases.
In some embodiments, the nitridation process is performed at a substrate temperature in the range of about 50 ℃ to about 450 ℃ and a pressure in the range of about 10 mtorr to about 150 mtorr. In some embodiments, the input RF power of the plasma is in the range of about 300W to about 2000W. In some embodiments, the RF power is applied in pulses having a duty cycle of about 5% to about 70%. The nitriding time period is in the range of about 20 seconds to about 150 seconds, depending on design and/or process requirements.
After the nitridation process, the gate dielectric layer 120N has a composition of SiO 2-x N x Wherein in some embodiments x is from about 0.01 to about 0.2, and in other embodiments x is from about 0.05 to 0.1. In some embodiments, gate dielectric layer 120N has a lower nitrogen concentration region where x is about 0.01 to about 0.05 and a higher nitrogen concentration region where x is about 0.1 to about 0.2.
After the nitridation process, a gate electrode layer 40 is formed over the channel region 22 of the fin structure at S108 of fig. 5, as shown in fig. 4C and 4D. In some embodiments, the gate electrode layer 40 comprises silicon, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the gate electrode layer 40 is in the range of about 100nm to about 200 nm. The gate electrode layer 40 is deposited using CVD (including LPCVD and PECVD, PVD, ALD) or other suitable process and is patterned using, for example, a hard mask layer comprising one or more layers of silicon nitride and silicon.
In the embodiment of fig. 4C-4D, one gate electrode layer 40 is disposed over two fin structures 20P in the P-type region and one gate electrode layer 40 is disposed over four fin structures 20N in the N-type region. However, the number of fin structures per gate electrode layer is not limited and may be 1, 2, 3, or more than 4. In other embodiments, one gate electrode layer 40 is formed over one or more N-type fin structures 20N and one or more P-type fin structures 20P.
After forming the gate electrode layer 40, in S109 of fig. 5, the gate sidewall spacers 45 are formed as shown in fig. 4E. A blanket layer of insulating material for the sidewall spacers is conformally formed using CVD or other suitable method. The blanket layer is conformally deposited such that it has substantially equal thickness on the vertical surfaces (e.g., sidewalls), horizontal surfaces, and top of the sacrificial gate structure. In some embodiments, the blanket layer is deposited to have a thickness in the range of about 2nm to about 10 nm. In one embodiment, the insulating material of the blanket layer is a silicon nitride based material, such as SiN, siON, siOCN or SiCN, and combinations thereof. Sidewall spacers are formed on opposite sidewalls of the gate electrode layer 40.
Subsequently, at S110 of fig. 5, source/drain epitaxial layers are formed. In some embodiments, the fin structure of the source/drain regions is recessed below the upper surface of the isolation insulating layer 30 using dry etching and/or wet etching, and then one or more semiconductor layers are epitaxially formed over the recessed fin structure. In other embodiments, one or more semiconductor layers are epitaxially formed over the source/drain regions of the un-recessed fin structure. The source/drain epitaxial layers of the n-type FET include one or more layers of SiC, siP, and SiCP, and the source/drain epitaxial layers of the p-type FET include one or more layers of SiGe, siGeSn, which may be doped with B. In at least one embodiment, the epitaxial layer is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. The LPCVD process uses the following gases at a temperature of about 400 ℃ to about 850 ℃ and a pressure of about 1 Torr to about 200 TorrThe body performs: such as SiH 4 、Si 2 H 6 Or Si (or) 3 H 8 A silicon source gas of the same type; such as GeH 4 Or Ge (Ge) 2 H 6 A germanium source gas of the same type; such as CH 4 Or SiH 3 CH 3 Such as a carbon source gas; such as pH 3 A phosphorus source gas of the same type; and/or such as B 2 H 6 Such as a boron source gas. In some embodiments, two or more layers having different compositions (e.g., different P, C, ge and/or B concentrations) are formed as source/drain epitaxial layers.
Subsequently, at S111 of fig. 5, a first interlayer dielectric (ILD) layer 50 is formed over the source/drain epitaxial layer and the gate electrode layer 40, as shown in fig. 4F. Materials for the first ILD layer 50 include compounds comprising Si, O, C, and/or H, such as silicon oxide, siCOH, and SiOC. An organic material such as a polymer may be used for the first ILD layer 50.
Fig. 6A is a perspective view after forming gate electrode layer 40, and fig. 6B shows a cross-sectional view of gate dielectric layer 120N and fin structure 20 along the X-direction.
In some embodiments, the height H1 of the channel region 22 of the fin structure 20 above the upper surface of the isolation insulating layer 30 is in the range of about 15nm to about 85nm, depending on design and/or process requirements. In some embodiments, the width W1 of the channel region 22 at its bottom is in the range of about 4nm to about 30nm, and the spacing S1 between adjacent channel regions 22 is in the range of about 6nm to about 30nm, depending on design and/or process requirements.
In some embodiments, the thickness T1 of the gate dielectric layer at the top end of the channel region 22 is in the range of about 0.5nm to about 6nm, depending on design and/or process requirements. In some embodiments, the nitrided portion T2 (SiON) has a thickness of about 20% to about 80% of T1, or about 30% to 50% of T1. In some embodiments, the interface between the nitrided portion (SiON) and the non-nitrided portion (silicon oxide) is located at the following locations: at this position, the nitrogen concentration is 1/e (e: euler's number) of the nitriding concentration of the surface of the nitrided portion, or the nitrogen concentration is lower than the detection limit of Secondary Ion Mass Spectrometry (SIMS). In some embodiments, the thickness T3 of the gate dielectric layer on the sidewalls of the channel region 22 is in the range of about 0.5nm to about 6nm, depending on design and/or process requirements. In some embodiments, T1> T3.
In some embodiments, as shown in fig. 7A, nitrogen atoms are substantially uniformly incorporated into the silicon oxide gate dielectric layer. In some embodiments, the uniformity of the nitrogen concentration in the nitrided portion of the gate dielectric layer (e.g., at the surface of the gate dielectric layer) is in the range of about 5% to 50% relative to the average nitrogen concentration in the nitrided portion, and in other embodiments in the range of about 10% to 25%.
In some embodiments, the nitrided gate dielectric layer 120N has a bottom region with a height hb=5% h1 and a top region with a height ht=5% h1, and the nitrogen concentration Cb of the bottom region and the nitrogen concentration Ct of the top region satisfy Cb/Ct from about 0.8 to about 1.0. In some embodiments, cb/Ct is from about 0.85 to about 0.95. In some embodiments, the bottom end of the bottom region is located 5nm from the upper surface of the isolation insulating layer, and the top end of the top region corresponds to the top end of the channel region 22. In some embodiments, the depth T4 of the nitrided portion of the gate dielectric layer 120N formed on the sidewalls of the channel region 22 is about 20% to about 80% of the total thickness T3 of the gate dielectric layer 120N formed on the sidewalls of the channel region 22, or about 30% to about 50% of T3.
Further, the nitrogen concentration gradually (e.g., monotonically) decreases from the surface to the interface between the gate dielectric layer 120N and the channel region 22 along the depth direction of the gate dielectric layer 120N. In some embodiments, the nitrogen concentration at the interface between gate dielectric layer 120N and channel region 22 is less than about 3 atomic% and greater than 0 atomic%. The nitrided gate dielectric layer 120N is a single layer silicon oxynitride (SiON) having a gradual change in nitrogen concentration as a whole, and thus differs from a double layer SiN/SiO in which the nitrogen concentration is changed in a stepwise manner 2 SiN/SiON or SiON/SiO 2 。
In some embodiments, as shown in fig. 7B, the nitrogen concentration in nitrided gate dielectric layer 120N is greater in the upper region than in the bottom region. In some embodiments, the gate dielectric layer formed on the sidewalls of the channel region 22 is only partially nitrided. In some embodiments, the height H2 of the nitrided portion of the gate dielectric layer formed on the sidewalls of the channel region 22 from the top end of the channel region 22 is about 15% to about 70% of the channel height H1, or about 20% to about 50% of the channel height H1. In some embodiments, the nitrogen concentration at the interface between gate dielectric layer 120N and channel region 22 is less than about 3 atomic% and greater than 0 atomic%.
In some embodiments, the nitrided gate dielectric layer 120N has a bottom region with a height hb=5% h1, a middle region with a height hm=5% h1, and a top region with a height ht=5% h1, and the nitrogen concentration Cm of the middle region and the nitrogen concentration Ct of the top region satisfy Cm/Ct from about 0.2 to about 0.4. In some embodiments, cb/Ct is from about 0.01 to about 0.05. The middle region is the region of ± 0.025H1 with respect to the height 0.5H1. In some embodiments, the nitrogen concentration at the middle region and/or bottom region of gate dielectric layer 120N is less than about 3 atomic% (and greater than 0 atomic%).
In some embodiments, angle θ 1 (formed by sidewall planes of the gate dielectric layer formed on the sidewalls of the channel region 22 and interface planes between the nitrided and remaining (non-nitrided) portions of the gate silicon oxide layer) is equal to or lower than 5 degrees. In some embodiments, the angle is equal to or greater than 1 degree.
As the top of the silicon oxide gate dielectric layer is nitrided more, damage to the gate dielectric layer covering the upper portion of the fin structure (source/drain regions) exposed to the gate electrode etching operation may be reduced.
In some embodiments, as shown in fig. 7C, the nitrogen concentration of nitrided gate dielectric layer 120N formed on the sidewalls of channel region 22 is substantially similar to fig. 7A, and the nitrogen concentration of nitrided gate dielectric layer 120N formed on the upper region is higher than the side and bottom regions.
The nitrogen concentration Cb of the bottom region and the nitrogen concentration Cm of the middle region satisfy Cb/Cm of about 0.8 to about 1.0. In some embodiments, cb/Cm is from about 0.85 to about 0.95. In some embodiments, the nitrogen concentration Cm of the middle region and the nitrogen concentration Ct of the top region satisfy a Cm/Ct of about 0.4 to about 0.8. In some embodiments, cm/Ct is from about 0.5 to about 0.6.
As shown in fig. 7A to 7C, the gate dielectric layer formed on the isolation insulating layer 30 is also nitrided. In some embodiments, the nitrogen concentration Ci of the gate dielectric layer formed on the isolation insulating layer 30 is different from the middle region nitrogen concentration Cm and/or the bottom region nitrogen concentration Cb. In some embodiments, the nitrogen concentration Ci is about 70% to 95% of the nitrogen concentration Cm and/or Cb, and in other embodiments, the nitrogen concentration Ci is about 105% to 130% of the nitrogen concentration Cm and/or Cb. In some embodiments, the nitrogen concentration Ci is less than the nitrogen concentration Ct of the top region. In some embodiments, the nitrogen concentration Ci is about 0.7 to 0.95 of the nitrogen concentration Ct. In some embodiments, the nitrogen concentration Ci of the gate dielectric layer formed on the isolation insulating layer 30 increases with increasing distance from the fin structure.
As described above, the uniformity of the nitrogen concentration in nitrided gate dielectric layer 120N (particularly the side portion formed on the sidewall of channel region 22) may be controlled at least by controlling N 2 And NH 3 Is controlled by the gas flow ratio of the gas flow ratio. In some embodiments, the catalyst is formed from NH 3 The radicals induced by the plasma are anisotropic and are defined by N 2 The radicals induced by the plasma are isotropic. When N is 2 The top region of the gate dielectric layer is nitrided more than the bottom region as the flow rate of the gate dielectric layer increases. FIG. 8 shows the presence of NH 3 /(N 2 +NH 3 ) The nitrogen concentration of the nitrided gate dielectric layer in the vertical direction (along the sidewalls of the channel region 22) at various flow ratios. In FIG. 8, example 1 corresponds to NH 3 /(N 2 +NH 3 ) In the case of a flow ratio of 0.8 to 1.0, example 2 corresponds to NH 3 /(N 2 +NH 3 ) In the case of a flow ratio of 0.4 to 0.6, and example 3 corresponds to NH 3 /(N 2 +NH 3 ) The flow ratio of about 0.3.
In some embodiments, NH 3 /(N 2 +NH 3 ) Is varied during nitridation operations to the gate dielectric layer. In some casesIn the examples, NH was at a high flow ratio similar to that of examples 1 or 2 3 /(N 2 +NH 3 ) To perform a first nitridation operation and then to perform a second nitridation operation at a low flow rate ratio similar to that of examples 2 or 3 and vice versa. In some embodiments, NH 3 /(N 2 +NH 3 ) The flow ratio of (c) is gradually changed during the nitriding operation.
In some embodiments, the nitridation process to the gate dielectric layer includes a plasma treatment using plasma treatment apparatus 1000 shown in fig. 9A. Fig. 9B illustrates pulsed bias plasma operations according to an embodiment of the present disclosure. In some embodiments, the substrate 10 with the fin structure, isolation insulating layer, and gate dielectric layer formed thereon is placed on the wafer table 1100 of the vacuum chamber, and the substrate 10 and/or the wafer table 1100 are biased, for example, by a DC voltage. RF power (transformer coupled plasma (TCP) power) is applied to the counter electrode (counter electrode) 1200, and in some embodiments the counter electrode 1200 is a coil disposed over or around the vacuum chamber.
During plasma nitridation operations, a DC bias voltage is applied to the wafer table 1100 and RF power is applied to the TCP electrode. In the TCP plasma approach, the coil electrode 1200 is placed over or around the plasma nitridation chamber and RF power is applied to the coil electrode 1200. In the pulse bias method, the bias voltage is applied as a pulse, as shown in fig. 9B, and the power of the RF voltage is constant.
In some embodiments, the high (or on) value of the DC pulse bias voltage (V1) is in the range of about 100V to about 900V, and in other embodiments in the range of about 200V to about 400V. In some embodiments, the low value of the DC pulse bias is zero (off). In some embodiments, the power of the RF voltage is in the range of about 400W to about 1200W, and in other embodiments in the range of about 600W to 1000W.
In some embodiments, the frequency of the pulsed bias voltage (1/(one cycle)) is in the range of about 200Hz to about 8000Hz, and in other embodiments in the range of about 1000Hz to about 4000 Hz.
The duty cycle (on-off period ratio) of the pulses is in the range of about 10% to about 80% in some embodiments, and in other embodiments in the range of about 20% to 60%. The duty cycle may be a range of any two values from 10%, 20%, 30%, 40%, 50%, 60%, 70% and 80%.
As described above, the process gas NH is introduced from a gas source 3 And/or N 2 And accordingly performing a nitridation process.
Fig. 10A shows a schematic diagram of a directional plasma processing apparatus according to an embodiment of the disclosure. Fig. 10B, 10C, and 10D illustrate schematic diagrams of directional plasma processing according to embodiments of the present disclosure.
As shown in fig. 10A, a directional plasma processing apparatus (e.g., directional nitridation apparatus 2000) includes a main chamber 2010 and a plasma generation chamber 2020 for generating plasma, wherein a wafer table 2030 for a wafer to be processed is disposed in the main chamber 2010. In some embodiments, the plasma is an RF (radio frequency) generated plasma using a high frequency power supply of 13.56MHz and/or 2.45 GHz. Other frequency ranges may be used. A divider plate 2026 is disposed between the main chamber 2010 and the plasma chamber 2020. The partition plate 2026 includes a slit 2022, and the plasma beam 2100 is introduced from the slit 2022 into the main chamber. In some embodiments, the adjustable meniscus 2024 is disposed over the slit 2022 on the plasma chamber side. One or more vacuum systems 2040, including, for example, a turbo-molecular pump, are coupled to the main chamber and the plasma chamber (not shown) to maintain a reduced pressure within the chamber. In some embodiments, the pressure in the main chamber is lower than the pressure in the plasma chamber during the nitridation process.
In some embodiments, the divider plate 2026 and wafer table 2030 are biased by a DC voltage to extract and control the plasma beam 2100, respectively. In addition, the wafer table 2030 may be moved by a movement mechanism 2035 to scan the wafer with respect to the plasma beam 2100.
In some embodiments, at least one of the RF and DC bias voltages is adjusted to achieve the following electric fields: the electric field causes the radicals (N radicals) to flow substantially horizontally along an in-plane direction (e.g., X direction) relative to the substrate surface, or to provide a large angle of incidence. In some embodiments, the radicals are tuned to have a momentum distribution of the energetic species such that the momentum of the radicals or energetic species along the front line is different, i.e., the momentum of the radicals on the top path is different than the momentum of the radicals on the bottom path. In some embodiments, the momentum of the radicals on the top path is different from the momentum of the radicals in the intermediate path above the bottom path, and the momentum of the radicals on the top path is the same as or different from the momentum of the radicals on the bottom path. Any combination can be achieved by adjusting the electromagnetic control to adjust the energy of the free radicals.
In some embodiments, as shown in fig. 10B and 10C, the position of the meniscus 2024 is adjusted to change the angle of incidence θi of the plasma beam 2100. As shown in fig. 10D, by scanning the wafer in the X direction, a groove pattern can be formed without substantially expanding the groove in the Y direction.
In some embodiments, the ratio of the amount of nitridation in the X-direction to the amount of nitridation in the Y-direction is about 2 or greater, and in other embodiments is about 5 or greater. In certain embodiments, the ratio is about 10 or greater. Desirably, the ratio is as high as possible, but in some embodiments the ratio may be up to about 100, and in other embodiments the ratio is up to about 50. Further, the nitriding amount in the Z direction (vertical direction) is smaller than the nitriding amount in the X direction. In some embodiments, the ratio of the amount of nitridation in the X-direction to the amount of nitridation in the Z-direction is about 2 or greater, and in other embodiments the ratio is about 5 or greater. In certain embodiments, the ratio is about 10 or greater. Desirably, the ratio is as high as possible, and in some embodiments the ratio may be up to about 100, and in other embodiments the ratio is up to about 50.
As described above, the process gas NH is introduced from a gas source 3 And/or N 2 And accordingly performing a nitridation process. In some embodiments, the directed plasma beam 2100 is applied to the top and sidewalls of the channel region of the fin structure (e.g., applied along the X-direction of fig. 4B). By adjusting during the nitriding processOr dynamically changing the angle thetai of the plasma beam 2100, various nitridation profiles as shown in fig. 7A-7C may be obtained. For example, a high angle θi forms a nitridation profile similar to that of fig. 7B, while a low angle θi forms a nitridation profile similar to that of fig. 7A.
The various embodiments or examples described herein provide several advantages over the prior art. In embodiments of the present disclosure, the N may be adjusted by 2 And NH 3 To control the nitrogen profile in the nitrided silicon oxide gate dielectric layer. The plasma treatment of the present embodiment can produce a relatively shallow nitrided portion as compared to thermal nitridation, and can suppress the problem of nitrogen accumulation at the interface between the gate dielectric layer and the channel region, which would otherwise cause a threshold voltage change. In addition, by introducing nitrogen to the top of the gate dielectric layer, the etch resistance in the gate electrode etching operation can be improved, and further the fin top damage problem can be suppressed.
It is to be understood that not necessarily all advantages have been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.
According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer formed comprises silicon oxide and the nitridation operation comprises using N 2 Gas and NH 3 Plasma nitriding operation of the gas. In one or more of the foregoing and following embodiments, the flow ratio NH 3 /(N 2 +NH 3 ) In the range of 0.1 to 0.3. In one or more of the foregoing and following embodiments, the portion of the gate dielectric layer formed on the sidewalls of the upper portion of the fin structure does not include nitrogen, or includes nitrogen in an amount less than 3 atomic%. In one or more of the foregoing and following embodiments, the top of the gate dielectric layer and the upper side of the gate dielectric layer are wrapped around The top of the gate dielectric layer is formed on top of the upper portion of the fin structure including nitrogen in an amount of 20 to 40 atomic percent, and the upper side of the gate dielectric layer continues from the top to the upper portion of the fin structure a distance below the top that is 15% of the height of the upper portion of the fin structure from the upper surface of the insulating layer. In one or more of the foregoing and following embodiments, an angle between an interface between the nitrided portion of the gate dielectric layer and the non-nitrided portion of the gate dielectric layer and a sidewall of the gate dielectric layer is 1 to 5 degrees. In one or more of the foregoing and following embodiments, a nitrogen concentration at an interface between the gate dielectric layer and an upper portion of the fin structure after the nitridation operation is less than 3 atomic percent. In one or more of the foregoing and following embodiments, the portion of the gate dielectric layer formed on the isolation insulating layer is also nitrided. In one or more of the foregoing and following embodiments, the process temperature of the nitriding operation is in the range of 50 ℃ to 450 ℃. In one or more of the foregoing and following embodiments, the process duration of the nitriding operation is in the range from 20 seconds to 150 seconds.
According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer formed comprises silicon oxide and the nitridation operation comprises using N 2 Gas and NH 3 Plasma nitridation of one or more of the gases and flow ratio NH 3 /(N 2 +NH 3 ) In the range of 0.4 to 1.0. In one or more of the foregoing and following embodiments, the flow ratio is in the range of 0.8 to 0.95. In one or more of the foregoing and following embodiments, the entire surface of the gate dielectric layer is nitrided. In one or more of the foregoing and following embodiments, after the nitridation operation, the gate dielectric layer has a nitrogen concentration at a top region of the gate dielectric layer that is greater than a nitrogen concentration at a bottom region of the gate dielectric layer. In one or more of the foregoing and followingIn an embodiment, after the nitridation operation, a nitrogen concentration at an interface between the gate dielectric layer and an upper portion of the fin structure is less than 3 atomic percent. In one or more of the foregoing and following embodiments, the nitrided portion of the gate dielectric layer formed on the sidewalls of the upper portion of the fin structure has a depth of 20% to 80% of the thickness of the gate dielectric layer formed on the sidewalls of the upper portion of the fin structure. In one or more of the foregoing and following embodiments, the gate dielectric layer is a single layer whose nitrogen concentration varies in the thickness direction after the nitridation operation.
According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The nitriding operation includes using N 2 Gas and NH 3 Plasma nitriding operation of one or more of the gases, and flow ratio NH during nitriding operation 3 /(N 2 +NH 3 ) And (3) a change. In one or more of the foregoing and following embodiments, the flow ratio is gradually varied. In one or more of the foregoing and following embodiments, the flow ratio is varied two or more times in a stepwise manner. In one or more of the foregoing and following embodiments, the nitriding operation comprises directional plasma nitriding.
According to another aspect of the present disclosure, a semiconductor device includes: the semiconductor device includes a semiconductor fin structure disposed over a substrate and including a channel region, an isolation insulating layer from which the channel region protrudes, a gate dielectric layer disposed over the channel region, and a gate electrode disposed over the gate dielectric layer. The gate dielectric layer comprises silicon oxide that is only partially nitrided. In one or more of the foregoing and following embodiments, the portion of the gate dielectric layer formed on the sidewalls of the channel region does not include nitrogen or includes nitrogen in an amount less than 3 atomic percent. In one or more of the foregoing and following embodiments, the top of the gate dielectric layer and the upper side of the gate dielectric layer include nitrogen in an amount of 20 to 40 atomic percent, the top of the gate dielectric layer is formed on top of the upper portion of the fin structure, and the upper side of the gate dielectric layer continues from the top to a distance below the top of the upper portion of the fin structure that is 15% of the height of the channel region from the upper surface of the isolation insulating layer. In one or more of the foregoing and following embodiments, an angle between an interface between the nitrided portion of the gate dielectric layer and the non-nitrided portion of the gate dielectric layer and a sidewall of the gate dielectric layer is 1 to 5 degrees. In one or more of the foregoing and following embodiments, the nitrogen concentration at the intermediate side portion of the gate dielectric layer disposed below the upper side portion on the sidewall of the channel region includes a lesser amount of nitrogen than the upper side portion. In one or more of the foregoing and following embodiments, the nitrogen concentration of the medial side is less than 3 atomic percent. In one or more of the foregoing and following embodiments, the nitrogen concentration at the interface between the gate dielectric layer and the channel region is less than 3 atomic%. In one or more of the foregoing and following embodiments, the horizontal portion of the gate dielectric layer formed on the isolation insulating layer includes nitrogen. In one or more of the foregoing and following embodiments, the amount of nitrogen in the horizontal portion is less than the amount of nitrogen in the top portion of the gate dielectric layer formed on top of the channel region.
According to another aspect of the present disclosure, a semiconductor device includes: the semiconductor device includes a semiconductor fin structure disposed over a substrate and including a channel region, an isolation insulating layer from which the channel region protrudes, a gate dielectric layer disposed over the channel region, and a gate electrode disposed over the gate dielectric layer. The gate dielectric layer includes a nitrided silicon oxide portion and a silicon oxide portion disposed between the nitrided silicon oxide portion and the channel region, and uniformity of nitrogen concentration in the nitrided silicon oxide portion is 10% to 25% relative to an average nitrogen concentration in the nitrided silicon oxide portion. In one or more of the foregoing and following embodiments, the gate dielectric layer has a nitrogen concentration at a top region of the gate dielectric layer that is greater than a nitrogen concentration at a bottom region of the gate dielectric layer. In one or more of the foregoing and following embodiments, the nitrided silicon oxide portion is disposed on the sidewall of the channel region to a depth of 20% to 80% of the thickness of the gate dielectric layer formed on the sidewall of the channel region. In one or more of the foregoing and following embodiments, the nitrogen concentration in the nitrided silicon oxide portion gradually decreases from the surface to the silicon oxide portion. In one or more of the foregoing and following embodiments, the nitrogen concentration in the nitrided silicon oxide portion of the gate dielectric layer disposed on the sidewall of the channel region gradually decreases from the top of the gate dielectric layer to the bottom of the gate dielectric layer.
According to another aspect of the present disclosure, a semiconductor device includes: the semiconductor device includes a semiconductor fin structure disposed over a substrate and including a channel region, an isolation insulating layer from which the channel region protrudes, a gate dielectric layer disposed over the channel region, a gate electrode disposed over the gate dielectric layer, and a gate sidewall spacer disposed on a sidewall of the gate electrode. The gate dielectric layer has a composition of SiO 2-x N x Wherein x is 0.01 to 0.2. In one or more of the foregoing and following embodiments, the gate dielectric layer includes a top portion disposed at a top end of the channel region and a side portion disposed at a sidewall of the channel region, and a nitrogen concentration of the top portion is different from the side portion. In one or more of the foregoing and following embodiments, the side portions include a top side portion, a middle side portion below the top side portion, and a bottom side portion below the middle side portion, and the nitrogen concentration of the top side portion is different from the nitrogen concentration of at least one of the middle side portion and the bottom side portion. In one or more of the foregoing and following embodiments, the nitrogen concentration of the medial side portion is different than the nitrogen concentration of the bottom side portion. In one or more of the foregoing and following embodiments, the nitrogen concentration of the bottom side portion is 0.85 to 0.95 times the nitrogen concentration of the top side portion. In one or more of the foregoing and following embodiments, the nitrogen concentration at the interface between the gate dielectric layer and the channel region is less than 3 atomic%.
The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Example 1 is a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning the semiconductor layer; forming an isolation insulating layer such that an upper portion of the fin structure protrudes from the isolation insulating layer; forming a gate dielectric layer by a deposition process; introducing nitrogen into the gate dielectric layer after forming the gate dielectric layer; and forming a gate electrode layer over the gate dielectric layer, wherein the formed gate dielectric layer is silicon oxide.
Example 2 is the method of example 1, wherein: introducing nitrogen includes the use of N 2 Gas and NH 3 Plasma nitriding operation of gas and flow ratio NH 3 /(N 2 +NH 3 ) In the range of 0.1 to 0.3.
Example 3 is the method of example 2, wherein a portion of the gate dielectric layer formed on a sidewall of an upper portion of the fin structure does not include nitrogen, or includes nitrogen in an amount less than 3 atomic%.
Example 4 is the method of example 3, wherein the top of the gate dielectric layer and the sides of the gate dielectric layer include nitrogen in an amount of 20 to 40 atomic%, the top of the gate dielectric layer being formed on top of the upper portion of the fin structure, the sides of the gate dielectric layer continuing from the top to a distance below the top of the upper portion of the fin structure that is 15% of the height of the upper portion of the fin structure from the upper surface of the isolation insulating layer.
Example 5 is the method of example 4, wherein an angle between an interface between the nitrided portion of the gate dielectric layer and the non-nitrided portion of the gate dielectric layer and a sidewall of the gate dielectric layer is 1 to 5 degrees.
Example 6 is the method of example 2, wherein, after the nitridation operation, a nitrogen concentration at an interface between the gate dielectric layer and an upper portion of the fin structure is less than 3 atomic percent.
Example 7 is the method of example 2, wherein a portion of the gate dielectric layer formed on the isolation insulating layer is also nitrided.
Example 8 is the method of example 2, wherein the process temperature of the nitriding operation is in a range of 50 ℃ to 450 ℃.
Example 9 is the method of example 8, wherein a process duration of the nitriding operation is in a range of 20 seconds to 150 seconds.
Example 10 is a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning the semiconductor layer; forming an isolation insulating layer such that an upper portion of the fin structure protrudes from the isolation insulating layer; forming a gate dielectric layer over the fin structure by a deposition process; performing a nitridation operation on the gate dielectric layer; and forming a gate electrode layer over the gate dielectric layer, wherein: the gate dielectric layer formed comprises silicon oxide, and the nitridation operation comprises using N 2 Gas and NH 3 Plasma nitridation of one or more of the gases and flow ratio NH 3 /(N 2 +NH 3 ) In the range of 0.4 to 1.0.
Example 11 is the method of example 10, wherein the flow ratio is in a range of 0.8 to 0.95.
Example 12 is the method of example 10, wherein an entire outer surface of the gate dielectric layer is nitrided.
Example 13 is the method of example 10, wherein, after the nitridation operation, a nitrogen concentration of the gate dielectric layer is greater at a top region of the gate dielectric layer than at a bottom region of the gate dielectric layer.
Example 14 is the method of example 10, wherein, after the nitridation operation, a nitrogen concentration at an interface between the gate dielectric layer and an upper portion of the fin structure is less than 3 atomic percent.
Example 15 is the method of example 10, wherein a depth of the nitrided portion of the gate dielectric layer formed on the sidewall of the upper portion of the fin structure is 20% to 80% of a thickness of the gate dielectric layer formed on the sidewall of the upper portion of the fin structure.
Example 16 is the method of example 10, wherein after the nitridation operation, the gate dielectric layer is a single layer having a nitrogen concentration that varies in a thickness direction.
Example 17 is a semiconductor device, comprising: a semiconductor fin structure disposed over the substrate and including a channel region; an isolation insulating layer from which the channel region protrudes; a gate dielectric layer disposed over the channel region; and a gate electrode disposed over the gate dielectric layer, wherein: the gate dielectric layer comprises silicon oxide that is only partially nitrided.
Example 18 is the semiconductor device of example 17, wherein a portion of the gate dielectric layer formed on a sidewall of the channel region does not include nitrogen, or includes nitrogen in an amount less than 3 atomic%.
Example 19 is the semiconductor device of example 18, wherein a top portion of the gate dielectric layer and an upper side portion of the gate dielectric layer include nitrogen in an amount of 20 to 40 atomic%, the top portion of the gate dielectric layer being formed on top of the channel region, the upper side portion of the gate dielectric layer continuing from the top portion to a distance below the top of the channel region that is 15% of a height of the channel region from an upper surface of the isolation insulating layer.
Example 20 is the semiconductor device of example 19, wherein an angle between an interface between the nitrided portion of the gate dielectric layer and the non-nitrided portion of the gate dielectric layer and a sidewall of the gate dielectric layer is 1 degree to 5 degrees.

Claims (10)

1. A method for manufacturing a semiconductor device, the method comprising:
forming a fin structure by patterning the semiconductor layer;
forming an isolation insulating layer such that an upper portion of the fin structure protrudes from the isolation insulating layer;
Forming a gate dielectric layer by a deposition process;
introducing nitrogen into the gate dielectric layer after forming the gate dielectric layer; and
a gate electrode layer is formed over the gate dielectric layer,
wherein the gate dielectric layer formed is silicon oxide.
2. The method according to claim 1, wherein:
introducing nitrogen includes the use of N 2 Gas and NH 3 Plasma nitriding of gases, and
flow ratio NH 3 /(N 2 +NH 3 ) In the range of 0.1 to 0.3.
3. The method of claim 2, wherein a portion of the gate dielectric layer formed on a sidewall of an upper portion of the fin structure does not include nitrogen, or includes nitrogen in an amount less than 3 atomic%.
4. The method of claim 3, wherein a top of the gate dielectric layer and sides of the gate dielectric layer comprise nitrogen in an amount of 20 to 40 atomic percent, the top of the gate dielectric layer formed on top of an upper portion of the fin structure, the sides of the gate dielectric layer continuing from the top to a distance below the top of the upper portion of the fin structure that is 15% of a height of the upper portion of the fin structure from an upper surface of the isolation insulating layer.
5. The method of claim 4, wherein an angle between an interface between the nitrided portion of the gate dielectric layer and the non-nitrided portion of the gate dielectric layer and a sidewall of the gate dielectric layer is 1 to 5 degrees.
6. The method of claim 2, wherein a nitrogen concentration at an interface between the gate dielectric layer and an upper portion of the fin structure after the nitridation operation is less than 3 atomic percent.
7. The method of claim 2, wherein the portion of the gate dielectric layer formed on the isolation insulating layer is also nitrided.
8. The method of claim 2, wherein the process temperature of the nitriding operation is in the range of 50 ℃ to 450 ℃.
9. A method for manufacturing a semiconductor device, the method comprising:
forming a fin structure by patterning the semiconductor layer;
forming an isolation insulating layer such that an upper portion of the fin structure protrudes from the isolation insulating layer;
forming a gate dielectric layer over the fin structure by a deposition process;
performing a nitridation operation on the gate dielectric layer; and
forming a gate electrode layer over the gate dielectric layer, wherein:
The gate dielectric layer formed comprises silicon oxide,
the nitriding operation includes using N 2 Gas and NH 3 Plasma nitridation of one or more of the gases, and
flow ratio NH 3 /(N 2 +NH 3 ) In the range of 0.4 to 1.0.
10. A semiconductor device, comprising:
a semiconductor fin structure disposed over the substrate and including a channel region;
an isolation insulating layer from which the channel region protrudes;
a gate dielectric layer disposed over the channel region; and
a gate electrode disposed over the gate dielectric layer, wherein:
the gate dielectric layer comprises silicon oxide that is only partially nitrided.
CN202210984942.2A 2022-02-25 2022-08-17 Method for manufacturing semiconductor device and semiconductor device Pending CN116454123A (en)

Applications Claiming Priority (3)

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US63/314,045 2022-02-25
US17/837,848 2022-06-10
US17/837,848 US20230274938A1 (en) 2022-02-25 2022-06-10 Method of manufacturing semiconductor devices and semiconductor devices

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CN116454123A true CN116454123A (en) 2023-07-18

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