CN116453578A - Cyclic redundancy check circuit and DDR memory - Google Patents

Cyclic redundancy check circuit and DDR memory Download PDF

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Publication number
CN116453578A
CN116453578A CN202310424643.8A CN202310424643A CN116453578A CN 116453578 A CN116453578 A CN 116453578A CN 202310424643 A CN202310424643 A CN 202310424643A CN 116453578 A CN116453578 A CN 116453578A
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pull
exclusive
cyclic redundancy
redundancy check
network
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Inventor
赖荣钦
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Dongxin Semiconductor Co ltd
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Dongxin Semiconductor Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a cyclic redundancy check circuit which is used for a DDR memory and comprises an exclusive-or operation module, wherein the exclusive-or operation module is used for processing each bit of write data written into a register of the DDR memory to generate a cyclic redundancy check code for judging whether data transmission is correct, the exclusive-or operation module is formed by cascade connection of a plurality of exclusive-or gate units, the exclusive-or gate units are provided with a pull-up network and a pull-down network, the pull-up network is electrically connected with the pull-down network, the connection point is an output end of the exclusive-or gate units, the pull-down network is formed by only one weak pull-down transistor, the drain electrode of the weak pull-down transistor is connected to the output end, and the source electrode of the weak pull-down transistor is grounded.

Description

Cyclic redundancy check circuit and DDR memory
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a cyclic redundancy check circuit and a DDR memory having the cyclic redundancy check circuit.
Background
DDR memory is currently the most widely used memory in computers and servers, with performance and cost advantages. The DDR memory herein is referred to as DDR DRAM (Double Data Rate Dynamic Random Access Memory ) (hereinafter sometimes simply referred to as DDR or DRAM).
In data transmission of DRAM, in order to check the accuracy of data transmission, cyclic redundancy check (CRC, cyclic redundancy check) is generally performed. Cyclic Redundancy Check (CRC) is a calculation method for checking the accuracy of data transmission on a communication link, and is the most commonly used check method in data communication. The basic idea of this way of checking is that the information M (X) to be transmitted is represented as a polynomial L divided by a predetermined divisor polynomial G (X), the remainder being the desired cyclic redundancy check code (i.e. CRC check code).
Fig. 1 is a block diagram showing cyclic redundancy check for write operations in a DDR memory.
As shown in fig. 1, the DRAM controller generates a CRC check code by the CRC engine and appends the CRC check code to the written data, which is then transmitted to the DRAM.
The DRAM receiving the transmission data to which the CRC check code is attached obtains the CRC check code in the transmission data by the CRC engine.
Then, the CRC check code generated by the DRAM controller is compared with the CRC check code obtained by the DRAM at this time, if the CRC check codes are the same, the data transmission is correct, and if the CRC check codes are different, the result is fed back through, for example, alert_n (not shown).
In the above cyclic redundancy check for DDR memory, the commonly used divisor polynomial is ATM-8HEC, which has the expression G (X) =Xζ8+Xζ2+Xζ1+1. The remainder of the input data burst (DQs bursts) of the DRAM is obtained by the divisor polynomial. The remainder is the CRC check code.
Fig. 2 is a schematic diagram showing an expression of a CRC check code, showing an expression of a CRC check code obtained by the divisor polynomial. In fig. 2, the expressions of 8 CRC check codes, i.e., newCRC (0) to NewCRC (7), obtained by processing for each bit when the Burst Length (Burst Length) is 8 bits are shown.
Fig. 3 is a diagram showing a CRC check code exclusive or (XOR) table.
As shown in fig. 3, a maximum of 40 input data are inputted to generate a specified CRC check code. As described above, there are 8 CRC check codes, and thus, there are 280 inputs in total for exclusive or (XOR) operations.
Fig. 4 is a logic circuit diagram showing an exclusive or gate unit performing the exclusive or (XOR) operation to generate a CRC check code.
A logic circuit diagram of a general exclusive or gate unit is shown in fig. 4. In fig. 4, a circuit diagram of a general XOR2 (two-input exclusive or gate), XOR3 (three-input exclusive or gate) composed of CMOS transistors is shown by way of example. The general XOR4 (four-input exclusive or gate) is not shown here because its circuit configuration is more complicated. In addition, for convenience of explanation, each circuit wiring is denoted by a reference numeral in fig. 4.
First, a general XOR2 having two inputs made of CMOS transistors will be described in detail.
As shown in the left half of fig. 4, in general XOR2, A, B represents the input signal of the exclusive or circuit, ab, bb represents the inverted value of the input signal A, B, and OUT represents the output of the exclusive or circuit.
The XOR2 circuit comprises a Pull-Up network (Pull Up Net, for short) and a Pull-Down network (PDN, for short), wherein one end of the Pull-Up network (Pull Up Net) is connected to a power supply, and the other end of the Pull-Up network (Pull Down Net, for short) is connected to the Pull-Down network PDN. One end of the pull-down network PDN is connected with the pull-up network PUN, and the other end of the pull-down network PDN is connected to the ground. The junction of the pull-up network put and the pull-down network PDN is the output OUT of the XOR2 circuit.
In addition, the internal structures of both the pull-up network PUN and the pull-down network PDN are symmetrically complementary. Specifically, the pull-up network PUN is composed of four PMOS transistors, and the pull-down network PDN is composed of four NMOS transistors. The exclusive-or function is realized by the serial-parallel relationship of each PMOS transistor and each NMOS transistor.
Next, a general XOR3 having three inputs made up of CMOS transistors will be described in detail.
As shown in the right half of fig. 4, in general XOR3, A, B, C represents the input signal of the exclusive or circuit, ab, bb, cb represent the inverse of the input signal A, B, C, and OUT represents the output of the exclusive or circuit.
Like the XOR2 circuit, the XOR3 circuit also includes a pull-up network put and a pull-down network PDN, one end of the pull-up network put being connected to a power supply and the other end being connected to the pull-down network PDN. One end of the pull-down network PDN is connected with the pull-up network PUN, and the other end of the pull-down network PDN is connected to the ground. The junction of the pull-up network put and the pull-down network PDN is the output OUT of the XOR3 circuit.
In addition, the internal structures of both the pull-up network PUN and the pull-down network PDN are symmetrically complementary. The pull-up network put and the pull-down network PDN are respectively constituted by the same number of PMOS transistors.
As is apparent from fig. 4, compared with the logic circuit of XOR2, XOR3 needs to be formed by using more CMOS transistors, and the circuit structure is more complex, and the occupied circuit layout area is larger.
Likewise, although not shown, it is apparent that if XOR4 having four inputs is used, a larger number of CMOS transistors are required to be formed, the circuit configuration becomes further complicated, and the occupied circuit layout area becomes further large.
Therefore, since the logic circuit structure of the xor gate unit having more inputs is extremely complex and the occupied circuit layout area is extremely large, it is difficult to use the xor gate unit having four inputs and more inputs in practical application.
Fig. 5 and 6 are circuit diagrams showing exclusive-or operation blocks respectively constructed using XOR2 and XOR 4. DI0 to DI39 in fig. 5 and 6 represent the maximum of 40 input data, and OUTPUT represents the OUTPUT of the exclusive or operation module.
Fig. 5 shows by way of example a specific circuit for implementing an exclusive or operation module using XOR 2. As can be seen in connection with fig. 3 and 5, in the case of using XOR2 as an exclusive or gate unit, in order to generate a specified CRC check code, a plurality of XOR2 needs to be concatenated to form an exclusive or operation module having 6 levels.
Fig. 6 shows by way of example a specific circuit for implementing an exclusive or operation module using XOR 4. Also, as can be seen in conjunction with fig. 3 and 5, in the case of using XOR4 as an exclusive or gate unit, in order to generate a specified CRC check code, a plurality of XOR4 needs to be concatenated to form an exclusive or operation module having 3 levels.
It is known that the fewer the number of inputs of the xor gate units used in the xor operation module, the smaller the circuit layout area occupied by a single xor gate unit, but the greater the number of xor gate units required for generating a specified CRC check code, the greater the number of levels of the xor operation module formed by the final concatenation, and the longer the processing time.
Conversely, the more the number of inputs of the exclusive-or gate units used in the exclusive-or operation module, the larger the circuit layout area occupied by a single exclusive-or gate unit, but the fewer the number of the exclusive-or gate units required for generating the specified CRC check code, the fewer the hierarchy of the exclusive-or operation module formed by the final cascade, and the shorter the processing time.
For example, based on the descriptions of fig. 4 to 6, if the XOR operation module is implemented using an XOR2 circuit having two inputs, the number of circuit levels becomes 6, and the processing time required for generating the specified CRC check code becomes long.
If the XOR4 circuit with four inputs is used to implement the XOR operation module, the circuit level is reduced to 3, and the processing time required to generate the specified CRC check code is reduced to half compared to the case of using the XOR2 circuit.
However, in connection with fig. 4, although the circuit structure of XOR4 is not specifically shown, it is known based on the circuit structures of XOR2 and XOR3 in fig. 4 that the logic circuit of XOR4 is necessarily more complex than XOR2, XOR3, and the circuit layout area occupied by a single exclusive or gate unit is increased, so that although the number required to generate a specified CRC check code is reduced, the layout area occupied thereof is still so large that in the existing cyclic redundancy check circuit design for DDR memory, it is almost impossible to implement an exclusive or operation module using XOR4 having four inputs and even more inputs.
Therefore, in the prior art, it is an issue to reduce the circuit layout and reduce the circuit processing time and improve the processing efficiency of the cyclic redundancy check while reducing the circuit layout and the DDR memory.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a cyclic redundancy check circuit and a DDR memory using the cyclic redundancy check circuit, which can greatly reduce the circuit layout area, achieve compactness and low cost, and also greatly reduce the circuit processing time and improve the processing efficiency of cyclic redundancy check.
Disclosure of Invention
A first aspect of the present invention is to provide a cyclic redundancy check circuit for a DDR memory, characterized in that,
comprises an exclusive or operation module which processes each bit of write data written into a register of the DDR memory to generate a cyclic redundancy check code for judging whether data transmission is correct,
the exclusive or operation module is formed by cascade connection of a plurality of exclusive or gate units,
the exclusive or gate unit has a pull-up network and a pull-down network,
the pull-up network is electrically connected with the pull-down network, the connection point is the output end of the exclusive-OR gate unit,
the pull-down network is composed of only one weak pull-down transistor with its drain connected to the output terminal and its source grounded.
Preferably, the memory device further includes a data path switching switch for switching an input path of the write data written into the register.
Preferably, the data path switching switches are provided in one-to-one correspondence with the exclusive or operation modules.
Preferably, when the result of the exclusive or gate unit is "1", the output of the exclusive or gate unit is driven high.
Preferably, the pull-up network is formed by cascade connection of a plurality of CMOS transistors.
Preferably, the weak pull-down transistor is an NMOS transistor.
Preferably, the pull-up network is composed of a plurality of PMOS transistors.
A second aspect of the present invention is to provide a DDR memory, characterized in that,
comprising a cyclic redundancy check circuit as described in the first aspect above.
Drawings
Fig. 1 is a block diagram showing cyclic redundancy check for write operations in a DDR memory.
Fig. 2 is a schematic diagram showing an expression of a CRC check code.
Fig. 3 is a diagram showing a CRC check code exclusive or (XOR) table.
Fig. 4 is a logic circuit diagram illustrating general exclusive or gates XOR2 and XOR 3.
Fig. 5 is a schematic diagram showing the implementation of an exclusive-or operation module using XOR 2.
Fig. 6 is a schematic diagram showing the implementation of an exclusive-or operation module using XOR 4.
Fig. 7 is a schematic diagram showing a cyclic redundancy check circuit and a processing sequence according to embodiment 1 of the present invention.
Fig. 8 is a logic circuit diagram showing an exclusive or gate unit included in the exclusive or operation module according to embodiment 1 of the present invention.
Detailed Description
The invention will be described in more detail hereinafter with reference to specific embodiments shown in the drawings. The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods according to embodiments of the present invention. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures.
Furthermore, various advantages and benefits of the present invention will become apparent to those of ordinary skill in the art upon reading the following detailed description of the specific embodiments. It should be understood, however, that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. The following embodiments are provided to enable a more thorough understanding of the present invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
Embodiment 1
In order to solve the problems of the prior art, embodiment 1 of the present invention relates to a cyclic redundancy check circuit, and the cyclic redundancy check circuit 100 according to embodiment 1 is specifically described below.
Fig. 7 is a circuit diagram showing a cyclic redundancy check circuit 100 according to embodiment 1 of the present invention. In the upper part of fig. 7, a cyclic redundancy check circuit is shown that generates 8 CRC check codes for 8 bits of data when the Burst Length (Burst Length) is 8 bits. In the lower part of fig. 7, a timing diagram for performing a CRC operation by the cyclic redundancy check circuit is shown.
In the prior art, in the case of writing data having a burst length of 8 bits to a register (registers), an exclusive or operation module needs to be provided for each bit of the written data, that is, 8 exclusive or operation modules need to be provided for cyclic redundancy check processing.
In contrast, in embodiment 1, as shown in fig. 7, when writing 8-bit data, i.e., 8-bit write data DQ0 to DQ7, having a burst length to a register (registers), the cyclic redundancy check circuit 100 includes only 4 exclusive or operation blocks 101, 102, 103, and 104.
The exclusive or operation module 101 generates respective cyclic redundancy check codes CRC0, CRC1 for the write data DQ0 and DQ 1. The exclusive or operation module 102 generates respective cyclic redundancy check codes CRC2, CRC3 for the write data DQ2 and DQ 3. The exclusive or operation module 103 generates respective cyclic redundancy check codes CRC4, CRC5 for the write data DQ4 and DQ 5. The exclusive or operation module 104 generates respective cyclic redundancy check codes CRC6, CRC7 for the write data DQ6 and DQ7.
The cyclic redundancy check circuit 100 further includes a data path switching switch crc_sw. The data path switching switches crc_sw are provided in one-to-one correspondence with the exclusive or operation modules. In the case of 4 exclusive or operation modules 101, 102, 103, 104, the cyclic redundancy check circuit 100 includes 4 switches crc_sw. The data path switching switch crc_sw is used to switch the input paths of each bit DQ0 to DQ7 of write data written into the register.
The specific processing procedure is described below with reference to the timing chart shown in the lower half of fig. 7:
first, a Cyclic Redundancy Check (CRC) enable signal crc_en becomes a high level.
At this time, in the first CRC operation (1 st CRC), the write data DQ0, DQ2, DQ4, DQ6 are processed by the four exclusive or operation modules 101, 102, 103, 104, respectively, to generate corresponding cyclic redundancy check codes CRC0, CRC2, CRC4, CRC6.
Then, the switch enable signal crc_sw becomes a high level.
At this time, the input paths of the write data are switched by the 4 crc_sws, and the objects to be processed are changed to the write data DQ1, DQ3, DQ5, DQ7, respectively.
Thus, in the second CRC operation (2 nd CRC), the write data DQ1, DQ3, DQ5, DQ7 are processed by the four exclusive or operation modules 101, 102, 103, 104, respectively, to generate corresponding cyclic redundancy check codes CRC1, CRC3, CRC5, CRC7.
In embodiment 1, by providing the data path switching switch crc_sw, only 4 exclusive-or operation blocks 101, 102, 103, 104 need be provided for 8-bit write data having a Burst Length (Burst Length), and the 4 exclusive-or operation blocks 101, 102, 103, 104 are reused by timing control of the data path switching switch crc_sw, thereby realizing cyclic redundancy check processing for each bit of data of 8-bit write data. Therefore, compared with the prior art, the number of the exclusive or operation modules is greatly reduced, and the miniaturization and the low cost of the DDR memory device are realized.
Next, the circuit configuration of the exclusive or operation blocks 101, 102, 103, 104 in the cyclic redundancy check circuit 100 according to embodiment 1 will be described in detail with reference to fig. 8.
Fig. 8 is a logic circuit diagram showing an exclusive or gate unit included in the exclusive or operation module according to embodiment 1 of the present invention.
Like the xor operation modules shown in fig. 5 and 6, the xor operation modules 101, 102, 103, 104 according to embodiment 1 of the present invention are each formed by cascade connection of a plurality of xor gate units. For example, in the case of using XOR2 as an exclusive or gate unit, a plurality of XOR2 constitute an exclusive or operation module having 6 levels by cascade connection. In the case of using XOR4 as an exclusive or gate unit, a plurality of XOR4 constitute an exclusive or operation module having 3 levels by cascade connection.
However, the exclusive-or operation blocks 101, 102, 103, 104 according to embodiment 1 are different from the prior art in that the specific logic circuit of each exclusive-or gate unit included in the exclusive-or operation blocks is different from the general XOR2, XOR3, or XOR 4. The following describes the difference in detail.
Fig. 8 shows logic circuits of XOR2, XOR3, and XOR4 as exclusive or gate units according to embodiment 1 of the present invention, by way of example.
For convenience of explanation, in fig. 8, like fig. 4, each circuit line is denoted by a reference numeral.
As shown in fig. 8, the XOR2 according to embodiment 1 is also constituted by CMOS transistors, as is the general XOR2 shown in fig. 4. The XOR2 has a Pull-Up network (Pull Up Net, abbreviated as "put") and a Pull-Down network (Pull Down Net, abbreviated as "PDN"). One end of the pull-up network is connected to the power supply, and the other end of the pull-up network is electrically connected with the pull-down network, and the connection point of the electrical connection is the output end of the XOR 2. In the logic circuit of XOR2 shown in fig. 8, A, B represents the input signal of XOR gate XOR2, ab and Bb represent the inverted value of input signal A, B, and OUT represents the output of XOR gate XOR 2.
In embodiment 1, the point different from fig. 4 is that the pull-down network is constituted by only one weak pull-down transistor. The weak pull-down transistor has a drain connected to the output terminal OUT and a source grounded.
In contrast to the logic circuit of the general XOR2 of fig. 4, only one weak pull-down transistor is provided in the pull-down network of the XOR2 according to embodiment 1, instead of the plurality of CMOS transistors constituting the pull-down network of the general XOR 2.
Alternatively, the pull-up network of the XOR2 is configured of a plurality of PMOS transistors, and the weak pull-down transistor as the pull-down network is configured as an NMOS transistor.
When the exclusive or operation module is configured by using a plurality of XOR2, the default value of the output data is "0" when the write data is processed. When the result of the output data is "1", the weak pull-down transistor drives the output data to "1".
With this structure, the same logic function can be obtained with fewer devices than in the prior art. Therefore, the XOR2 according to embodiment 1 has a significantly reduced number of devices, a reduced manufacturing cost, and a simple circuit structure, and occupies a significantly reduced layout area.
Similarly, fig. 8 also shows a logic circuit diagram of XOR3 according to embodiment 1. Similar to XOR2 described above, XOR3 is also composed of CMOS transistors. XOR3 has a pull-up network and a pull-down network. One end of the pull-up network is connected to the power supply, and the other end of the pull-up network is electrically connected with the pull-down network, and the connection point of the electrical connection is the output end of the XOR 3. In the logic circuit of XOR3 shown in fig. 8, A, B, C represents the input signal of XOR gate XOR3, ab, bb, cb represent the inverted value of input signal A, B, C, and OUT represents the output of XOR gate XOR 3.
As shown in fig. 8, the pull-down network of XOR3 according to embodiment 1 is also composed of only one weak pull-down transistor. The plurality of CMOS transistors constituting the pull-down network of the general XOR3 are replaced by only one weak pull-down transistor. The weak pull-down transistor has a drain connected to the output terminal OUT and a source grounded.
Alternatively, the pull-up network of the XOR3 is configured by a plurality of PMOS transistors, and the weak pull-down transistor as the pull-down network is configured as an NMOS transistor.
When the exclusive or operation module is configured by using a plurality of XOR3, the default value of the output data is "0" when the write data is processed. When the result of the output data is "1", the weak pull-down transistor drives the output data to "1".
With this structure, the same logic function can be obtained with fewer devices than in the prior art. Therefore, the XOR3 according to embodiment 1 has a significantly reduced number of devices, a reduced manufacturing cost, and a simple circuit structure, and occupies a significantly reduced layout area.
Further, fig. 8 also shows a logic circuit diagram of XOR4 according to embodiment 1. Similarly to XOR2, XOR3 described above, XOR4 is also constituted by CMOS transistors. XOR4 has a pull-up network and a pull-down network. One end of the pull-up network is connected to the power supply, and the other end of the pull-up network is electrically connected with the pull-down network, and the connection point of the electrical connection is the output end of the XOR 4. In the logic circuit of XOR4 shown in fig. 8, A, B, C, D represents the input signal of exclusive or gate XOR3, a ', B', C ', D' represent the inverted value of input signal A, B, C, D, and OUT represents the output of exclusive or gate XOR 4.
As shown in fig. 8, the pull-down network of XOR4 according to embodiment 1 is also composed of only one weak pull-down transistor. The plurality of CMOS transistors constituting the pull-down network of the general XOR4 are replaced by only one weak pull-down transistor. The drain of the weak pull-down transistor is connected to the output terminal OUT, the source is grounded.
Alternatively, the pull-up network of the XOR4 is configured by a plurality of PMOS transistors, and the weak pull-down transistor as the pull-down network is configured as an NMOS transistor.
When the exclusive or operation module is configured by using a plurality of the XORs 4, the output data default value is "0" when the write data is processed. When the result of the output data is "1", the weak pull-down transistor drives the output data to "1".
With this structure, the same logic function can be obtained with fewer devices than in the prior art. Therefore, compared with the general XOR4 shown in fig. 4, the XOR4 according to embodiment 1 has a significantly reduced number of devices, a reduced manufacturing cost, and a simple circuit structure, and occupies a significantly reduced layout area.
As is clear from the above description, the logic circuits of XOR2, XOR3, XOR4, which can be the exclusive or gate unit according to embodiment 1, are greatly simplified as compared with the conventional one, the required devices are greatly reduced, and the layout area occupied is also greatly reduced.
Therefore, when the problem of how to achieve a balance between circuit area and circuit processing time, and how to reduce circuit layout, achieve compactness and low cost of a DDR memory, and greatly reduce circuit processing time and improve processing efficiency of cyclic redundancy check is faced in the prior art, it is possible to construct an exclusive or operation module having exclusive or gate units as described above using exclusive or gate units having a larger number of inputs than the prior art by employing the exclusive or operation module having exclusive or gate units according to embodiment 1 of the present invention. For example, more XOR3 or XOR4 can be used than the number of XOR2 inputs, thereby reducing the level of the constructed exclusive or operation module from 6 to 4 or3, greatly reducing the processing time determined by the number of levels.
That is, by using the exclusive or operation module including the exclusive or gate unit according to embodiment 1 of the present invention, a cyclic redundancy check circuit can be obtained, the circuit layout area can be greatly reduced, the compactness and the cost can be reduced, the circuit processing time can be greatly reduced, and the processing efficiency of cyclic redundancy check can be improved.
Embodiment 2
Embodiment 2 of the present invention relates to a DDR memory. The DDR memory includes the cyclic redundancy check circuit 100 described in embodiment 1. The DDR memory according to embodiment 2 can greatly reduce the circuit layout area, thereby realizing compactness and low cost, and can also greatly reduce the circuit processing time and improve the processing efficiency of the cyclic redundancy check.
While embodiments 1 and 2 of the present invention have been described above, the present invention can be freely combined with each other, or each embodiment can be appropriately modified or omitted within the scope of the present invention. Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. Numerous modifications, not illustrated, can be interpreted as being envisaged without departing from the scope of the invention.
Description of the reference numerals
100 cyclic redundancy check circuit
101. 102, 103, 104 exclusive-or operation module

Claims (8)

1. A cyclic redundancy check circuit for DDR memory is characterized in that,
comprises an exclusive or operation module which processes each bit of write data written into a register of the DDR memory to generate a cyclic redundancy check code for judging whether data transmission is correct,
the exclusive or operation module is formed by cascade connection of a plurality of exclusive or gate units,
the exclusive or gate unit has a pull-up network and a pull-down network,
the pull-up network is electrically connected with the pull-down network, the connection point is the output end of the exclusive-OR gate unit,
the pull-down network is composed of only one weak pull-down transistor with its drain connected to the output terminal and its source grounded.
2. The cyclic redundancy check circuit of claim 1, wherein,
the register further includes a data path switching switch that switches an input path of the write data written to the register.
3. The cyclic redundancy check circuit of claim 2, wherein,
the data path switching switches are arranged in one-to-one correspondence with the exclusive or operation modules.
4. The cyclic redundancy check circuit of claim 1 or2, wherein,
when the result of the exclusive or gate unit is "1", the output of the exclusive or gate unit is driven high.
5. The cyclic redundancy check circuit of claim 1 or2, wherein,
the pull-up network is formed by cascading a plurality of CMOS transistors.
6. The cyclic redundancy check circuit of claim 1 or2, wherein,
the weak pull-down transistor is an NMOS transistor.
7. The cyclic redundancy check circuit of claim 1 or2, wherein,
the pull-up network is composed of a plurality of PMOS transistors.
8. A DDR memory is characterized in that,
comprising a cyclic redundancy check circuit as claimed in any one of claims 1 to 7.
CN202310424643.8A 2023-04-19 2023-04-19 Cyclic redundancy check circuit and DDR memory Pending CN116453578A (en)

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