CN116450560A

CN116450560A - Dual-active storage main board and server

Info

Publication number: CN116450560A
Application number: CN202310466596.3A
Authority: CN
Inventors: 王其萌; 李善荣; 翟乐
Original assignee: Xian Chaoyue Shentai Information Technology Co Ltd
Current assignee: Xian Chaoyue Shentai Information Technology Co Ltd
Priority date: 2023-04-26
Filing date: 2023-04-26
Publication date: 2023-07-18

Abstract

The invention discloses a double-active storage main board, which comprises the following steps: the first Shenwei CPU and the second Shenwei CPU are interconnected; the switching chip is provided with a first non-transparent bridge and a second non-transparent bridge at the upstream and a plurality of interfaces at the downstream, wherein the first non-transparent bridge is connected with the first Shenwei CPU, and the second non-transparent bridge is connected with the second Shenwei CPU; a plurality of hard disks, each hard disk being connected with one of the interfaces; each interface of the Switch chip is connected with the first non-transparent bridge or the second non-transparent bridge, so that the first Shenwei CPU accesses the hard disk through the first non-transparent bridge and each interface, and after the first Shenwei CPU fails, the second Shenwei CPU accesses the hard disk through the second non-transparent bridge and each interface. The invention also discloses a server. The invention provides a memory motherboard of a double-control full flash memory based on a domestic CPU, the stability of the data processing task is ensured, and the reading and writing speed is greatly improved.

Description

Dual-active storage main board and server

Technical Field

The invention relates to the field of storage, in particular to a dual-active storage main board and a server.

Background

With the development of information technology, data and information are particularly important, and especially, the problem of data storage is increasingly important. However, the conventional domestic server cannot process information in time when the CPU controller fails, so that the task is interrupted, the data is lost, and the transmission rate of a common hard disk is low, so that the stability of the data processing task cannot be ensured.

Disclosure of Invention

In view of this, in order to overcome at least one aspect of the above-mentioned problems, an embodiment of the present invention provides a dual active memory motherboard, including:

the first Shenwei CPU and the second Shenwei CPU are interconnected;

a Switch chip, wherein a first non-transparent bridge and a second non-transparent bridge are arranged on the upstream of the Switch chip, a plurality of interfaces are arranged on the downstream of the Switch chip, the first non-transparent bridge is connected with the first Shenwei CPU, and the second non-transparent bridge is connected with the second Shenwei CPU;

a plurality of hard disks, each of which is connected with one of the interfaces;

each interface of the Switch chip is connected with the first non-transparent bridge or the second non-transparent bridge, so that the first Shenwei CPU accesses the hard disk through the first non-transparent bridge and each interface, and after the first Shenwei CPU fails, the second Shenwei CPU accesses the hard disk through the second non-transparent bridge and each interface.

In some embodiments, the first Shenwei CPU and the second Shenwei CPU each have two PCIE x 4 lanes, two PCIE x8 lanes;

and the first Shenwei CPU and the second Shenwei CPU are connected to the Switch chip through one PCIEX 8 channel.

In some embodiments, the dual live storage system further comprises:

the first network card is connected to the first Shenwei CPU through one PCIEx 4 channel of the first Shenwei CPU;

the second network card is connected to the second Shenwei CPU through one PCIEx 4 channel of the second Shenwei CPU;

the first Shenwei CPU and the second Shenwei CPU are interconnected through the first network card and the second network card, and the state of the other party is obtained through detecting the heartbeat signal.

In some embodiments, the dual live storage system further comprises:

a first system disk connected to the first Shenwei CPU through another PCIE x 4 channel of the first Shenwei CPU;

and the second system disk is connected to the second Shenwei CPU through another PCIEx 4 channel of the second Shenwei CPU.

In some embodiments, the dual live storage system further comprises:

the first PCIE-SATA chip is connected to the first Shenwei CPU through another PCIEx 8 channel of the first Shenwei CPU;

the second PCIE-SATA chip is connected to the second Shenwei CPU through another PCIEx 8 channel of the second Shenwei CPU;

the first PCIE to SATA chip and the second PCIE to SATA chip are both configured to implement SATA interface expansion, and further connect to a SATA hard disk through the SATA interface.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a server, which is characterized by including a dual active storage motherboard, the dual active storage motherboard including:

the first Shenwei CPU and the second Shenwei CPU are interconnected;

In some embodiments, the dual live storage system further comprises:

The invention has one of the following beneficial technical effects: the invention provides a double-control full-flash memory storage main board based on a domestic CPU, which ensures the stability of data processing tasks and greatly improves the reading and writing speed.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a dual active memory motherboard according to an embodiment of the present invention;

fig. 2 is a PCIE channel allocation schematic diagram of a CPU according to an embodiment of the present invention;

fig. 3 is a schematic diagram of CPU switching according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.

According to an aspect of the present invention, an embodiment of the present invention proposes a dual active memory motherboard, as shown in fig. 1, which may include:

the first Shenwei CPU and the second Shenwei CPU are interconnected;

wherein each interface of the Switch chip is connected with the first non-transparent bridge or the second non-transparent bridge, so that the first Shenwei CPU accesses the hard disk through the first non-transparent bridge and each interface, and after the first Shenwei CPU fails, the second Shenwei CPU accesses the hard disk through the second non-transparent bridge and each interface.

The invention provides a dual-control full-flash memory storage system based on a domestic CPU, which ensures the stability of data processing tasks and greatly improves the reading and writing speed.

In some embodiments, as shown in fig. 1, the motherboard provided by the invention is composed of two domestic CPUs Shenwei 3231 and a matched PCIE switch PEX8796, the flash disk is extended through 8796, and the service system transmits data with the outside through a tera-megafiber. The two CPUs are mutually independent and mutually back up and cache in a double-activity mode, and mutually monitor the state of the other party. When one CPU fails, the other CPU immediately takes over the storage task, and the data in the cache is written into the NVME storage disk in time.

The main board is designed to have two CPUs provided with operating systems which independently run, and a system disk is expanded by PCIE interfaces of the CPUs.

Optionally, the CPU on the motherboard may extend an m.2 interface through PCIE and extend a SATA interface through PCIE to SATA chip, and the system may be installed in an m.2 or SATA hard disk.

According to the invention, two CPUs are connected to the same PEX8796 through PCIE, the PEX8796 supports double main equipment and also supports Non-Transparent (NT) Port (Non-transparent bridge), and when one CPU fails, the other CPU can take over data, so that data processing is ensured not to be interrupted.

The 12M-key NVME of the invention is connected with PEX8796 through a m.2 seat on the board,

the CPU is connected with AST2500 through PCIE switch, and AST2500 is used as a display chip.

In some embodiments, the dual live storage system further comprises:

Specifically, as shown in fig. 2, two shenwei CPUs (for example, 3231) monolithically integrate PCIE signals of 40lan, including two paths of pcie×16 and two paths of pcie×4.PCIE x 4 is used to extend the m.2 system disk and the tera 1820 network card for data interaction. Meanwhile, one PCIE×16 is split into two PCIE×8 paths, one PCIE switch (such as PEX 8796) is connected with one PCIE switch, and the other PCIE is converted into a SATA chip to expand the SATA hard disk.

In some embodiments, two CPUs are connected to PEX8796 through PCIE signals, PEX8796 supports dual master devices, and supports Non-Transparent (NT) ports (Non-transparent bridge), the NT bridge splits one transparent Port into two Non-transparent ports, supports two systems to access simultaneously, and the two CPU systems can access data of the counterpart system through address conversion by the bridge piece, can process device information downstream of 8796 simultaneously, and can read data of the counterpart system through address conversion by PEX8796, so that the two CPUs can backup each other for buffering.

In some embodiments, two CPU systems expand the tera module through the 1820 network card chip that CPU directly links to carry on the detection of system heartbeat, make two CPUs can monitor the state of the other party in real time, another CPU can smooth take over the business while guaranteeing a certain CPU trouble.

In some embodiments, as shown in FIG. 3, CPU1 normally manages, accesses the devices below, CPU2 runs but does not participate in device management, and when CPU1 fails, CPU2 takes over the system while, at the same time, reconfiguring PEX8796, taking over system traffic.

In some embodiments, as shown in fig. 1, the motherboard provided by the present invention extends 12 PCIE3.0×4 m.2 interfaces through PEX8796, so as to install 12 m.2 hard disks, thereby greatly improving the upper limit of the data reading speed. Meanwhile, PEX8796 leads out one path of pcie×4 to be connected to motherboard management chip AST2500 for display use.

In some embodiments, as shown in fig. 1, the reading of all data discs on the motherboard and the interaction of external information are all realized by a single PEX8796, in the whole system, the PEX8796 communicates with two upstream CPUs through a non-transparent bridge, so that the space on the motherboard is greatly saved,

in some embodiments, as shown in fig. 1, the motherboard provided by the invention can be externally connected with two SFP+multi-megaoptical ports and 4 kilomega RJ45 network ports, both of which are led out by PEX8796, so that high-speed interaction with external data is ensured.

The invention provides a double-control full-flash memory storage main board based on a domestic CPU, which ensures the stability of data processing tasks and greatly improves the reading and writing speed.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a server, including a dual active storage motherboard, the dual active storage motherboard including:

the first Shenwei CPU and the second Shenwei CPU are interconnected;

In some embodiments, the dual live storage system further comprises:

Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the methods described above when executed.

Further, it should be appreciated that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims

1. A dual active memory motherboard, comprising:

the first Shenwei CPU and the second Shenwei CPU are interconnected;

2. The dual active memory motherboard of claim 1, wherein the first Shenwei CPU and the second Shenwei CPU each have two PCIE x 4 lanes and two PCIE x8 lanes;

3. The dual active memory motherboard of claim 2, wherein said dual active memory system further comprises:

4. The dual active memory motherboard of claim 2, wherein said dual active memory system further comprises:

5. The dual active memory motherboard of claim 2, wherein said dual active memory system further comprises:

6. A server comprising a dual active storage motherboard, the dual active storage motherboard comprising:

the first Shenwei CPU and the second Shenwei CPU are interconnected;

7. The server of claim 6, wherein the first Shenwei CPU and the second Shenwei CPU each have two PCIE x 4 lanes, two PCIE x8 lanes;

8. The server of claim 7, wherein the dual live storage system further comprises:

9. The server of claim 7, wherein the dual live storage system further comprises:

10. The server of claim 7, wherein the dual live storage system further comprises: