CN116450517B - Assessment method of HDL vulnerability analysis tool based on side channel information - Google Patents
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Abstract
The invention discloses an evaluation method of HDL vulnerability analysis tools based on side channel information, which comprises static evaluation and dynamic evaluation; static evaluation includes: analyzing a test scene, and confirming the range of a parameter K and a parameter H; selecting a plurality of static test cases to prepare for testing; a3: setting test parameters of an analysis tool; and calculating and obtaining static indexes under different test parameters to obtain a test result. Dynamic evaluation includes: according to the test scene, a test chip and a side channel signal acquisition component are selected; dividing the region of the target test chip, selecting a dynamic test case, and collecting side channel signals of each region; acquiring side channel signals, and acquiring the resolution and the corresponding probability of each region; and calculating a consistency index and an average value. The invention provides a HDL code vulnerability analysis tool utility evaluation system, which realizes the evaluation of HDL code vulnerability analysis tool utility.
Description
Technical Field
The invention relates to the technical field of hardware security, in particular to an evaluation method of HDL vulnerability analysis tools based on side channel information.
Background
Hardware security is a typical interdisciplinary field, and relates to a plurality of fields of mathematics, computers, signal processing, analysis and the like, and with the upgrading of intelligent equipment, an FPGA device is widely used in the fields of aviation, aerospace, petroleum, electric power, weaponry and the like. The hardware description language (HDL, hardwareDescriptionLanguage) is an important part of the design of the FPGA, various loopholes and defects exist in the design process of HDL codes, and the possibility and the risk of being utilized exist. Therefore, the safe and reliable HDL code design also becomes the basic guarantee of the safe application of the FPGA device and the intelligent equipment.
The side channel analysis is an important means for analyzing the vulnerability of the FPGA device, the vulnerability analysis of HDL codes is consistent with the basic thought of the vulnerability analysis of software codes, and the vulnerability analysis of HDL codes is aimed at, for example, application number: CN201711103362.3, named as a hardware vulnerability assessment method based on HDL codes, takes HDL developed programs as input of grammar and semantic analysis, calculates vulnerability weights of all sides by establishing connection topological relations of all HDL modules, so as to assess the vulnerability of all modules and further conduct vulnerability grade division on all modules; however, because the execution of HDL code is implemented in a specific hardware environment, the utility of the HDL code vulnerability analysis tools is currently difficult to evaluate accurately.
Disclosure of Invention
In order to solve the problems, the invention provides an evaluation method of an HDL vulnerability analysis tool based on side channel information, which is used for carrying out utility evaluation on the HDL vulnerability analysis tool based on test cases and mainly comprises evaluation before HDL code operation and during HDL code operation, wherein the evaluation method is respectively defined as HDL code static analysis and HDL code dynamic test; the HDL code vulnerability analysis tool utility evaluation system is constructed, and the accurate evaluation of the HDL code vulnerability analysis tool utility is realized.
The invention provides an evaluation method of HDL vulnerability analysis tools based on side channel information, which comprises the following specific technical scheme:
the method comprises static evaluation and dynamic evaluation;
the static evaluation is carried out by the following specific procedures:
a1: analyzing a test scene, and confirming the range of the maximum layer number K of the HDL code unit module and the total number H of gate turnover times;
a2: selecting a plurality of static test cases to prepare for testing according to the determined range of the maximum layer number K of the HDL code unit module and the total number H of gate turnover times;
a3: setting test parameters of a vulnerability analysis tool to be evaluated, wherein the test parameters are the number of layers of the HDL code unit module which can be identified currently by the tool;
a4: based on the vulnerability analysis tool, testing the test cases, calculating and obtaining static indexes under different test parameters, and obtaining test results.
The dynamic evaluation comprises the following specific processes:
b1: according to the test scene, a test chip and a side channel signal acquisition component are selected;
b2: dividing regions of a target test chip, selecting dynamic test cases according to the divided regions, and collecting side channel signals of each region;
b3: setting the repetition times and probability threshold of side channel signal acquisition, and carrying out repeated side channel signal acquisition on each divided region based on the corresponding dynamic test case to acquire the resolution and the corresponding probability of each region;
b4: according to the resolution ratio, adjusting the dynamic test case, carrying out consistency index test, and calculating a consistency index mean value by repeatedly carrying out the consistency index test;
the consistency index represents the ability of the channel signal detection at the inner side of the area to resist the influence of the channel signal at the side of the adjacent area.
Further, the maximum layer number K of the HDL code unit module is 6, and the total number of gate turning times H is in the range of 100000-200000.
Further, the static index includes code coverage and accuracy.
Further, the code coverage is calculated as follows:
wherein I represents the number of selected test cases for testing, M i Indicating the total number of gate inversions, N, of the ith test case i Representing the total number of door turnover times of the correct identification module of the current vulnerability analysis tool;
further, the accuracy is calculated as follows:
wherein Q is i Representing the total number of code units of the ith test case, P i The total number of code units representing the number of door flips of the current vulnerability analysis tool correctly identifies the module.
In step B2, dividing the target test chip into nine equal division areas, setting a probe at the center of each area, and setting the height of the probe to be 3mm;
when the side channel signal is acquired in a certain area, the door turnover times of other areas are kept unchanged.
Further, in step B3, the number of acquisition repetitions is 100, and the probability threshold range is [75, 85].
Further, in step B3, dynamic test case correction is further included before the repeated side channel signal acquisition, so that the probability of each test result should be within the probability threshold range when the test is repeated.
Further, the consistency index is specifically calculated as follows:
wherein M represents the number of areas divided by the target test chip, L ij Representing the energy variation coefficient, increasing the number of gate inversions F when the jth region i If the side channel signal energy of the ith area is detected, the L is recorded ij =1, if the side channel signal energy increase of the i-th region is detected, the symbol L ij ＝0。
The beneficial effects of the invention are as follows:
according to the method, a test case is selected to evaluate the utility of the HDL code vulnerability analysis tool according to a test scene, the evaluation is performed before HDL code operation and during HDL code operation, an HDL code vulnerability analysis tool utility evaluation system is provided, accurate evaluation of the utility of the HDL code vulnerability analysis tool is achieved, the method can be used for evaluating the utility of the current typical HDL code vulnerability analysis tool, and meanwhile, the evaluation index provided by the method has stronger universality and accuracy for the current common side channel analysis tool, so that standardized development of the hardware security analysis tool is facilitated.
Drawings
FIG. 1 is a schematic diagram of a static evaluation flow;
FIG. 2 is a schematic diagram of a dynamic evaluation flow;
fig. 3 is a schematic view of region division.
Detailed Description
In the following description, the technical solutions of the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the embodiments of the present invention, it should be noted that, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship conventionally put in use of the product of the present invention as understood by those skilled in the art, merely for convenience of describing the present invention and simplifying the description, and is not indicative or implying that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used merely for distinguishing between descriptions and not for understanding as indicating or implying a relative importance.
In the description of the embodiments of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Example 1
The embodiment 1 of the invention discloses an evaluation method of HDL vulnerability analysis tools based on side channel information, which comprises the steps of static efficiency evaluation, wherein the vulnerability analysis tools based on the side channel information accurately identify the gate turnover times of each code unit module of HDL, and analyze the leakage degree of side channel signals before HDL code is executed; in the case of non-execution of HDL code, the result of recognition of the number of gate flips of each code unit module by the analysis tool should be stable.
As shown in fig. 1, the specific step flow is as follows:
a1: analyzing a test scene, and confirming the range of the maximum layer number K of the HDL code unit module and the total number H of gate turnover times;
the maximum number of layers K of the HDL code unit module and the total number of gate turnovers H are related according to the actual test scenario, which is not limited herein, in this embodiment, the maximum number of layers K of the HDL code unit module is 6, and the total number of gate turnovers H ranges from 100000 to 200000.
A2: selecting a plurality of static test cases to prepare for testing according to the determined range of the maximum layer number K of the HDL code unit module and the total number H of gate turnover times;
in the embodiment, four test cases are selected for testing;
a3: setting test parameters of a vulnerability analysis tool to be evaluated, wherein the test parameters are the number of layers of the HDL code unit module which can be identified currently by the tool.
A4: based on the vulnerability analysis tool, testing the test cases, calculating and obtaining static indexes under different test parameters, and obtaining test results.
In this embodiment, the static index includes code coverage rate and accuracy rate;
the code coverage is calculated as follows:
wherein I represents the number of selected test cases for testing, M i Indicating the total number of gate inversions, N, of the ith test case i Representing the total number of door turnover times of the correct identification module of the current vulnerability analysis tool;
the accuracy is calculated as follows:
wherein Q is i Representing the total number of code units of the ith test case, P i The total number of code units representing the number of door flips of the current vulnerability analysis tool correctly identifies the module.
In this embodiment, the test parameters are set to be 4,5, and 6, respectively, for example, to perform a test, and explanation is made;
and in the test, gate turnover times Q1, Q2, Q3, Q4 and Q5 of the test case are counted by the saif file and used as calculation reference values, index calculation is carried out, and the test results are shown in the following tables 1 and 2.
Table 1: code coverage test results
Table 2: accuracy test results
The larger the number of correctly identifiable unit module layers of the vulnerability analysis tool is, the higher the code coverage rate and the accuracy are; and (3) the time cost caused by the increase of the number of the identification unit module layers is increased, and the identifiable unit module layers, the corresponding accuracy and the time cost are output as a static evaluation result.
Example 2
The embodiment 1 of the invention discloses an evaluation method of HDL vulnerability analysis tools based on side channel information, which comprises dynamic performance evaluation, wherein the vulnerability analysis tools based on the side channel information can identify the characteristics of typical HDL codes, including energy characteristics, waveform characteristics and the like, through detection and analysis of the side channel information. In the case of HDL code execution, HDL code unit modules are to be implemented in an FPGA-specific area by placement and routing.
As shown in fig. 2, the specific step flow is as follows:
b1: according to the test scene, a test chip and a side channel signal acquisition component are selected, and a side channel information detection scheme is determined;
the detection scheme is that region division design is carried out according to the layout and wiring conditions of the chip;
in this embodiment, the side channel signal acquisition component is matched with the characteristics of the selected test chip;
in practice, the test chip is subjected to uncovering treatment, so that electromagnetic signals when the chip runs a specified test case are collected conveniently, and further the change of the door turnover frequency is judged through the peak value change of the electromagnetic signals in each area.
B2: dividing regions of a target test chip, selecting dynamic test cases according to the divided regions, and collecting side channel signals of each region;
the division of the areas and the position setting of the probes are performed according to the actual situation, and are not particularly limited herein, as shown in fig. 3, in this embodiment, the target test chip is divided into nine equally divided areas, the probes are set in the center of each area, and the probe height is set to 3mm.
B3: setting the repetition times and probability threshold of side channel signal acquisition, and carrying out repeated side channel signal acquisition on each divided region based on the corresponding dynamic test case to acquire the resolution and the corresponding probability of each region;
the number of acquisition repetitions and the probability threshold may be set according to actual situations, which are not limited in detail herein, and in this embodiment, the number of acquisition repetitions is 100, and the probability threshold range is [75, 85];
when the test is repeated, the probability of each test result is within the probability threshold value range;
in the test, the resolution F corresponding to the ith area is tested i When the door overturning times of other areas are kept unchanged;
the acquisition repetition number is the number of times of acquiring side channel signals by testing the same division area based on the corresponding same dynamic test case;
the probability range represents a range threshold of the detectable probability of the gate turnover number in the ith area; when the ith area is tested based on the corresponding dynamic test case, the range of the probability of the ratio of the door turnover times detected in the ith area to the door turnover times of the dynamic test case;
the resolution F i The minimum detectable gate flip times difference for side channel signal detection; in the test, the door turnover number identification probability is in the probability threshold range, and the minimum difference value of the door turnover number change can be detected;
the number of acquisition repetition is 100, and the probability threshold range is [75, 85]]The resolution F i The specific acquisition process is as follows:
setting a resolution initial value and a minimum resolution step, performing 100 repeated tests on a certain divided area based on the resolution initial value, judging whether the detectable probability is in a probability threshold range according to a detection result of the number of times of gate turnover, if not, performing increasing or decreasing adjustment on the resolution initial value, performing 100 repeated tests on the certain divided area again according to the adjusted resolution until the probability of gate turnover identification of the test is in the probability threshold range, and determining the minimum value corresponding to the probability obtained by the multiple times of resolution adjustment in the probability threshold range as the resolution F i ；
The minimum resolution step is a difference value between resolutions corresponding to probabilities within a probability threshold range, for example, when the minimum resolution step is 100, the resolution corresponding to the divided area 1 is 400; the process is as follows: 100 repeated tests can be carried out as an initial value of the resolution, if the probability is far smaller than the minimum value 75 of the probability threshold range, the resolution can be adjusted to be 500, 100 repeated tests are carried out again, if the probability is slightly larger than the maximum value 85 of the probability threshold range, the resolution is adjusted to be 400 based on the minimum step of the resolution, 100 repeated tests are carried out again, the probability is within the probability threshold range and the probabilities are both within the range of the resolution before and after the minimum step of the resolution, the probabilities are outside the probability threshold range, the identification resolution of the door turning times is 400 based on the current dividing region and the corresponding probe under the condition that the probability threshold range is [75, 85] and the repetition times are 100.
100 repetitions, with probabilities in the range 75, 85, the results are exemplified in Table 3 below;
table 3: resolution test results
| Region(s) | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
| Resolution ratio | 400 | 400 | 500 | 900 | 600 | 400 | 600 | 500 | 400 |
| Probability of | 82％ | 80％ | 83％ | 79％ | 81％ | 81％ | 84％ | 77％ | 80％ |
B4: and (3) according to the resolution ratio adjustment dynamic test case, carrying out consistency index test, and calculating a consistency index mean value by repeatedly carrying out the consistency index test.
The consistency index represents the capability of detecting the channel signal at the inner side of the area to resist the influence of the channel signal at the side of the adjacent area;
the specific calculation is as follows:
wherein M represents the number of areas divided by the target test chip, L ij Representing the energy variation coefficient, increasing the number of gate inversions F when the jth region i If the side channel signal energy of the ith area is detected, the L is recorded ij =1, if the side channel signal energy increase of the i-th region is detected, the symbol L ij ＝0。
In this example, 5 times of repeated one-time index test are performed, and the conditions of obtaining the consistency index and the average value thereof are shown in the following table 4;
table 4: consistency index test results
| Number of tests | 1 | 2 | 3 | 4 | 5 | Mean value of |
| Consistency index | 86.1％ | 85.7％ | 86.1％ | 90.3％ | 87.5％ | 87.14％ |
And outputting the repetition number and the average value result of the consistency index test and the acquisition repetition number and the probability threshold value of the consistency index as dynamic evaluation results.
The invention is not limited to the specific embodiments described above. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification, as well as to any novel one, or any novel combination, of the steps of the method or process disclosed.
Claims (7)
1. An evaluation method of HDL vulnerability analysis tool based on side channel information, characterized in that the method comprises static evaluation and dynamic evaluation;
the static evaluation is carried out by the following specific procedures:
a1: analyzing a test scene, and confirming the range of the maximum layer number K of the HDL code unit module and the total number H of gate turnover times;
a2: selecting a plurality of static test cases to prepare for testing according to the determined range of the maximum layer number K of the HDL code unit module and the total number H of gate turnover times;
a3: setting test parameters of a vulnerability analysis tool to be evaluated, wherein the test parameters are the number of layers of the HDL code unit module which can be identified currently by the tool;
a4: based on the vulnerability analysis tool, testing the test cases, calculating and obtaining static indexes under different test parameters, and obtaining test results;
the static index comprises code coverage rate and accuracy rate;
the dynamic evaluation comprises the following specific processes:
b1: according to the test scene, a test chip and a side channel signal acquisition component are selected;
b2: dividing regions of a target test chip, selecting dynamic test cases according to the divided regions, and collecting side channel signals of each region;
b3: setting the repetition times and probability threshold of side channel signal acquisition, and carrying out repeated side channel signal acquisition on each divided region based on the corresponding dynamic test case to acquire the resolution and the corresponding probability of each region;
the dynamic test case correction is further included before repeated side channel signal acquisition, so that the probability of each test result is within a probability threshold range when repeated tests are carried out;
the acquisition repetition number is the number of times of acquiring side channel signals by testing the same division area based on the corresponding same dynamic test case;
the probability range represents a range threshold of the detectable probability of the gate turnover number in the ith area; when the ith area is tested based on the corresponding dynamic test case, the range of the probability of the ratio of the door turnover times detected in the ith area to the door turnover times of the dynamic test case;
the resolution is the minimum detectable gate turnover frequency difference for detecting the side channel signals; in the test, the door turnover number identification probability is in the probability threshold range, and the minimum difference value of the door turnover number change can be detected;
b4: according to the resolution ratio, adjusting the dynamic test case, carrying out consistency index test, and calculating a consistency index mean value by repeatedly carrying out the consistency index test;
the consistency index represents the ability of the channel signal detection at the inner side of the area to resist the influence of the channel signal at the side of the adjacent area.
2. The method for evaluating an HDL vulnerability analysis tool based on side channel information of claim 1, wherein the maximum number of layers K of the HDL code unit modules is 6, and the total number of gate flips H is in the range of 100000-200000.
3. The method for evaluating an HDL vulnerability analysis tool based on side channel information of claim 1, wherein the code coverage is calculated as follows:
wherein I represents the number of selected test cases for testing, M i Indicating the total number of gate inversions, N, of the ith test case i Representing the currentThe vulnerability analysis tool correctly identifies the total number of door flips for the module.
4. The method for evaluating an HDL vulnerability analysis tool based on side channel information of claim 1, wherein the accuracy is calculated as follows:
wherein Q is i Representing the total number of code units of the ith test case, P i The total number of code units representing the number of door flips of the current vulnerability analysis tool correctly identifies the module.
5. The method for evaluating HDL vulnerability analysis tool based on side channel information according to claim 1, wherein in step B2, the target test chip is divided into nine divided areas, the probe is set at the center of each area, and the probe height is set to 3mm;
when the side channel signal is acquired in a certain area, the door turnover times of other areas are kept unchanged.
6. The method for evaluating an HDL vulnerability analysis tool based on side channel information of claim 1, wherein in step B3, the number of acquisition repetition is 100, and the probability threshold range is [75, 85].
7. The method for evaluating an HDL vulnerability analysis tool based on side channel information of claim 1, wherein the consistency index is specifically calculated as follows:
wherein M represents the number of areas divided by the target test chip, L ij Representing energy variation coefficients, when the jth zone is added with a gateNumber of turns F i If the side channel signal energy of the ith area is detected, the L is recorded ij =1, if the side channel signal energy increase of the i-th region is detected, the symbol L ij ＝0。
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| CN114547966A (en) * | 2022-01-10 | 2022-05-27 | 浙江大学 | Neural network accelerator fault vulnerability assessment method based on hardware characteristic information |
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| US10409994B1 (en) * | 2017-03-01 | 2019-09-10 | National Technology & Engineering Solutions Of Sandia, Llc | FPGA/ASIC framework and method for requirements-based trust assessment |
| CN107341101A (en) * | 2017-06-01 | 2017-11-10 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method for measuring FPGA software rest mass |
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