CN116449133A - Probe card and probe card testing method - Google Patents
Probe card and probe card testing method Download PDFInfo
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- CN116449133A CN116449133A CN202310391057.8A CN202310391057A CN116449133A CN 116449133 A CN116449133 A CN 116449133A CN 202310391057 A CN202310391057 A CN 202310391057A CN 116449133 A CN116449133 A CN 116449133A
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- 239000000523 sample Substances 0.000 title claims abstract description 106
- 238000012360 testing method Methods 0.000 title claims abstract description 66
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- 238000012544 monitoring process Methods 0.000 claims description 11
- 230000009471 action Effects 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 4
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/003—Environmental or reliability tests
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
Abstract
The invention discloses a probe card and a probe card testing method. The first electrical structure is connected with the pin body in series; the second electrical structure is connected with the first electrical structure in parallel; the first electrical structure and the second electrical structure are connected in parallel and then are electrically connected with the pad of the sample to be tested. The invention solves the problem that in the prior art, in the process of performing TDDB test and Vramp test, the instantaneous current generated when the dielectric film or oxide layer is broken down increases and the metal connection between the gate oxide layer and the power supply is easy to blow.
Description
Technical Field
The application relates to the technical field of test equipment, in particular to a probe card and a probe card test method.
Background
In reliability testing, time-dependent dielectric breakdown (TDDB) and ramp voltage (Vramp) tests are used to measure dielectric layer quality. Wherein the TDDB test is to generate and accumulate defects (traps) in the dielectric film by applying an electric field, and the dielectric film fails when the traps form conductive paths in the dielectric film; vramp testing is performed by applying a linear ramp voltage to the gate until the oxide breaks down. As shown in fig. 1-2, under normal conditions, the curves jump upwards to reach the multiplying power and are captured by the machine when the TDDB test and the Vramp test fail, and then the test is ended.
As shown in fig. 3 to 4, in the process of performing the TDDB test and the Vramp test, a short circuit is caused due to an increase in an instantaneous current generated when the dielectric film or the oxide layer is broken through, which is easy to blow a metal connection line between the gate oxide layer and the power supply, and thus the current is reduced, so that the machine cannot determine whether to fail, and the machine may continue to be pressurized until reaching a set upper voltage limit or a set upper time limit.
Based on this, a new solution is needed.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a probe card and a probe card testing method, so as to at least solve the problem that a metal wire between a gate oxide layer and a power supply is easily blown in the process of performing TDDB test and Vramp test in the prior art.
The embodiment of the invention provides the following technical scheme:
the embodiment of the invention comprises a probe card main body, wherein a plurality of pin structures are arranged on the probe card main body, each pin structure comprises a pin body, and the pin structure further comprises:
the first electrical structure is connected with the pin body in series;
the second electrical structure is connected with the first electrical structure in parallel;
the first electrical structure and the second electrical structure are connected in parallel and then are electrically connected with the pad of the sample to be tested.
Further, the first electrical structure is one or more of a fuse, a self-restoring fuse, and an electronic fuse.
Further, the second electrical structure is one or more of a resistor, a potentiometer and a variable resistor.
The invention discloses a probe card testing method, which is applied to the probe card and comprises the following steps:
connecting a pin structure of the probe card with a pad of a sample to be tested;
applying a low voltage Vuse and a high voltage Vstress to the pin structure in a circulating manner based on a stress-induced leakage current test, and monitoring a use current Iuse and a pressure current Isstress generated by the pad
Under the condition that the high voltage Vstress is increased until the dielectric layer is broken down, the pressure current Isstress blows a first electrical structure on the pin structure and slowly rises under the action of a second electrical structure on the pin structure;
judging whether the sample to be tested is invalid or not based on the current Iase in the pad.
Further, the determining whether the sample to be tested fails based on the current in the pad includes:
and judging that the sample to be tested fails under the condition that the current Iase in the gasket is increased to a preset failure current multiplying power.
Further, the determining whether the sample to be tested fails based on the current in the pad includes:
and judging that the sample to be tested fails under the condition that the current Iase in the gasket is increased to a preset upper limit threshold value.
Further, based on the stress-induced leakage current test, cyclically applying a low voltage vue and a high voltage Vstress on the pin structure and monitoring the pad generated usage current Iuse and pressure current Istress comprises:
applying the low voltage Vuse to the pin structure and monitoring the use current Iue in the pad, and then applying the high voltage Vstress to the pin structure and monitoring the pressure current Istres in the pad;
repeating the steps until the pressure current Istress blows the first electrical structure.
Further, after judging that the sample to be tested fails, the pressurizing of the sample to be tested is stopped.
Further, connecting the pin structure of the probe card with the pad of the sample to be tested includes:
and connecting the first electrical structure and the second electrical structure on the pin structure in parallel and then connecting the first electrical structure and the second electrical structure with the pad.
Further, after the first electrical structure and the second electrical structure on the pin structure are connected in parallel and then connected to the pad, the method further comprises:
and connecting the other pin structures of the probe card with 0V to ensure the accuracy and stability of the measurement signals.
Compared with the prior art, the probe card and the probe card testing method provided by the embodiment of the invention have the advantages that the first electrical structure is connected in series on the pin body of the probe card, and the second electrical structure is arranged to be connected with the first electrical structure, so that the Vramp test and the TDDB test are carried out by combining the stress-induced leakage current testing method, and the problem that the metal connection between the gate oxide layer and the power supply is easy to burn due to the increase of the transient current generated when the dielectric film or the oxide layer is broken down in the process of carrying out the TDDB test and the Vramp test in the prior art is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a graph showing a first trend of gate current with voltage during breakdown of a dielectric layer of a MOS device according to the prior art;
FIG. 2 is a graph showing a first trend of gate current over time when a dielectric layer of a prior art MOS device breaks down;
FIG. 3 is a graph showing a second trend of gate current over time during breakdown of a dielectric layer of a MOS device according to the prior art;
FIG. 4 is a graph showing a second trend of gate current over time during breakdown of a dielectric layer of a MOS device according to the prior art;
FIG. 5 is a schematic diagram of a probe card according to an embodiment of the invention;
FIG. 6 is a diagram illustrating a current test performed by using a probe card for Vramp testing in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure of two pins of a probe card according to an embodiment of the invention;
fig. 8 is a diagram illustrating a current test performed using a probe card for TDDB testing in accordance with an embodiment of the present invention.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.
Aiming at the problems that in the prior art, the TDDB test and the Vramp test can generate instant current to blow a metal connection line between a gate oxide layer and a power supply, so that a machine can continuously pressurize until the set upper voltage limit or the set upper time limit is reached.
The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.
Example 1
As shown in fig. 5, a probe card according to an embodiment of the invention includes a probe card body 10, a plurality of pin structures 20 are disposed on the probe card body 10, and the pin structures 20 include a pin body 21, a first electrical structure 22 and a second electrical structure 23. The first electrical structure 22 is connected in series with the pin body 21; the second electrical structure 23 is connected in parallel with the first electrical structure 22; the first electrical structure 22 and the second electrical structure 23 are electrically connected in parallel and then electrically connected with the pad of the sample to be tested.
The first electrical structure 22 may be one or more of a fuse, a self-restoring fuse, and an electronic fuse.
Preferably, the first electrical structure 22 is a fuse.
The second electrical structure 23 may be one or more of a resistor, a potentiometer, and a variable resistor.
Preferably, the second electrical structure 23 is a resistor.
After the first electrical structure 22 and the second electrical structure 23 are connected in parallel, voltage can be applied to the pin body 21 by combining with the SILC test to perform the TDDB test and the Vramp test, and under the condition of generating the transient current, the transient current will blow the first electrical structure 22 and slowly rise under the action of the second electrical structure 23, thereby avoiding the metal wiring between the gate oxide layer and the power supply from being blown and judging whether the sample to be tested fails.
The rated current and rated voltage of the first electrical structure 22 can be flexibly set according to requirements.
The resistance of the second electrical structure 23 can be flexibly set according to the requirement to adjust the rising rate of the instantaneous current in the second electrical structure 23.
The probe card of the embodiment of the invention has simple testing process, does not need to additionally introduce a new testing port or greatly change the existing testing structure, has wide application range, and can change the mutation current by adjusting the size of the second electrical structure 23.
Example 2
The probe card testing method of the embodiment of the invention is applied to the probe card of the embodiment 1, and comprises the following steps:
step S102, connecting a pin structure of a probe card with a pad of a sample to be tested;
step S104, based on stress-induced leakage current test, circularly applying low voltage Vuse and high voltage Vstress to the pin structure, and monitoring use current Iuse and pressure current Isstress generated by the pad;
step S106, under the condition that the high voltage Vstress is increased until the dielectric layer is broken down, the pressure current Isstress blows the first electrical structure on the pin structure and slowly rises under the action of the second electrical structure on the pin structure;
step S108, judging whether the sample to be tested fails or not based on the current Iase in the pad.
In step S102, connecting a pin structure of the probe card with the pad of the sample to be tested includes:
and connecting the first electrical structure and the second electrical structure on the pin structure in parallel and then connecting the first electrical structure and the second electrical structure with the pad of the sample so as to obtain the current of the pad.
Connecting a pin structure of the probe card with the pad of the sample to be tested further comprises:
the other pin structures of the probe card are connected with 0V to ensure the accuracy and stability of the measurement signals and reduce the measurement error.
Step S104 includes:
firstly applying a low voltage Vuse to a pin structure, monitoring a use current Irose in a liner, then applying a high voltage Vstress to the pin structure, and monitoring a pressure current Istres in the liner;
repeating the steps until the pressure current Istres blows the first electrical structure.
Wherein, before applying each high voltage vstres on the pin structure, a low voltage is applied and the current Iuse is tested.
In the SILC test, a high voltage is applied to accelerate the generation and accumulation of leakage current, and then the voltage is reduced to observe the change and recovery of the leakage current in the dielectric layer, so that the circulation is repeated, the characteristics of stability, vulnerability, service life and the like of the leakage current in the dielectric layer can be analyzed, and the reliability and degradation mechanism of the device can be evaluated.
The dielectric layer can be an oxide layer or a dielectric film.
In some of these embodiments, in the case of Vramp testing using a probe card, determining whether the sample under test has failed based on the pad usage current Iuse includes:
and under the condition that the current Iase in the gasket is increased to a preset failure current multiplying power, judging that the sample to be tested fails.
Specifically, when the SILC voltage is applied to the pin structure (i.e., the low voltage Vuse and the high voltage Vstress are cyclically applied), if the first electrical structure of the pin structure is not fused, the current Iuse used at this time will not change significantly, the pressure current Istress will rise slowly, and when the high voltage Vstress increases to cause the dielectric layer to break down, the pressure current Istress will rise instantaneously to blow the first electrical structure in the pin structure, at this time, the Istress current will rise slowly due to the existence of the second electrical structure, so as to avoid the metal wiring between the gate oxide layer and the power supply from being blown, and meanwhile, the current Iuse used before the dielectric layer breaks down will be significantly increased, reaching the preset failure current multiplying power, at this time, the machine station determines that the sample is failed, and stops pressurizing the sample.
And finally, under the condition that the sample to be tested is judged to be invalid, stopping pressurizing the sample to be tested so as to reduce further damage or destruction to the sample.
In some of these embodiments, in the case of performing the TDDB test using the probe card, determining whether the sample to be tested is invalid based on the pad use current Iuse further includes:
and judging that the sample to be tested fails under the condition that the current Iase in the gasket is increased to a preset upper limit threshold value.
Specifically, the SILC voltage is applied to the pin structure (i.e., the low voltage Vuse and the high voltage Vstress are cyclically applied), when the first electrical structure of the pin structure is not fused, the low voltage Vuse is applied to the pin structure, iuse does not change significantly, the pressure current Istress will rise slowly, and when the high voltage Vstress is increased to break through the dielectric layer, the pressure current Istress increases to fuse the first electrical structure of the pin structure, iuse will rise significantly, and reach the preset upper threshold, and at this time, the test of the sample to be tested is stopped.
And finally, under the condition that the sample to be tested is judged to be invalid, stopping pressurizing the sample to be tested so as to reduce further damage or destruction to the sample.
One specific embodiment of a probe card according to embodiments of the present invention for Vramp testing is as follows:
as shown in fig. 6 to 7, in the case that the probe card includes PIN1 and PIN2, and PIN1 and PIN2 are correspondingly connected with PAD1 and PAD2 of the sample, SILC voltage is applied to PIN1, PIN2 is connected with 0V, and meanwhile current change of PAD1 is monitored (as shown in fig. 6), iuse current under low voltage Vuse stress does not change obviously, and Istress rises slowly under the condition that the first electrical structure W of PIN1 is not fused;
when the high voltage Vstress increases to the breakdown dielectric layer, the pressure current Istress will suddenly increase to blow the first electrical structure W of PIN1, at this time, the pressure current Istress will slowly rise because of the existence of the second electrical structure R, and the use current Iuse under the low voltage Vuse will be significantly increased compared with that before breakdown, so as to reach the failure current multiplying power set by the machine, and the machine will immediately judge that the sample fails and stop pressurizing the sample.
The embodiment of the invention combines the probe card with the novel structure of the embodiment 1 with the SILC test, thereby avoiding the instant current from blowing the metal wiring between the gate oxide layer and the power supply and facilitating the Vramp test.
One specific embodiment of performing TDDB testing on a probe card according to embodiments of the present invention is as follows:
as shown in fig. 7 to 8, in the case that the probe card includes PIN1 and PIN2, and PIN1 and PIN2 are correspondingly connected with PAD1 and PAD2 of the sample, SILC voltage is applied to PIN1, PIN2 is connected with 0V, and meanwhile current change of PAD1 is monitored (as shown in fig. 8), iuse current under low voltage Vuse stress does not change obviously, and Istress rises slowly under the condition that the first electrical structure W of PIN1 is not fused;
when the high voltage Vstress increases to the breakdown dielectric layer, the pressure current Istress will suddenly increase to blow the first electrical structure W of PIN1, at this time, the pressure current Istress will slowly rise because of the existence of the second electrical structure R, and the usage current Iuse under the low voltage Vuse will obviously rise compared with that before breakdown, reaching the upper current limit set by the machine, the machine judges that the sample fails, and the test on the sample is stopped.
The probe card combined with the SILC test mode has the following beneficial effects in a specific operation process:
(1) The testing process is simple, a new testing port is not additionally introduced, and the existing testing structure is not required to be changed;
(2) The second electrical structure enables the current to rise slowly, so that the situation that the machine cannot judge the failure of the sample due to the sudden drop of the current can be effectively prevented, the machine and the probe card are protected, and the machine is saved;
(3) The application range is wide, and the mutation current can be changed by adjusting the size of the second electrical structure.
In this specification, identical and similar parts of the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a probe card, includes the probe card main part, be equipped with a plurality of pin structures on the probe card main part, the pin structure includes the pin body, its characterized in that, the pin structure still includes:
the first electrical structure is connected with the pin body in series;
the second electrical structure is connected with the first electrical structure in parallel;
the first electrical structure and the second electrical structure are connected in parallel and then are electrically connected with the pad of the sample to be tested.
2. The probe card of claim 1, wherein the first electrical structure is one or more of a fuse, a self-healing fuse, and an electronic fuse.
3. The probe card of claim 1, wherein the second electrical structure is one or more of a resistor, a potentiometer, and a variable resistor.
4. A probe card testing method, which is applied to the probe card of any one of claims 1 to 3, comprising:
connecting a pin structure of the probe card with a pad of a sample to be tested;
applying a low voltage Vuse and a high voltage Vstress to the pin structure in a circulating manner based on a stress-induced leakage current test, and monitoring a use current Iuse and a pressure current Isstress generated by the pad
Under the condition that the high voltage Vstress is increased until the dielectric layer is broken down, the pressure current Isstress blows a first electrical structure on the pin structure and slowly rises under the action of a second electrical structure on the pin structure;
judging whether the sample to be tested is invalid or not based on the current Iase in the pad.
5. The probe card testing method of claim 4, wherein said determining whether the sample under test has failed based on the current in use in the pad comprises:
and judging that the sample to be tested fails under the condition that the current Iase in the gasket is increased to a preset failure current multiplying power.
6. The probe card testing method of claim 4, wherein said determining whether the sample under test has failed based on the current in use in the pad comprises:
and judging that the sample to be tested fails under the condition that the current Iase in the gasket is increased to a preset upper limit threshold value.
7. The probe card testing method of claim 4, wherein cyclically applying a low voltage vue and a high voltage Vstress on the pin structure based on a stress-induced leakage current test, and monitoring the pad generated usage current Iuse and pressure current Istress comprises:
applying the low voltage Vuse to the pin structure and monitoring the use current Iue in the pad, and then applying the high voltage Vstress to the pin structure and monitoring the pressure current Istres in the pad;
repeating the steps until the pressure current Istress blows the first electrical structure.
8. The probe card testing method of claim 4, wherein pressurizing the sample to be tested is stopped after judging that the sample to be tested is invalid.
9. The probe card testing method of claim 4, wherein connecting the pin structures of the probe card to the pads of the sample under test comprises:
and connecting the first electrical structure and the second electrical structure on the pin structure in parallel and then connecting the first electrical structure and the second electrical structure with the pad.
10. The method of claim 9, further comprising, after connecting the first electrical structure and the second electrical structure on the pin structure in parallel and then to the pad:
and connecting the other pin structures of the probe card with 0V to ensure the accuracy and stability of the measurement signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310391057.8A CN116449133A (en) | 2023-04-12 | 2023-04-12 | Probe card and probe card testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310391057.8A CN116449133A (en) | 2023-04-12 | 2023-04-12 | Probe card and probe card testing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116449133A true CN116449133A (en) | 2023-07-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310391057.8A Pending CN116449133A (en) | 2023-04-12 | 2023-04-12 | Probe card and probe card testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116449133A (en) |
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2023
- 2023-04-12 CN CN202310391057.8A patent/CN116449133A/en active Pending
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