CN116436470A

CN116436470A - Device and chip for parallel-serial conversion

Info

Publication number: CN116436470A
Application number: CN202310404891.6A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Biren Intelligent Technology Co Ltd
Priority date: 2023-04-14
Filing date: 2023-04-14
Publication date: 2023-07-14

Abstract

The invention provides a device and a chip for parallel-serial conversion. The device comprises: a multi-modulus divider configured to receive a clock signal and generate a divided clock signal of any division ratio from the received clock signal; a shift register electrically connected to the multi-modulus divider, configured to receive parallel data to be converted and the frequency-divided clock signal, and to convert the parallel data into odd-bit serial data and even-bit serial data according to the frequency-divided clock signal; and a pre-driver, electrically connected to the shift register, configured to receive and mix the odd-bit serial data and the even-bit serial data to generate final serial data. The device for parallel-to-serial conversion can support any of a plurality of parallel-to-serial conversion modes, and can support the equalization function of any order and adjust the corresponding order coefficient, thereby remarkably improving the adjustment space of the equalization function of the device for parallel-to-serial conversion.

Description

Device and chip for parallel-serial conversion

Technical Field

Embodiments of the present invention relate generally to the field of data processing, and more particularly, to an apparatus and chip for parallel-to-serial conversion.

Background

SerDes (Serializer/Deserializer) includes a Serializer and a Deserializer, which are typically used to convert parallel data into serial data for transmission via the Serializer (Serializer) and to convert received serial data into parallel data via the Deserializer (Deserializer). A serializer, also known as a SerDes transmitter (Tx) or parallel to serial conversion circuit, may be used to convert multiple parallel data into one-way serial data for transmission, and may be used to drive an equalization driver connected to the serializer to compensate for channel impairments to the data signal transmitted by the serializer.

Conventional serializers typically support only a fixed one of the conversion modes, and do not support any of a plurality of conversion modes. For example, a serializer that supports conversion of 4-way parallel data into 1-way serial data has and only supports a conversion mode of 4-way parallel data into 1-way serial data, but cannot support other conversion modes such as conversion of 10-way parallel data into 1-way serial data, or conversion of 5-way parallel data into 1-way serial data. Moreover, conventional serializers typically only support equalization of a fixed order, and thus do not support adjustment of the order and corresponding order coefficients for equalization.

In summary, the conventional serializer has the following disadvantages: any of a plurality of parallel-to-serial conversion modes is not supported, and adjustment of the order and corresponding order coefficients for data equalization is not supported.

Disclosure of Invention

In view of the above problems, the present invention provides a device and a chip for parallel-to-serial conversion, which can support any of a plurality of parallel-to-serial conversion modes, and can support an equalization function of any order and adjust a corresponding order coefficient, thereby significantly improving an adjustment space for the equalization function of the device for parallel-to-serial conversion.

According to a first aspect of the present invention there is provided an apparatus for parallel to serial conversion, the apparatus comprising: a multi-modulus divider configured to receive a clock signal and generate a divided clock signal of any division ratio from the received clock signal; a shift register electrically connected to the multi-modulus divider, configured to receive the parallel data to be converted and the frequency-divided clock signal, and to convert the parallel data into odd-bit serial data and even-bit serial data according to the frequency-divided clock signal; and a pre-driver, electrically connected to the shift register, configured to receive and mix the odd-bit serial data and the even-bit serial data to generate converted serial data.

In some embodiments, the multi-modulus divider is further configured to receive a control signal to enable switching of multiple modes of parallel-to-serial conversion based on the received control signal.

In some embodiments, the shift register includes a first shift register configured to convert parallel data into odd-bit serial data according to the frequency division clock signal and a second shift register configured to convert parallel data into even-bit serial data according to the frequency division clock signal.

In some embodiments, the pre-driver includes: a misalignment driving unit configured to stagger the odd-bit serial data and the even-bit serial data by one unit data length so as to generate final serial data; and at least one phase delay driving unit, each configured to delay the generated final serial data by one unit data length.

In some embodiments, the misalignment driving unit includes: a multiplexer set configured to convert the odd-bit serial data and the even-bit serial data into final serial data; two first latches configured to receive and latch odd-bit serial data, wherein an output of a previous first latch is electrically connected to a receiving of a next first latch, and an output of the next first latch is electrically connected to a first input of the multiplexer set; and a second latch configured to receive and latch the even bit serial data, wherein an output of the second latch is electrically connected to a second input of the set of multiplexers.

In some embodiments, the clock signal input of the previous first latch is electrically connected to the clock signal input of the second latch.

In some embodiments, the phase delay driving unit includes: a multiplexer set configured to convert the odd-bit serial data and the even-bit serial data into final serial data; a first latch configured to receive and latch odd-bit serial data, wherein an input of the first latch is electrically connected to an output of a first latch in a previous phase delay drive unit or to an output of a subsequent first latch in a dislocation drive unit, the output of the first latch being electrically connected to a first input of a set of multiplexers; and a second latch configured to receive and latch the even-bit serial data, wherein an input of the second latch is electrically connected to an output of the second latch in the previous phase delay drive unit or the misalignment drive unit, and an output of the second latch is electrically connected to a second input of the multiplexer set.

In some embodiments, the clock signal input of the first latch is electrically connected to the clock signal input of the second latch.

In some embodiments, the final serial data output by the pre-driver includes a plurality of serial data having a phase difference, the plurality of serial data having a phase difference including: leading serial data; master serial data with a phase lag behind that of the preamble serial data; and post-cursor serial data phase-delayed from the main-cursor serial data.

In some embodiments, the apparatus for parallel-to-serial conversion further comprises: and an equalization driver electrically connected to the pre-driver and configured to receive the final serial data output by the pre-driver to generate equalized serial data.

In some embodiments, the equalization driver is configured to: receiving the pre-label serial data, the post-label serial data and the main label serial data generated by the pre-driver; and equalizing the master serial data according to the order of the pre-label serial data and the order of the post-label serial data to generate equalized output data.

According to a second aspect of the present invention, there is provided a chip comprising: a clock circuit for outputting a clock signal; and means for parallel-to-serial conversion according to the first aspect of the present invention, the means for parallel-to-serial conversion being electrically connected to the clock circuit.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

The above and other features, advantages and aspects of embodiments of the present invention will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements.

Fig. 1 shows a schematic diagram of an apparatus for parallel-to-serial conversion according to the prior art.

Fig. 2 shows a schematic diagram of an apparatus for parallel-to-serial conversion according to an embodiment of the invention.

Fig. 3 shows an example circuit diagram of a multi-modulus divider, according to an embodiment of the present invention.

Fig. 4 shows an example circuit diagram of a divide-by-two frequency divider according to an embodiment of the invention.

Fig. 5 shows an example circuit diagram of a shift register according to an embodiment of the present invention.

Fig. 6 shows a timing chart when the shift register performs parallel-to-serial conversion according to an embodiment of the present invention.

Fig. 7 shows an example circuit diagram of a pre-driver according to an embodiment of the present invention.

Fig. 8 shows a timing diagram of a pre-driver according to an embodiment of the present invention.

Fig. 9 shows a circuit schematic of a chip according to an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, in which various details of the embodiments of the present invention are included to facilitate understanding, and are to be considered merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Fig. 1 shows a schematic diagram of an apparatus 100 for parallel-to-serial conversion according to the prior art. As shown in fig. 1, an apparatus 100 for parallel-to-serial conversion includes a serializer 102, and the serializer 102 may include a shift register 110 and a pre-driver 120. In general, serializer 102 divides the parallel-to-serial conversion process of data into two steps: firstly, N pieces of parallel data are converted into 2 pieces of parallel data, i.e., parallel odd-bit serial data and even-bit serial data, via the shift register 110; the parallel odd-bit serial data and even-bit serial data are then converted into one-way serial data via the pre-driver 120. The quality of the output serial data can be improved by converting the N pieces of parallel data into 2 pieces of parallel data and then converting the 2 pieces of parallel data into one path of serial data. As shown in fig. 1, the apparatus 100 for parallel-to-serial conversion further includes an equalization driver 130, and the equalization driver 130 is driven by the pre-driver 120 to equalize the outputted serial data. However, as described above, the serializer of the prior art has disadvantages in that: any of a plurality of parallel-to-serial conversion modes is not supported, and adjustment of the order and corresponding order coefficients for data equalization is not supported.

To at least partially address one or more of the above problems, as well as other potential problems, example embodiments of the present invention propose a solution for parallel-to-serial conversion. In this aspect, by including a multi-modulus divider in the present invention, it is configured to receive a clock signal and generate a divided clock signal of an arbitrary division ratio from the received clock signal; a shift register electrically connected to the multi-modulus divider, configured to receive the parallel data to be converted and the frequency-divided clock signal, and to convert the parallel data into odd-bit serial data and even-bit serial data according to the frequency-divided clock signal; and a pre-driver electrically connected with the shift register and configured to receive and mix the odd-bit serial data and the even-bit serial data to generate converted serial data.

The apparatus for parallel-to-serial conversion will be described below with reference to fig. 2 to 8. Fig. 2 shows a schematic diagram of an apparatus 200 for parallel-to-serial conversion according to an embodiment of the invention. As shown in fig. 2, apparatus 200 includes a multi-modulus divider 205, a shift register 210, a pre-driver 220, and an equalization driver 230. It should be understood that apparatus 200 may also include additional elements not shown and/or may omit elements shown, the scope of the invention being not limited in this respect.

Regarding the multi-modulus divider 205, it may generate clock signals of different frequencies as needed. For example, according to an embodiment of the present invention, the multi-modulus divider 205 is configured to receive the clock signal clk and generate a divided clock signal from the received clock signal clk. In some embodiments, the multi-modulus divider 205 may be any value multi-modulus divider to generate a divided clock signal clk/N of any division ratio from the received clock signal clk. According to an embodiment of the present invention, the multi-modulus divider 205 may be further configured to receive a control signal ctrl to enable switching of parallel-to-serial conversion of multiple modes via a chip register (not shown) based on the received control signal ctrl. The principle of operation of the multi-modulus divider 205 will be described in detail below in conjunction with fig. 3 and 4.

As for the shift register 210, it can receive a plurality of data inputted in parallel and register in the shift register, and then shift-output the registered plurality of data as serial data according to a clock signal. For example, according to an embodiment of the present invention, the shift register 210 may be electrically connected to the multi-modulus divider 205, configured to receive parallel data to be converted and the divided clock signal clk/N, and to convert the parallel data into serial data according to the divided clock signal clk/N.

In some embodiments, the shift register 210 may include a plurality of shift registers to first convert a plurality of parallel data into odd-bit serial data and even-bit serial data, and then mix the odd-bit serial data and the even-bit serial data into a series of serial data (e.g., by the pre-driver 220). For example, as shown in FIG. 2, the shift register 210 includes a first shift register 210-1 and a second shift register 210-2. The first shift register 210-1 is configured to convert parallel data into odd-bit serial data according to the divided clock signal clk/N, and the second shift register 210-2 is configured to convert parallel data into even-bit serial data according to the divided clock signal clk/N. The operation of the shift register 210 will be described in detail with reference to fig. 5 and 6.

As described above, since the multi-modulus divider 205 can generate the divided clock signal clk/N of an arbitrary division ratio, the shift register 210 electrically connected to the multi-modulus divider 205 can automatically perform data conversion of different modes according to different divided clock signals clk/N. For example, when the divided clock signal clk/N is a divided clock signal with a division ratio of 1/4, the shift registers 210-1, 210-2 may convert 4-way parallel data into 1-way serial data; when the divided clock signal clk/N is a divided clock signal with a division ratio of 1/8, the shift registers 210-1, 210-2 may convert 8-way parallel data into 1-way serial data. Thus, the apparatus for parallel-to-serial conversion according to the embodiment of the present invention can realize support of any of a plurality of parallel-to-serial conversion modes.

Regarding the pre-driver 220, it may mix, for example, odd-bit data and even-bit data input in parallel to generate final serial data. For example, according to an embodiment of the present invention, the pre-driver 220 may be electrically connected to the shift register 210 and configured to receive and mix the odd-bit serial data and the even-bit serial data output by the shift register 210 to generate final serial data.

According to an embodiment of the present invention, the pre-driver 220 may also be configured to drive the equalization driver 230 and support an arbitrary order equalization function of the equalization driver 230 when driving the equalization driver 230. In an embodiment, the final serial data that the pre-driver 220 is configured to generate may include a plurality of serial data having a phase difference, for example, three data signals of the front-mark serial data, the main-mark serial data, and the rear-mark serial data, to drive the equalization driver 230 to perform the equalization function, and the pre-driver 220 may be further configured to adjust the order and coefficient of the front-mark serial data, the main-mark serial data, and the rear-mark serial data so that the equalization driver 230 may implement the equalization function to any degree. The operation principle of the pre-driver 220 will be described in detail with reference to fig. 7 and 8.

Regarding the equalization driver 230, it may perform an equalization function on serial data to compensate for channel impairments to the serial data to be output during transmission. For example, according to an embodiment of the present invention, the equalization driver 230 may be electrically connected with the pre-driver 220 and configured to receive serial data output by the pre-driver 220 to generate equalized serial data.

Fig. 3 shows an example circuit diagram of multi-modulus divider 205, according to an embodiment of the present invention. As shown in fig. 3, the multi-modulus divider 250 includes a plurality of divide-by-two frequency dividers 310-0, 310-1 through 310-n (which may be collectively referred to as divide-by-two frequency dividers 310) connected in series.

Regarding the divide-by-two or divide-by-three 310, it may divide the received clock signal by two or three. In some embodiments, divide-by-two 310 may include a plurality of latches and a plurality of logic gates, with the plurality of latches and the plurality of logic gates forming a loop. The circuit configuration and the operation principle of the divide-by-two/three frequency divider 310 will be described in detail with reference to fig. 4.

Fig. 4 shows an example circuit diagram of the divide-by-two 310 in fig. 3. As shown in fig. 4, the divide-by-two 310 may include 4

latches

410 and 3 logic gates 420.

In the divide-by-two-three frequency divider 310, F _in The port is a clock signal input of the divide-by-two-three divider 310, which may be configured to receive a clock signal (e.g., the clock signal clk in fig. 3 or a divided clock signal output by a previous divider); p-port and mod _in The ports together are configured to control the divide-by-two or divide-by-three 310.

Regarding the P-port, it may be configured to receive a control word P < n:0> as shown in FIG. 3, for example.

With respect to mod _in A port that may be configured to receive, for example, the one shown in fig. 3Control signal modi<n:0>。

For example, when the control signal modi < n:0> is modi=1 and the control word P < n:0> is p=0, the divide-by-two divider 310 divides the received clock signal by two. If the control signal mod i < n:0> is mod i=1 and the control word P < n:0> is p=1, the divide-by-three divider 310 divides the received clock signal by three. In yet another example, when the control signal mod < n:0> is mod i=1 and the control word P < n:0> is p=0, the divide-by-two frequency divider 310 divides the received clock signal by two.

Returning to fig. 3, by controlling each divide-by-two-three frequency divider 310, a multi-modulus frequency divider 205 consisting of n-stage divide-by-two-three frequency dividers 310 may be implemented as 2 ⁿ ～2 ⁽ⁿ⁺¹⁾ -frequency division of any consecutive integer between 1. In other words, the multi-modulus divider 205 may generate a division ratio of 2 for the received clock signal clk ⁿ ～2 ⁽ⁿ⁺¹⁾ -1 a divided clock signal of any integer between. I.e., divided clock signal clk/N as shown in FIG. 2, where N is 2 ⁿ ～2 ⁽ⁿ⁺¹⁾ -an integer between 1. In still other embodiments, the number of stages n of the divide-by-two and three divider 310 in the multi-modulus divider 250 may also be programmable such that the multi-modulus divider 250 may implement a divided clock signal of any division ratio.

Fig. 5 shows an exemplary circuit diagram of shift register 210 according to an embodiment of the invention. As shown in fig. 5, the shift register 210 includes a plurality of multiplexers 510 and a plurality of D flip-flops 520, wherein the number of multiplexers 510 is the same as the number of D flip-flops 520. For example, shift register 210 may include N multiplexers 510 and N D-flip-flops 520 to convert N parallel data into 1 serial data.

As shown in fig. 5, the shift register 210 may include a first port for receiving a load signal load and a second port for receiving a clock signal clk. The shift register 210 may further include an output port D for outputting serial data _out 。

Regarding the load signal load, it may be sent to the shift register 210 by, for example, the multi-modulus divider 205. When the load signal load is high, a plurality of data input in parallel are simultaneously loaded into a plurality of multiplexers 510 of the shift register 210. When the load signal load is low, the multiplexer 510 disconnects the plurality of data input in parallel from the D flip-flops 520, in which case all the D flip-flops 520 can be connected end to serially output the loaded plurality of data bit by bit according to the clock signal clk, thereby enabling the conversion of the plurality of data input in parallel into 1-way serial data.

With further reference to fig. 5, an example circuit diagram of a shift register (e.g., first shift register 210-1 of fig. 2) that converts parallel input data into odd-bit serial data is specifically shown. As shown in fig. 5, N pieces of input data (i.e., the input data in fig. 5<2N-1>Input data<2N-3>To input data<1>) Is input into the shift register 210. Specifically, the load signal load is controlled to be high so that the input data<2N-1>Input data<2N-3>To input data<1>Is simultaneously loaded into N multiplexers 510 in shift register 210. After the data loading is completed, the load signal load is controlled to be low level so that the loaded input data<2N-1>Input data<2N-3>To input data<1>From output port D according to clock signal clk _out Serial data is serially output as odd bits.

Fig. 6 shows a timing chart when the shift register 210 of fig. 5 performs parallel-to-serial conversion.

As shown in fig. 6, in the first clock cycle of the clock signal clk, the load signal load is high, and N input data, i.e., input data<2N-1>、<2N-3>、<2N-5>To the point of<1>Is simultaneously loaded into the shift register 210. After the first clock cycle of the clock signal clk, the load signal load remains low, and N input data loaded into the shift register 210 follows the clock cycle of the clock signal clk from the output port D _out And outputting bit by bit. Note that the shift register 210 serially outputs input data from low order to high order. For example, during the second clock cycle of the clock signal clk, the shift register 210 outputs and inputsData<1>The method comprises the steps of carrying out a first treatment on the surface of the In the third clock period of the clock signal clk, the shift register 210 outputs the input data<3>. And so on until all N input data are output.

In some embodiments, if all N input data are not all output from output port D _out The serial output, but the load signal load goes high again, in which case the data already loaded and not yet output in the shift register 210 will be overwritten by new input data. That is, each time the load signal load goes high, new input data may be loaded to the shift register 210 to be serially output. Therefore, by controlling the duty cycle of the load signal load, the shift register 210 can be made to realize parallel-to-serial conversion of different modes.

Fig. 7 shows an exemplary circuit diagram of the pre-driver 220 according to an embodiment of the present invention. According to an embodiment of the present invention, the pre-driver 220 may include a misalignment driving unit 702 and at least one phase delay driving unit 705.

Regarding the misalignment driving unit 702, it may be configured such that the received odd-bit serial data and even-bit serial data are misaligned by one unit data length UI in order to convert the odd-bit serial data and even-bit serial data into 1-way serial data, thereby generating final serial data.

According to an embodiment of the present invention, as shown in fig. 7, the misalignment driving unit 702 may include two first latches 710, a second latch 720, and a multiplexer set 730.

Regarding the first latch 710, it may be configured to receive and latch odd-bit serial data. As shown, two first latches 710 are connected in series, wherein the input of the previous first latch is for receiving odd serial data input to the pre-driver 220, the output of the previous first latch is electrically connected to the receiving of the next first latch, and the output of the next first latch is electrically connected to the first input of the multiplexer set 730.

Regarding the second latch 720, it may be configured to receive and latch even-bit serial data. As shown, an input of the second latch 720 is for receiving even bit serial data input to the pre-driver 220, and an output of the second latch 720 is electrically connected to a second input of the multiplexer set 730.

Further, in the misalignment driving unit 702 shown in fig. 7, the clock signal input of the previous first latch 710 is electrically connected to the clock signal input of the second latch 720.

Regarding the multiplexer set 730, it may be configured to convert odd-bit serial data and even-bit serial data into final serial data. For example, the multiplexer set 730 is configured to receive odd bit serial data from the next first latch 710 and even bit serial data from the second latch 720.

Thus, the bit shift driving unit 702 latches the received odd-bit serial data by using the two first latches 710 connected in series, and latches the received even-bit serial data by using one second latch 720, so that the odd-bit serial data and the even-bit serial data can be shifted by one unit data length UI and then input into the multiplexer set 730 for 2-way to 1-way parallel-serial conversion.

As for the phase delay driving unit 705, it may be configured to delay the generated final serial data by one unit data length UI. As shown in fig. 7, the pre-driver 220 may include a plurality of phase delay driving units 705, thus enabling the pre-driver 220 to output a plurality of serial data having a phase difference.

According to an embodiment of the present invention, as shown in fig. 7, the phase delay driving unit 705 may include a first latch 715, a second latch 725, and a multiplexer set 735.

Regarding the first latch 715, it may be configured to receive and latch odd-bit serial data. As shown, an input of a first latch 715 is electrically connected to an output of a previous first latch, and an output of the first latch 715 is electrically connected to a first input of a set of multiplexers 735. For example, the input of the first latch 715 may be electrically connected to the output of the first latch 715 in the previous phase delay drive unit 705 or to the output of the next first latch 710 in the previous misalignment drive unit 702.

With respect to the second latch 725, it may be configured to receive and latch even-bit serial data. As shown, an input of a second latch 725 is electrically connected to an output of a previous second latch, and an output of the second latch 725 is electrically connected to a second input of the multiplexer set 735. For example, an input of the second latch 725 may be electrically connected to an output of the second latch 725 of 705 in the previous phase delay drive unit (or the second latch 720 of the previous offset drive unit 702).

Further, in the phase delay driving unit 705 as shown in fig. 7, the clock signal input terminal of the first latch 715 is electrically connected to the clock signal input terminal of the second latch 725.

Regarding the multiplexer set 735, it may be configured to convert odd-bit serial data and even-bit serial data to final serial data. For example, the multiplexer set 735 is configured to receive odd serial data from the first latches 715 and even serial data from the second latches 725.

Thus, each phase delay driving unit 705 delays the data phase by one unit data length UI by adding one first latch 715 and one second latch 725 in the circuit, thereby delaying the generated final serial data by one unit data length UI. Accordingly, by including the misalignment driving unit 702 and the at least one phase delay driving unit 705 connected in series in the pre-driver 220, the final serial data generated by the pre-driver 220 may include a plurality of serial data having a phase difference.

Regarding the plurality of serial data having the phase difference, it may include a front-mark serial data, a main-mark serial data, and a rear-mark serial data, wherein the phase of the main-mark serial data lags the front-mark serial data, and the phase of the rear-mark serial data lags the main-mark serial data. As will be described in detail below in connection with fig. 8.

Fig. 8 shows a timing diagram of the pre-driver 220 according to an embodiment of the present invention.

As shown in fig. 8, the pre-driver 220 generates a plurality of serial data having a phase difference according to the clock signal clk based on the received odd-bit serial data and even-bit serial data. When it is determined that serial data of a certain specific phase is primary standard serial data, serial data of a phase leading the primary standard serial data may be regarded as leading standard serial data, and serial data of a phase lagging the primary standard serial data may be regarded as trailing standard serial data.

That is, returning to fig. 2, the pre-driver 220 in fig. 2 may be configured to generate the front-mark serial data, the rear-mark serial data, and the main-mark serial data to drive the equalization driver 230.

The equalization driver 230 shown in fig. 2 may then be configured to receive the pre-label serial data, the post-label serial data, and the main label serial data generated by the pre-driver 220, in accordance with an embodiment of the present invention; and equalizing the master serial data according to the order of the pre-label serial data and the order of the post-label serial data to generate equalized serial data.

Regarding the order of the preamble serial data, it may correspond to the number of serial data included in the preamble serial data. In one example, the determined master serial data is preceded by n serial data, i.e., n serial data phase-advanced from the master serial data, and the order of the preamble serial data is n. For example, if the main label serial data is preceded by 3 serial data, the order of the pre-label serial data is 3.

Regarding the order of the successor serial data, it may correspond to the number of serial data included in the successor serial data. In one example, the determined master serial data is followed by m serial data, i.e., m serial data phase-delayed from the master serial data, the order of the post serial data is m. For example, if the main label serial data is followed by 2 serial data, the order of the post label serial data is 2.

Referring back to fig. 7, since the final serial data generated by each driving unit (which may be regarded as each order) in the pre-driver 220 can push the multiplexer set, i.e., the plurality of multiplexers, in the driving unit, and each multiplexer is connected to one pin (leg) in the equalization driver 230, when the driving function of the equalization driver 230 is enabled, the coefficient h of the corresponding order can be changed by changing the number of multiplexers enabled in the multiplexer set. When a certain order is not required, the coefficient h corresponding to that order can be adjusted to h=0 by disabling all multiplexers in the corresponding multiplexer set.

From the above, the embodiment of the present invention realizes the equalization function supporting an arbitrary order when the equalization driver 230 is driven subsequently by determining the main-standard serial data among the plurality of serial data having the phase difference generated by the pre-driver 220 and accordingly determining the pre-standard serial data and the number thereof and the post-standard serial data and the number thereof. In addition, by adjusting the number of multiplexers enabled in the set of multiplexers for each drive unit in the pre-driver 220, an adjustment of the order coefficients can be achieved, thereby significantly increasing the adjustment space for the equalization function of the final serial data.

Fig. 9 shows a circuit schematic of a chip 900 according to an embodiment of the invention. Referring to fig. 9, a chip 900 includes a clock circuit 910 and a device 920 for parallel-to-serial conversion. The clock circuit 910 is electrically connected to the means 920 for parallel-to-serial conversion. In an embodiment of the present invention, the means 920 for parallel-to-serial conversion receives the clock signal clk from the clock circuit 910 to effect parallel-to-serial conversion of the input data. In one embodiment, clock circuit 910 may be, for example, a quartz crystal resonator, but the invention is not limited thereto. The apparatus 920 for parallel-to-serial conversion may be the apparatus 210 for parallel-to-serial conversion shown in fig. 2, and the detailed description thereof may refer to the descriptions of fig. 1 to 8, which are not repeated herein.

The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

The above is only an alternative embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An apparatus for parallel-to-serial conversion, comprising:

a multi-modulus divider configured to receive a clock signal and generate a divided clock signal of any division ratio from the received clock signal;

a shift register electrically connected to the multi-modulus divider, configured to receive parallel data to be converted and the frequency-divided clock signal, and to convert the parallel data into odd-bit serial data and even-bit serial data according to the frequency-divided clock signal; and

and a pre-driver, electrically connected to the shift register, configured to receive and mix the odd-bit serial data and the even-bit serial data to generate final serial data.

2. The apparatus of claim 1, wherein the multi-modulus divider is further configured to receive a control signal to enable switching of multiple modes of parallel-to-serial conversion based on the received control signal.

3. The apparatus of claim 1, wherein the shift register comprises a first shift register configured to convert the parallel data into the odd-bit serial data according to the divided clock signal and a second shift register configured to convert the parallel data into the even-bit serial data according to the divided clock signal.

4. The apparatus of claim 1, wherein the pre-driver comprises:

a misalignment driving unit configured to stagger the odd-bit serial data and the even-bit serial data by one unit data length so as to generate the final serial data; and

at least one phase delay driving unit, each configured to delay the generated final serial data by one unit data length.

5. The apparatus of claim 4, wherein the misalignment driving unit comprises:

a multiplexer set configured to convert the odd-bit serial data and the even-bit serial data into the final serial data;

two first latches configured to receive and latch the odd-bit serial data, wherein an output of a previous first latch is electrically connected to a receiving of a subsequent first latch, an output of the subsequent first latch being electrically connected to a first input of the set of multiplexers; and

and a second latch configured to receive and latch the even bit serial data, wherein an output of the second latch is electrically connected to a second input of the set of multiplexers.

6. The apparatus of claim 5, wherein the clock signal input of the previous first latch is electrically connected to the clock signal input of the second latch.

7. The apparatus of claim 4, wherein the phase delay driving unit comprises:

a first latch configured to receive and latch the odd-bit serial data, wherein an input of the first latch is electrically connected to an output of a first latch in a previous phase delay drive unit or to an output of a subsequent first latch in a dislocation drive unit, the output of the first latch being electrically connected to a first input of the set of multiplexers; and

and a second latch configured to receive and latch the even bit serial data, wherein an input of the second latch is electrically connected to an output of a second latch in a previous phase delay driving unit or a dislocation driving unit, and an output of the second latch is electrically connected to a second input of the multiplexer set.

8. The apparatus of claim 7, wherein the clock signal input of the first latch is electrically connected to the clock signal input of the second latch.

9. The apparatus of claim 4, wherein the final serial data output by the pre-driver comprises a plurality of serial data having a phase difference, the plurality of serial data having a phase difference comprising:

leading serial data;

main standard serial data, wherein the phase of the main standard serial data lags behind the front standard serial data; and

and the post-label serial data is delayed in phase with the main-label serial data.

10. The apparatus as recited in claim 9, further comprising:

an equalization driver, electrically connected to the pre-driver, is configured to receive the final serial data output by the pre-driver to generate equalized serial data.

11. The apparatus of claim 10, wherein the equalization driver is configured to:

receiving the pre-label serial data, the post-label serial data and the main label serial data generated by the pre-driver; and

and equalizing the main standard serial data according to the order of the front standard serial data and the order of the rear standard serial data to generate the equalized output data.

12. A chip, comprising:

a clock circuit for outputting a clock signal; and

the apparatus for parallel-to-serial conversion according to any one of claims 1-11, the apparatus for parallel-to-serial conversion being electrically connected to the clock circuit.