CN116436452A - Maximum voltage selection circuit - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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Abstract
The invention discloses a maximum voltage selection circuit which comprises a voltage detection module, an enabling control module, an output module and at least one current source. The voltage detection module is used for generating a detection signal according to a first input voltage and a second input voltage, the output module is used for providing an output voltage according to the state of the detection signal, the detection signal in the first state is used for generating the output voltage according to the first input voltage, the output voltage is generated according to the detection signal in the second state, the enabling control module is connected between the voltage detection module and the at least one current source, and the enabling control module is used for controlling the on-off of a current path between the voltage detection module and the at least one current source according to an enabling signal. The maximum voltage selection circuit can ensure normal voltage selection function and greatly reduce static power consumption of the circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly to a maximum voltage selection circuit.
Background
At present, with the rapid development of semiconductor technology, the use of integrated circuits has spread throughout various fields, and in particular, for power control type switching circuits (such as DC-DC circuits and miniaturized switching power circuits), the integrated circuits have been widely used in the fields of power electronics, scientific research, industrial control equipment, communication equipment, instruments, switching equipment, access equipment, mobile communication, router communication, industrial control, automotive electronics, aerospace, and the like.
In the switching power supply chip, it is necessary to compare the voltage values of the two voltages in some cases and output the comparison result for the relevant logic judgment. Taking a buck-boost converter as an example, when the input voltage Vin is greater than the output voltage Vout, the circuit needs to connect the driving power supply of the power tube in the boost switching circuit to the input voltage Vin; when the input voltage Vin is smaller than the output voltage Vout, the circuit needs to connect the driving power supply of the power transistor in the step-up switching circuit to the output voltage Vout. Therefore, a voltage comparison circuit (or referred to as a maximum voltage selection circuit) is required to be disposed in the buck-boost converter to determine the maximum voltage between the input voltage Vin and the output voltage Vout, but the conventional voltage selection circuit cannot adjust its own power consumption according to the operating state of the buck-boost converter, which may cause an increase in static power consumption of the circuit, and is not beneficial to implementation of a low-power-consumption and high-precision switching power supply chip.
Fig. 1 is a schematic diagram showing a circuit configuration of a conventional maximum voltage selection circuit. As shown in fig. 1, a conventional maximum voltage selection circuit 100 includes a voltage detection circuit 110 and an output circuit 120. The voltage detection circuit 110 includes resistors R0 to R2, PMOS transistors Mp1 to Mp3, NMOS transistors Mn2 to Mn4, and a switch K1. The resistor R0 and the NMOS transistor Mn2 are connected in series between the first input voltage Vin1 and ground, and the gate and drain of the NMOS transistor Mn2 are shorted. The resistor R1, the PMOS transistor Mp1, and the NMOS transistor Mn4 are connected in series between the second input voltage Vin2 and ground, the gate and the drain of the PMOS transistor Mp1 are shorted, and the gate of the NMOS transistor Mn4 and the gate of the NMOS transistor Mn2 are connected together. The resistor R2, the PMOS transistor Mp2, and the NMOS transistor Mn3 are connected in series between the first input voltage Vin1 and the ground, the gate of the PMOS transistor Mp2 is connected to the gate of the PMOS transistor Mp1, the gate of the NMOS transistor Mn3 is connected to the gate of the NMOS transistor Mn2, and the node 101 between the PMOS transistor Mp2 and the NMOS transistor Mn3 is the output of the voltage detection circuit 110. The PMOS transistor Mp3 and the switch K1 are connected in series between both ends of the PMOS transistor Mp 2. The output circuit 120 includes PMOS transistors Mp4 to Mp5 and inverters INV1 to INV3. The source of the PMOS transistor Mp4 is configured to receive the first input voltage Vin1, the drain is connected to the output terminal of the output voltage Vmax, the source of the PMOS transistor Mp5 is configured to receive the second input voltage Vin2, the drain is connected to the output terminal of the output voltage Vmax, the inverter INV1 is connected between the node 101 and the gate of the PMOS transistor Mp4, and the inverters INV2 and INV3 are serially connected between the node 101 and the gate of the PMOS transistor Mp 5.
In the conventional maximum voltage selection circuit 100, the circuit power consumption is fixed, and when the system circuit is switched to the low power consumption mode, the maximum voltage selection circuit 100 still consumes part of the quiescent current, so that the quiescent power consumption of the circuit is increased, which is unfavorable for realizing the low power consumption and high precision switching power supply chip.
Disclosure of Invention
In view of the above, the present invention is directed to a maximum voltage selection circuit, which can adjust the power consumption of the circuit according to the operation mode of the system circuit, and is beneficial to reducing the static power consumption of the circuit.
According to an embodiment of the present invention, there is provided a maximum voltage selection circuit including: at least one first current source; the voltage detection module is used for generating a detection signal according to the first input voltage and the second input voltage; and an output module for providing an output voltage according to a state of the detection signal, and generating the output voltage according to the first input voltage in response to the detection signal of a first state, and generating the output voltage according to the second input voltage in response to the detection signal of a second state, wherein the maximum voltage selection circuit further includes: and the enabling control module is connected between the voltage detection module and the at least one first current source and is configured to control the on-off of a current path between the voltage detection module and the at least one first current source according to an enabling signal.
Optionally, the detection signals include a first detection signal and a second detection signal, the first state of the detection signals is that the first detection signal is at a low level, the second detection signal is at a high level, the second state of the detection signals is that the first detection signal is at a high level, and the second detection signal is at a low level.
Optionally, the voltage detection module includes: the first detection module is used for outputting the first detection signal at a first node according to the first input voltage and the second input voltage; and a second detection module for outputting the second detection signal at a second node according to the first input voltage and the second input voltage.
Optionally, the first detection module includes: a first resistor, wherein a first end of the first resistor is connected with the first input voltage; a first transistor, wherein a first end of the first transistor is connected with a second end of the first resistor, and a control end and a second end of the first transistor are in short circuit; a second resistor connected between the first terminal and the control terminal of the first transistor; a third resistor connected between the second terminal of the first transistor and the enable control module; a fourth resistor, wherein a first end of the fourth resistor is connected with the second input voltage; and a second transistor, a first end of the second transistor is connected with a second end of the fourth resistor, a control end of the second transistor is connected with a control end of the first transistor, and a second end of the second transistor is connected with the first node.
Optionally, the second detection module includes: a fifth resistor, wherein a first end of the fifth resistor is connected with the first input voltage; a third transistor, a first end of which is connected to the second end of the fifth resistor, and a second end of which is connected to the second node; a sixth resistor, wherein a first end of the sixth resistor is connected with the second input voltage; a first end of the fourth transistor is connected with the second end of the sixth resistor, and a control end and a second end of the fourth transistor are in short circuit and are connected with the control end of the third transistor; a seventh resistor connected between the first terminal and the control terminal of the fourth transistor; and an eighth resistor connected between the second terminal of the fourth transistor and the enable control module.
Optionally, the number of the at least one first current source is two, and the enabling control module includes: a fifth transistor connected between the second terminal of the third resistor and one of the two first current sources; a ninth resistor and a sixth transistor connected in series between the first node and a fourth node; a tenth resistor connected in parallel between both ends of the sixth transistor; an eleventh resistor and a seventh transistor connected in series between the second node and a third node; a twelfth resistor connected between both ends of the seventh transistor; and an eighth transistor connected between a second terminal of the eighth resistor and the other of the two first current sources, wherein control terminals of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are configured to receive the enable signal.
Optionally, the output module includes: a first power switch configured to generate the output voltage from the first input voltage in response to a state of the first detection signal; and a second power switch configured to generate the output voltage from the second input voltage in response to a state of the second detection signal.
Optionally, the maximum voltage selection circuit further includes: the input end of the first level conversion module is used for receiving the first detection signal and generating a first driving voltage applied to the control end of the first power switch according to the first detection signal; and the input end of the second level conversion module is used for receiving the second detection signal and generating a second driving voltage applied to the control end of the second power switch according to the second detection signal.
Optionally, the output end of the first level conversion module is further connected to the third node, and the output end of the second level conversion module is further connected to the fourth node, so as to form a negative feedback loop.
Optionally, the first level conversion module and the second level conversion module are implemented through an inverter, and the voltage domain of the first driving voltage is a first input voltage to ground, and the voltage domain of the second driving voltage is a second input voltage to ground.
Optionally, each power switch further comprises a logic module, and the control terminal of the power switch receives the corresponding driving voltage via the logic module.
Optionally, the logic module includes an inverter.
Optionally, the maximum voltage selection circuit further includes a plurality of hysteresis modules, each hysteresis module is parallel-connected with the corresponding first current source, and each hysteresis module is configured to provide a hysteresis current at a parallel node of the corresponding first current source according to the corresponding first detection signal or second detection signal.
Optionally, each hysteresis module includes: and a ninth transistor and a second current source, which are connected in series between the parallel node of the corresponding first current source and the ground, wherein the control end of the ninth transistor is used for receiving the corresponding first detection signal or second detection signal.
The maximum voltage selection circuit comprises a voltage detection module, an enabling control module, an output module and at least one current source. The voltage detection module is used for generating a detection signal according to a first input voltage and a second input voltage, the output module is used for providing an output voltage according to the state of the detection signal, the detection signal in the first state is used for generating the output voltage according to the first input voltage, the output voltage is generated according to the detection signal in the second state, the enabling control module is connected between the voltage detection module and the at least one current source, and the enabling control module is used for controlling the on-off of a current path between the voltage detection module and the at least one current source according to an enabling signal. When the system is in a low power consumption mode, the enabling control module cuts off a current path between the voltage detection module and at least one current source according to a corresponding enabling signal, so that the static current in the maximum voltage selection circuit is equal to 0, partial power consumption can only occur to the circuit during turning, and the circuit does not consume current after turning is completed. Compared with the traditional maximum voltage selection circuit, the maximum voltage selection circuit can ensure the normal voltage selection function, simultaneously greatly reduce the static power consumption of the circuit and is beneficial to the realization of a low-power consumption switching power supply chip.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram showing a circuit configuration of a conventional maximum voltage selection circuit.
Fig. 2 shows a circuit configuration diagram of a maximum voltage selection circuit according to an embodiment of the present invention.
Fig. 3a and 3b show two operation waveforms of the maximum voltage selection circuit according to the embodiment of the present invention, respectively.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "coupled to" another element or element/circuit is "coupled between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly coupled to" another element, it means that there are no intervening elements present between the two.
In this application, the MOS transistor includes a first terminal, a second terminal, and a control terminal, and in an on state of the MOS transistor, a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the PMOS transistor are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the NMOS transistor are respectively a drain electrode, a source electrode and a grid electrode.
Fig. 2 shows a circuit configuration diagram of a maximum voltage selection circuit 200 according to an embodiment of the present invention. As shown in fig. 2, the maximum voltage selection circuit 200 of the present embodiment includes a voltage detection module 210, an enable control module 220, an output module 250, and current sources 231 and 232. The current sources 231 and 232 are used to provide bias current to the voltage detection module 210. Among them, since the bias currents supplied by the current sources 231 and 232 are equal in magnitude, the current sources 231 and 232 are collectively referred to as "first current sources" in other descriptions herein. Of course, the present invention is not limited to the number of first current sources, and in other embodiments, 1 first current source or other numbers of first current sources may be used to provide bias current to the voltage detection module 210.
The voltage detection module 210 is configured to receive a first input voltage Vin1 and a second input voltage Vin2, and generate a detection signal according to the first input voltage Vin1 and the second input voltage Vin2. In an exemplary embodiment, the detection signals include a detection signal Va and a detection signal Vb, and the voltage detection module 210 further includes a detection module 211 and a detection module 212, where the detection module 211 is configured to provide the detection signal Va at the node a according to the first input voltage Vin1 and the second input voltage Vin2, and the detection module 212 is configured to provide the detection signal Vb at the node B according to the first input voltage Vin1 and the second input voltage Vin2. In response to a result of comparison between the first input voltage Vin1 and the second input voltage Vin2, the detection signal Va and the detection signal Vb have opposite potentials.
The output module 250 is configured to provide an output voltage Vmax based on a state of a detection signal output by the voltage detection module 210, and to generate the output voltage Vmax from the first input voltage Vin1 in response to the detection signal of a first state, and to generate the output voltage Vmax from the second input voltage Vin2 in response to the detection signal of a second state. For example, the first state of the detection signal is that the detection signal Va is at a low level and the detection signal Vb is at a high level; the second state of the detection signal is that the detection signal Va is high level and the detection signal Vb is low level.
The enabling control module 220 is connected between the voltage detection module 210 and the at least one first current source, and is configured to control the on-off of a current path between the voltage detection module 210 and the at least one first current source according to an enabling signal Vs, so that the power consumption of the maximum voltage selection circuit 200 can be adjusted according to the operation mode of the system. For example, the enabling control module 220 is configured to disconnect the current path between the voltage detection module 210 and the at least one first current source when the system is in the low power consumption mode, in turn reducing the static power consumption of the maximum voltage selection circuit 200.
In an exemplary embodiment, the detection module 211 includes resistors R0, R1, R5, R6 and transistors M0 and M1. The transistors M0 and M1 are PMOS transistors. The first end of the resistor R0 is connected to the first input voltage Vin1, the second end of the resistor R0 is connected to the source of the transistor M0 and the first end of the resistor R5, the second end of the resistor R5 is connected to the gate of the transistor M0, the gate and the drain of the transistor M0 are shorted, the shorting point is a node E, the first end of the resistor R6 is connected to the drain of the transistor M0, and the second end of the resistor R6 is connected to the current source 231 through the enable control module 220. The resistor R1 has a first end connected to the second input voltage Vin2, a second end connected to the source of the transistor M1, a gate of the transistor M1 connected to the node E, and a drain of the transistor M1 connected to the node a for outputting the detection signal Va.
Likewise, the detection module 212 includes resistors R2, R3, R4, R7 and transistors M2 and M3. The transistors M2 and M3 are PMOS transistors. A first terminal of the resistor R2 is connected to the first input voltage Vin1, a second terminal of the resistor R2 is connected to a source of the transistor M2, and a drain of the transistor M2 is connected to the node B for outputting the detection signal Vb. The first end of the resistor R3 is connected to the second input voltage Vin2, the second end of the resistor R3 is connected to the first end of the resistor R4 and the source of the transistor M3, the second end of the resistor R4 is connected to the gate of the transistor M3, the gate of the transistor M3 is shorted to the drain, the short junction is the node F, the gate of the transistor M2 is also connected to the node F, the first end of the resistor R7 is connected to the drain of the transistor M3, and the second end of the resistor R7 is connected to the current source 232 via the enable control module 220.
For example, the enable control module 220 includes transistors M4, M5, M6, M7 and resistors R8, R9, R10, R11. The transistors M4, M5, M6, M7 are NMOS transistors. The transistor M5 is connected between the second end of the resistor R6 and the current source 231, the drain of the transistor M5 is connected to the second end of the resistor R6, and the source of the transistor M5 is connected to the current source 231. Resistor R8 and transistor M6 are connected in series between node a and node D, with a first end of resistor R8 connected to node a, a second end of resistor R8 connected to the drain of transistor M6, a source of transistor M6 connected to node D, and resistor R11 connected between the drain and source of transistor M6. Resistor R9 and transistor M7 are connected in series between node B and node C, wherein a first terminal of resistor R9 is connected to node B, a second terminal of resistor R8 is connected to the drain of transistor M7, the source of transistor M7 is connected to node C, and resistor R10 is connected between the drain and source of transistor M7. The transistor M4 is connected to the second terminal of the resistor R7 and the current source 232, wherein the drain of the transistor M4 is connected to the second terminal of the resistor R7, and the source of the transistor M4 is connected to the current source 232. Further, the gates of the transistors M4, M5, M6, M7 are used to receive the enable signal Vs, and the transistors M4, M5, M6, M7 are turned on or off in response to the level state of the enable signal Vs.
Further, the output module 250 of the present embodiment includes two power switches Mp0 and Mp1, the power switch Mp0 is configured to generate the output voltage Vmax according to the first input voltage Vin1 in response to the state of the detection signal Va, and the power switch Mp1 is configured to generate the output voltage Vmax according to the second input voltage Vin2 in response to the state of the detection signal Vb. The power switches Mp0 and Mp1 are for example implemented by PMOS transistors, the source of the transistor Mp0 being arranged to receive said first input voltage Vin1, the drain of the transistor Mp0 being connected to an output terminal providing said output voltage Vmax, the source of the transistor Mp1 being arranged to receive said second input voltage Vin2, the drain of the transistor Mp1 being connected to an output terminal providing said output voltage Vmax.
Further, the maximum voltage selection circuit 200 of the present embodiment further includes a level conversion module 241 and a level conversion module 242. The input terminal of the level conversion module 241 is configured to receive the detection signal Va, and generate a driving voltage Vc for applying to the gate of the power switch Mp0 according to the detection signal Va. An input terminal of the level conversion module 241 is configured to receive the detection signal Vb and generate a driving voltage Vd for being applied to the gate of the power switch Mp1 according to the detection signal Vb. For example, the level conversion modules 241 and 242 may be implemented by inverters, and the output terminal of the level conversion module 241 may be further connected to the node C to form a negative feedback loop with the node B, and the output terminal of the level conversion module 242 may be further connected to the node D to form a negative feedback loop with the node a, so that the pull-down of the node B and the node a may be accelerated by the negative feedback control of the level conversion modules 241 and 242, respectively.
As shown in fig. 2, the level conversion module 241 includes a PMOS transistor M10 and an NMOS transistor M11 connected in series between the first input voltage Vin1 and ground, gates of the PMOS transistor M10 and the NMOS transistor M11 are used for receiving the detection signal Va, and drain connection points of the PMOS transistor M10 and the NMOS transistor M11 are used for outputting the driving voltage Vc. The level conversion module 242 includes a PMOS transistor M8 and an NMOS transistor M9 connected in series between the second input voltage Vin2 and ground, gates of the PMOS transistor M8 and the NMOS transistor M9 are used for receiving the detection signal Vb, and drain connection points of the PMOS transistor M8 and the NMOS transistor M9 are used for outputting the driving voltage Vd.
Further, the power switches Mp0 and Mp1 in the output module 250 of the present embodiment further include logic modules 251 and 252 corresponding thereto. The gate of the power switch Mp0 receives the corresponding driving voltage Vc via the logic module 251, and the gate of the power switch Mp1 receives the corresponding driving voltage Vd via the logic module 252. By way of example, logic blocks 251 and 252 may be implemented by inverters.
Further, the maximum voltage selection circuit 200 of the present embodiment further includes a plurality of hysteresis modules 261 and 262. Each hysteresis module is arranged in parallel with the corresponding first current source, and each hysteresis module is used for providing hysteresis current at a parallel node of the corresponding first current source according to the corresponding detection signal Va or Vb. As shown in fig. 2, a hysteresis module 261 is disposed in parallel with the current source 231, and the hysteresis module 261 is configured to provide a hysteresis current at a parallel node according to the detection signal Va. The hysteresis module 162 is arranged in parallel with the current source 232, and the hysteresis module 261 is configured to provide a hysteresis current at the parallel node according to the detection signal Vb.
Further, the hysteresis module 261 includes a transistor M12 and a current source 201, wherein the transistor M12 is implemented by an NMOS transistor, a drain of the transistor M12 is connected to a first terminal of the current source 231, a gate of the transistor M12 is connected to the node a to receive the detection signal Va, a source of the transistor M12 is connected to the first terminal of the current source 201, and a second terminal of the current source 201 is grounded. The hysteresis module 262 includes a transistor M13 and a current source 202, wherein the transistor M13 is implemented by an NMOS transistor, a drain of the transistor M13 is connected to a first terminal of the current source 232, a gate of the transistor M13 is connected to the node B to receive the detection signal Vb, a source of the transistor M13 is connected to a first terminal of the current source 202, and a second terminal of the current source 202 is grounded. In the present embodiment, since the hysteresis currents provided by the current sources 201 and 202 are equal in magnitude, the current sources 201 and 202 are collectively referred to as "second current sources" in other descriptions herein. In addition, the magnitude relation between the hysteresis current provided by the second current source and the bias current provided by the first current source is not limited, and the hysteresis current and the bias current may be equal or unequal.
Fig. 3a and 3b show two operation waveforms of the maximum voltage selection circuit according to the embodiment of the present invention, respectively. Fig. 3a shows a waveform diagram of the variation of the output voltage Vmax in the process of the second input voltage Vin2 rising from 0 when the first input voltage Vin1 is unchanged, and fig. 3b shows a waveform diagram of the variation of the output voltage Vmax in the process of the second input voltage Vin2 falling from the power supply voltage when the first input voltage Vin1 is unchanged. In an exemplary implementation, the maximum voltage selection circuit 200 of the present embodiment may be applied to a switching converter, where the first input voltage Vin1 and the second input voltage Vin2 correspond to an input voltage and an output voltage of the switching converter, respectively.
When the switching converter is under heavy load, the quiescent current of the maximum voltage selection circuit 200 is negligible with respect to the load, and has little effect on the efficiency, and the NMOS transistors M4, M5, M6, M7 in the enable control module 220 are turned on when the enable signal Vs is at a high level, and the maximum voltage selection circuit 200 of the present embodiment operates in the high current mode, and the operation principle of the maximum voltage selection circuit 200 of the present embodiment is described below with reference to fig. 3 a.
When the first input voltage Vin1 is unchanged and the second input voltage Vin2 starts rising from 0, since the second input voltage Vin2 is lower than the first input voltage Vin1, the PMOS transistor M1 is turned off, the PMOS transistor M2 is turned on, the node B is pulled up to the potential of the first input voltage Vin1 by the PMOS transistor M2, the node a is pulled down to the low potential by the NMOS transistor M6, the detection signal Va is at the low level, the detection signal Vb is at the high level, the NMOS transistor M9 in the level conversion module 242 is turned on, the PMOS transistor M8 is turned off, the driving voltage Vd is pulled down to the low level, the PMOS transistor M10 in the level conversion module 241 is turned on, the NMOS transistor M11 is turned off, the driving voltage Vc is pulled up to be equal to the first input voltage Vin1 (i.e., the high level), the power switch Mp0 in the output module 250 is turned off, and the output voltage Vmax is equal to the first input voltage Vin1. Along with the rising of the second input voltage Vin2, when the second input voltage Vin2 exceeds the first input voltage Vin1, the PMOS transistor M1 starts to be turned on, the PMOS transistor M2 is turned off, the node a is pulled high, the node B is pulled low, then the NMOS transistor M11 in the level conversion module 241 is turned on, the PMOS transistor M10 is turned off, the driving voltage Vc is at a low level, the PMOS transistor M8 in the level conversion module 242 is turned on, the NMOS transistor M9 is turned off, the driving voltage Vd is pulled high to be equal to the second input voltage Vin2 (i.e., at a high level), the power switch Mp0 in the final output module 250 is turned off, the power switch Mp1 is turned on, and the output voltage Vmax is equal to the second input voltage Vin2.
As can be seen from the above description, in the process that the first input voltage Vin1 is unchanged and the second input voltage Vin2 rises from 0, the inversion threshold of the maximum voltage selection circuit 200 of the present embodiment is:
where Ibias represents the bias current supplied by the current source 231, vth_m11 represents the on threshold of the NMOS transistor M11, and when the detection signal va=vth_m11, the output voltage Vmax of the maximum voltage selection circuit 200 is switched from the first input voltage Vin1 to the second input voltage Vin2. By way of example, the resistance values of the resistor R9 and the resistor R8 in the maximum voltage selection circuit 200 are equal, the resistance value of the resistor R0 and the resistance value of the resistor R3 are equal, and the resistance value of the resistor R2 and the resistance value of the resistor R1 are equal, so that the flip threshold of the maximum voltage selection circuit 200 can be set by adjusting the resistance values of the resistors R0, R1, and R8.
Similarly, when the second input voltage Vin2 is unchanged and the first input voltage Vin1 starts to rise from 0, the inversion threshold of the maximum voltage selection circuit 200 of the present embodiment is:
where vth_m9 represents the on threshold of the NMOS transistor M9, and when the detection signal vb=vth_m9, the output voltage Vmax of the maximum voltage selection circuit 200 is switched from the second input voltage Vin2 to the first input voltage Vin1.
When the switching converter is in light load, in order to reduce the power consumption of the circuit, the switching converter is in sleep mode, the enable signal Vs is at low level, and the NMOS transistors M4, M5, M6, M7 in the enable control module 220 are turned off, under which condition the maximum voltage selection circuit 200 of the present embodiment operates in the small current mode, and the operation principle of the maximum voltage selection circuit 200 of the present embodiment is described with reference to fig. 3 a.
When the NMOS transistors M4, M5, M6, M7 are turned off, the voltage of the node E in the detection module 211 is equal to the first input voltage Vin1, and the voltage of the node F in the detection module 212 is equal to the second input voltage Vin2. When the first input voltage Vin1 is unchanged and the second input voltage Vin2 starts rising from 0, the PMOS transistor M1 is turned off, the PMOS transistor M2 is turned on, the node B is pulled up to a high potential by the PMOS transistor M2, the NMOS transistor M9 in the level conversion module 242 is turned on, the PMOS transistor M8 is turned off, and the driving voltage Vd is pulled down to a low level because the second input voltage Vin2 is smaller than the first input voltage Vin1. And node D is also low, node a is pulled low due to the presence of the negative feedback loop, i.e. the detection signal Va is low, the PMOS transistor M10 in the level conversion module 241 is turned on, the NMOS transistor M11 is turned off, the driving voltage Vc is pulled high equal to the first input voltage Vin1 (i.e. high), the power switch Mp0 in the output module 250 is turned on, the power switch Mp1 is turned off, and the output voltage Vmax is equal to the first input voltage Vin1. Meanwhile, since the potential of the node C is equal to the first input voltage Vin1, the current in the PMOS transistor M2 is equal to 0, i.e., the circuit has no power consumption at this time. Along with the rising of the second input voltage Vin2, when the second input voltage Vin2 exceeds the first input voltage Vin1, the PMOS transistor M1 starts to be turned on, the PMOS transistor M2 is turned off, the node a is pulled high, the NMOS transistor M11 in the level conversion module 241 is turned on, the PMOS transistor M10 is turned off, and the driving voltage Vc is at a low level. And node C is also pulled low, node B is also pulled low due to the presence of the negative feedback loop, and then PMOS transistor M8 in level shift module 242 is turned on, NMOS transistor M9 is turned off, driving voltage Vd is pulled high equal to second input voltage Vin2 (i.e., high level), and finally power switch Mp0 in output module 250 is turned off, power switch Mp1 is turned on, and output voltage Vmax is equal to second input voltage Vin2. Meanwhile, since the voltage of the node D is equal to the second input voltage Vin2, the current in the PMOS transistor M1 is equal to 0. Wherein, when the enable signal Vs is at a low level, the flip threshold of the maximum voltage selection circuit 200 is:
max(Vin2,Vin1)―Vth_M1＝min(Vin2,Vin1)
wherein vth_m1 represents the on threshold of the PMOS transistor M1, i.e., when the maximum voltage between the first input voltage Vin1 and the second input voltage Vin2 minus the on threshold of the PMOS transistor M1 is equal to the minimum voltage between the first input voltage Vin1 and the second input voltage Vin2, the output voltage Vmax of the maximum voltage selection circuit 200 is switched from the first input voltage Vin1 to the second input voltage Vin2.
As can be seen from the above description, when the enable signal Vs is at a low level, the quiescent current in the maximum voltage selection circuit 200 of the present embodiment is equal to 0, only when the circuit is turned over, the circuit consumes no more current after the turn over is completed, so that the power consumption of the circuit can be greatly reduced compared with the conventional maximum voltage selection circuit, which is beneficial to the implementation of the low-power switching power supply chip.
In summary, the maximum voltage selection circuit according to the embodiments of the present invention includes a voltage detection module, an enable control module, an output module, and at least one current source. The voltage detection module is used for generating a detection signal according to a first input voltage and a second input voltage, the output module is used for providing an output voltage according to the state of the detection signal, the detection signal in the first state is used for generating the output voltage according to the first input voltage, the output voltage is generated according to the detection signal in the second state, the enabling control module is connected between the voltage detection module and the at least one current source, and the enabling control module is used for controlling the on-off of a current path between the voltage detection module and the at least one current source according to an enabling signal. When the system is in a low power consumption mode, the enabling control module cuts off a current path between the voltage detection module and at least one current source according to a corresponding enabling signal, so that the static current in the maximum voltage selection circuit is equal to 0, partial power consumption can only occur to the circuit during turning, and the circuit does not consume current after turning is completed. Compared with the traditional maximum voltage selection circuit, the maximum voltage selection circuit can ensure the normal voltage selection function, simultaneously greatly reduce the static power consumption of the circuit and is beneficial to the realization of a low-power consumption switching power supply chip.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A maximum voltage selection circuit, comprising:
at least one first current source;
the voltage detection module is used for generating a detection signal according to the first input voltage and the second input voltage; and
an output module for providing an output voltage in accordance with the state of the detection signal, and generating the output voltage in accordance with the first input voltage in response to the detection signal of a first state, generating the output voltage in accordance with the second input voltage in response to the detection signal of a second state,
wherein the maximum voltage selection circuit further comprises:
and the enabling control module is connected between the voltage detection module and the at least one first current source and is configured to control the on-off of a current path between the voltage detection module and the at least one first current source according to an enabling signal.
2. The maximum voltage selection circuit of claim 1, wherein the detection signal comprises a first detection signal and a second detection signal, the voltage detection module comprising:
the first detection module is used for outputting the first detection signal at a first node according to the first input voltage and the second input voltage; and
a second detection module for outputting the second detection signal at a second node according to the first input voltage and the second input voltage,
the first state of the detection signal is that the first detection signal is at a low level, and the second detection signal is at a high level, and the second state of the detection signal is that the first detection signal is at a high level, and the second detection signal is at a low level.
3. The maximum voltage selection circuit of claim 2, wherein the first detection module comprises:
a first resistor, wherein a first end of the first resistor is connected with the first input voltage;
a first transistor, wherein a first end of the first transistor is connected with a second end of the first resistor, and a control end and a second end of the first transistor are in short circuit;
a second resistor connected between the first terminal and the control terminal of the first transistor;
a third resistor connected between the second terminal of the first transistor and the enable control module;
a fourth resistor, wherein a first end of the fourth resistor is connected with the second input voltage; and
a second transistor, a first end of the second transistor is connected with a second end of the fourth resistor, a control end of the second transistor is connected with a control end of the first transistor, a second end of the second transistor is connected with the first node,
the second detection module includes:
a fifth resistor, wherein a first end of the fifth resistor is connected with the first input voltage;
a third transistor, a first end of which is connected to the second end of the fifth resistor, and a second end of which is connected to the second node;
a sixth resistor, wherein a first end of the sixth resistor is connected with the second input voltage;
a first end of the fourth transistor is connected with the second end of the sixth resistor, and a control end and a second end of the fourth transistor are in short circuit and are connected with the control end of the third transistor;
a seventh resistor connected between the first terminal and the control terminal of the fourth transistor; and
and the eighth resistor is connected between the second end of the fourth transistor and the enabling control module.
4. The maximum voltage selection circuit of claim 3, wherein the number of the at least one first current source is two, the enable control module comprising:
a fifth transistor connected between the second terminal of the third resistor and one of the two first current sources;
a ninth resistor and a sixth transistor connected in series between the first node and a fourth node;
a tenth resistor connected in parallel between both ends of the sixth transistor;
an eleventh resistor and a seventh transistor connected in series between the second node and a third node;
a twelfth resistor connected between both ends of the seventh transistor; and
an eighth transistor connected between the second terminal of the eighth resistor and the other of the two first current sources,
the control ends of the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are used for receiving the enabling signal.
5. The maximum voltage selection circuit of claim 4, wherein the output module comprises:
a first power switch configured to generate the output voltage from the first input voltage in response to a state of the first detection signal; and
a second power switch configured to generate the output voltage from the second input voltage in response to a state of the second detection signal.
6. The maximum voltage selection circuit of claim 5, further comprising:
the input end of the first level conversion module is used for receiving the first detection signal and generating a first driving voltage applied to the control end of the first power switch according to the first detection signal; and
and the input end of the second level conversion module is used for receiving the second detection signal and generating a second driving voltage applied to the control end of the second power switch according to the second detection signal.
7. The maximum voltage selection circuit of claim 6, wherein the output of the first level shift module is further connected to the third node and the output of the second level shift module is further connected to the fourth node to form a negative feedback loop.
8. The maximum voltage selection circuit of claim 6, wherein the first and second level shifting blocks are implemented by inverters, and
the voltage domain of the first driving voltage is a first input voltage to the ground, and the voltage domain of the second driving voltage is a second input voltage to the ground.
9. The maximum voltage selection circuit of claim 6, wherein each power switch further comprises a logic module, and a control terminal of the power switch receives a corresponding driving voltage via the logic module,
wherein the logic module includes an inverter.
10. The maximum voltage selection circuit of claim 4, further comprising a plurality of hysteresis modules, each hysteresis module being arranged in parallel with a corresponding first current source, each hysteresis module for providing a hysteresis current at a parallel node of the corresponding first current source in dependence upon the corresponding first or second detection signal,
wherein each hysteresis module respectively comprises:
and a ninth transistor and a second current source, which are connected in series between the parallel node of the corresponding first current source and the ground, wherein the control end of the ninth transistor is used for receiving the corresponding first detection signal or second detection signal.
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| CN202310204640.3A CN116436452A (en) | 2023-03-06 | 2023-03-06 | Maximum voltage selection circuit |
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| CN202310204640.3A CN116436452A (en) | 2023-03-06 | 2023-03-06 | Maximum voltage selection circuit |
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| CN116436452A true CN116436452A (en) | 2023-07-14 |
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