CN116436421A - Isolation amplifier and electronic device - Google Patents

Isolation amplifier and electronic device Download PDF

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Publication number
CN116436421A
CN116436421A CN202310315372.2A CN202310315372A CN116436421A CN 116436421 A CN116436421 A CN 116436421A CN 202310315372 A CN202310315372 A CN 202310315372A CN 116436421 A CN116436421 A CN 116436421A
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CN
China
Prior art keywords
clock signal
circuit
signal
isolation amplifier
modulator
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CN202310315372.2A
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Chinese (zh)
Inventor
陈益群
施云生
邓维平
林清俤
沈超
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Ningbo Qunxin Microelectronics Co ltd
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Ningbo Qunxin Microelectronics Co ltd
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Priority to CN202310315372.2A priority Critical patent/CN116436421A/en
Publication of CN116436421A publication Critical patent/CN116436421A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

An isolation amplifier and an electronic device, the isolation amplifier comprising: the clock signal generating circuit, the modulator, the first transmitting circuit, the first receiving circuit, the second transmitting circuit, the second receiving circuit, the first coupling capacitance, the second coupling capacitance, and the demodulator, wherein: a modulator, the signal input end of which inputs an analog signal; the first output end of the first transmitting circuit is coupled with the input end of the first transmitting circuit and outputs a modulation signal corresponding to the analog signal; the second output end of the first transmitting circuit is coupled with the input end of the second transmitting circuit and outputs a target clock signal; the target clock signal is one of N paths of clock signals; a demodulator, the first input end of which is coupled with the output end of the first receiving circuit, and inputs a modulation signal; the second input end of the first receiving circuit is coupled with the output end of the second receiving circuit, and the target clock signal is input. By the scheme, the circuit area of the isolation amplifier can be reduced, the transmission bandwidth is improved, and the cost is reduced.

Description

Isolation amplifier and electronic device
Technical Field
The present invention relates to the field of electronic devices, and in particular, to an isolation amplifier and an electronic device.
Background
The isolation amplifier is a device capable of collecting and amplifying and outputting current analog signals between two voltage domains which are electrically isolated, and can provide electrical insulation for electronic equipment, isolate a ground loop and noise and improve anti-interference capability.
In the conventional isolation amplifier, a clock signal and a modulated data signal (hereinafter referred to as a modulation signal) are encoded by an encoder, and the encoded signal is transmitted to a receiving circuit via a transmitting circuit; the receiving circuit transmits the received encoded signal to the decoder, which restores the encoded signal to a modulated signal and a clock signal.
However, to implement the same isolation amplifier in which the clock signal and the modulation signal are multiplexed, the encoder typically employs manchester encoding or the like, resulting in a smaller transmission bandwidth. In addition, the decoder needs to use an additional phase-locked loop circuit or delay phase-locked loop circuit when recovering the clock signal from the encoded signal, so that the circuit area is large and the cost is high.
Disclosure of Invention
The embodiment of the invention solves the technical problems of larger circuit area, smaller transmission bandwidth and higher cost of the isolation amplifier.
To solve the above technical problem, an embodiment of the present invention provides an isolation amplifier, including: the clock signal generating circuit, the modulator, the first transmitting circuit, the first receiving circuit, the second transmitting circuit, the second receiving circuit, the first coupling capacitance, the second coupling capacitance, and the demodulator, wherein: the clock signal generating circuit is suitable for generating N paths of clock signals and outputting the N paths of clock signals to the modulator; n is more than or equal to 2; the signal input end of the modulator inputs an analog signal; the first output end of the first transmitting circuit is coupled with the input end of the first transmitting circuit and outputs a modulation signal corresponding to the analog signal; the second output end of the first transmitting circuit is coupled with the input end of the second transmitting circuit and outputs a target clock signal; the target clock signal is one of the N paths of clock signals; the first coupling capacitor is coupled between the output end of the first transmitting circuit and the input end of the first receiving circuit; the second coupling capacitor is coupled between the output end of the second transmitting circuit and the input end of the second receiving circuit; the first input end of the demodulator is coupled with the output end of the first receiving circuit and inputs the modulation signal; the second input end of the second receiving circuit is coupled with the output end of the second receiving circuit, and the target clock signal is input.
Optionally, the modulator comprises a sigma-delta modulator.
Optionally, the clock signal generating circuit is adapted to generate N clock signals with different delays and output the N clock signals to the sigma-delta modulator.
Optionally, N is related to the order M of the sigma-delta modulator.
Optionally, the N clock signals are divided into M groups; the ith group of clock signals comprises a first clock signal and a second clock signal, and a first time delay exists between the second clock signal and the first clock signal; a second time delay exists between a first clock signal of the ith group of clock signals and a first clock signal of the i-1 th group of clocks, and the second time delay is larger than the first time delay; i is more than or equal to 1 and less than or equal to M.
Optionally, the target clock signal is: a first clock signal of the M-th group clock signal in time sequence.
Optionally, the clock signal generating circuit includes a clock signal generating unit and a delay unit; wherein: the clock signal generating unit is suitable for generating a reference clock signal and outputting the reference clock signal to the delay unit; the delay unit is adapted to generate N clock signals with different delays based on the order M of the sigma-delta modulator.
Optionally, the first coupling capacitor and the second coupling capacitor are integrated in the same capacitor device and are independent from each other.
Optionally, the first coupling capacitor is an independent device; and/or the second coupling capacitance is an independent device.
The embodiment of the invention also provides electronic equipment, which comprises the isolation amplifier.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the modulator outputs a modulation signal to the first transmitting circuit, and the modulation signal is transmitted to the first receiving circuit through the first transmitting circuit and then is input to the demodulator; the modulator outputs the target clock signal to the second transmitting circuit, and transmits the target clock signal to the second receiving circuit via the second transmitting circuit, and inputs the target clock signal to the demodulator. The demodulator demodulates the modulated signal based on the modulated signal and the target clock signal. According to the isolation amplifier provided by the embodiment of the invention, the target clock signal is transmitted through the clock signal channel formed by the second transmitting circuit and the second receiving circuit, and an encoder and a decoder are not required to be arranged, so that the cost of the isolation amplifier can be effectively reduced.
The first coupling capacitor and/or the second coupling capacitor are independent capacitive devices, or the first coupling capacitor and the second coupling capacitor are integrated in the same capacitive device. Because the first coupling capacitor and the second coupling capacitor are independent capacitor devices, the requirements on the production process can be reduced compared with the integration of the coupling capacitors in a transmitting circuit and a receiving circuit.
Drawings
FIG. 1 is a schematic diagram of an isolation amplifier of the prior art;
FIG. 2 is a schematic diagram of an isolation amplifier in an embodiment of the invention;
FIG. 3 is a timing diagram of a 4-way clock signal in an embodiment of the invention;
fig. 4 is a schematic diagram of a delay unit according to an embodiment of the present invention.
Detailed Description
Referring to fig. 1, a schematic diagram of an isolation amplifier of the prior art is shown. In fig. 1, an oversampling clock signal clk is generated by an oversampling clock signal generating circuit 11 and input to a sigma-delta (Σ - Δ) modulator 12. The analog Signal is input to the Signal input terminal of the sigma-delta modulator 12, and the analog Signal is modulated by the sigma-delta modulator 12 to obtain a modulated Signal mdat. The modulated Signal mdat is a data stream consisting of logic "1" and logic "0", wherein the density of the logic "1" is proportional to the amplitude of the analog Signal.
The sigma-delta modulator 12 inputs the modulation signal mdat and the clock signal clk to the encoder 13, and the encoder 13 encodes the modulation signal mdat and the clock signal clk to obtain an encoded signal. The encoder 13 may encode the modulation signal mdat and the clock signal clkclk by manchester encoding or the like. The encoder outputs the encoded signal to the transmitting circuit 14, and the transmitting circuit 14 is coupled to the receiving circuit 16 via the high-voltage coupling capacitor 15, converts the encoded signal into an electrical signal, and transmits the electrical signal to the receiving circuit 16. The receiving circuit 16 receives the electric signal, converts it into an encoded signal, and sends the encoded signal to the decoder 17. The decoder 17 decodes the encoded signal to restore the clock signal clk and the modulation signal mdat. The sigma-delta demodulator 18 demodulates the modulated Signal mdat to obtain a corresponding analog Signal.
In the conventional isolation amplifier, the modulation signal mdat and the clock signal clk are encoded by the encoder 13, and the encoded signal is decoded by the decoder 17.
However, to implement the same isolation amplifier in which the clock signal and the modulation signal are multiplexed, the encoder typically employs manchester encoding or the like, resulting in a smaller transmission bandwidth. In addition, the decoder needs to use an additional phase-locked loop circuit or delay phase-locked loop circuit when recovering the clock signal from the encoded signal, so that the circuit area is large and the cost is high.
In the embodiment of the invention, a data signal path is formed by the first transmitting circuit and the first receiving circuit to transmit the modulation signal; the target clock signal is transferred through a clock signal path formed by the second transmitting circuit and the second receiving circuit. Therefore, the target clock signal and the modulation signal are respectively transmitted through two independent paths, and an encoder and a decoder are not required to be arranged, so that the circuit area and the cost of the isolation amplifier can be effectively reduced. In addition, since the encoder is not required to encode the target clock signal and the modulation signal, the transmission bandwidth of the isolation amplifier is large.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, a schematic diagram of an isolation amplifier in an embodiment of the invention is shown.
In an embodiment of the present invention, the isolation amplifier may include: the clock signal generating circuit 21, the modulator 22, the first transmitting circuit 23, the first coupling capacitance 24, the first receiving circuit 25, the second transmitting circuit 26, the second coupling capacitance 27, the second receiving circuit 28, and the demodulator 29.
In implementations, an output of the clock signal generation circuit 21 may be coupled to a clock signal input of the modulator 22; the clock signal generation circuit 21 may generate N clock signals and output the N clock signals to the modulator 22; that is, the N-way clock signal is input to the modulator 22 via the clock signal input terminal of the modulator 22;
the Signal input end of the modulator 22 may input an analog Signal, which is a Signal to be modulated; the modulator 22 can adjust the input analog Signal to obtain a modulated Signal mdat corresponding to the analog Signal; a first output terminal of the modulator 22 is coupled to an input terminal of the first transmitting circuit 23, and transmits a modulated signal mdat to the first transmitting circuit 23; a second output terminal of the modulator 22 is coupled to an input terminal of the second transmitting circuit 26, outputting a target clock signal clk; the target clock signal clk is one of N paths of clock signals;
the first coupling capacitor 24 may be coupled between the first transmitting circuit 23 and the first receiving circuit 25, and the first coupling capacitor 24 may be a high-voltage coupling capacitor;
the second coupling capacitor 27 may be coupled between the second transmitting circuit 26 and the second receiving circuit 28, and the first coupling capacitor 24 may be a high-voltage coupling capacitor;
a first input of the demodulator 29 may be coupled to an output of the first receiving circuit 25, inputting a modulated signal mdat; a second terminal of the demodulator 29 may be coupled to an output terminal of the second receiving circuit 28, inputting the target clock signal clk; the demodulator 29 may perform demodulation processing on the modulated signal mdat based on the received modulated signal mdat and the target clock signal clk.
In an implementation, the first transmitting circuit 23 may convert the modulated signal mdat into an electrical signal and couple to the first receiving circuit 24 via the first coupling capacitor 24.
Accordingly, the second transmitting circuit 26 may convert the target clock signal clk into an electrical signal and couple to the second receiving circuit 28 via the second coupling capacitor 27.
In implementations, modulator 22 may be a sigma-delta (sigma-delta) modulator. Accordingly, demodulator 29 may be a sigma-delta demodulator. The sigma-delta modulator may modulate an input analog signal based on the input N clock signals and the analog signal to obtain a modulated signal corresponding to the analog signal.
Specifically, the working principle and working process of the sigma-delta modulator, and the working principle and working process of the sigma-delta demodulator may be correspondingly referred to the prior art, and the embodiments of the present invention will not be described in detail.
In fig. 1, only the oversampling clock signal generating circuit 11 is shown to generate one clock signal. In a specific application, the number of ways of the clock signal output by the oversampling clock signal generating circuit 11 is also substantially related to the order of the sigma-delta modulator. If the order of the sigma-delta modulator is 1 order, the oversampling clock signal generating circuit 11 outputs 2 clock signals; if the order of the sigma-delta modulator is 2 nd order, the oversampling clock signal generating circuit 11 outputs 4-way clock signals, and so on.
In the embodiment of the present invention, when the sigma-delta modulator is adopted, the number of paths N of the clock signal generated by the clock signal generating circuit 21 is related to the order M of the sigma-delta modulator. Specifically, n=2m.
For example, the order m=1 of the sigma-delta modulator, and the clock signal generating circuit 21 generates 2-way clock signals. As another example, the order m=2 of the sigma-delta modulator, and the clock signal generating circuit 21 generates 4-way clock signals.
In the embodiment of the present invention, the N clock signals generated by the clock signal generating circuit 21 all correspond to different delays. In other words, each path of clock signal has a time delay, and the time delays corresponding to the clock signals of different paths are different.
In implementations, the N-way clock signals may be divided into M groups, each of which may correspond to a first order of the sigma-delta modulator.
For example, the 4-way clock signals are divided into 2 groups, a first group of clock signals corresponding to a first order of the sigma-delta modulator and a second group of clock signals corresponding to a second order of the sigma-delta modulator.
For M groups of clock signals, the ith group of clock signals comprises a first clock signal and a second clock signal, and a first time delay exists between the first clock signal and the second clock signal; a second delay exists between the first clock signal of the i-th group clock signal and the first clock signal of the i-1 th group clock signal; the second time delay is larger than the first time delay, and i is more than or equal to 1 and less than or equal to M.
In a particular application, the second delay may be substantially greater than the first delay. For example, the first delay is 5ns and the second delay is 50ns.
In implementations, the target clock signal clk may be the first clock signal in the mth group of clock signals. The duty cycle of the target clock signal clk may be less than 50%.
Referring to fig. 3, a timing diagram of a 4-way clock signal, i.e., a sigma-delta modulator is shown in an embodiment of the present invention. The following is a description with reference to fig. 3.
As shown in fig. 3, the 4-way clock signals are divided into 2 groups, the 1 st group clock signal includes a first clock signal Φ1 and a second clock signal Φ1d, and the 2 nd group clock signal includes a first clock signal Φ2 and a second clock signal Φ2d. The time delay between phi 1 and phi 1d is t1-t0, and the time delay between phi 2 and phi 2d is t3-t2. Normally, t 1-t0=t3-t 2. The time delay between phi 1 and phi 2 is t2-t0.
For the 4-way clock signal described above, the clock signal Φ2 is selected as the target clock signal clk.
In an implementation, if there are 6 clock signals, i.e. the sigma-delta modulator is third order, the 6 clock signals may be divided into 3 groups, wherein: the first set of clock signals comprises a first clock signal phi 1 and a second clock signal phi 1d, the second set of clock signals comprises a first clock signal phi 2 and a second clock signal phi 2d, and the third set of clock signals comprises a first clock signal phi 3 and a second clock signal phi 3d. The delay between phi 2 and phi 1, the delay between phi 3 and phi 2, may be equal. For the 6-way clock signal described above, the clock signal Φ3 is selected as the target clock signal clk.
In an implementation, the clock signal generating circuit 21 may include a clock signal generating unit 211 and a delay unit 212, where:
a clock signal generating unit 211 adapted to generate a reference clock signal and output it to the delay unit 212;
the delay unit 212 may generate N clock signals with different delays based on the order M of the sigma-delta modulator.
In implementations, the N-way clock signal may have different delays relative to the reference clock signal. For example, n=4, where the delay of the first clock signal with respect to the reference clock signal is 0, the delay of the second clock signal with respect to the first clock signal is Δt1, the delay of the third clock signal with respect to the second clock signal is Δt2, and the delay of the fourth clock signal with respect to the third clock signal is Δt1. Both Δt1 and Δt3 are not 0.
Referring to fig. 4, a schematic diagram of the structure of a delay unit 212 in an embodiment of the present invention is provided. In fig. 4, the input terminal of the delay unit may input a reference clock signal clk0, which is generated by the clock signal generation unit 211. Delay unit 212 may be comprised of 2 NAND gates (NAVs) and several inverters (invs) that ultimately output clock signal φ 1, clock signal φ 1d, clock signal φ 2, and clock signal φ 2d.
In implementations, the delay duration between clock signals may be adjusted by adjusting the number of inverters in delay unit 212.
It will be appreciated that the specific circuit configuration of delay unit 212 is merely an example, and this example is not intended to limit the scope of the present invention. In particular, the delay unit may also be implemented by adopting other hardware circuit structures.
In an implementation, the reference clock signal output by the clock signal generating unit 211 may be an oversampling clock signal.
The delay unit may also be implemented in software only, i.e. a controller or control unit generates clock signals with different delays. The delay unit may also be implemented in a combination of hardware and software.
In summary, in the embodiment of the present invention, a data signal path is formed by the first transmitting circuit and the first receiving circuit, so as to transmit a modulation signal; the target clock signal is transferred through a clock signal path formed by the second transmitting circuit and the second receiving circuit. Thus, the target clock signal and the modulation signal are transmitted through two independent paths, and an encoder and a decoder are not required to be arranged. Because the target clock signal is transmitted to the decoder through the clock signal path, a phase-locked loop circuit or a delay phase-locked loop circuit for clock signal recovery is not required to be additionally arranged, and the circuit area and the cost of the isolation amplifier can be effectively reduced. In addition, since the encoder is not required to encode the target clock signal and the modulation signal, the transmission bandwidth of the isolation amplifier is large.
In implementations, the first coupling capacitance may be a separate high voltage coupling capacitor. Alternatively, the first coupling capacitance is a separately packaged high voltage coupling capacitor.
The second coupling capacitance may be a separate high voltage coupling capacitor. Alternatively, the second coupling capacitance is a separately packaged high voltage coupling capacitor.
In an implementation, the first coupling capacitor and the second coupling capacitor may also be integrated in the same high-voltage coupling capacitor chip. In the high-voltage coupling capacitor chip, the first coupling capacitor and the second coupling capacitor are arranged independently of each other.
Because the first coupling capacitor and the second coupling capacitor are independent capacitor devices, compared with the coupling capacitor generated by adopting an integrated circuit manufacturing (BCD) process on a transmitting circuit and a receiving circuit, the independent capacitor devices can reduce the process requirement of the isolation amplifier. And, the independent capacitor device also has the advantage of lower cost.
In a specific implementation, the clock signal generating unit 21, the modulator 22, and the first and second transmitting circuits 23, 26 may be integrated in a transmitting chip. The first receiving circuit 25, the second receiving circuit 28 and the demodulator may be integrated in a receiving chip. The first coupling capacitor 24 and the second coupling capacitor 27 may be integrated in a high voltage coupling capacitor chip. Therefore, the isolation amplifier provided by the embodiment of the invention can be composed of a transmitting chip, a high-voltage coupling capacitor chip and a receiving chip.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. An isolation amplifier, comprising: the clock signal generating circuit, the modulator, the first transmitting circuit, the first receiving circuit, the second transmitting circuit, the second receiving circuit, the first coupling capacitance, the second coupling capacitance, and the demodulator, wherein:
the clock signal generating circuit is suitable for generating N paths of clock signals and outputting the N paths of clock signals to the modulator; n is more than or equal to 2; the signal input end of the modulator inputs an analog signal; the first output end of the first transmitting circuit is coupled with the input end of the first transmitting circuit and outputs a modulation signal corresponding to the analog signal; the second output end of the first transmitting circuit is coupled with the input end of the second transmitting circuit and outputs a target clock signal; the target clock signal is one of the N paths of clock signals;
the first coupling capacitor is coupled between the output end of the first transmitting circuit and the input end of the first receiving circuit;
the second coupling capacitor is coupled between the output end of the second transmitting circuit and the input end of the second receiving circuit;
the first input end of the demodulator is coupled with the output end of the first receiving circuit and inputs the modulation signal; the second input end of the second receiving circuit is coupled with the output end of the second receiving circuit, and the target clock signal is input.
2. The isolation amplifier of claim 1, wherein the modulator comprises a sigma-delta modulator.
3. The isolation amplifier of claim 2, wherein the clock signal generation circuit is adapted to generate and output N clock signals having different delays to the sigma-delta modulator.
4. An isolation amplifier according to claim 3, wherein N is related to the order M of the sigma-delta modulator.
5. The isolation amplifier of claim 4, wherein said N clock signals are divided into M groups; the ith group of clock signals comprises a first clock signal and a second clock signal, and a first time delay exists between the second clock signal and the first clock signal; a second time delay exists between a first clock signal of the ith group of clock signals and a first clock signal of the i-1 th group of clocks, and the second time delay is larger than the first time delay; i is more than or equal to 1 and less than or equal to M.
6. The isolation amplifier of claim 5, wherein said target clock signal is: a first clock signal of the M-th group clock signal in time sequence.
7. The isolation amplifier of claim 4, wherein said clock signal generation circuit comprises a clock signal generation unit and a delay unit; wherein:
the clock signal generating unit is suitable for generating a reference clock signal and outputting the reference clock signal to the delay unit;
the delay unit is adapted to generate N clock signals with different delays based on the order M of the sigma-delta modulator.
8. The isolation amplifier of claim 1, wherein the first coupling capacitor and the second coupling capacitor are integrated in the same capacitive device and are independent of each other.
9. The isolation amplifier of claim 1, wherein the first coupling capacitance is a stand-alone device; and/or the second coupling capacitance is an independent device.
10. An electronic device comprising an isolation amplifier as claimed in any one of claims 1 to 9.
CN202310315372.2A 2023-03-28 2023-03-28 Isolation amplifier and electronic device Pending CN116436421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310315372.2A CN116436421A (en) 2023-03-28 2023-03-28 Isolation amplifier and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310315372.2A CN116436421A (en) 2023-03-28 2023-03-28 Isolation amplifier and electronic device

Publications (1)

Publication Number Publication Date
CN116436421A true CN116436421A (en) 2023-07-14

Family

ID=87078965

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310315372.2A Pending CN116436421A (en) 2023-03-28 2023-03-28 Isolation amplifier and electronic device

Country Status (1)

Country Link
CN (1) CN116436421A (en)

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