CN116431524A

CN116431524A - Method and device for recovering effective data table in power failure and memory controller

Info

Publication number: CN116431524A
Application number: CN202210001697.9A
Authority: CN
Inventors: 骆小敏; 陈正亮; 王琛銮; 盛栋梁; 褚世凯
Original assignee: Lianyun Technology Hangzhou Co ltd
Current assignee: Lianyun Technology Hangzhou Co ltd
Priority date: 2022-01-04
Filing date: 2022-01-04
Publication date: 2023-07-14

Abstract

The application discloses a method and device for recovering an effective data table in power failure and a memory controller. The method for recovering the effective data table by power failure comprises the following steps: acquiring an L2P mapping table, wherein the L2P mapping table comprises a plurality of mapping units, each mapping unit comprises multi-bit data, the multi-bit data represents a logical address and a physical address of at least one physical page, and the physical page is used for storing effective data; setting scanning conditions according to the L2P mapping table; and scanning the L2P mapping table according to the scanning condition to count the quantity of the effective data belonging to the same physical block in the L2P mapping table, thereby obtaining an effective data count table. The method for recovering the effective data table after power failure can provide a correct, quick and consistent effective data count table, and ensures the consistency of the effective data count table and the L2P mapping table.

Description

Method and device for recovering effective data table in power failure and memory controller

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a method and apparatus for recovering an effective data table during power failure, and a memory controller.

Background

Solid state disk (Solid State Drive, which may be abbreviated as SSD) is a non-volatile data storage device composed of a controller and an array of memory chips. The storage medium of the solid state disk comprises a flash memory chip or a DRAM chip. The interface of the solid state disk can be compatible with a traditional hard disk which uses a magnetic disk as a storage medium, and has the advantages of small volume, light weight, low power consumption, no noise, high read-write speed and the like compared with the traditional hard disk, so the interface of the solid state disk has been widely used for replacing the traditional hard disk, for example, the interface of the solid state disk is applied to various fields such as notebook computers, industrial control, video monitoring, network terminals, navigation equipment and the like.

Because the data read-write of the storage chip of the solid state disk depends on physical characteristics, the existing file system cannot directly access or operate the storage chip. The control system of the solid state disk further includes additional cache chips, such as SRAM chips and DRAM chips, for storing the L2P mapping table (Logical To Physical Table, a mapping table of logical addresses to physical addresses, which may be simply referred to as an L2P mapping table). And the controller of the solid state disk reads the L2P mapping table to perform address mapping, and converts the logical address provided by the file system into the physical address of the memory chip, so that the data operation of the memory chip is realized.

Because both SRAM and DRAM chips are volatile storage media, once the solid state disk is powered down, the data on both SRAM and DRAM chips is lost, and therefore, how to save and restore a complete L2P mapping table and other management tables becomes a very important issue. The prior art generally stores the L2P mapping table and other management tables in the SRAM chip back to the nonvolatile memory chip periodically, and after power-up, transfers data back to the cache chip, and updates the unsynchronized portions. However, the problem of poor data consistency between the L2P mapping table and the valid data count table still exists in the prior art, and time overhead caused by excessive interaction is large.

For this reason, it is desirable to provide an improved method of recovering a valid data table from a power outage to solve the above-mentioned problems.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a method for recovering an effective data table in a power failure, an effective data counting device and a memory controller, so that the effective data counting table can be correctly, quickly and consistently obtained.

According to an aspect of the present invention, there is provided a method of recovering a valid data table from a power outage, an L2P mapping table comprising a plurality of mapping units, each of said mapping units comprising multi-bit data, said multi-bit data characterising a logical address and a physical address of at least one physical page, said physical page being for storing valid data, said method comprising:

setting scanning conditions according to the L2P mapping table recovered in advance;

and scanning the L2P mapping table according to the scanning condition to count the quantity of the effective data belonging to the same physical block in the L2P mapping table, thereby obtaining an effective data count table.

Optionally, setting the scanning condition according to the L2P mapping table includes: and setting the length and the offset of the scanned multi-bit data according to the format of the L2P mapping table, wherein the length and the offset represent the physical block where the physical page corresponding to the mapping unit is located.

Optionally, setting the scanning condition according to the L2P mapping table further includes: and setting the times of scanning the L2P mapping table according to the number of physical blocks corresponding to the L2P mapping table.

Optionally, before scanning the L2P mapping table, the method further includes: and acquiring the starting address and the size of the L2P mapping table to determine the scanning range of the L2P mapping table.

Optionally, the step of scanning the L2P mapping table is performed by a hardware acceleration module, and the valid data count table is temporarily stored in the hardware acceleration module.

Optionally, when the total number of the physical blocks corresponding to the L2P mapping table is greater than the depth supported by the hardware acceleration module, setting a total cycle number of scanning the L2P mapping table to be greater than 1, and executing a step of scanning the L2P mapping table for an address range represented by a scanning condition corresponding to each cycle, so as to obtain a count value of effective data of each physical block in the flash memory chip;

and when the total number of the physical blocks corresponding to the L2P mapping table is not more than the depth supported by the hardware acceleration module, executing the step of scanning the L2P mapping table once by using the hardware acceleration module.

Optionally, the total number of loops is a value obtained by dividing the total number of the physical blocks corresponding to the L2P mapping table by a depth supported by a hardware acceleration module, and rounding up.

Optionally, setting a total cycle number of scanning the L2P mapping table according to a relation between the total number of physical blocks corresponding to the L2P mapping table and a depth supported by the hardware acceleration module, the total cycle number being greater than 0,

in each cycle, the step of scanning the L2P mapping table is performed for an address range indicated by a scanning condition corresponding to each cycle.

Optionally, the hardware acceleration module includes one or more of a hardware register, a central processing unit, an application specific integrated circuit, and a combinational logic circuit.

According to a second aspect of the present invention, there is provided a valid data counting apparatus comprising:

a processor for pre-restoring an L2P mapping table, the L2P mapping table including a plurality of mapping units, each of the mapping units including multi-bit data, the multi-bit data representing a logical address and a physical address of at least one physical page, the physical page being for storing valid data;

and the hardware acceleration module is used for setting scanning conditions according to the L2P mapping table and scanning the L2P mapping table according to the scanning conditions so as to count the quantity of the effective data belonging to the same physical block in the L2P mapping table, thereby obtaining an effective data count table.

Optionally, the setting, by the hardware acceleration module, the scan condition according to the L2P mapping table includes: and setting the length and the offset of the scanned multi-bit data according to the format of the L2P mapping table, wherein the length and the offset represent the physical block where the physical page corresponding to the mapping unit is located.

Optionally, when the total number of the physical blocks corresponding to the L2P mapping table is greater than the depth supported by the hardware acceleration module, the hardware acceleration module sets a total cycle number of scanning the L2P mapping table to be greater than 1, and performs a step of scanning the L2P mapping table for an address range indicated by a scanning condition corresponding to each cycle, so as to obtain a count value of effective data of each physical block in the flash memory chip;

and when the total number of the physical blocks corresponding to the L2P mapping table is not more than the depth supported by the hardware acceleration module, the hardware acceleration module executes the step of scanning the L2P mapping table once.

Optionally, the total number of cycles set by the hardware acceleration module is a value obtained by dividing the total number of physical blocks corresponding to the L2P mapping table by a depth supported by the hardware acceleration module, and the value is rounded upwards.

Optionally, the hardware acceleration module sets a total number of cycles for scanning the L2P mapping table according to a relationship between the total number of physical blocks corresponding to the L2P mapping table and a depth supported by the hardware acceleration module, the total number of cycles being greater than 0,

in each cycle, the hardware acceleration module performs a step of scanning the L2P mapping table for an address range represented by a scanning condition corresponding to each cycle.

According to a third aspect of the present invention, there is provided a memory controller comprising a control unit and a storage unit coupled, the control unit performing the method of power-down restoration of a valid data table as described above, the storage unit being for storing the L2P table.

According to the method for recovering the effective data table after power failure, the effective data counting device and the memory controller, the effective data counting table is obtained according to the L2P mapping table, so that the effective data counting table has consistency with the L2P table, the data correctness of the effective data counting table is ensured, and the timeliness of data recovery is ensured.

Furthermore, the technical scheme adopts a hardware acceleration mode to obtain the effective data count table, which is beneficial to rapidly analyzing the content of the L2P mapping table, calculating the effective data count in batches and reducing the time expenditure caused by excessive interaction.

Furthermore, when the technical scheme is accelerated by utilizing hardware, even if the depth supported by the hardware is smaller than the total number of physical blocks, the complete effective data count table can be obtained by calling and executing the step of scanning the L2P table for multiple times, so that the hardware resource is controllable and the expandability is good.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic block diagram of a conventional computer system;

FIG. 2 shows a schematic block diagram of a computer system according to an embodiment of the invention;

FIG. 3 shows a schematic block diagram of a valid data counting apparatus according to an embodiment of the invention;

fig. 3a shows a schematic diagram of the operation of the effective data counting device according to the first embodiment of the present invention;

FIG. 3b shows a schematic diagram of the operation of a valid data counting device according to a second embodiment of the invention;

fig. 4 shows a flowchart of a method of power down restoration of a valid data table according to an embodiment of the invention.

Detailed Description

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the invention. The figures are not necessarily drawn to scale.

The flowcharts, block diagrams in the figures illustrate the possible architectural framework, functions, and operations of the systems, methods, apparatus of the embodiments of the present invention, and the blocks in the flowcharts and block diagrams may represent a module, a program segment, or a code segment, which is an executable instruction for implementing the specified logical function(s). It should also be noted that the executable instructions that implement the specified logic functions may be recombined to produce new modules and program segments. The blocks of the drawings and the order of the blocks are thus merely to better illustrate the processes and steps of the embodiments and should not be taken as limiting the invention itself.

The following terminology is used hereinafter.

Address mapping: mapping of logical addresses to physical addresses, the core function of the memory control system, is the basis for many other modules.

Power down recovery (Power off Recovery, which may be referred to simply as POR): after the computer system is powered down, data recovery is performed on the data stored in the volatile storage medium.

Garbage collection (Garbage Collection, which may be abbreviated as GC): and recycling the space occupied by dirty data generated by the off-site update.

Fig. 1 shows a schematic block diagram of a conventional computer system. Computer system 100 includes a host 110, a control system 120, and a memory 130. Hereinafter, a solid state disk is described as an example. The solid state disk includes, for example, a control system 120 and a memory 130 as shown in the figure, and a storage medium of the memory 130 is, for example, a flash memory chip array.

The host interface 121 of the control system 120 is connected to the host 110 to transmit instructions. Host interface 121 is, for example, SATA, M.2, mSATA, and PCI-E. The processor 123 is connected to a host interface 121, a cache controller 124, and a memory controller 128. The cache chips in the control system 120 include SRAM chips 125 and DRAM chips 126, for example, to store an L2P mapping table. The processor 123 is used to implement a core software layer of memory control, FTL (Flash Translation Layer ), so that the operating system and the file system can access memory as if they were accessing a hard disk. The FTL also has features such as supporting all SLC (Single Level Cell ) and MLC (Multi-Level Cell), supporting bad block management, wear leveling, garbage collection, power down recovery, write balancing techniques, etc. The core function of FTL is address mapping, wherein processor 123 reads the cache chip via cache controller 124 to obtain an L2P mapping table, based on which logical addresses received from host 110 are mapped to physical addresses of memory 130. The memory controller 128 of the control system 120 is coupled to the memory 130 for performing data access operations to corresponding memory locations of the memory 130 based on physical addresses provided by the processor 123.

The cache chips in the control system 120 include SRAM chips 125 and DRAM chips 126. The high-capacity DRAM chip 126 may support address mapping of a high-capacity solid state hard disk, for example, for a 1TB memory chip array, a 1GB cache chip is used to store an L2P mapping table, and the two are, for example, 1: 1000.

Memory 130 includes an array of flash memory chips. To improve the data read/write performance, the memory controller 128 of the control system 120 may read/write the flash memory chip of the memory 130 via the multiple channels CH0 and CH 1. Each channel is connected to a set of flash memory chips. Each flash memory chip includes a plurality of physical blocks, each physical block including a plurality of physical pages. Data access operations to flash memory chips include read, write, and erase. Due to the physical characteristics of the flash memory chip, a basic unit of data operation is, for example, a physical page, and a basic unit of erase operation is, for example, a physical block.

When the host 110 performs a data operation, the control system 120 receives an instruction from the host 110. The control system 120 maps logical addresses in the instructions to physical addresses that characterize locations in the memory 130, including channels, physical blocks, physical pages, and the like. In the read operation, the control system 120 reads user data and metadata in units of physical pages, and acquires read data corresponding to a logical address based on the user data and metadata. In the write operation, the control system 120 generates user data and metadata from the write data in the instruction, and then writes the user data and metadata in units of physical pages. The metadata includes data other than user data, for example, the above-described L2P mapping table also needs to be written into the memory 130 as metadata, so that the L2P mapping table can be restored when the control system 120 is powered off.

In order to support power-down recovery of the valid data count table (valid data count table, which may be simply referred to as VC table), in the above conventional computer system, on one hand, the valid data count table is periodically stored in the memory 130 when the computer system is running, and on the other hand, the computer system is usually externally connected with a large capacitor, so that the VC table can be forcedly synchronized in the memory 130 when abnormal power-down occurs.

FIG. 2 shows a schematic block diagram of a computer system according to an embodiment of the invention. Computer system 100 includes a host 110, a control system 120, and a memory 130. Hereinafter, a solid state disk is described as an example. The solid state disk includes, for example, a control system 120 and a memory 130 as shown in the figure, and a storage medium of the memory 130 is, for example, a flash memory chip array.

In this embodiment, during the power-down recovery process, the effective data counting device 127 in the control system 120 adopts a hardware acceleration mode to obtain an effective data count table according to the L2P mapping table recovered by the processor 123, thereby ensuring data consistency and running speed.

Fig. 3 shows a schematic block diagram of a valid data counting device according to an embodiment of the invention.

As shown in fig. 3, the valid data counting apparatus 127 includes an initialization module 1271, a hardware acceleration module 1272, and a recovery module 1273, which are connected via a data bus, to which the processor 123 and the cache controller 124 are also connected, and to which the cache controller 124 is connected a cache chip. The valid data counting device 127 is configured to restore a valid data count table stored in the cache chip according to the L2P mapping table restored by the computer system when the computer system is powered on, where the valid data count table includes count values of valid data included in each physical block in the flash memory chip.

The L2P mapping table includes a plurality of mapping units, each mapping unit including multi-bit data, the multi-bit data characterizing logical addresses and physical addresses of at least one physical page, the physical page being for storing valid data.

Embodiments of the present disclosure utilize an L2P mapping table to recover a valid data count table. The logical addresses of the physical pages and the physical addresses of the physical pages are in one-to-one correspondence, the set of the correspondence between the logical addresses of the physical pages and the physical addresses of the physical pages is an L2P mapping table, and the set of the correspondence between the physical block numbers and the number of the physical pages in which the effective data are stored in the physical blocks is an effective data count table.

Specifically, according to the valid data counting apparatus 127 provided in the embodiments of the present disclosure, when the computer system is powered down and recovered, the initialization module 1271 performs an initialization process on the valid data count table, which may be implemented using an array or other manners, for example.

The hardware acceleration module 1272 is used to initiate hardware acceleration after the computer system recovers the L2P mapping table, the hardware acceleration module 1272 is, for example, a hardware register, and furthermore, the hardware acceleration module 1272 may be selected from one or more of a hardware register, a central processing unit, an application specific integrated circuit, and a combinational logic circuit. As an example, the L2P mapping table is restored by the processor 123 connected to the data bus, for example, by scanning each physical block in the flash memory chip in advance, or by updating the L2P mapping table newly stored in the flash memory chip.

The hardware acceleration module 1272 configures corresponding registers according to the content format of the fixed L2P mapping table, rapidly parses the content of the L2P mapping table, and calculates valid data counts in batches.

Specifically, the hardware acceleration module 1272 sets a scanning condition according to the L2P mapping table, and scans the L2P mapping table to count the number of valid data belonging to the same physical block, and obtains the valid data count table after obtaining the count value of the valid data of each physical block in the flash memory chip. Optionally, the valid data count table is temporarily stored in a random access memory (Random Access Memory, RAM) of the hardware acceleration module 1272, and after the hardware acceleration module 1272 performs the steps of scanning the L2P mapping table once and acquiring the valid data count value according to the scanning condition, the valid data count table is sent to a later storage module (e.g., a cache controller).

The depth of the ram within the hardware acceleration module 1272 is limited, e.g., 1K physical block corresponding entry values, each entry size 4B, for a total of 4KB of ram size can be staged. When the total number of physical blocks is greater than the depth supported by the hardware acceleration module 1272, the steps of scanning the L2P mapping table and counting the number of valid data belonging to the same physical block according to the scanning conditions are repeatedly performed to obtain a count value of valid data of each physical block in the flash memory chip, and different scanning conditions are set to count the number of physical addresses of physical blocks located in different ranges each time the scanning of the L2P mapping table is performed.

Optionally, before scanning the L2P mapping table, the hardware acceleration module 1272 obtains the start address and the size of the L2P mapping table to determine the range of scanning the L2P mapping table.

As one example, the method for setting the scan condition by the hardware acceleration module 1272 includes: according to the format of the L2P mapping table, setting the length block_shift and the OFFSET block_offset of scanned multi-bit data, wherein the length and the OFFSET represent the physical BLOCK of the physical page corresponding to the mapping unit. Therefore, after the scanning condition including the length and the offset of the multi-bit data is set, the L2P mapping table is scanned based on the scanning condition, so that the physical block where the physical page corresponding to each mapping unit is located can be known, and after the whole L2P mapping table is scanned, the count value of the effective data contained in each physical block is known, so that the effective data count table is obtained.

As an example, when the total number of physical blocks is not more than 1K, the hardware acceleration module 1272 performs a step of scanning the L2P mapping table once and counting the number of valid data belonging to the same physical block according to the scanning condition, so as to obtain the valid data count table, see fig. 3a.

First, the complete L2P table 201 in the storage medium is obtained, and the starting position and size of the L2P table 201 are sent to the hardware acceleration module 1272. In this exemplary L2P mapping table, 6 mapping units are included, of which 205, 208 belong to physical block blk 3; 206, 209, 210 belonging to physical block blk 4; there is 207 belonging to physical block blk 5.

The format of each mapping unit in the L2P table is fixed, and in this exemplary mapping unit 202, the length block_shift=10 of the multi-bit data is selected, and the OFFSET block_offset=15.

The module 203 characterizes the hardware acceleration module 1272 and the format of the internal memory, wherein 213 corresponds to the physical block blk3, the count value is 2, and corresponds to the

mapping units

205, 208 in the L2P table; 211 corresponds to a physical block blk4, the count value is 3, and represents

mapping units

206, 209 and 210 in the L2P table; 212 corresponds to the physical block blk5, the count value is 1, representing the mapping unit 207 in the L2P table; each count value is accumulated by each L2P mapping unit entry belonging to one physical block.

The hardware acceleration module 1272, after retrieving the valid data count table 204, stores it in the cache controller 124 shown in fig. 2.

As another example, when the total number of physical blocks exceeds 1K, the number of times of scanning the L2P mapping table is set according to the number of physical blocks corresponding to the L2P mapping table. The hardware acceleration module 1272 repeatedly performs the steps of scanning the L2P mapping table and counting the number of valid data belonging to the same physical block according to the scanning condition, so as to obtain a complete valid data count table, see fig. 3a.

For example, the mapping unit 321 shown in fig. 3b represents the physical block blk bit number 11bit at this time. While the hardware acceleration module only supports a depth of 1K (maximum 10bit wide).

In the L2P table, it is assumed that now as shown, there are a total of 8 mapping units, of which there are 303, 306 belonging to the physical block blk 3; there are 304, 307, 310 belonging to the physical block blk 4; a bin 305 belonging to physical block blk 5; 309 belonging to the physical block blk 1011; there is 308 belonging to a physical block blk 1012.

In the first round of hardware acceleration, as shown in BLOCK 301, the hardware acceleration module 1272 needs to set the scan condition to select the length block_shift=10, the OFFSET block_offset=15, the number of scans mask_shift=1, the number of scans mask_value=0, the number of scans mask_shift=1 indicates the common scan (mask_shift+1) round, the number of scans mask_value=0 indicates the current scan round, and the first round only calculates the valid data count VALUE of the physical BLOCK blk 0-1000. Wherein 320 corresponds to 2 mapping units of the physical block blk 3; 318 correspond to 3 mapping units of physical block blk 4; 319 corresponds to 1 mapping unit of a physical block blk 5.

In the second round of hardware acceleration, as shown in BLOCK 302, the hardware acceleration module 1272 needs to set the scanning condition to select the length block_shift=10, the OFFSET block_offset=15, the number of scans mask_shift=1, the number of scans mask_value=1, and the number of scans mask_value=1 to represent the second round of current scanning, and then the second round only calculates the valid data count VALUEs of the physical BLOCKs blk 1000-2000. Wherein 312 corresponds to 1 mapping unit of physical block blk 1011; 313 corresponds to 1 mapping unit of the physical block blk 1012.

The valid data count table 322 corresponds to the first round hardware acceleration output of the module 301; the valid data count table 323 corresponds to the second round hardware acceleration output of the module 302.

In the above embodiment, the hardware acceleration module 1272 is used for solidifying a software algorithm, and the purposes of accelerating calculation and reducing the time cost of data calculation are achieved through a hardware acceleration means.

In some alternative embodiments, the L2P table may also be scanned by a software calculation method, to count the number of valid L2P entries belonging to the same physical block, that is, to calculate the number of data physically written on the same physical block, thereby obtaining the valid data count table.

The recovery module 1273 uses the hardware acceleration of the hardware acceleration module 1272 and recovers the valid data count table according to the recovered L2P mapping table, so that the valid data count table has consistency with the L2P table, thereby ensuring the data correctness of the valid data count table and ensuring the timeliness of data recovery.

Specifically, after the recovered L2P mapping table of the computer system is obtained, the recovery module 1273 sets the total number of cycles n according to the total number of physical blocks in the flash memory chip, determines whether the number of cycles is less than n, starts hardware acceleration when the number of cycles is less than n, sets corresponding scanning conditions according to the format content of the L2P mapping table, calculates the number of valid data in the physical blocks, determines that the cycle is completed when the number of cycles is not less than n, and obtains the count value of the valid data in all the physical blocks in the flash memory chip, namely, obtains the valid data count table of the flash memory chip, and loads the valid data count table into the cache chip.

Optionally, the valid data counting device 127 further comprises a lookup module 1274 and an update module 1275 connected to the data buses. The searching module 1274 is configured to select a proper physical block when the computer system performs garbage collection, for example, select a physical block with the least number of valid data, so that garbage collection can be completed with maximum efficiency, and data handling efficiency is improved. The update module 1275 is used to update relevant information in the valid data count table when new data is written to the computer system or valid data becomes invalid.

Optionally, the effective data counting device 127 further includes a timing restore module 1276, where the timing restore module 1276 is used as a redundancy module, and the timing restore module 1276 may be a conventional timing restore module.

In the above-mentioned effective data counting device 127, the effective data count table is obtained according to the L2P mapping table recovered by the processor 123 by adopting a hardware acceleration manner, so that the effective data count table has consistency with the L2P table, thereby ensuring the data correctness of the effective data count table and the timeliness of data recovery.

The term "module" as used herein may refer to, be part of, or include the following: an application specific integrated circuit (Application Specific Integrated Circuit), which may simply be an ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

Those skilled in the art will appreciate that the various modules or units of a data processing system according to the present invention may be implemented in hardware, firmware, or software. The software includes, for example, code programs formed using various programming languages such as JAVA, C/C++/C#, SQL, and the like. Although steps and sequences of steps of embodiments of the present invention are presented in terms of methods and apparatus, executable instructions for implementing the specified logical function(s) of the steps may be rearranged to produce new steps. The order of the steps should not be limited to only the order of the steps in the method and method illustration, but may be modified at any time as required by the function. For example, some of the steps may be performed in parallel or in reverse order.

Also, those of ordinary skill in the art will recognize that structures and methods of examples described in connection with the embodiments disclosed herein may be implemented using different configurations or adaptations of each structure or reasonable variations of that structure to achieve the described functionality, but such implementations should not be construed as outside the scope of the present application. Also, it should be understood that the connection relationship between the respective components of the amplifier of the foregoing drawings in the embodiments of the present application is illustrative and not limiting in any way.

Fig. 4 shows a flowchart of a method of power down restoration of a valid data table according to an embodiment of the invention. As shown in fig. 4, the method for recovering the valid data table after power failure includes steps S1 to S5.

In step S1, an L2P mapping table is obtained, the L2P mapping table comprising a plurality of mapping units, each mapping unit comprising multi-bit data, the multi-bit data characterizing a logical address and a physical address of at least one physical page, the physical page being for storing valid data. In this step, for example, the L2P mapping table is restored first, and the restored L2P mapping table is loaded into the cache chip.

In step S2, the total number of loops n is set according to the L2P map. The total number of loops n is, for example, a value obtained by dividing the total number of physical blocks in the flash memory chip by the depth supported by the hardware acceleration module, and rounding up. Optionally, before scanning the L2P mapping table, the method further includes: the starting address and the size of the L2P mapping table are obtained to determine the scanning range of the L2P mapping table.

Then, it is judged whether the number of times of circulated is less than n, wherein when the number of times of circulated is judged to be less than n, steps S3, S4 and S5 are performed, and when the number of times of circulated is judged to be not less than n, the circulated is ended, at which time a valid data count table of the flash memory chip has been obtained, and the valid data count table is stored in the cache chip.

In step S3, scanning conditions are set according to the L2P map. In this step, according to the format of the L2P mapping table, the length block_shift and the OFFSET block_offset of the scanned multi-bit data are set, and the length and the OFFSET characterize the physical BLOCK where the physical page corresponding to the mapping unit is located. Therefore, after the scanning condition including the length and the offset of the multi-bit data is set, the L2P mapping table is scanned based on the scanning condition, so that the physical block where the physical page corresponding to each mapping unit is located can be known, and after the whole L2P mapping table is scanned, the count value of the effective data contained in each physical block is known, so that the effective data count table is obtained. When the L2P mapping table is scanned every time, different scanning conditions are set, and the step of scanning the L2P mapping table, that is, steps S4 and S5 are executed, is executed for the address range indicated by the scanning condition corresponding to each cycle, so as to obtain the count value of the effective data of each physical block in the flash memory chip.

In steps S4 and S5, the L2P mapping table is scanned according to the scanning conditions to count the number of valid data belonging to the same physical block in the L2P mapping table, thereby obtaining a valid data count table. In this step, for example, hardware acceleration is performed using a hardware register, and the number of physical pages (i.e., the count value of valid data) included in the physical block for storing valid data is obtained using a scanning condition.

Optionally, the method for recovering the valid data table by power outage further comprises: when valid data is updated or becomes invalid, the valid data count table is updated.

In the above steps, a hardware acceleration mode is adopted, and the effective data count table is obtained according to the L2P mapping table recovered by the processor, so that the effective data count table has consistency with the L2P table, thereby ensuring the data correctness of the effective data count table and ensuring the timeliness of data recovery.

The data processing system and method according to the present invention may be deployed on a single server or on multiple servers. For example, different modules may be deployed on different servers, respectively, to form a dedicated server. Alternatively, the same functional units, modules, or systems may be distributed across multiple servers to relieve load pressure. The server includes, but is not limited to, a plurality of PCs, PC servers, blades, supercomputers, etc. connected on the same local area network and through the Internet.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of recovering a valid data table from a power outage, wherein an L2P mapping table comprises a plurality of mapping units, each of said mapping units comprising multi-bit data, said multi-bit data representing a logical address and a physical address of at least one physical page, said physical page being for storing valid data, said method comprising:

2. The method of recovering a valid data table from a power outage of claim 1, wherein setting the scan condition according to the L2P mapping table comprises: and setting the length and the offset of the scanned multi-bit data according to the format of the L2P mapping table, wherein the length and the offset represent the physical block where the physical page corresponding to the mapping unit is located.

3. The method of recovering a valid data table from a power outage of claim 2, wherein setting the scanning conditions according to the L2P mapping table further comprises: and setting the times of scanning the L2P mapping table according to the number of physical blocks corresponding to the L2P mapping table.

4. The method of recovering a valid data table from a power outage of claim 1, further comprising, prior to scanning the L2P mapping table: and acquiring the starting address and the size of the L2P mapping table to determine the scanning range of the L2P mapping table.

5. The method of claim 1, wherein the step of scanning the L2P mapping table is performed by a hardware acceleration module, the valid data count table being temporarily stored in the hardware acceleration module.

6. The method of recovering a valid data table from a power outage of claim 5,

when the total number of the physical blocks corresponding to the L2P mapping table is greater than the depth supported by the hardware acceleration module, setting the total cycle number of scanning the L2P mapping table to be greater than 1, and executing the step of scanning the L2P mapping table according to the address range represented by the scanning condition corresponding to each cycle number respectively to obtain the count value of the effective data of each physical block in the flash memory chip;

7. The method of claim 6, wherein the total number of cycles is a value obtained by dividing the total number of physical blocks corresponding to the L2P mapping table by a depth supported by a hardware acceleration module.

8. The method of recovering a valid data table from a power outage of claim 5,

setting the total circulation times of scanning the L2P mapping table according to the relation between the total number of the physical blocks corresponding to the L2P mapping table and the depth supported by the hardware acceleration module, wherein the total circulation times are more than 0,

9. The method of recovering a valid data table according to any one of claims 5 to 8, wherein the hardware acceleration module comprises one or more of a hardware register, a central processing unit, an application specific integrated circuit, a combinational logic circuit.

10. A valid data counting apparatus, comprising:

11. The efficient data counting apparatus of claim 10, wherein the hardware acceleration module setting the scan condition according to the L2P map comprises: and setting the length and the offset of the scanned multi-bit data according to the format of the L2P mapping table, wherein the length and the offset represent the physical block where the physical page corresponding to the mapping unit is located.

12. The valid data counting device as claimed in claim 11, wherein,

when the total number of the physical blocks corresponding to the L2P mapping table is greater than the depth supported by the hardware acceleration module, the hardware acceleration module sets the total cycle number of scanning the L2P mapping table to be greater than 1, and performs the step of scanning the L2P mapping table for the address range represented by the scanning condition corresponding to each cycle respectively so as to obtain the count value of the effective data of each physical block in the flash memory chip;

13. The apparatus according to claim 12, wherein the total number of cycles set by the hardware acceleration module is a value obtained by dividing a total number of the physical blocks corresponding to the L2P mapping table by a depth supported by the hardware acceleration module, and rounding up.

14. The valid data counting device as claimed in claim 11, wherein,

the hardware acceleration module sets the total circulation times of scanning the L2P mapping table according to the relation between the total number of the physical blocks corresponding to the L2P mapping table and the depth supported by the hardware acceleration module, the total circulation times are more than 0,

15. The active data counting apparatus of claim 11, wherein the hardware acceleration module comprises one or more of a hardware register, a central processing unit, an application specific integrated circuit, a combinational logic circuit.

16. A memory controller comprising a control unit and a storage unit coupled, the control unit performing the method of recovering a valid data table from a power outage of any of claims 1-9, the storage unit for storing the L2P table.