CN116419079A - Pixel circuit, image sensor and method for reducing pixel fixed image noise - Google Patents

Abstract

The invention provides a pixel circuit, an image sensor and a method for reducing pixel fixed image noise, comprising the following steps: performing global exposure on each pixel; resetting a capacitance storing a signal representing an image; sampling signals for characterizing the image based on the corresponding capacitances, respectively; reading out a signal representing the image; in the sampling phase, the control signal of the transistor for sampling the signal representing the image is a step level, having at least two steps, the voltage of each step decreasing in turn. According to the invention, the control signal of the sampling transistor is set to be a step level, so that the difference value between the gate terminal voltage and the threshold voltage when the transistor is turned off is reduced, the influence of channel charge injection effect on each pixel is further reduced, and the fixed image noise is reduced; in the case where the threshold voltage is unknown, a plurality of steps are provided to capture the position of the threshold voltage so that the difference between the gate terminal voltage and the threshold voltage decreases when the transistor is turned off.

Description

Pixel circuit, image sensor and method for reducing pixel fixed image noise

Technical Field

The present invention relates to the field of image sensors, and more particularly, to a pixel circuit, an image sensor, and a method for reducing noise of a fixed pixel image.

Background

In the process of exposing and sampling pixels, the image sensor generates fixed pattern noise (FPN: fixed Pattern Noise) due to the deviation of the manufacturing process, and the factors caused by the fixed pattern noise (PFPN: pixel Fixed Pattern Noise) for a single pixel are as follows: the threshold voltages of the active transistors are not uniform; in addition, non-uniformity of dark current of the photodiode and the like may also cause fixed pattern noise. The actual threshold voltage of the active transistor is different from the preset threshold voltage due to the deviation of the manufacturing process, and the actual threshold voltage of each active transistor is inconsistent, so that the accuracy of the read signal of the image sensor is greatly affected by the channel charge injection effect (the channel charge injection effect is mainly reflected in the condition that the transistor leaks from the transistor when in a state of being turned on to be turned off, and the signal in the capacitor can be affected if the channel charge injection effect leaks into the capacitor for storing the signal) when the voltage of the control terminal is larger than the actual threshold voltage difference value; the channel charge injection effect of different active transistors is different, the influence on each pixel is different, and the consistency of the final read image is greatly affected.

In addition, the existing image sensor has complex control time sequence and low efficiency when resetting and sampling pixels.

Therefore, how to overcome the influence of the channel charge injection effect and improve the accuracy, consistency and operation efficiency of the read signal has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a pixel circuit, an image sensor and a method for reducing pixel fixed image noise, which are used for solving the problems of the prior art that the charge injection effect affects the accuracy and consistency of the readout signal of the image sensor, the control timing is complex, and the efficiency is low.

To achieve the above and other related objects, the present invention provides a method of reducing fixed pixel image noise, the method of reducing fixed pixel image noise at least comprising:

performing global exposure on each pixel;

resetting a capacitance storing a signal representing an image;

sampling the signals for representing the image based on the corresponding capacitances respectively;

reading out the signal for representing the image;

in the sampling stage, the control signal of the transistor for sampling the signal for representing the image is a step level, the step level is provided with at least two steps, and the voltage of each step is sequentially reduced.

Optionally, the signals for characterizing the image include a reset signal and an image signal.

Optionally, the first step of the control signal is a transistor on level, and the second step is between the transistor on level and a transistor off level.

More optionally, the second step is between the transistor turn-on level and a threshold voltage of a corresponding transistor.

Optionally, the method for reducing fixed pixel image noise further comprises: resetting each pixel before the global exposure.

Optionally, the at least two steps include one step that is the turn-on level of the corresponding transistor and at least one step that is greater than the threshold voltage of the corresponding transistor.

More optionally, the method for reducing fixed pixel image noise further includes: and adjusting the conversion gains of the reset signal and the image signal based on the gain control signal to respectively acquire a reset signal and an image signal with high conversion gain and/or low conversion gain.

More optionally, during the sampling phase:

setting a conversion gain mode;

turning on a first control transistor to store the reset signal to a first capacitor;

turning off the first control transistor;

Transferring the exposure charge to a floating diffusion point;

turning on a second control transistor to store the image signal to a second capacitor;

turning off the second control transistor;

in the readout phase:

turning on a pixel selection transistor and reading out the reset signal;

turning on a third control transistor to read out half of the sum of the reset signal and the image signal;

turning off the third control transistor;

and the voltage of the control terminal when at least one of the first control transistor, the second control transistor and the third control transistor is turned on and off is the step level.

More optionally, the step arrangement of the corresponding transistor employing the step level in each of the pixels is uniform.

To achieve the above and other related objects, the present invention provides a pixel circuit, which is suitable for the above method for reducing noise of a fixed image, and includes at least:

a storage control module connected to the floating diffusion points for storing signals for characterizing the image based on the capacitances, respectively;

in the sampling stage, the control signals of the transistors for sampling the reset signal and the image signal in the storage control module are step levels, the step levels have at least two steps, and the voltage of each step is reduced in sequence.

Optionally, the storage control module includes at least one storage control unit, where the storage control units include a reset voltage signal transmission branch and an image voltage signal transmission branch, and are respectively configured to transmit and store the reset signal and the image signal, where the reset voltage signal transmission branch includes a first control transistor and a first capacitor, the image voltage signal transmission branch includes a second control transistor and a second capacitor, and the storage control unit further includes a third control transistor, where:

a first connection of the first control transistor and a first connection of the second control transistor are coupled to the floating diffusion point; the control end of the first control transistor is connected with a first control signal, the second connection end of the first control transistor is connected with the first connection end of the third control transistor, and the first control transistor is connected with a first reference potential through the first capacitor; the control end of the second control transistor is connected with a second control signal, and the second connection end of the second control transistor is connected with a second connection end of the third control transistor and is connected with a second reference potential through the second capacitor; and the control end of the third control transistor is connected with a third control signal.

More optionally, each storage control unit further includes: a first source follower transistor, a second source follower transistor, and a pixel selection transistor;

the control end of the first source following transistor is connected to the floating diffusion point, the first connection end is connected with a variable voltage, and the second connection end is connected with the first connection end of the first control transistor and the first connection end of the second control transistor;

the control end of the second source following transistor is connected with the first connecting end of the third control transistor, the first connecting end is connected with a first power supply voltage, and the second connecting end is connected with the first connecting end of the pixel selection transistor;

the control end of the pixel selection transistor is connected with a pixel selection signal, and the second connection end is used as the output end of the corresponding storage control unit.

More optionally, the storage control unit is configured to store a reset signal and an image signal of a high conversion gain and/or a low conversion gain, the storage control unit is connected to the floating diffusion point, and store the reset signal and the image signal of a corresponding conversion gain mode based on the storage control signal; when the storage control module is used for storing reset signals and image signals with high conversion gain and low conversion gain, the storage control module comprises a high-gain storage control unit and a low-gain storage control unit:

The high-gain storage control unit and the low-gain storage control unit are arranged in parallel and are both connected to a floating diffusion point; the high-gain storage control unit is used for respectively storing a reset signal and an image signal with high conversion gain, and the low-gain storage control unit is used for respectively storing a reset signal and an image signal with low conversion gain.

More optionally, when the high gain storage control unit and the low gain storage control unit exist, the high gain storage control unit and the low gain storage control unit correspond to the same or different column lines so as to realize serial output or parallel output of signals respectively.

Optionally, the pixel circuit further includes: the photosensitive control module and the resetting module; wherein,,

the photosensitive control module is connected between the floating diffusion point and a third reference potential, is controlled by a transmission control signal, and is used for generating exposure charges according to a photoelectric effect and transferring and outputting the exposure charges according to the transmission control signal;

the reset module comprises a reset transistor, wherein the control end of the reset transistor is connected with a reset control signal, the first connecting end of the reset transistor is connected with a second power supply voltage, and the second connecting end of the reset transistor is connected to the floating diffusion point.

More optionally, the pixel circuit further includes:

the gain control module receives a gain control signal to enable the pixel circuit to work in different conversion gain modes, wherein the different conversion gain modes comprise a high gain conversion mode and a low gain conversion mode;

the storage control module is used for respectively storing a reset signal and an image signal with high conversion gain and/or respectively storing a reset signal and an image signal with low conversion gain.

To achieve the above and other related objects, the present invention provides an image sensor including at least:

a control circuit, a readout circuit, and the pixel circuit;

the control circuit provides control signals for the readout circuit and the pixel circuit; the readout circuit is connected to the output end of the pixel circuit and is used for reading out the reset signal and the image signal in the pixel circuit.

As described above, the pixel circuit, the image sensor, and the method of reducing pixel fixed image noise of the present invention have the following advantageous effects:

1. the pixel circuit, the image sensor and the method for reducing the pixel fixed image noise set the control signal of the transistor for sampling the signal representing the image in the sampling stage as the step level, so that the difference value between the gate terminal voltage and the threshold voltage when the transistor is turned off is reduced, the influence of the channel charge injection effect on the pixel is further reduced, and the fixed image noise is reduced.

2. According to the pixel circuit, the image sensor and the method for reducing the pixel fixed image noise, under the condition that the threshold voltage is unknown, the steps are arranged to capture the position of the threshold voltage, so that the difference value between the gate terminal voltage and the threshold voltage is reduced when the transistor is turned off, the influence of the channel charge injection effect on the pixel array is improved, and the fixed noise is reduced.

3. The pixel circuit and the image sensor adopt the structure of three control transistors, so that the complexity of control time sequence can be greatly reduced, and the working efficiency is improved.

Drawings

Fig. 1 is a schematic diagram of a pixel circuit according to the present invention.

Fig. 2 is a schematic diagram of another structure of the pixel circuit of the present invention.

Fig. 3 is a schematic diagram of a pixel circuit according to another embodiment of the present invention.

Fig. 4 is a schematic diagram of still another structure of the pixel circuit according to the present invention.

Fig. 5 is a schematic diagram of an image sensor according to the present invention.

Fig. 6 shows a control timing diagram of a method for reducing pixel fixed image noise according to the present invention.

Fig. 7 is a schematic diagram showing a method for reducing noise of a fixed pixel image according to the present invention.

Fig. 8 is a schematic diagram showing another control timing of the method for reducing pixel fixed image noise according to the present invention.

Description of element reference numerals

1. Pixel circuit

11. Storage control module

111. First storage control module

112. High gain memory control unit

113. Low gain memory control unit

12. Photosensitive control module

13. Reset module

14. Gain control module

2. Reading circuit

3. Control circuit

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the spirit of the invention, and various modifications and adaptations of the invention may be made to the details of the present description based on various points of view and applications.

Please refer to fig. 1-8. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

As shown in fig. 1, the present embodiment proposes a pixel circuit 1, the pixel circuit 1 including:

a memory control module 11, connected to the floating diffusion point, for storing signals for characterizing the image based on capacitance.

Specifically, the storage control module 11 includes at least one storage control unit. In this embodiment, the storage control module 11 includes a first storage control module 111 for storing a reset signal, an image signal, of a high conversion gain or a low conversion gain; the first storage control unit 111 includes a reset voltage signal transmission branch and an image voltage signal transmission branch, which are respectively used for transmitting and storing the reset signal and the image signal, wherein the reset voltage signal transmission branch includes a first control transistor M1 and a first capacitor C1, the image voltage signal transmission branch includes a second control transistor M2 and a second capacitor C2, and the first storage control unit 111 further includes a third control transistor M3. A first connection terminal of the first control transistor M1 and a first connection terminal of the second control transistor M2 are coupled to the floating diffusion FD; the control end of the first control transistor M1 is connected with a first control signal gs_rst2, the second connection end is connected with the first connection end of the third control transistor M3, and the second connection end is connected with a first reference potential through the first capacitor C1; the control end of the second control transistor M2 is connected with a second control signal gs_sig, and the second connection end of the second control transistor M2 is connected with a second connection end of the third control transistor M3 and is connected with a second reference potential through the second capacitor C2; the control end of the third control transistor M3 is connected to a third control signal gs_rst1.

It should be noted that, as an example, the first control transistor M1, the second control transistor M2, and the third control transistor M3 are all NMOS transistors, and the first connection terminal is a drain terminal, the second connection terminal is a source terminal, and the control terminal is a gate terminal; the first reference potential and the second reference potential are both ground potentials; in practical use, the corresponding device types may be selected according to the needs, and the first reference potential and the second reference potential may be set, where the device types of the control transistors may be different, and the levels of the first reference potential and the second reference potential may also be different, which is not limited by the embodiment.

Specifically, channel charge injection effect influencing factors are: the channel charge of the inversion layer of the MOSFET in the on state is as follows:

Q _ch ＝WLC _OX (V _g -V _in -V _TH )；

wherein V is _g Is a gridPolar voltage, V _TH V is the threshold voltage of the transistor _in Is the source voltage of the transistor. When V is _g And V is equal to _TH The greater the difference in (b) is, the more serious the channel charge injection is when the MOSFET is turned off; during sampling, when the control signals gs_rst1, gs_sig, gs_rst2 change from high level to low level, charges are injected into the first capacitor C1 and the second capacitor C2, thereby causing fixed image noise. In the sampling stage, the control signals of transistors for sampling the reset signals and the image signals in the storage control module 11 are set to be step levels; in this embodiment, the control signal of at least one of the first control transistor M1, the second control transistor M2, and the third control transistor M3 is a step level, the step level has at least two steps, and the voltage of each step is sequentially reduced. Based on the step level setting, the amount of charge overflowed by the channel charge injection effect can be effectively reduced, and then the fixed pattern noise of the pixel is reduced. In one example, the first control transistor M1 and the second control transistor M2 are both selected to be the step level.

Specifically, when the first memory control unit 111 is reset, the first control transistor M1 and the second control transistor M2 are turned on, the first capacitor C1 is reset by the first control transistor M1, and the second capacitor C2 is reset by the second control transistor M2. When the reset signal is sampled, the first control transistor M1 is conducted, and the reset signal is stored in the first capacitor C1; when sampling the image signal, the second control transistor M2 is turned on, and the image signal is stored in the second capacitor C2. For the structure of two control transistors, it is necessary to repeatedly turn on and off the control transistors to realize reset and sampling, and it is apparent that the control timing of the pixel circuit 1 of the present embodiment is greatly simplified.

As shown in fig. 1, as another implementation manner of the present invention, the first storage control unit 111 further includes: a first source follower transistor M4, a second source follower transistor M5, and a pixel select transistor M6. The control end of the first source follower transistor M4 is connected to the floating diffusion point FD, the first connection end is connected to the variable voltage VRSF, and the second connection end is connected with the first connection end of the first control transistor M1 and the first connection end of the second control transistor M2; the control end of the second source follower transistor M5 is connected to the first connection end of the third control transistor M3, the first connection end is connected to the first power supply voltage VDD1, and the second connection end is connected to the first connection end of the pixel selection transistor M6; the control terminal of the pixel selection transistor M6 is connected to the pixel selection signal gs_sel, and the second connection terminal is used as the output terminal pixout of the corresponding memory cell.

It should be noted that, as an example, the first source follower transistor M4, the second source follower transistor M5, and the pixel selection transistor M6 all use NMOS transistors, and the first connection terminal is a drain terminal, the second connection terminal is a source terminal, and the control terminal is a gate terminal; the first reference potential and the second reference potential are both ground potentials; in practical use, the corresponding device types may be selected according to the needs, and the device types of the transistors may be different, which is not limited by the present embodiment.

As shown in fig. 1, as another implementation of the present invention, the pixel circuit 1 further includes: the photosensitive control module 12 and the reset module 13. The photosensitive control module 12 is connected between the floating diffusion FD and a third reference potential, and is controlled by a transmission control signal tx, for generating an exposure charge according to a photoelectric effect, and transferring and outputting the exposure charge according to the transmission control signal tx. As an example, the photosensitive control module 12 includes a photodiode PD and a transfer transistor M7; the anode of the photodiode PD is connected with the third reference potential, and the cathode of the photodiode PD is connected with the second connection end of the transmission transistor M7; the first connection terminal of the transmission transistor M7 is connected to the floating diffusion FD, and the control terminal is connected to the transmission control signal tx. The reset module 13 includes a reset transistor M8, a control terminal of the reset transistor M8 is connected to a reset control signal rst, a first connection terminal is connected to a second power supply voltage VDD2, and a second connection terminal is connected to the floating diffusion FD.

It should be noted that, as an example, the transmission transistor M7 and the reset transistor M8 are NMOS transistors, and the first connection terminal is a drain terminal, the second connection terminal is a source terminal, and the control terminal is a gate terminal; the third reference potential is ground potential; the second power supply voltage VDD2 is equal to the first power supply voltage VDD 1; in practical use, the corresponding device types can be selected according to the needs, the device types of the transistors can be different, and the power supply voltages can be different, not limited by the embodiment.

As shown in fig. 1, as another implementation of the present invention, the pixel circuit 1 further includes: gain control module 14. The gain control module 14 receives the gain control signal dcg to make the pixel circuit 1 operate in different conversion gain modes, including a high gain conversion mode and a low gain conversion mode. The gain control module 14 is connected between the second connection terminal of the reset transistor M8 and the floating diffusion FD, and adjusts the equivalent charge storage capacity of the floating diffusion FD based on the gain control signal dcg, so that the first storage control module 111 stores the reset signal and the image signal with high conversion gain or stores the reset signal and the image signal with low conversion gain respectively, i.e. the high gain or the low gain is adjustable, but is not limited to one type. As an example, the gain control module 14 includes a gain control transistor M9 and a gain adjustment capacitance Cdcg; the control end of the gain control transistor M9 is connected to the gain control signal dcg, a first connection end is connected to the second connection end of the reset transistor M8, and is connected to the fourth reference potential through the gain adjustment capacitor Cdcg, and the second connection end is connected to the floating diffusion FD.

It should be noted that, as an example, the gain control transistor M9 adopts an NMOS transistor, where a first connection terminal is a drain terminal, a second connection terminal is a source terminal, and a control terminal is a gate terminal; the fourth reference potential is ground potential; in practical use, the corresponding device types can be selected according to the needs, and the embodiment is not limited to the above; the gain adjustment capacitance Cdcg may be a parasitic capacitance of the connection point of the reset transistor M8 and the gain control transistor M9 to ground, or may be a device capacitance (i.e., an external capacitor).

Example two

As shown in fig. 2, the present embodiment provides a pixel circuit 1, which is different from the first embodiment in that the storage control module 11 includes a high gain storage control unit 112 and a low gain storage control unit 113, and the storage control module 11 is configured to store a reset signal and an image signal of high conversion gain and low conversion gain.

As shown in fig. 2, the high gain memory control unit 112 and the low gain memory control unit 113 are disposed in parallel and are both connected to the floating diffusion FD; the high gain storage control unit 112 is configured to store a reset signal and an image signal of a high conversion gain, respectively, and the low gain storage control unit 113 is configured to store a reset signal and an image signal of a low conversion gain, respectively.

Specifically, in this embodiment, the high-gain storage control unit 112 and the low-gain storage control unit 113 have the same structure as the first storage control module 111, and the control signals are adaptively adjusted. The high gain memory control unit 112: the control end of the first control transistor M1 is connected to a first high gain control signal gs_rst2h, the control end of the second control transistor M2 is connected to a second high gain control signal gs_sigh, the control end of the third control transistor M3 is connected to a third high gain control signal gs_rst1h, the first connection end of the first source follower transistor M4 is connected to a first variable voltage VRSF1, the first connection end of the second source follower transistor M5 is connected to a third power supply voltage VDD3, the control end of the pixel select transistor M6 is connected to a high gain row select signal gs_selh, and the second connection end of the pixel select transistor M6 is used as a high gain output end pixouth of a corresponding memory cell. The low gain memory control unit 112: the control end of the first control transistor M1 is connected to a first low-gain control signal gs_rst2l, the control end of the second control transistor M2 is connected to a second low-gain control signal gs_sigl, the control end of the third control transistor M3 is connected to a third low-gain control signal gs_rst1l, the first connection end of the first source follower transistor M4 is connected to a second variable voltage VRSF2, the first connection end of the second source follower transistor M5 is connected to a fourth power supply voltage VDD4, the control end of the pixel select transistor M6 is connected to a low-gain row select signal gs_sell, and the second connection end of the pixel select transistor M6 is used as a low-gain output end pixtl of a corresponding memory cell. At this time, the high gain memory control unit 112 and the low gain memory control unit 113 correspond to different column lines to realize parallel output of signals.

It is to be noted that, as an example, the first variable voltage VRSF1 and the second variable voltage VRSF2 have equal values; the third power supply voltage VDD3 is equal to the fourth power supply voltage VDD4 in value and equal to the second power supply voltage VDD2 in value; each reference potential in the high gain memory control unit 112 and the low gain memory control unit 113 is a ground potential; in practical use, the values of the variable voltages, the values of the power supply voltages and the levels of the reference potentials can be set as required, and the embodiment is not limited thereto.

As shown in fig. 3, as another implementation of the present invention, the first source follower transistor M4 in the high gain memory control unit 112 and the low gain memory control unit 113 are shared. As shown in fig. 4, as another implementation manner of the present invention, the high gain storage control unit 112 and the low gain storage control unit 113 correspond to the same column line to realize serial output of signals.

Specifically, the memory control module 11 of the present embodiment may acquire the reset signal of the high conversion gain, the image signal, and the reset signal of the low conversion gain, the image signal based on the high gain memory control unit 112 and the low gain memory control unit 113 at the same time. Similarly, the control signal of at least one of the first control transistor M1, the second control transistor M2, and the third control transistor M3 in the high-gain memory control unit 112 and the low-gain memory control unit 113 is a step level having at least two steps, and the voltages of the steps decrease in sequence. Based on the step level setting, the amount of charge overflowed by the channel charge injection effect can be effectively reduced, and then the fixed pattern noise of the pixel is reduced.

It should be noted that other circuit structures and principles of the pixel circuit 1 of the present embodiment are similar to those of the embodiments, and are not described herein.

Example III

As shown in fig. 5, the present embodiment provides an image sensor including:

control circuit 3, readout circuit 2, and pixel circuit 1.

The pixel circuit 1 adopts the structure of the first embodiment or the second embodiment, and is not described in detail herein. The control circuit 3 provides control signals to the readout circuit 2 and the pixel circuit 1. The readout circuit 2 is connected to the output end of the pixel circuit 1, and is used for reading out the reset signal and the image signal in the pixel circuit 1, and any circuit structure capable of reading out the reset signal and the image signal of the pixel circuit 1 is suitable for the present invention, and is not described in detail herein.

Example IV

As shown in fig. 6, the present embodiment provides a method for reducing noise of a fixed image of a pixel, in this embodiment, the method is implemented based on the pixel circuit of the first embodiment, and in practical use, any hardware circuit structure capable of implementing the method is applicable, which is not limited to this embodiment. The method for reducing the pixel fixed image noise comprises the following steps:

1) Global exposure is performed for each pixel.

Specifically, as an implementation manner of the present invention, the method for reducing fixed pixel image noise further includes: resetting each pixel before the global exposure; as shown in fig. 6, at time t0, the transfer control signal tx jumps to a high level, the transfer transistor M7 is turned on, and the residual charge in the photodiode PD is discharged, thereby ensuring the accuracy of the detection signal.

Specifically, at time t1, the transfer control signal tx transitions to a low level, the transfer transistor M7 turns off, and then each pixel is exposed, and the photodiode PD in each pixel converts the detected optical signal into an electrical signal.

2) The capacitance storing the signal characterizing the image is reset.

Specifically, in this embodiment, the signals for representing the image include a reset signal and an image signal, and accordingly, the first capacitor C1 is used for storing the reset signal, and the second capacitor C2 is used for storing the image signal. As shown in fig. 6, after the exposure is completed, the variable voltage VRSF is at a low level at time t2-t 5; at time t3-t4, the first control signal gs_rst2 and the second control signal gs_sig jump to a high level, the first control transistor M1 and the second control transistor M2 are turned on, at this time, the first capacitor C1 is discharged through the second control transistor M2, and the second capacitor C2 is discharged through the first control transistor M1, and resets the first capacitor C1 and the second capacitor C2.

At times t3-t4, the row selection signal gs_sel may be at a high level or a low level, and accordingly, the pixel selection transistor M6 may be in an on state or an off state, which is not limited herein. In addition, the signal for representing the image may only include the image signal, and at this time, only the capacitor storing the image signal is reset, which is not described in detail herein.

3) Sampling the signals for representing the image based on the corresponding capacitances respectively; in the sampling stage, the control signal of the transistor for sampling the signal for representing the image is a step level, the step level is provided with at least two steps, and the voltage of each step is sequentially reduced.

Specifically, step 3) includes: turning on the first control transistor M1 to store the reset signal Vrst to the first capacitor C1; turning off the first control transistor M1; transferring the exposed charge to a floating diffusion FD; turning on the second control transistor M2 to store the image signal Vsig to the second capacitor C2; the second control transistor M2 is turned off.

More specifically, at time t6-t15, the reset control signal rst is at low level, and enters a sampling stage. At time t8-t9, the first control signal gs_rst2 is a step level, and the first control transistor M1 is turned on and then turned off; when the first control transistor M1 is turned on, the first capacitor C1 stores a reset signal Vrst. The invention reduces the amount of charge overflowed by channel charge injection effect by setting the step level of at least two steps, wherein the at least two steps comprise one step which is the turn-on level of the corresponding transistor and at least one step which is larger than the threshold voltage of the corresponding transistor. As an example, the step level has two steps, wherein a first step is an on level of the first control transistor M1, and a second step is between the on level and the off level of the first control transistor M1; further, the second step is between the on level of the first control transistor M1 and the threshold voltage of the first control transistor M1. As shown in fig. 7, the first control transistor M1 is controlled to be turned on and off based on a control signal of two steps, and assuming that the actual threshold value of the first control transistor M1 is Vth1 (the second step is between an on level and a threshold voltage), the control signal jumps to the first step at time T0, and the first control transistor M1 is turned on; at time T1, the control signal jumps to a second level, the first control transistor M1 is still in a conducting state, and the first control transistor M1 is turned off when the control signal jumps to a low level (AGND) until time T2; compared with the first step, the difference between the control signal of the first control transistor M1 and the threshold voltage is changed from DeltaV 1 to DeltaV 2 in the second step, and obviously, the difference between the gate terminal voltage and the threshold voltage is reduced in the turn-off process, so that the amount of electric charge overflowed by the channel charge injection effect can be effectively reduced, the amount of overflowed electric charge entering the first capacitor C1 is reduced, and the accuracy of signals is further ensured. As another example, the step level includes two or more steps, the voltage of each step is sequentially reduced, and since the threshold voltage of the control transistor is unknown, the position of the actual threshold voltage can be captured by a plurality of steps, so that the voltage difference of the gate voltage and the threshold voltage can be reduced. As shown in fig. 7, assuming that the actual threshold value of the first control transistor M1 is Vth2 (greater than Vth1, and the same level as that corresponding to the second step), at time T1, the first control transistor M1 may be turned on or off, but the difference between the control signal of the first control transistor M1 and the threshold voltage is Δv3 when turned off, that is, the difference when turned off normally; for the case that the actual threshold is greater than the corresponding level of the second step, the difference between the control signal of the first control transistor M1 and the threshold voltage when the first control transistor M1 is turned off, that is, the difference when the first control transistor M1 is turned off normally.

More specifically, after the sampling of the reset signal is finished, the transmission transistor M7 is turned on at the time t10-t11, and the signal in the photodiode PD is stored to the floating diffusion point FD; at time t12-t13, the second control transistor M2 is turned on and then turned off based on the step level, so as to reduce the amount of charge overflowed by the channel charge injection effect, and the second capacitor C2 stores the image signal Vsig. The step level of the second control signal gs_sig is set in the same manner as the first control signal gs_rst2, and will not be described in detail herein.

Specifically, as another implementation manner of the present invention, the method for reducing fixed pixel image noise further includes: the conversion gains of the reset signal and the image signal are adjusted based on the gain control signal dcg, the reset signal and the image signal with high conversion gain or low conversion gain are respectively obtained, and the conversion gain mode is set before the reset signal Vrst and the image signal Vsig are stored. As shown in fig. 6, at time t7-t14, the gain control signal dcg is set to low level to obtain a reset signal and an image signal with high conversion gain; if at time t7-t14, the gain control signal dcg is set to high level to obtain a reset signal and an image signal with low conversion gain; the present embodiment is not limited to this.

4) Reading out the signal for characterizing the image.

Specifically, step 4) includes: turning on a pixel selection transistor M6, and reading out the reset signal Vrst; turning on a third control transistor M3 to read out half of the sum of the reset signal Vrst and the image signal Vsig; the third control transistor M3 is turned off.

More specifically, after the sampling is completed, at the time t16-t19, the row selection signal gs_sel jumps to a high level, and the reset signal Vrst is read out; at time t17-t18, the third control transistor M3 is turned on and then turned off based on the step level, so as to reduce the amount of charge overflowed by the channel charge injection effect from entering the first capacitor C1 and the second capacitor C2; half of the sum of the reset signal Vrst and the image signal Vsig, i.e. 1/2 (vrst+vsig), is read out.

The control terminal voltage when at least one of the first control transistor M1, the second control transistor M2, and the third control transistor M3 is turned on and off is the step level. Preferably, the control terminal voltages of the first control transistor M1, the second control transistor M2 and the third control transistor M3 are set to the step level when they are turned on and off, so as to minimize the influence of the channel charge injection effect.

As another example, the step settings of the corresponding transistors in each of the pixels employing the step levels are uniform to ensure uniformity of the readout signals. For example, in one example, the first control transistor M1 step arrangement for each pixel in the pixel array is uniform, and the second control transistor M2 step arrangement for each pixel in the pixel array is uniform; of course, in a further example, it is also possible that the first control transistor M1 and the second control transistor M2 for each pixel in the pixel array are arranged in a uniform step, and the first control transistor M1 and the second control transistor M2 are arranged in a uniform step among the pixels.

Example five

As shown in fig. 8, the present embodiment provides a method for reducing fixed image noise of pixels, which is different from the fourth embodiment in that the method for reducing fixed image noise of pixels can obtain reset signals and image signals with high conversion gain and low conversion gain. The method for reducing the pixel fixed image noise comprises the following steps:

1) Global exposure is performed for each pixel.

The specific steps are the same as those of the fourth embodiment, and are not described in detail herein.

2) The capacitance storing the signal characterizing the image is reset.

Specifically, as shown in fig. 8, after the exposure is finished, at time t2-t5, the first variable voltage VRSF1 and the first variable voltage VRSF2 are at low level; at time t3-t4, the first high gain control signal gs_rst2h, the second high gain control signal gs_sigh, the first low gain control signal gs_rst2l, and the second low gain control signal gs_sigl are hopped to be high level, the first control transistor M1 and the second control transistor M2 in the high gain storage control unit 112 and the low gain storage control unit 113 are turned on, at this time, the first capacitor C1 is discharged through the second control transistor M2, the second capacitor C2 is discharged through the first control transistor M1, and the first capacitor C1 and the second capacitor C2 in the high gain storage control unit 112 and the low gain storage control unit 113 are reset.

At times t3 to t4, the high gain row selection signal gs_selh and the low gain row selection signal gs_sell may be at a high level or at a low level, which is not limited herein.

3) Sampling the signals for representing the image based on the corresponding capacitances respectively; in the sampling stage, the control signal of the transistor for sampling the signal for representing the image is a step level, the step level is provided with at least two steps, and the voltage of each step is sequentially reduced.

Specifically, a reset signal of a high conversion gain, an image signal, and a reset signal of a low conversion gain, the image signal are sampled in the set order.

As shown in fig. 8, at time t6-t21, the reset control signal rst is at low level, and enters a sampling stage. At time t7-t8, the first low-gain control signal gs_rst2l is turned on and then turned off based on the step level, so as to store the reset signal Vrstl with low conversion gain in the first capacitor C1 of the low-gain storage control unit 113. At time t9, the gain control signal dcg transitions to a low level. At time t10-t11, the first high-gain control signal gs_rst2h is turned on and then turned off based on the step level, so as to store the reset signal Vrsth with high conversion gain in the first capacitor C1 of the high-gain storage control unit 112. After the sampling of the reset signal is finished, the transmission transistor M7 is turned on at the moment of t12-t13, and the signal in the photodiode PD is stored into the floating diffusion point FD; at time t14-t15, the second high-gain control signal gs_sign turns on and then turns off the second control transistor M2 in the high-gain storage control unit 112 based on the step level to store the high-conversion-gain image signal Vsigh in the second capacitor C2 of the high-gain storage control unit 112. At time t16, the gain control signal dcg transitions to a high level. turning on the transfer transistor M7 at times t17-t18, and storing the signal in the photodiode PD to the floating diffusion FD; at time t19-t20, the second low-gain control signal gs_sig turns on and then turns off the second control transistor M2 in the low-gain storage control unit 113 based on the step level to store the low-conversion-gain image signal Vsigl in the second capacitor C2 of the low-gain storage control unit 113.

It should be noted that the high-low level state of the gain control signal dcg can be interchanged, which is not limited to the present embodiment. The other principles are the same as those of the fourth embodiment, and are not described in detail herein.

4) Reading out the signal for characterizing the image.

Specifically, at time t22-t25, the high gain row selection signal gs_selh and the low gain row selection signal gs_sell are hopped to be high level, and the high conversion gain reset signal Vrsth and the low conversion gain reset signal Vrstl are read out respectively; at time t23-t24, the third high gain control signal gs_rst1h and the third low gain control signal gs_rst1l are turned on and then turned off, respectively, based on the step level, the corresponding third control transistor M3 to read out half of the sum of the high conversion gain reset signal Vrsth and the high conversion gain image signal Vsigh, and half of the sum of the low conversion gain reset signal Vrstl and the low conversion gain image signal Vsigl, i.e., 1/2 (vrsth+vsigh) and 1/2 (vrstl+vsigl), respectively.

In the present embodiment, the parallel readout mode is adopted, and in practical use, the serial readout mode may be adopted, so that the corresponding control timing is adaptively adjusted, which is not limited to the present embodiment. Other principles are the same as those of the fourth embodiment, and are not described in detail herein.

In summary, the present invention provides a pixel circuit, an image sensor and a method for reducing noise of a fixed pixel image, including: performing global exposure on each pixel; resetting a capacitance storing a signal representing an image; sampling the signals for representing the image based on the corresponding capacitances respectively; reading out the signal for representing the image; in the sampling stage, the control signal of the transistor for sampling the signal for representing the image is a step level, the step level is provided with at least two steps, and the voltage of each step is sequentially reduced. The pixel circuit, the image sensor and the method for reducing the fixed image noise of the pixels set the control signal of the transistor used for sampling the signal used for representing the image in the sampling stage as a step level, so that the difference value between the gate terminal voltage and the threshold voltage when the transistor is turned off is reduced, the influence of the channel charge injection effect on each pixel is further reduced, and the fixed image noise is reduced; setting a plurality of steps to capture the position of the threshold voltage under the condition that the threshold voltage is unknown, so that the difference value between the gate terminal voltage and the threshold voltage is reduced to the minimum when the transistor is turned off; by adopting the structure of three control transistors, the complexity of control time sequence can be greatly reduced, and the working efficiency is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations which can be accomplished by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.

Claims (17)

1. A method of reducing fixed pixel image noise, the method comprising:

performing global exposure on each pixel;

resetting a capacitance storing a signal representing an image;

sampling the signals for representing the image based on the corresponding capacitances respectively;

reading out the signal for representing the image;

in the sampling stage, the control signal of the transistor for sampling the signal for representing the image is a step level, the step level is provided with at least two steps, and the voltage of each step is sequentially reduced.

2. The method of reducing pixel fixed image noise of claim 1, wherein: the signal for characterizing the image includes a reset signal and an image signal.

3. The method of reducing pixel fixed image noise of claim 1, wherein: the first step of the control signal is a transistor on level, and the second step is between the transistor on level and the transistor off level.

4. A method of reducing fixed pixel image noise as defined in claim 3, wherein: the second step is between the transistor turn-on level and a threshold voltage of a corresponding transistor.

5. The method of reducing pixel fixed image noise of claim 1, wherein: the method for reducing the fixed pixel image noise further comprises the following steps: resetting each pixel before the global exposure.

6. The method of reducing pixel fixed image noise of claim 1, wherein: the at least two steps include one step that is the turn-on level of the corresponding transistor and at least one step that is greater than the threshold voltage of the corresponding transistor.

7. A method of reducing fixed pixel image noise according to any of claims 1-6, wherein: the method for reducing the fixed pixel image noise further comprises the following steps: and adjusting the conversion gain of the signal for representing the image based on the gain control signal, and respectively acquiring the signal for representing the image under high conversion gain and/or low conversion gain.

8. The method of reducing pixel fixed image noise of claim 7, wherein:

in the sampling phase:

setting a conversion gain mode;

turning on a first control transistor to store the reset signal to a first capacitor;

turning off the first control transistor;

transferring the exposure charge to a floating diffusion point;

turning on a second control transistor to store the image signal to a second capacitor;

turning off the second control transistor;

in the readout phase:

turning on a pixel selection transistor and reading out the reset signal;

turning on a third control transistor to read out half of the sum of the reset signal and the image signal;

turning off the third control transistor;

and the voltage of the control end of at least one of the first control transistor, the second control transistor and the third control transistor is the step level.

9. The method of reducing pixel fixed image noise of claim 8, wherein: the step arrangement of the corresponding transistors using the step level in each pixel is uniform.

10. A pixel circuit adapted for use in a method of reducing pixel fixed image noise according to any one of claims 1-9, said pixel circuit comprising at least:

A storage control module connected to the floating diffusion point for storing a signal for characterizing an image based on the capacitance;

in the sampling stage, the control signals of the transistors for sampling the reset signal and the image signal in the storage control module are step levels, the step levels have at least two steps, and the voltage of each step is reduced in sequence.

11. The pixel circuit of claim 10, wherein: the storage control module comprises at least one storage control unit, the storage control unit comprises a reset voltage signal transmission branch and an image voltage signal transmission branch, the reset voltage signal transmission branch comprises a first control transistor and a first capacitor, the image voltage signal transmission branch comprises a second control transistor and a second capacitor, the storage control unit further comprises a third control transistor, wherein:

a first connection of the first control transistor and a first connection of the second control transistor are coupled to the floating diffusion point; the control end of the first control transistor is connected with a first control signal, the second connection end of the first control transistor is connected with the first connection end of the third control transistor, and the first connection end of the first control transistor is connected with a first reference potential through the first capacitor; the control end of the second control transistor is connected with a second control signal, and the second connection end of the second control transistor is connected with the second connection end of the third control transistor and is connected with a second reference potential through the second capacitor; and the control end of the third control transistor is connected with a third control signal.

12. The pixel circuit of claim 11, wherein: each storage control unit further includes: a first source follower transistor, a second source follower transistor, and a pixel selection transistor;

the control end of the first source following transistor is connected to the floating diffusion point, the first connection end is connected with a variable voltage, and the second connection end is connected with the first connection end of the first control transistor and the first connection end of the second control transistor; the control end of the second source following transistor is connected with the first connecting end of the third control transistor, the first connecting end is connected with a first power supply voltage, and the second connecting end is connected with the first connecting end of the pixel selection transistor;

the control end of the pixel selection transistor is connected with a pixel selection signal, and the second connection end is used as the output end of the corresponding storage control unit.

13. The pixel circuit of claim 11, wherein: the storage control unit is used for storing a reset signal and an image signal of high conversion gain and/or low conversion gain, is connected to the floating diffusion point and stores the reset signal and the image signal of a corresponding conversion gain mode based on the storage control signal; when the storage control module is used for storing reset signals and image signals with high conversion gain and low conversion gain, the storage control module comprises a high-gain storage control unit and a low-gain storage control unit:

The high-gain storage control unit and the low-gain storage control unit are arranged in parallel and are both connected to a floating diffusion point; the high-gain storage control unit is used for respectively storing a reset signal and an image signal with high conversion gain, and the low-gain storage control unit is used for respectively storing a reset signal and an image signal with low conversion gain.

14. The image sensor of claim 13, wherein when the high gain memory control unit and the low gain memory control unit are present, the high gain memory control unit and the low gain memory control unit correspond to the same or different column lines to achieve serial output or parallel output of signals, respectively.

15. The pixel circuit of claim 10, wherein: the pixel circuit further includes: the photosensitive control module and the resetting module; wherein,,

the photosensitive control module is connected between the floating diffusion point and a third reference potential, is controlled by a transmission control signal, and is used for generating exposure charges and transferring and outputting the exposure charges according to the transmission control signal;

the reset module comprises a reset transistor, wherein the control end of the reset transistor is connected with a reset control signal, the first connecting end of the reset transistor is connected with a second power supply voltage, and the second connecting end of the reset transistor is connected to the floating diffusion point.

16. The pixel circuit according to any one of claims 10 to 15, wherein the pixel circuit further comprises:

the gain control module receives a gain control signal to enable the pixel circuit to work in different conversion gain modes, wherein the different conversion gain modes comprise a high gain conversion mode and a low gain conversion mode;

the storage control module is used for storing signals with high conversion gain and/or signals with low conversion gain.

17. An image sensor, the image sensor comprising at least:

control circuitry, readout circuitry and pixel circuitry according to any one of claims 10 to 16;

the control circuit provides control signals for the readout circuit and the pixel circuit; the readout circuit is connected to the output end of the pixel circuit and is used for reading out the reset signal and the image signal in the pixel circuit.

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