CN116417025A

CN116417025A - Power failure processing method, solid state disk and computing device

Info

Publication number: CN116417025A
Application number: CN202310188105.3A
Authority: CN
Inventors: 梁永贵; 姚益民
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-03-01
Filing date: 2023-03-01
Publication date: 2023-07-11

Abstract

The application provides a power failure processing method, a solid state disk and computing equipment. The solid state disk comprises a main control chip, a standby capacitor, a volatile memory chip and at least one nonvolatile memory chip, wherein the standby capacitor, the volatile memory chip and the at least one nonvolatile memory chip are electrically connected with the main control chip; the power-down memory space comprises a part of memory space in at least one nonvolatile memory chip, and the power-down memory space is a single-layer unit type memory space. The problem that the data to be stored in the volatile memory chip cannot be completely written into the nonvolatile memory chip and the data is lost due to the fact that the power supply time of the backup capacitor is short in the related technology is solved.

Description

Power failure processing method, solid state disk and computing device

Technical Field

The application relates to the technical field of solid state disks, in particular to a power failure processing method, a solid state disk and computing equipment.

Background

Solid State Disk (Solid State Disk or Solid State Drive, SSD for short), also called Solid State drive, is a hard Disk made of Solid State electronic memory chip array. In order to improve the read-write performance of the solid state disk, most of the solid state disk writes data into the volatile memory chip first, and then writes the data in the volatile memory chip into the nonvolatile memory chip for permanent storage.

When the solid state disk is powered down, the data of the volatile memory chip can be completely lost, so that the storage effect of the data is affected. In the related art, the solid state disk can be temporarily powered through the standby capacitor arranged in the solid state disk, so that the data in the volatile memory chip can still be written into the nonvolatile memory chip when the solid state disk is powered down.

However, in the related art, the power supply time of the backup capacitor is short, so that the solid state disk cannot write all the data to be stored in the volatile memory chip into the nonvolatile memory chip when the power is turned off, and further the problem of data loss occurs.

Disclosure of Invention

The embodiment of the application provides a power failure processing method, a solid state disk and computing equipment, which are used for solving the problems that in the related art, the power supply time of a standby capacitor is short, and the solid state disk cannot completely write data to be stored in a volatile memory chip into the nonvolatile memory chip when power fails, so that data loss occurs.

In a first aspect, an embodiment of the present application provides a power failure processing method, which is applied to a solid state disk, where the solid state disk includes a main control chip, and a standby capacitor, a volatile memory chip and at least one nonvolatile memory chip that are electrically connected to the main control chip, and the method includes:

when the main control chip detects that the solid state disk is in a power-down state, the backup capacitor is controlled to supply power to the solid state disk, and data to be stored in the volatile memory chip are obtained; wherein the data to be stored comprises data to be stored of various data types;

the main control chip determines a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and stores the data to be stored into the corresponding power-down storage space;

the power-down storage space comprises at least one part of storage space in the nonvolatile memory chip, and the power-down storage space is a single-layer unit type storage space.

The beneficial effects of this embodiment are: on the one hand, the embodiment utilizes the characteristic of high data storage speed of the single-layer unit type storage space, when the solid state disk is in a power-down state, the data to be stored in the volatile memory chip is stored in the single-layer unit type power-down storage space in the nonvolatile memory chip, so that the storage speed of the data to be stored is improved, a large amount of data can be stored in the nonvolatile memory chip within a limited storage time of the solid state disk, the situation that the data to be stored in the volatile memory chip cannot be completely written into the nonvolatile memory chip when the solid state disk is powered down is reduced, and the possibility of losing the data to be stored is further caused. On the other hand, the embodiment can directly determine the corresponding power-down storage space according to the data type of the data to be stored, and store the data to be stored into the corresponding power-down storage space, so that the time-consuming searching of the available power-down storage space is avoided, and the storage speed of the data to be stored is improved.

In the above preferred technical solution of the power-down processing method, the determining, by the main control chip, a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, and storing the data to be stored in the corresponding power-down storage space includes:

the main control chip determines a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, determines a storage channel corresponding to the corresponding power-down storage space, and stores the data to be stored into the corresponding power-down storage space through the corresponding storage channel.

The beneficial effects of this embodiment are: the main control chip can directly determine the power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, determine the storage channel corresponding to the corresponding power-down storage space, and directly store the data to be stored into the corresponding power-down storage space through the corresponding storage channel, so that the time-consuming searching of the available power-down storage space and the corresponding storage channel is avoided, and the storage speed of the data to be stored is improved.

In the above preferred technical solution of the power-down processing method, the main control chip determines, for data to be stored of each data type, a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, determines a storage channel corresponding to the corresponding power-down storage space, and stores the data to be stored into the corresponding power-down storage space through the corresponding storage channel, including:

the main control chip reads a first corresponding relation table and a second corresponding relation table stored in the volatile memory chip, or reads the first corresponding relation table and the second corresponding relation table stored in the nonvolatile memory chip; the first corresponding relation table is a corresponding relation table of a data type and a power-down storage space, and the second corresponding relation table is a corresponding relation table of the power-down storage space and a storage channel;

the main control chip determines a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored and the first corresponding relation table, determines a storage channel corresponding to the corresponding power-down storage space according to the corresponding power-down storage space and the second corresponding relation table, and stores the data to be stored into the corresponding power-down storage space through the corresponding storage channel.

The beneficial effects of this embodiment are: the first corresponding relation table of the data types and the power-down storage space and the second corresponding relation table of the power-down storage space and the storage channel can be stored in the volatile memory chip or the nonvolatile memory chip, and the main control chip can directly read the first corresponding relation table and the second corresponding relation table when the solid state disk is powered down, so that the power-down storage space suitable for storing the data to be stored of each data type and the storage channel leading to the power-down storage space are determined, and the main control chip can quickly store the data to be stored in the power-down storage space, and the storage speed of the data to be stored is improved.

In the above preferred technical solution of power failure processing, the method further includes:

the main control chip generates a power-down data completion identifier corresponding to the data type of the data to be stored after storing the data to be stored into the corresponding power-down storage space through the corresponding storage channel aiming at the data to be stored of each data type, and stores the power-down data completion identifier into the power-down storage space;

and when the main control chip detects that the solid state disk is in a power-on state and the power-down storage space stores the power-down data completion identification, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip.

The beneficial effects of this embodiment are: after the main control chip stores the data to be stored into the corresponding power-down storage space through the corresponding storage channel, generating a power-down data completion identifier corresponding to the data type of the data to be stored so as to indicate that the data to be stored which is required to be stored into the power-down storage space is stored. The main control chip stores the power-down data completion identification into the power-down storage space so that whether the data to be stored are completely stored into the power-down storage space or not can be determined according to whether the power-down data completion identification is stored in the power-down storage space or not, and the integrity check of the main control chip to the data to be stored is realized. In addition, after the main control chip performs integrity check on the data to be stored in the power-down storage space, the data to be stored which is checked successfully is stored in the non-power-down storage space of the nonvolatile memory chip, on one hand, compared with the storage spaces of other non-single-layer unit types, the power-down storage space is small in available capacity of the storage space of the single-layer unit type, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip, and the number of occupied units (cells) of the data to be stored can be reduced; on the other hand, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip, and the data can be cleared in the power-down storage space subsequently, so that the available power-down storage space can be provided for secondary power down of the solid state disk, and the condition of insufficient power-down storage space during secondary power down is prevented.

In the above preferred technical solution of the power-down processing method, when the main control chip detects that the solid state disk is in a power-up state and the power-down storage space stores a power-down data completion identifier, storing the data to be stored in the power-down storage space into a non-power-down storage space of the nonvolatile memory chip, the method includes:

when the main control chip detects that the solid state disk is in a power-on state and the power-down data stored in the power-down storage space is marked after the power-down data is stored, the data to be stored in the power-down storage space are stored in the volatile memory chip;

and the main control chip stores the data to be stored in the volatile memory chip into a non-power-down storage space of the nonvolatile memory chip.

The beneficial effects of this embodiment are: when the main control chip stores the data to be stored in the power-down storage space into the non-power-down storage space of the non-volatile memory chip, the data to be stored in the volatile memory chip can be stored into the non-power-down storage space of the non-volatile memory chip for management, and then the data to be stored in the volatile memory chip can be stored into the non-power-down storage space of the non-volatile memory chip when the main control chip reaches a certain data amount, so that the access times of the non-volatile memory chip are reduced, and the service life of the solid state disk is prolonged.

In the above preferred technical solution of the power-down processing method, when the main control chip detects that the solid state disk is in a power-up state and the power-down storage space stores a power-down data completion identifier, storing the data to be stored in the power-down storage space into a non-power-down storage space of a nonvolatile memory chip, the method includes:

when the main control chip detects that the solid state disk is in a power-on state and the power-down data stored in the power-down storage space is marked after the power-down data is stored, the data to be stored in the power-down storage space are directly stored in the non-power-down storage space of the non-volatile memory chip.

The beneficial effects of this embodiment are: the main control chip can directly store the data to be stored in the acquired power-down storage space into the non-power-down storage space of the nonvolatile memory chip, so that the data storage speed is improved.

In the above preferred technical solution of the power failure processing method, the method further includes:

and the main control chip formats the power-down storage space into the storage space of the single-layer unit type so as to perform data clearing processing on the power-down storage space.

The beneficial effects of this embodiment are: after the main control chip stores the data to be stored in the power-down storage space into the non-power-down storage space, the power-down storage space can be formatted into a single-layer unit type storage space, so that data clearing processing is performed on the power-down storage space, the main control chip does not need to consume time to search the available power-down storage space when the solid state disk is powered down for the second time, the data to be stored can be directly stored into the corresponding power-down storage space, and the data storage speed is improved.

the main control chip determines the data volume of the data to be stored of each data type and the corresponding capacity of each power-down storage space;

the main control chip adjusts the power-down storage space corresponding to the data to be stored according to the data quantity of the data to be stored of each data type and the capacity corresponding to each power-down storage space so as to acquire the adjusted power-down storage space, and determines an adjusted storage channel corresponding to the adjusted power-down storage space;

storing the data to be stored in the corresponding power-down storage space through the corresponding storage channel, including:

And the main control chip stores the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

The beneficial effects of this embodiment are: the main control chip can adjust the power-down storage space corresponding to the data to be stored according to the data quantity of the data to be stored of each data type and the capacity corresponding to each power-down storage space, and acquire the adjusted storage channels corresponding to the adjusted power-down storage space, so that the data to be stored with large data quantity can be stored in the corresponding power-down storage spaces through the storage channels in a segmented and parallel mode, and the storage time of all the data to be stored is shortened.

the main control chip determines the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type;

the main control chip determines the number of the power-down storage spaces corresponding to the data to be stored according to the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type;

the main control chip adjusts the power-down storage space corresponding to the data to be stored according to the number of the power-down storage spaces to obtain the adjusted power-down storage space, and determines an adjusted storage channel corresponding to the adjusted power-down storage space;

The beneficial effects of this embodiment are: the main control chip can determine the number of the power-down storage spaces corresponding to the data to be stored according to the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type, adjust the power-down storage spaces corresponding to the data to be stored according to the number of the power-down storage spaces, and acquire the adjusted storage channels corresponding to the adjusted power-down storage spaces so as to ensure that the data to be stored with higher priority can pass through a plurality of storage channels in parallel in a sectional manner and be quickly stored in the power-down storage spaces, thereby avoiding the problem of power-down loss of the data to be stored with higher priority.

the main control chip determines the abrasion degree of each power-down storage space;

the main control chip adjusts the power-down storage space corresponding to the data to be stored according to the abrasion degree of each power-down storage space to obtain an adjusted power-down storage space, and determines an adjusted storage channel corresponding to the adjusted power-down storage space;

The beneficial effects of this embodiment are: the main control chip adjusts the storage channel and the power-down storage space according to the abrasion degree of the power-down storage space so as to ensure that the main control chip preferentially uses the power-down storage space with low abrasion degree to store data to be stored, and the storage safety of the data to be stored is improved.

In a second aspect, an embodiment of the present application provides a power-down processing apparatus, including:

the control module is used for controlling the preparation electric capacitor to supply power to the solid state disk when the solid state disk is detected to be in a power-down state, and acquiring data to be stored in the volatile memory chip; wherein the data to be stored comprises data to be stored of various data types;

the processing module is used for determining a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and storing the data to be stored into the corresponding power-down storage space;

The power-down storage space comprises part of storage space in at least one nonvolatile memory chip, and the power-down storage space is a single-layer unit type storage space.

In the above preferred technical solution of the power failure processing apparatus, the processing module is specifically configured to:

for data to be stored of each data type, determining a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, determining a storage channel corresponding to the corresponding power-down storage space, and storing the data to be stored into the corresponding power-down storage space through the corresponding storage channel.

The beneficial effects of this embodiment are: the processing module can directly determine the corresponding power-down storage space according to the data type of the data to be stored, determine the storage channel corresponding to the corresponding power-down storage space, and directly store the data to be stored to the corresponding power-down storage space through the corresponding storage channel, so that the time-consuming searching of the available power-down storage space is avoided, and the storage speed of the data to be stored is improved.

reading a first corresponding relation table and a second corresponding relation table stored in the volatile memory chip, or reading the first corresponding relation table and the second corresponding relation table stored in the nonvolatile memory chip; the first corresponding relation table is a corresponding relation table of a data type and a power-down storage space, and the second corresponding relation table is a corresponding relation table of the power-down storage space and a storage channel;

For data to be stored of each data type, determining a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored and the first corresponding relation table, determining a storage channel corresponding to the corresponding power-down storage space according to the corresponding power-down storage space and the second corresponding relation table, and storing the data to be stored into the corresponding power-down storage space through the corresponding storage channel.

The beneficial effects of this embodiment are: the first corresponding relation table of the data types and the power-down storage space and the second corresponding relation table of the power-down storage space and the storage channel can be stored in the volatile memory chip or the nonvolatile memory chip, the processing module can directly read the first corresponding relation table and the second corresponding relation table when the solid state disk is powered down, and the power-down storage space suitable for storing the data to be stored of each data type and the storage channel leading to the power-down storage space are determined, so that the main control chip can quickly store the data to be stored in the power-down storage space, and the storage speed of the data to be stored is improved.

In the above preferred technical solution of the power failure processing apparatus, the processing module is further configured to:

for data to be stored of each data type, after the data to be stored is stored into the corresponding power-down storage space through the corresponding storage channel, generating a power-down data completion identifier corresponding to the data type of the data to be stored, and storing the power-down data completion identifier into the power-down storage space;

when the solid state disk is detected to be in a power-on state and the power-down storage space stores the power-down data completion identification, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip.

The beneficial effects of this embodiment are: after the processing module stores the data to be stored into the corresponding power-down storage space through the corresponding storage channel, generating a power-down data completion identifier corresponding to the data type of the data to be stored so as to indicate that the data to be stored which is required to be stored into the power-down storage space is stored. The processing module stores the power-down data completion identification into the power-down storage space so that whether the data to be stored are completely stored into the power-down storage space or not can be determined according to whether the power-down data completion identification is stored in the power-down storage space or not, and the integrity check of the data to be stored by the processing module is realized. In addition, after the processing module performs integrity check on the data to be stored in the power-down storage space, the data to be stored which is checked to be successful is stored in the non-power-down storage space of the nonvolatile memory chip, on one hand, compared with the storage spaces of other non-single-layer unit types, the power-down storage space is small in available capacity of the storage space of the single-layer unit type, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip, and the number of occupied units (cells) of the data to be stored can be reduced; on the other hand, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip, and the data can be cleared in the power-down storage space subsequently, so that the available power-down storage space can be provided for secondary power down of the solid state disk, and the condition of insufficient power-down storage space during secondary power down is prevented.

when the solid state disk is detected to be in a power-on state and the power-down data stored in the power-down storage space is marked by completion, the data to be stored in the power-down storage space are stored into the volatile memory chip;

and storing the data to be stored in the volatile memory chip into a non-power-down storage space of the nonvolatile memory chip.

The beneficial effects of this embodiment are: when the processing module stores the data to be stored in the power-down storage space into the non-power-down storage space of the nonvolatile memory chip, the data to be stored in the volatile memory chip can be stored into the volatile memory chip for management, and then the data to be stored in the volatile memory chip is stored into the non-power-down storage space of the nonvolatile memory chip, so that the processing module can store the data to be stored in the volatile memory chip into the non-power-down storage space of the nonvolatile memory chip when the data to be stored in the volatile memory chip reaches a certain data amount, the access times of the nonvolatile memory chip are reduced, and the service life of the solid-state hard disk is prolonged.

when the solid state disk is detected to be in a power-on state and the power-down data stored in the power-down storage space is marked, the data to be stored in the power-down storage space is directly stored in the non-power-down storage space of the nonvolatile memory chip.

The beneficial effects of this embodiment are: the processing module can directly store the data to be stored in the acquired power-down storage space into the non-power-down storage space of the nonvolatile memory chip, so that the data storage speed is improved.

and formatting the power-down storage space into the storage space of the single-layer unit type so as to perform data clearing processing on the power-down storage space.

The beneficial effects of this embodiment are: after the processing module stores the data to be stored in the power-down storage space into the non-power-down storage space, the power-down storage space can be formatted into a single-layer unit type storage space so as to carry out data clearing processing on the power-down storage space, so that when the solid state disk is powered down for the second time, the processing module does not need to consume time to search the available power-down storage space, the data to be stored can be directly stored into the corresponding power-down storage space, and the data storage speed is improved.

determining the data quantity of data to be stored of each data type and the corresponding capacity of each power-down storage space;

according to the data volume of the data to be stored of each data type and the corresponding capacity of each power-down storage space, adjusting the power-down storage space corresponding to the data to be stored to obtain an adjusted power-down storage space, and determining an adjusted storage channel corresponding to the adjusted power-down storage space;

The beneficial effects of this embodiment are: the processing module can adjust the power-down storage space corresponding to the data to be stored according to the data quantity of the data to be stored of each data type and the capacity corresponding to each power-down storage space, and acquire the adjusted storage channels corresponding to the adjusted power-down storage space, so that the data to be stored with large data quantity can be stored in the corresponding power-down storage spaces through the storage channels in a segmented and parallel mode, and the storage time of all the data to be stored is shortened.

determining the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type;

determining the number of the power-down storage spaces corresponding to the data to be stored according to the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type;

according to the number of the power-down storage spaces, the power-down storage spaces corresponding to the data to be stored are adjusted to obtain adjusted power-down storage spaces, and an adjusted storage channel corresponding to the adjusted power-down storage spaces is determined;

and storing the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

The beneficial effects of this embodiment are: the processing module can determine the number of the power-down storage spaces corresponding to the data to be stored according to the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type, adjust the power-down storage spaces corresponding to the data to be stored according to the number of the power-down storage spaces, and acquire the adjusted storage channels corresponding to the adjusted power-down storage spaces so as to ensure that the data to be stored with higher priority can pass through a plurality of storage channels in parallel in a sectional manner and be quickly stored in the power-down storage spaces, thereby avoiding the problem of power-down loss of the data to be stored with higher priority.

determining the wear degree of each power-down storage space;

according to the wear degree of each power-down storage space, the power-down storage space corresponding to the data to be stored is adjusted to obtain an adjusted power-down storage space, and an adjusted storage channel corresponding to the adjusted power-down storage space is determined;

The beneficial effects of this embodiment are: the processing module adjusts the storage channel and the power-down storage space according to the abrasion degree of the power-down storage space so as to ensure that the main control chip preferentially uses the power-down storage space with low abrasion degree to store data to be stored, and the storage safety of the data to be stored is improved.

In a third aspect, an embodiment of the present application provides a solid state hard disk, including:

the device comprises a main control chip, a standby capacitor, a volatile memory chip and at least one nonvolatile memory chip, wherein the standby capacitor, the volatile memory chip and the at least one nonvolatile memory chip are electrically connected with the main control chip; wherein, the liquid crystal display device comprises a liquid crystal display device,

the main control chip is used for controlling the standby capacitor to supply power to the solid state disk when the solid state disk is detected to be in a power-down state, and acquiring data to be stored in the volatile memory chip; wherein the data to be stored comprises data to be stored of various data types;

The main control chip is further used for determining a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and storing the data to be stored into the corresponding power-down storage space through a corresponding storage channel;

In a fourth aspect, an embodiment of the present application provides a computing device, including a motherboard and a solid state disk described in the third aspect;

the solid state disk comprises a hard disk connector;

and the main board is connected with the solid state disk through the main board interface and the hard disk connector.

In a fifth aspect, an embodiment of the present application provides a computer readable storage medium, where computer execution instructions are stored in the computer readable storage medium, where the computer execution instructions are used to implement the power failure processing method of the solid state disk in the first aspect when executed by a processor.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the following description will briefly describe the drawings that are required to be used in the embodiments or the related technical descriptions, and it is obvious that, in the following description, the drawings are some embodiments of the present application, and other drawings may be obtained according to the drawings without any inventive effort to those skilled in the art.

FIG. 1 is a block diagram of a solid state disk according to an embodiment of the present disclosure;

fig. 2 is a schematic flow chart of a first embodiment of a power failure processing method provided in the embodiments of the present application;

fig. 3 is a schematic flow chart of a second embodiment of a power failure processing method provided in the embodiment of the present application;

fig. 4 is a schematic flow chart of a third embodiment of a power failure processing method provided in the embodiment of the present application;

fig. 5 is a schematic flow chart of a fourth embodiment of a power failure processing method provided in the embodiments of the present application;

fig. 6 is a schematic flow chart of a fifth embodiment of a power failure processing method provided in the embodiments of the present application;

fig. 7 is a schematic structural diagram of an embodiment of a power failure processing device according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which a person of ordinary skill in the art would have, based on the embodiments in this application, come within the scope of protection of this application.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims of this application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Noun interpretation:

solid State Disk (Solid State Disk or Solid State Drive, abbreviated as SSD): also known as solid state drives, are hard disks made with arrays of solid state electronic memory chips.

A memory chip: belongs to a general integrated circuit, and is a specific application of the concept of an embedded system chip in the storage industry. By embedding software in a single chip, multifunction and high performance are achieved, as well as support for multiple protocols, multiple hardware, and different applications. The most commonly used memory chips in the market include volatile memory chips (e.g., dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM)) and nonvolatile memory chips (e.g., flash memory chips NAND Flash).

Storage channel: and the link path between the main control chip and the nonvolatile memory chip is used for issuing IO read-write operation and control commands to the nonvolatile memory chip, and at least one nonvolatile memory chip can be connected below each storage channel.

Flash translation layer (Flash Translation Layer, FTL) map: and a corresponding relation conversion table of a logical block address (Logical Block Address, abbreviated as LBA) maintained in the solid state disk and a flash memory space allocation range (Physical Block Address, abbreviated as PBA) in the actual solid state disk. The actual physical location of storage of the data to be stored can be controlled by the table.

In the related art, when the solid state disk is in a power-down state, the standby capacitor arranged in the solid state disk can supply power to the solid state disk for a short time, so that the main control chip can write data in the volatile memory chip into the nonvolatile memory chip. However, the power supply time of the backup capacitor of the solid state disk is short, so that when the solid state disk is powered down, the data to be stored in the volatile memory chip cannot be completely written into the nonvolatile memory chip, and further the problem of data loss is caused.

Based on the technical problems, the embodiment of the application provides a method for improving the speed of a main control chip for storing data to be stored into a nonvolatile memory chip when a solid state disk is powered down.

The power failure processing scheme of the solid state disk in the embodiment of the application is described in detail below.

For example, fig. 1 is a block diagram of a solid state disk provided in an embodiment of the present application, as shown in fig. 1, the solid state disk 10 may include: a main control chip 101, a volatile memory chip 102, at least one nonvolatile memory chip, and a standby capacitor 103. By way of example, fig. 1 shows four non-volatile memory chips, non-volatile memory chip 104, non-volatile memory chip 105, non-volatile memory chip 106, and non-volatile memory chip 107, respectively. The main control chip 101 is connected to the nonvolatile memory chip 104 through a first memory channel, is connected to the nonvolatile memory chip 105 through a second memory channel, is connected to the nonvolatile memory chip 106 through a third memory channel, and is connected to the nonvolatile memory chip 107 through a third memory channel. It should be noted that one memory channel may correspond to at least one nonvolatile memory chip. It should be noted that, the main control chip 101 may be connected to the volatile memory chip 102 through a volatile memory channel, and the main control chip 101 may be electrically connected to the spare capacitor 103.

In addition, the solid state disk 10 may also include a hard disk connector (not shown in FIG. 1) so that the solid state disk 10 may be connected to a computing device through the hard disk connector. The computing device may be a terminal device (such as a mobile phone, a computer), a server, etc.

It should be noted that, the main control chip 101 is used as a control unit of the solid state disk 10 to coordinate the operation and data storage of the whole solid state disk 10. For example, the data to be stored in the volatile memory chip 102 needs to be stored in the nonvolatile memory chip via the main control chip 101, that is, the main control chip 101 may acquire the data to be stored in the volatile memory chip 102 and store the data to be stored in the nonvolatile memory chip. It should be noted that, the main control Chip 101 may be a System on Chip (SoC), the main control Chip 101 may be a micro control unit (Micro Control Unit, MCU), and the main control Chip 101 may be other chips with control processing capability.

It should be noted that, the backup capacitor 103 is a backup power supply device disposed on the solid state disk 10, for example, the backup capacitor 103 may be a battery backup unit (Backup Battery Unit, abbreviated as BBU) or an uninterruptible power supply (Uninterruptible Power Supply, abbreviated as UPS).

The volatile memory chip 102 is used as a storage unit for temporarily storing data in the solid state disk 10, and has the characteristic of losing data when power is lost. The volatile memory chip 102 may be a dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM), a static random access memory (Static Random Access Memory, abbreviated as SRAM), or other chips that require power to store data.

The nonvolatile memory chip is used as a storage unit for permanently storing data of the solid state disk 10, and has the characteristic of storing data even if power is lost. The nonvolatile Memory chip may be a Read Only Memory (ROM), a programmable ROM (Programmable Read Only Memory PROM), an electrically rewritable ROM (Electrically Alterable Read Only Memory, EAROM), a Flash Memory, or other chips that do not require power supply and can also store data.

It should be noted that, fig. 1 is only a block diagram of a solid state disk provided by an embodiment of the present application, and the embodiment of the present application does not limit actual forms of various devices included in fig. 1, nor limit an interaction manner between devices in fig. 1, and in application of the solution, the configuration may be set according to actual requirements.

The technical solutions of the embodiments of the present application are described in detail below by means of specific embodiments. It should be noted that the following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

Fig. 2 is a schematic flow chart of a first embodiment of a power failure processing method provided in the embodiment of the present application. Referring to fig. 2, the method specifically includes the steps of:

s201: when the main control chip detects that the solid state disk is in a power-down state, the preparation electric capacitor is controlled to supply power to the solid state disk, and data to be stored in the volatile memory chip are obtained.

In this embodiment, when the solid state disk is plugged into the motherboard of the computing device through the hard disk connector, the computing device may supply power to the solid state disk. The main control chip can control the computing device to serve as a main power supply device so that the computing device can supply power to the solid state disk in a whole mode, namely, the main control chip, the volatile memory chip and the nonvolatile memory chip are controlled to be powered by the computing device.

The main control chip can detect whether the solid state disk is in a power-down state, that is, detect whether the computing equipment is currently used as a main power supply device, and carry out whole-disk power supply on the solid state disk through the hard disk connector. In one implementation manner, the main control chip can determine whether the solid state disk is in a power-down state according to whether a power supply current value for supplying power to the solid state disk by the computing device is lower than a preset current value. In one implementation manner, the main control chip can determine whether the solid state disk is in a power-down state according to whether a power supply voltage value for supplying power to the solid state disk by the computing device is lower than a preset voltage value. In one implementation manner, the main control chip can determine whether the solid state disk is in a power-down state according to whether the power supply frequency of the computing device for supplying power to the solid state disk is smaller than a preset power supply frequency.

When the main control chip detects that the solid state disk is in a power-down state, that is, when the computing equipment is determined not to serve as a main power supply device currently for carrying out whole-disk power supply on the solid state disk, the standby capacitor is controlled to carry out whole-disk power supply on the solid state disk. On the one hand, the main control chip controls the preparation electric capacitor to supply power to the solid state disk, so that the main control chip can execute the power failure processing method of the solid state disk. On the other hand, as the volatile memory chip is a volatile medium and has the characteristic of losing data when power is lost, the main control chip controls the preparation electric capacitor to supply power to the solid state disk, so that the data to be stored in the volatile memory chip can be prevented from being lost due to power failure of the volatile memory chip.

In addition, when the main control chip detects that the solid state disk is in a power-down state, the main control chip can also acquire data to be stored in the volatile memory chip, wherein the data to be stored comprises data to be stored of various data types. For example, the data to be stored includes data to be stored of a user data type, data to be stored of a metadata type, FTL data type data to be flushed.

S202: the main control chip determines a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and stores the data to be stored into the corresponding power-down storage space.

In this embodiment, the solid state disk includes a plurality of memory Channels (CH) therein, and each CH corresponds to at least one Chip Enable (CE), that is, each memory Channel corresponds to at least one nonvolatile memory Chip. Each CE includes a plurality of cores (DIE), each DIE includes a plurality of planes (planes), each Plane includes a plurality of blocks (blocks), wherein the blocks are minimum erasure units. Each Block includes a plurality of pages (pages), where a Page is the smallest unit of reading and writing. Each Page includes a plurality of cells (cells), where a Cell is the smallest data storage unit.

The cells in the nonvolatile memory chip may be divided into a Single-Level Cell (SLC) type, a double-Level Cell (MLC) type, a triple-Level Cell (TLC) type, and the like according to the number of bits stored. In the SLC type memory space, each cell stores 1 bit of data; in the MLC-type memory space, each cell stores 2 bits of data; in a TLC type memory space, each cell stores 3 bits of data. The more bits stored at a time on a cell, the greater the capacity the cell has. In addition, it should be noted that the write latency of the SLC type memory space is 200-300 microseconds, the write latency of the MLC type memory space is 600-900 microseconds, and the write latency of the TLC type memory space is 900-1350 microseconds, that is, the SLC type memory space has the fastest memory speed.

The main control chip can format part of storage space in at least one nonvolatile memory chip in the solid state disk into single-layer unit type storage space, and determine the storage space as power-down storage space. The power-down storage space comprises power-down storage spaces corresponding to data to be stored of various data types.

In one implementation, the main control chip may format, based on an initialization instruction sent by the computing device, a portion of a storage space in at least one nonvolatile memory chip in the solid state disk into a single-layer unit type storage space when the solid state disk is initialized, and determine the storage space as a power-down storage space. It should be noted that, the power-down storage space may be a part of storage space in one nonvolatile memory chip under one storage channel, and may be all storage space in one nonvolatile memory chip under one storage channel; may be part of the memory space in a plurality of non-volatile memory chips under one memory channel; may be all of the memory space in the plurality of non-volatile memory chips under one memory channel; and part or all of the storage space in one or more nonvolatile memory chips corresponding to the storage channels respectively can be also used. This embodiment is not limited thereto. It should be further noted that, in one implementation, the power-down storage space may also be part or all of at least one single storage particle (non-volatile memory chip (such as an aoteng chip)) with higher performance, which is externally connected to the solid state disk.

In another implementation manner, the main control chip may format a part of storage space in at least one nonvolatile memory chip in the solid state disk into a single-layer unit type storage space based on an initialization instruction sent by the computing device at any time when the solid state disk is not in a power-down state, and determine the storage space as the power-down storage space.

In still another implementation manner, when the solid state disk is in a power-down state, the main control chip may format a portion of the storage space in at least one nonvolatile memory chip in the solid state disk into a single-layer unit type storage space based on information that the capacity of the power-down storage space cannot meet the current storage requirement, and determine the storage space as the power-down storage space.

Specifically, data to be stored in the nonvolatile memory chips is stored in each cell of each nonvolatile memory chip in a charged manner. When the main control chip formats part of storage space in the nonvolatile memory chip into a single-layer unit type storage space, the number of threshold voltages of Cell storage data corresponding to the part of storage space in at least one nonvolatile memory chip is modified, and the part of storage space in at least one nonvolatile memory chip in the solid state disk is formatted into the single-layer unit type storage space. Illustratively, when the number of threshold voltages is 1, the memory space is a single-layer cell type, when the number of threshold voltages is 3, the memory space is a double-layer cell type, and when the number of threshold voltages is 7, the memory space is a triple-layer cell type.

In this embodiment, the main control chip may determine, according to the data type of the data to be stored, a corresponding power-down storage space for each data type of the data to be stored, and directly store the data to be stored into the corresponding power-down storage space. Specifically, based on the fact that the main control chip is connected with the nonvolatile memory chip through the storage channel, that is, the main control chip stores data to be stored into the power-down storage space through the storage channel, when the power-down storage space corresponding to the data to be stored is determined, the main control chip can determine the storage channel corresponding to the power-down storage space, and store the data to be stored into the corresponding power-down storage space through the corresponding storage channel.

It should be noted that, the first corresponding relation table of the data type of the data to be stored and the power-down storage space can be stored in the volatile memory chip, and the second corresponding relation table of the power-down storage space and the storage channel is stored; the nonvolatile memory chip can also store a first corresponding relation table of the data type of the data to be stored and the power-down storage space, and store a second corresponding relation table of the power-down storage space and the storage channel. After the main control chip controls the standby capacitor to supply power to the solid state disk, the two corresponding relation tables stored in the volatile memory chip can be read, or the two corresponding relation tables stored in the nonvolatile memory chip can be read, so that a power-down storage space corresponding to the data to be stored is determined according to the first corresponding relation table and the data type of the data to be stored, and a storage channel corresponding to the power-down storage space is determined according to the corresponding power-down storage space and the second corresponding relation table, so that the data to be stored is stored into the corresponding power-down storage space through the corresponding storage channel.

It should be further noted that, when the main control chip stores the data to be stored of each data type into the corresponding power-down storage space through the corresponding storage channel, the main control chip stores the data to be stored of multiple data types into the corresponding power-down storage space through the corresponding storage channel. For example, after determining that the data to be stored includes the data to be stored of the user data type and the data to be stored of the metadata type, the main control chip may determine, according to the first correspondence table and the second correspondence table, that the data to be stored of the user data type, the corresponding power-down storage space is a first power-down storage space, and determine that a storage channel corresponding to the first power-down storage space is a first storage channel; the main control chip can determine the data to be stored of the metadata type according to the first corresponding relation table and the second corresponding relation table, the corresponding power-down storage space is a second power-down storage space and a third power-down storage space, and the storage channels corresponding to the second power-down storage space and the third power-down storage space are a second storage channel and a third storage channel, wherein the second power-down storage space corresponds to the second storage channel, and the third power-down storage space corresponds to the third storage channel. The main control chip can divide the data to be stored in the metadata type to obtain the first data to be stored in the metadata type and the second data to be stored in the metadata type. The main control chip can store the data to be stored of the user data type into the first power-down storage space through the first storage channel, simultaneously store the first data to be stored of the metadata type into the second power-down storage space through the second storage channel, and simultaneously store the second data to be stored of the metadata type into the third power-down storage space through the third storage channel.

It should be further noted that, when the main control chip formats a part of storage space in at least one nonvolatile memory chip in the solid-state hard disk into a single-layer unit type storage space and determines the storage space as a power-down storage space, that is, when the main control chip determines the power-down storage space, the main control chip may modify the flash memory space allocation range in the flash memory conversion layer mapping table according to the physical position of the power-down storage space, and the main control chip may store the data to be stored acquired from the volatile memory chip to the physical position corresponding to the power-down storage space through the corresponding storage channel according to the flash memory space allocation range in the modified flash memory conversion layer mapping table.

In this embodiment, when the main control chip detects that the solid state disk is in a power failure state, the preparation electric capacitor is controlled to supply power to the solid state disk, and the data to be stored in the volatile memory chip is stored in the power failure storage space of the single-layer unit type in the nonvolatile memory chip by utilizing the characteristic that the storage space of the single-layer unit type is fast in data storage speed, so that the storage speed of the data to be stored is improved, a large amount of data can be stored in the nonvolatile memory chip in a limited storage time of the solid state disk, the possibility that the data to be stored in the volatile memory chip cannot be completely written in the nonvolatile memory chip when the solid state disk is powered down is reduced, and further data loss occurs. In addition, the embodiment can directly determine the power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, determine the storage channel corresponding to the power-down storage space, and store the data to be stored into the corresponding power-down storage space through the corresponding storage channel, so that the search of the available power-down storage space is avoided, and the storage speed of the data to be stored is improved.

On the basis of the first embodiment of the method, a detailed description will be given below of a process of storing the data to be stored in the power-down storage space into the non-power-down storage space of the nonvolatile memory chip after the main control chip stores the data to be stored into the power-down storage space through the second embodiment of the method.

Fig. 3 is a schematic flow chart of a second embodiment of a power failure protection method provided in the embodiment of the present application, where the method specifically includes the following steps:

s301: the main control chip is used for generating a power-down data completion identifier corresponding to the data type of the data to be stored after the data to be stored is stored to the corresponding power-down storage space through the corresponding storage channel aiming at the data to be stored of each data type, and storing the power-down data completion identifier to the power-down storage space.

In this embodiment, for each data type of data to be stored, after the data to be stored is stored in the corresponding power-down storage space through the corresponding storage channel, the main control chip may generate a power-down data completion identifier corresponding to the data type of the data to be stored, and store the power-down data completion identifier in the power-down storage space.

For example, the main control chip may determine, for data to be stored of a user data type, that a power-down storage space corresponding to the data to be stored of the type is a first power-down storage space, and that a storage channel corresponding to the first power-down storage space is a first storage channel. The main control chip can generate a first power-down data completion identifier corresponding to the user data type after storing the data to be stored of the user data type into the first power-down storage space through the first storage channel, and store the first power-down data completion identifier into the first power-down storage space.

For another example, the main control chip can determine, for the data to be stored of the metadata type, that the power-down storage space corresponding to the data to be stored of the metadata type is a second power-down storage space and a third power-down storage space, and determine that the storage channels corresponding to the second power-down storage space and the third power-down storage space are a second storage channel and a third storage channel. The second storage channel is a storage channel of the main control chip leading to the second power-down storage space, and the third storage channel is a storage channel of the main control chip leading to the third power-down storage space. The main control chip can divide the data to be stored of the metadata type to obtain first data to be stored of the metadata type and second data to be stored of the metadata type, and after the first data to be stored of the metadata type is stored in the second power-down storage space through the second channel, the main control chip can generate a second power-down data completion identifier corresponding to the metadata type and store the second power-down data completion identifier in the second power-down storage space. After the second data to be stored of the metadata type is stored in the third power-down storage space through the third channel, the main control chip can generate a third power-down data completion identifier corresponding to the metadata type, and store the third power-down data completion identifier in the third power-down storage space.

S302: when the main control chip detects that the solid state disk is in a power-on state and the power-down data in the power-down storage space is stored to finish identification, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the non-volatile memory chip.

In this embodiment, when the main control chip detects that the solid state disk is in a power-on state, that is, when the solid state disk is not in a power-off state, whether power-off data completion identification is stored in the power-off storage space can be detected. When the main control chip detects that the power-down data stored in the power-down storage space is marked, the main control chip determines that the data to be stored in the power-down storage space is stored, and the main control chip can store the data to be stored in the power-down storage space into the non-power-down storage space of the non-volatile memory chip. In addition, when the main control chip detects that the power-down data in the power-down storage space is not stored for completing identification, the main control chip determines that the data to be stored in the power-down storage space is not stored, and at the moment, the main control chip can repair the data to be stored in the power-down storage space.

In particular, in the process that the main control chip stores the data to be stored in the power-down storage space into the non-power-down storage space of the nonvolatile memory chip, one implementation manner is that the main control chip stores the data to be stored in the power-down storage space into the volatile memory chip so that the volatile memory chip performs data arrangement on the data to be stored, and the main control chip stores the data to be stored in the volatile memory chip into the non-power-down storage space of the nonvolatile memory chip. The other implementation mode is that the main control chip directly stores the data to be stored in the power-down storage space into the non-power-down storage space of the nonvolatile memory chip. It should be noted that, the non-power-down memory space of the nonvolatile memory chip may be a single-layer unit type memory space, a double-layer unit type memory space, or a three-layer unit type memory space, which is not limited in this embodiment.

It should be further noted that, after the main control chip stores the data to be stored in all the power-down storage spaces into the non-power-down storage space of the nonvolatile memory chip, a whole Block (Block) erasing manner may be adopted to format the power-down storage space into a single-layer unit type storage space (idle available power-down storage space) so as to perform data clearing processing on the power-down storage space, so that when the solid state disk is powered down for the second time, the main control chip does not need to consume time to find the available power-down storage space, and directly stores the data to be stored into the corresponding power-down storage space.

In this embodiment, after the main control chip stores the data to be stored in the corresponding power-down storage space through the corresponding storage channel, a power-down data completion identifier corresponding to the type of the data to be stored is generated, so as to indicate that the data to be stored, which needs to be stored in the power-down storage space, has been stored. The main control chip stores the power-down data completion identification into the power-down storage space so that whether the data to be stored are completely stored into the power-down storage space or not can be determined according to whether the power-down data completion identification is stored in the power-down storage space or not, and the integrity check of the main control chip to the data to be stored is realized. In addition, after the main control chip performs integrity check on the data to be stored in the power-down storage space, the data to be stored which is checked successfully is stored in the non-power-down storage space of the nonvolatile memory chip, on one hand, compared with the storage spaces of other non-single-layer unit types, the power-down storage space is small in available capacity of the storage space of the single-layer unit type, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip, and the number of units (cells) occupied by the data to be stored can be reduced; on the other hand, the data to be stored in the power-down storage space is stored in the non-power-down storage space of the nonvolatile memory chip, and the power-down storage space can be subjected to data clearing processing in a whole erasing mode subsequently so as to obtain an idle available power-down storage space, so that the available power-down storage space can be provided for secondary power-down of the solid state disk, and the condition of insufficient power-down storage space during secondary power-down is prevented.

On the basis of the first embodiment of the method, a specific implementation process of determining a storage channel and a power-down storage space for the main control chip and storing data to be stored into the corresponding power-down storage space through the corresponding storage channel is described in detail below through the third embodiment of the method.

Fig. 4 is a schematic flow chart of a third embodiment of a power failure protection method provided in the embodiment of the present application, where the method specifically includes the following steps:

s401: the main control chip determines a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and determines a storage channel corresponding to the corresponding power-down storage space.

In this embodiment, the main control chip may determine, for each data type of data to be stored, a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, and determine a storage channel leading to the power-down storage space.

For example, the main control chip may determine that the power-down storage space corresponding to the user data type is a first power-down storage space, and the storage channel corresponding to the first power-down storage space is a first storage channel, where the first storage channel is a storage channel of the main control chip leading to the first power-down storage space. The main control chip can determine that the power-down storage space corresponding to the metadata type is a second power-down storage space and a third power-down storage space, and the storage channels corresponding to the second power-down storage space and the third power-down storage space are a second storage channel and a third storage channel, wherein the second storage channel is a storage channel of the main control chip leading to the second power-down storage space, and the third storage channel is a storage channel of the main control chip leading to the third power-down storage space.

S402: the main control chip determines the data volume of the data to be stored of each data type and the corresponding capacity of each power-down storage space.

In this embodiment, the main control chip may obtain the data size of the data to be stored of each data type and the capacity corresponding to each power-down storage space.

For example, when the main control chip determines that the data to be stored in the volatile memory chip includes the data to be stored of the user data type and the data to be stored of the metadata type, the data amount of the data to be stored of the user data type may be determined to be 3MB, and the data amount of the data to be stored of the metadata type may be determined to be 1MB. The main control chip can also determine that the power-down storage space corresponding to the user data type is a first power-down storage space, and the capacities of the first power-down storage spaces are all 2MB. The main control chip can also determine that the power-down storage space corresponding to the metadata type is a second power-down storage space and a third power-down storage space, and determine that the capacity corresponding to the second power-down storage space and the third power-down storage space is 2MB.

S403: and the main control chip adjusts the power-down storage space corresponding to the data to be stored according to the data quantity of the data to be stored of each data type and the capacity corresponding to each power-down storage space so as to acquire the adjusted power-down storage space and determine an adjusted storage channel corresponding to the adjusted power-down storage space.

In this embodiment, the main control chip may adjust the power-down storage space corresponding to the data to be stored according to the data amount of the data to be stored of each data type and the capacity corresponding to each power-down storage space, so as to obtain the adjusted power-down storage space, and determine an adjusted storage channel corresponding to the adjusted power-down storage space.

For example, when determining that the first power-down storage space (with the capacity of 2 MB) cannot store the data to be stored (with the data amount of 3 MB) of the user data type, the main control chip may adjust the power-down storage space corresponding to the data to be stored, determine that the power-down storage space corresponding to the data to be stored of the user data type is the first power-down storage space (with the capacity of 2 MB) and the second power-down storage space (with the capacity of 2 MB), and determine that the power-down storage space corresponding to the data to be stored of the metadata type is the third power-down storage space (with the capacity of 2 MB). Because the first storage channel is a storage channel of the main control chip leading to the first power-down storage space, the second storage channel is a storage channel of the main control chip leading to the second power-down storage space, and the third storage channel is a storage channel of the main control chip leading to the third power-down storage space, the main control chip determines that the storage channel for transmitting the data to be stored of the user data type is the first storage channel (corresponding to the first power-down storage space) and the second storage channel (corresponding to the second power-down storage space), and the storage channel for transmitting the data to be stored of the metadata type is the third storage channel (corresponding to the third power-down storage space).

S404: and the main control chip stores the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

In this embodiment, after determining the adjusted storage channel and the adjusted power-down storage space, the main control chip may store the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

It should be noted that, after determining the adjusted power-down storage space, the main control chip may update the first correspondence table (correspondence table between types of data to be stored and the power-down storage space) stored in the volatile memory chip and at least one nonvolatile memory chip according to the adjusted power-down storage space, so that when the main control chip generates secondary power-down for the solid-state disk, the power-down storage space corresponding to the types of data to be stored may be determined according to the updated correspondence table.

In this embodiment, the main control chip may adjust the power-down storage space corresponding to the data to be stored according to the data amount of the data to be stored of each data type and the capacity corresponding to each power-down storage space, so as to obtain the adjusted power-down storage space, determine the adjusted storage channel corresponding to the adjusted power-down storage space, so as to ensure that the data to be stored with large data amount can be stored in the corresponding power-down storage spaces in parallel through the plurality of storage channels, shorten the time for storing the data to be stored with large data amount into the nonvolatile memory chip, and further ensure that all the data to be stored can be completely stored into the nonvolatile memory chip in a limited time.

On the basis of the first embodiment of the method, a detailed description is given below of another specific implementation process of determining a storage channel and a power-down storage space for the main control chip and storing the data to be stored into the corresponding power-down storage space through the corresponding storage channel by the fourth embodiment of the method.

Fig. 5 is a schematic flow chart of a fourth embodiment of a power failure protection method provided in the embodiment of the present application, where the method specifically includes the following steps:

s501: the main control chip determines a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and determines a storage channel corresponding to the corresponding power-down storage space.

In this embodiment, the main control chip determines, for each data type of data to be stored, a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, and determines a storage channel corresponding to the corresponding power-down storage space.

For example, the main control chip determines, according to a first correspondence table of a data type of data to be stored and a power-down storage space, that a power-down storage space corresponding to the data to be stored of a user data type is a first power-down storage space and a second power-down storage space, and determines, according to a second correspondence table of the power-down storage space and a storage channel, that a storage channel corresponding to the first power-down storage space is a first storage channel, and that a storage channel corresponding to the second power-down storage space is a second storage channel, that is, the main control chip may determine that a storage channel corresponding to the data to be stored of the user data type is the first storage channel and the second storage channel. The main control chip determines that the power-down storage space corresponding to the data to be stored in the metadata type is a third power-down storage space, and determines that the storage channel corresponding to the third power-down storage space is a third storage channel, that is, the main control chip can determine that the storage channel corresponding to the data to be stored in the metadata type is the third storage channel.

S502: the main control chip determines the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type.

In this embodiment, the main control chip may obtain the total number of the power-down storage spaces and the priority of the data to be stored of each data type.

For example, the master control chip may obtain that the total number of the power-down storage spaces is 3, the priority of the data to be stored of the user data type is low-level, and the priority of the data to be stored of the metadata type is high-level.

S503: and the main control chip determines the number of the power-down storage spaces corresponding to the data to be stored according to the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type.

In this embodiment, the volatile memory chip and at least one nonvolatile memory chip may store a table of correspondence between priorities, total number of power-down storage spaces, and number of power-down storage spaces. The main control chip can determine the number of the power-down storage spaces corresponding to the data to be stored of each data type according to the priority corresponding to the data to be stored of each data type and a corresponding relation table of the total number of the power-down storage spaces and the number of the power-down storage spaces.

For example, the main control chip may determine, based on the correspondence table, that the number of power-down storage spaces corresponding to the data to be stored of the user data type is 1 when determining that the priority of the data to be stored of the user data type is low and the total number of power-down storage spaces is 3. The main control chip may determine that the number of the power-down storage spaces corresponding to the data to be stored of the metadata type is 2 based on the correspondence table when determining that the priority of the data to be stored of the metadata type is high and the total number of the power-down storage spaces is 3.

S504: the main control chip adjusts the power-down storage spaces corresponding to the data to be stored according to the number of the power-down storage spaces so as to obtain the adjusted power-down storage spaces, and determines the adjusted storage channels corresponding to the adjusted power-down storage spaces.

In this embodiment, the main control chip may adjust the power-down storage space corresponding to the data to be stored according to the number of the power-down storage spaces, so as to obtain the adjusted power-down storage space, and determine an adjusted storage channel corresponding to the adjusted power-down storage space.

For example, the main control chip may determine that the number of power-down storage spaces corresponding to the data to be stored of the user data type is 1, and determine that the number of power-down storage spaces corresponding to the data to be stored of the metadata type is 2. The main control chip can adjust the power-down storage space corresponding to the data to be stored of the user data type from the first power-down storage space and the second power-down storage space to be the first power-down storage space according to the number of the power-down storage spaces. After the power-down storage space is adjusted, the main control chip can adjust a storage channel for transmitting data to be stored of a user data type from the first storage channel and the second storage channel to be the first storage channel. The main control chip adjusts the power-down storage space corresponding to the data to be stored in the metadata type from the third power-down storage space to be a second power-down storage space and a third power-down storage space, and further adjusts the storage channel for transmitting the data to be stored in the metadata type from the third storage channel to be a second storage channel and a third storage channel.

S505: and the main control chip stores the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

It should be noted that, after determining the adjusted power-down storage space, the main control chip may update the first correspondence table stored in the volatile memory chip and the at least one nonvolatile memory chip according to the information, so that when the main control chip generates secondary power-down for the solid state disk, the power-down storage space corresponding to the data type of the data to be stored may be determined according to the updated first correspondence table.

In this embodiment, the main control chip may determine the number of the power-down storage spaces corresponding to the data to be stored according to the total number of the power-down storage spaces and the priorities corresponding to the data to be stored of each data type, and adjust the power-down storage spaces corresponding to the data to be stored according to the number of the power-down storage spaces, so as to adjust the storage channels, so as to ensure that the data to be stored with higher priority can pass through a plurality of storage channels in parallel and be stored into the power-down storage spaces quickly, thereby avoiding the problem of power-down loss of the data to be stored with higher priority.

On the basis of the first embodiment of the method, a detailed description is given below of another specific implementation process of determining a storage channel and a power-down storage space for the main control chip and storing the data to be stored into the corresponding power-down storage space through the corresponding storage channel by the fifth embodiment of the method.

Fig. 6 is a schematic flow chart of a fifth embodiment of a power failure protection method provided in the embodiment of the present application, where the method specifically includes the following steps:

s601: the main control chip determines a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and determines a storage channel corresponding to the corresponding power-down storage space.

S602: and the main control chip determines the abrasion degree of each power-down storage space.

In this embodiment, the main control chip may determine the wear level of each power-down storage space.

For example, the main control chip may determine that the wear level of the first power-down storage space is 23, the wear level of the second power-down storage space is 56, the wear level of the third power-down storage space is 76, and the wear level of the fourth power-down storage space is 12.

S603: and the main control chip adjusts the power-down storage space corresponding to the data to be stored according to the abrasion degree of each power-down storage space so as to acquire the adjusted power-down storage space and determine an adjusted storage channel corresponding to the adjusted power-down storage space.

In this embodiment, the main control chip may compare the wear degree of each power-down storage space, and determine the power-down storage space with the minimum wear degree as the power-down storage space corresponding to the data to be stored, so as to obtain the adjusted power-down storage space. And the main control chip determines the storage channel corresponding to the adjusted power-down storage space as the adjusted storage channel.

For example, since the wear degree (12) of the fourth power-down storage space is smaller than the wear degree (76) of the third power-down storage space, the main control chip may adjust the power-down storage space corresponding to the data to be stored of the metadata type from the third power-down storage space to the fourth power-down storage space, and since the third power-down storage space corresponds to the third storage channel, the fourth power-down storage space corresponds to the fourth storage channel, and therefore the main control chip adjusts the storage channel for transmitting the data to be stored of the metadata type from the third storage channel to the fourth storage channel.

S604: and the main control chip stores the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

It should be noted that, after determining the adjusted power-down storage space, the main control chip may update the first correspondence table between the data types stored in the volatile memory chip and the at least one nonvolatile memory chip and the power-down storage space according to the information, so that when the main control chip generates secondary power-down for the solid state disk, the power-down storage space corresponding to the type of the data to be stored may be determined according to the updated first correspondence table.

In this embodiment, the main control chip may adjust the power-down storage space for storing the data to be stored according to the wear degree of the power-down storage space, so as to adjust the storage channel for transmitting the data to be stored, so as to ensure that the power-down storage space with low wear degree is preferentially used for storing the data to be stored, thereby avoiding the problem that the data to be stored is stored in the power-down storage space with high wear degree, and data loss is easy to occur.

The following are device embodiments of the present application, which may be used to perform method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

Fig. 7 is a schematic structural diagram of an embodiment of a power failure processing device according to an embodiment of the present application; as shown in fig. 7, the power-down processing device 70 includes: a control module 71 and a processing module 72. The control module 71 is configured to control the preparation electric capacitor to supply power to the solid state disk when detecting that the solid state disk is in a power failure state, and obtain data to be stored in the volatile memory chip; the data to be stored comprises data to be stored of various data types; the processing module 72 is configured to determine, for each data type of data to be stored, a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, and store the data to be stored into the corresponding power-down storage space; the power-down storage space comprises part of storage space in at least one nonvolatile memory chip, and the power-down storage space is a single-layer unit type storage space.

The power failure processing device provided in the embodiment of the present application may execute the technical solution shown in the embodiment of the method, and its implementation principle and beneficial effects are similar, and will not be described herein again.

In the above preferred technical solution of the power failure processing apparatus, the processing module 72 is specifically configured to: for the data to be stored of each data type, determining a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, determining a storage channel corresponding to the corresponding power-down storage space, and storing the data to be stored into the corresponding power-down storage space through the corresponding storage channel.

In the above preferred technical solution of the power failure processing apparatus, the processing module 72 is specifically configured to: reading a first corresponding relation table and a second corresponding relation table stored in a volatile memory chip, or reading the first corresponding relation table and the second corresponding relation table stored in a nonvolatile memory chip; the first corresponding relation table is a corresponding relation table of the data type and the power-down storage space, and the second corresponding relation table is a corresponding relation table of the power-down storage space and the storage channel; for the data to be stored of each data type, determining a power-down storage space corresponding to the data to be stored according to the data type and the corresponding relation table of the data to be stored, determining a storage channel corresponding to the corresponding power-down storage space, and storing the data to be stored into the corresponding power-down storage space through the corresponding storage channel.

In the above preferred embodiment of the power-down processing device, the processing module 72 is further configured to: for the data to be stored of each data type, after the data to be stored is stored to the corresponding power-down storage space through the corresponding storage channel, generating a power-down data completion identifier corresponding to the data type of the data to be stored, and storing the power-down data completion identifier to the power-down storage space; when the solid state disk is detected to be in a power-on state and the power-down data in the power-down storage space is stored to complete identification, the data to be stored in the power-down storage space is stored in a non-power-down storage space of the non-volatile memory chip.

In the above preferred technical solution of the power failure processing apparatus, the processing module 72 is specifically configured to: when the solid state disk is detected to be in a power-on state and the power-down data in the power-down storage space is stored to complete identification, the data to be stored in the power-down storage space are stored into a volatile memory chip; and storing the data to be stored in the volatile memory chip into a non-power-down storage space of the nonvolatile memory chip.

In the above preferred technical solution of the power failure processing apparatus, the processing module 72 is specifically configured to: when the solid state disk is detected to be in a power-on state and the power-down data in the power-down storage space is stored to finish identification, the data to be stored in the power-down storage space is directly stored in the non-power-down storage space of the non-volatile memory chip.

In the above preferred embodiment of the power-down processing device, the processing module 72 is further configured to: and formatting the power-down storage space into a single-layer unit type storage space so as to perform data clearing processing on the power-down storage space.

In the above preferred technical solution of the power failure processing apparatus of a solid state disk, the processing module 72 is further configured to: determining the data quantity of data to be stored of each data type and the corresponding capacity of each power-down storage space; according to the data volume of the data to be stored of each data type and the corresponding capacity of each power-down storage space, the power-down storage space corresponding to the data to be stored is adjusted to obtain an adjusted power-down storage space, and an adjusted storage channel corresponding to the adjusted power-down storage space is determined; and the main control chip stores the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

In the above preferred embodiment of the power-down processing device, the processing module 72 is further configured to: determining the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type; determining the number of the power-down storage spaces corresponding to the data to be stored according to the total number of the power-down storage spaces and the priority corresponding to the data to be stored of each data type; according to the number of the power-down storage spaces, the power-down storage spaces corresponding to the data to be stored are adjusted to obtain adjusted power-down storage spaces, and an adjusted storage channel corresponding to the adjusted power-down storage spaces is determined; and storing the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

In the above preferred embodiment of the power-down processing device, the processing module 72 is further configured to: determining the wear degree of each power-down storage space; according to the wear degree of each power-down storage space, adjusting the power-down storage space corresponding to the data to be stored to obtain an adjusted power-down storage space, and determining an adjusted storage channel corresponding to the adjusted power-down storage space; and storing the data to be stored into the adjusted power-down storage space through the adjusted storage channel.

Fig. 8 is a schematic structural diagram of a computing device according to an embodiment of the present application. As shown in fig. 8, the computing device 80 includes a motherboard 81 and a solid state disk 82. The motherboard 81 includes a motherboard interface 811, and the solid state disk 82 includes a hard disk connector 822. The main board 81 is connected to the solid state disk 82 through a main board interface 811 and a hard disk connector 822.

In one possible implementation, computing device 80 may also include a patch cord, and motherboard 81 may be connected to solid state disk 82 through motherboard interface 811, the patch cord, and hard disk connector 822.

The computing device may be a terminal device (mobile phone, computer) or a server.

It should be noted that, in this embodiment of the present application, the solid state disk 82 is a solid state disk provided in fig. 1, which may execute the technical solution shown in the embodiment of the method, and its implementation principle and beneficial effects are similar, and are not repeated here.

The embodiment of the application also provides a computer readable storage medium, wherein computer executable instructions are stored in the computer readable storage medium, and the computer executable instructions are used for realizing the technical scheme provided by any one of the method embodiments when being executed by a processor.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features can be replaced equivalently; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. The power failure processing method is characterized by being applied to a solid state disk, wherein the solid state disk comprises a main control chip, and a standby capacitor, a volatile memory chip and at least one nonvolatile memory chip which are electrically connected with the main control chip, and the method comprises the following steps:

2. The power-down processing method according to claim 1, wherein the main control chip determines, for data to be stored of each data type, a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, and stores the data to be stored into the corresponding power-down storage space, including:

3. The power-down processing method according to claim 2, wherein the main control chip determines, for data to be stored of each data type, a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored, determines a storage channel corresponding to the corresponding power-down storage space, and stores the data to be stored into the corresponding power-down storage space through the corresponding storage channel, including:

4. The power down processing method according to claim 2, further comprising:

5. The power-down processing method according to claim 4, wherein when the main control chip detects that the solid state disk is in a power-up state and the power-down storage space stores a power-down data completion identifier, storing data to be stored in the power-down storage space into a non-power-down storage space of the nonvolatile memory chip, the method comprises:

6. The power down processing method according to claim 5, further comprising:

7. The power down processing method according to claim 2, further comprising:

8. The power down processing method according to claim 2, further comprising:

9. A solid state disk, comprising:

the main control chip is further used for determining a power-down storage space corresponding to the data to be stored according to the data type of the data to be stored aiming at the data to be stored of each data type, and storing the data to be stored into the corresponding power-down storage space;

10. A computing device comprising a motherboard and the solid state disk of claim 9;

the solid state disk comprises a hard disk connector;